JP2018046747A - Control method for power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply circuit and a control method for the power supply circuit, capable of efficiently taking out power from each voltage source.SOLUTION: A power supply circuit includes: voltage sources 11_1 to 11_5; voltage control circuits 14_1 and 14_2 for stepping up input voltage; and a voltage source connection switch 13 for connecting at least one of the voltage sources 11_1 to 11_5 to either one of the voltage control circuits 14_1 or 14_2. For example, the voltage source connection switch 13 connects a voltage source having voltage lower than predetermined reference voltage among the voltage sources 11_1 to 11_5 to the voltage control circuit 14_1, and connects a voltage source having voltage higher than the predetermined reference voltage among the voltage sources 11_1 to 11_5 to the voltage control circuit 14_2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply circuit and a control method for the power supply circuit, for example, a power supply circuit including a plurality of voltage sources, and a control method for the power supply circuit.

  In recent years, energy harvesting technology that converts personal energy such as light energy, vibration energy, heat energy, radio waves (electromagnetic waves) into electric power has attracted attention. By using the energy harvesting technology, it is not necessary to install a battery in the electronic device, and the convenience of the electronic device can be improved.

  Patent Document 1 discloses a technique related to an assembled battery that can individually check the states of a plurality of batteries. Patent Document 2 discloses a technique related to an electronic device that can increase the degree of freedom of use of a plurality of batteries and improve the use efficiency of the batteries.

JP 11-273747 A Japanese Patent No. 2959657

  When energy harvesting technology is used, the voltage obtained with one voltage source is very small. For this reason, it is necessary to provide a voltage control circuit (boost circuit) in order to boost the voltage of the voltage source to a voltage that can drive the electronic device. In addition, with a voltage source using energy harvesting technology, the power obtained with one voltage source is small. For this reason, it is necessary to provide a plurality of voltage sources in order to drive the electronic device, and to collect the power obtained by these voltage sources.

  However, if a voltage control circuit is provided for each of the plurality of voltage sources, the circuit area of the power supply circuit increases. On the other hand, if a single voltage control circuit is shared by a plurality of voltage sources in order to reduce the circuit area, power loss occurs because the output voltage of each voltage source is not constant. There is a problem that can not be taken out.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A power supply circuit according to an embodiment includes at least one of N (N ≧ 3) voltage sources, first and second voltage control circuits that boost an input voltage, and N voltage sources. And a voltage source connection switch for connecting one to one of the first and second voltage control circuits.
In the power supply circuit according to the embodiment, the first and second voltage control circuits and the voltage source connection switch are formed on the same chip. The first voltage control circuit and the voltage source connection switch are connected via a first wiring provided outside the chip, and the second voltage control circuit and the voltage source connection switch are connected to the outside of the chip. Are connected via a second wiring provided in the.

  According to one embodiment, a method for controlling a power supply circuit monitors the voltages of N voltage sources, and sets at least one of the N voltage sources as a first and a second voltage according to the voltages of the N voltage sources. Connect to any one of the second voltage control circuits.

  According to the embodiment, it is possible to provide a power supply circuit that can efficiently extract power from each voltage source and a control method for the power supply circuit.

1 is a block diagram showing a power supply circuit according to a first exemplary embodiment; FIG. 3 is a block diagram illustrating an example of a voltage source connection switch included in the power supply circuit according to the first embodiment. It is a circuit diagram which shows the specific example of a voltage source connection switch. FIG. 3 is a circuit diagram illustrating an example of a voltage control circuit included in the power supply circuit according to the first embodiment; FIG. 3 is a block diagram illustrating an example of a voltage source switching circuit included in the power supply circuit according to the first embodiment. It is a circuit diagram which shows the specific example of a voltage source switching circuit. FIG. 3 is a diagram illustrating an example of a voltage monitor circuit included in the power supply circuit according to the first embodiment. 3 is a timing chart showing the operation of the power supply circuit according to the first exemplary embodiment; FIG. 3 is a block diagram showing an example of operation of the power supply circuit according to the first exemplary embodiment. It is a block diagram which shows an example of operation | movement of the power supply circuit concerning a comparative example. FIG. 3 is a block diagram showing a power supply circuit according to a second exemplary embodiment. 6 is a timing chart illustrating an operation of the power supply circuit according to the second exemplary embodiment; FIG. 6 is a block diagram showing an example of the operation of the power supply circuit according to the second exemplary embodiment. FIG. 4 is a diagram illustrating a configuration example of a power supply circuit according to a third embodiment. It is a figure which shows the power supply circuit concerning a comparative example. It is a figure which shows an example of arrangement | positioning of each pad with which the power supply circuit concerning Embodiment 3 is provided. It is a figure which shows an example of arrangement | positioning of each pad with which the power supply circuit concerning Embodiment 3 is provided. It is a figure which shows an example of arrangement | positioning of each pad with which the power supply circuit concerning Embodiment 3 is provided. FIG. 9 is a block diagram illustrating an example of a power supply system according to a fourth embodiment. It is a figure which shows the relationship between the output voltage of RF-DC conversion circuit, and output electric power. FIG. 10 is a block diagram showing another example of the power supply system according to the fourth exemplary embodiment. FIG. 10 is a block diagram showing another example of the power supply system according to the fourth exemplary embodiment. FIG. 10 is a block diagram showing another example of the power supply system according to the fourth exemplary embodiment.

<Embodiment 1>
The first embodiment will be described below with reference to the drawings.
FIG. 1 is a block diagram of a power supply circuit 1 according to the first embodiment. As shown in FIG. 1, the power supply circuit 1 according to this embodiment includes voltage sources 11_1 to 11_5, a voltage source connection switch 13, voltage control circuits 14_1 and 14_2, a voltage source switching circuit 16, a voltage monitor circuit 17, and a control circuit. 18 and a clock generation circuit 20. The power supply circuit 1 supplies power to the load circuit 15.

  Each of the voltage sources 11_1 to 11_5 generates power supply voltages V1 to V5, and outputs the generated power supply voltages V1 to V5 to the voltage source connection switch 13 and the voltage source switching circuit 16. The voltage sources 11_1 to 11_5 generate a power supply voltage (power) using an energy harvesting technique. For example, the voltage sources 11_1 to 11_5 convert personal energy such as light, vibration energy, thermal energy, and radio waves (electromagnetic waves) into electric power.

  For example, when converting light energy into electric power, a photoelectric conversion element (solar cell) can be used. When converting vibration energy into electric power, a piezoelectric element can be used. When converting thermal energy into electric power, a thermoelectric element (Peltier element) can be used. In the case of converting radio waves into electric power, for example, a circuit (rectenna) including an antenna and a rectifying element can be used. When energy harvesting technology is used, the voltage obtained with one voltage source is very small. For example, the power supply voltage obtained when radio waves are converted into electric power is about 0.1V to 0.2V.

  When converting radio waves into electric power, in order to convert radio waves in a plurality of frequency bands into electric power, voltage sources 11_1 to 11_5 corresponding to the respective frequency bands (that is, voltage sources 11_1 that receive radio waves in the respective frequency bands). To 11_5) may be provided. Here, the predetermined frequency band is a frequency band in which many radio waves are used (that is, a frequency band with high energy) such as a frequency band of a mobile phone, a frequency band of a wireless LAN, and a frequency band of terrestrial digital broadcasting. . As described above, when radio waves having different frequency bands are used, the power supply voltages obtained from the voltage sources 11_1 to 11_5 may be different for each frequency band.

  The voltage source connection switch 13 switches the connection state between the voltage sources 11_1 to 11_5 and the voltage control circuits 14_1 and 14_2. That is, in the voltage source connection switch 13, the voltage source 11_n (1 ≦ n ≦ 5) is connected to the voltage control circuit 14_1, the voltage source 11_n is connected to the voltage control circuit 14_2, and the voltage source 11_n is a voltage. The three connection states of the state not connected to any of the control circuits 14_1 and 14_2 are switched.

  FIG. 2 is a block diagram illustrating an example of the voltage source connection switch 13 provided in the power supply circuit 1 according to the present embodiment. As shown in FIG. 2, the voltage source connection switch 13 includes a plurality of switches SW1_1 to SW5_1, SW1_2 to SW5_2. The voltage source 11_1 is connected to the voltage control circuit 14_1 via the switch SW1_1, and is connected to the voltage control circuit 14_2 via the switch SW1_2. The voltage source 11_2 is connected to the voltage control circuit 14_1 via the switch SW2_1, and is connected to the voltage control circuit 14_2 via the switch SW2_2. The same applies to the voltage sources 11_3 to 11_5.

  For example, the voltage source connection switch 13 can be brought into a state where the voltage source 11_1 is connected to the voltage control circuit 14_1 by turning on the switch SW1_1 and turning off the switch SW1_2. Further, the voltage source connection switch 13 can be brought into a state in which the voltage source 11_1 is connected to the voltage control circuit 14_2 by turning off the switch SW1_1 and turning on the switch SW1_2. In addition, the voltage source connection switch 13 can be in a state where the voltage source 11_1 is not connected to any of the voltage control circuits 14_1 and 14_2 by turning off the switch SW1_1 and the switch SW1_2. The same applies to the voltage sources 11_2 to 11_5. The plurality of switches SW1_1 to SW5_1 and SW1_2 to SW5_2 are controlled using a control signal output from the control circuit 18.

  FIG. 3 is a circuit diagram showing a specific example of the voltage source connection switch 13. As shown in FIG. 3, for example, the switch SW1_1 can be configured using a PMOS transistor MP1_1, an NMOS transistor MN1_1, and an inverter INV1_1. The voltage source 11_1 is connected to the source of the PMOS transistor MP1_1 and the drain of the NMOS transistor MN1_1, and the voltage control circuit 14_1 is connected to the drain of the PMOS transistor MP1_1 and the source of the NMOS transistor MN1_1. The gate of the NMOS transistor MN1_1 is connected to the input side of the inverter INV1_1, and the gate of the PMOS transistor MP1_1 is connected to the output side of the inverter INV1_1.

  When the control signal CTR1_1 is at a high level, a high level signal is supplied to the gate of the NMOS transistor MN1_1, and a low level signal is supplied to the gate of the PMOS transistor MP1_1. Therefore, in this case, the NMOS transistor MN1_1 and the PMOS transistor MP1_1 are turned on, and the voltage source 11_1 and the voltage control circuit 14_1 are connected. In other words, the power supply voltage V1 is supplied to the voltage control circuit 14_1. The switch SW1_2 is similar to the switch SW1_1.

  Note that the configuration example of the switches SW1_1 and SW1_2 illustrated in FIG. 3 is an example, and the switches SW1_1 and SW1_2 may have other configurations. For example, the switch SW1_1 may be configured using only a PMOS transistor, or may be configured using only an NMOS transistor. In consideration of the low power supply voltage V1 supplied from the voltage source 11_1, when the switch SW1_1 is configured using one MOS transistor, it is preferable to use an NMOS transistor.

  For example, the voltage source connection switch 13 connects a voltage source whose voltage is lower than a predetermined reference voltage among the voltage sources 11_1 to 11_5 to the voltage control circuit 14_1, and the voltage of the voltage sources 11_1 to 11_5 is equal to or higher than the predetermined reference voltage. The voltage source may be connected to the voltage control circuit 14_2. In this way, voltage sources having comparable power supply voltages can be connected to the voltage control circuits 14_1 and 14_2.

  The voltage control circuits 14_1 and 14_2 shown in FIG. 1 boost the respective input voltages Vin_1 and Vin_2, and output the boosted output voltage Vout to the load circuit 15. The output voltage output from the voltage control circuit 14_1 and the output voltage output from the voltage control circuit 14_2 are substantially the same (Vout). The voltage control circuit 14_1 boosts the input voltage in accordance with the clock signal CLK_1 supplied from the clock generation circuit 20. The voltage control circuit 14_2 boosts the input voltage in accordance with the clock signal CLK_2 supplied from the clock generation circuit 20. The clock generation circuit 20 generates clock signals CLK_1 and CLK_2 according to the control signal supplied from the control circuit 18. Each of the voltage control circuits 14_1 and 14_2 is supplied with clock signals CLK_1 and CLK_2 as clock signals CLK_1 and CLK_2 so that the output voltage of the voltage control circuit 14_1 and the output voltage of the voltage control circuit 14_2 are substantially the same. .

  For example, the voltage control circuit 14_1 boosts the input voltage according to the duty ratio of the clock signal CLK_1 supplied to the voltage control circuit 14_1. Similarly, the voltage control circuit 14_2 boosts the input voltage according to the duty ratio of the clock signal CLK_2 supplied to the voltage control circuit 14_2.

  FIG. 4 is a circuit diagram illustrating an example of the voltage control circuit 14_1 (the voltage control circuit 14_2 has the same configuration). As shown in FIG. 4, the voltage control circuit 14_1 can be configured using a switching regulator including an inductor L1, a PMOS transistor MP10, an NMOS transistor MN10, and a capacitor C1.

  The input voltage Vin_1 supplied from the voltage source is supplied to one end of the inductor L1. The drain of the NMOS transistor MN10 is connected to the other end of the inductor L1 and the source of the PMOS transistor MP10, the source is grounded, and the clock signal CLK_1 is supplied to the gate. The source of the PMOS transistor MP10 is connected to the other end of the inductor L1 and the drain of the NMOS transistor MN10, the drain is connected to one end of the capacitor C1, and the clock signal CLK_1 is supplied to the gate. An output voltage Vout is output from the drain of the PMOS transistor MP10.

  When the clock signal CLK_1 is at a high level, the NMOS transistor MN10 is turned on and the PMOS transistor MP10 is turned off. At this time, the input voltage Vin_1 is supplied to one end of the inductor L1, and the other end is grounded, so that a current flows through the inductor L1. Thereby, energy is stored in the inductor L1. Thereafter, when the clock signal CLK_1 becomes low level, the NMOS transistor MN10 is turned off and the PMOS transistor MP10 is turned on. As a result, the energy stored in the inductor L1 is released from the drain of the PMOS transistor MP10 and the output voltage Vout is output. The output voltage Vout is determined according to the duty ratio of the clock signal CLK_1. Here, the duty ratio of the clock signal CLK_1 can be obtained by calculating high level time / (high level time + low level time).

  The output voltage Vout of the voltage control circuit 14_1 increases as the duty ratio of the clock signal CLK_1 increases. In the power supply circuit according to this embodiment, the output voltage Vout of the voltage control circuit 14_1 and the output voltage Vout of the voltage control circuit 14_2 are the same. Therefore, for example, when the input voltage Vin_1 supplied to the voltage control circuit 14_1 is lower than the input voltage Vin_2 supplied to the voltage control circuit 14_2, the duty ratio of the clock signal CLK_1 is larger than the duty ratio of the clock signal CLK_2.

  The voltage source switching circuit 16 illustrated in FIG. 1 sequentially switches the connection between each of the voltage sources 11_1 to 11_5 and the voltage monitor circuit 17. In other words, the voltage source switching circuit 16 outputs any one power supply voltage among the voltage sources 11_1 to 11_5 to the voltage monitor circuit 17.

  FIG. 5 is a block diagram illustrating an example of the voltage source switching circuit 16. As shown in FIG. 5, the voltage source switching circuit 16 includes a plurality of switches SW_M1 to SW_M5. The voltage source 11_1 is connected to the voltage monitor circuit 17 via the switch SW_M1, the voltage source 11_2 is connected to the voltage monitor circuit 17 via the switch SW_M2, and the voltage source 11_3 is connected to the voltage monitor circuit via the switch SW_M3. 17, the voltage source 11_4 is connected to the voltage monitor circuit 17 via the switch SW_M4, and the voltage source 11_5 is connected to the voltage monitor circuit 17 via the switch SW_M5.

  Then, any one of the voltage sources 11_1 to 11_5 can be output to the voltage monitor circuit 17 by turning on one of the switches SW_M1 to SW_M5. The switches SW_M1 to SW_M5 are controlled using control signals CTR_M1 to CTR_M5 output from the control circuit. Note that when the power supply voltages of the voltage sources 11_1 to 11_5 are not monitored, all of the switches SW_M1 to SW_M5 are in an off state.

  FIG. 6 is a circuit diagram illustrating a specific example of the switches SW_M1 to SW_M5 included in the voltage source switching circuit 16. Note that FIG. 6 shows only the switch SW_M1, but the same applies to the other switches SW_M2 to SW_M5. As shown in FIG. 6, for example, the switch SW_M1 can be configured using a PMOS transistor MP_M1, an NMOS transistor MN_M1, and an inverter INV1_M1. The voltage source 11_1 is connected to the source of the PMOS transistor MP_M1 and the drain of the NMOS transistor MN_M1, and the voltage monitor circuit 17 is connected to the drain of the PMOS transistor MP_M1 and the source of the NMOS transistor MN_M1. The gate of the NMOS transistor MN_M1 is connected to the input side of the inverter INV1_M1, and the gate of the PMOS transistor MP_M1 is connected to the output side of the inverter INV1_M1.

  When the control signal CTR_M1 is at a high level, a high level signal is supplied to the gate of the NMOS transistor MN_M1, and a low level signal is supplied to the gate of the PMOS transistor MP_M1. Therefore, in this case, the NMOS transistor MN_M1 and the PMOS transistor MP_M1 are turned on, and the voltage source 11_1 and the voltage monitor circuit 17 are connected. In other words, the power supply voltage V <b> 1 is supplied to the voltage monitor circuit 17.

  The voltage monitor circuit 17 monitors the power supply voltages V1 to V5 of the voltage sources 11_1 to 11_5. That is, the voltage monitor circuit 17 monitors the power supply voltage of any one of the voltage sources 11_1 to 11_5 selected by the voltage source switching circuit 16.

  FIG. 7 is a block diagram illustrating an example of the voltage monitor circuit 17. As shown in FIG. 7, the voltage monitor circuit 17 includes a reference voltage generation circuit 19 and a comparison circuit CMP1. The reference voltage generation circuit 19 generates a reference voltage Vref. The reference voltage generation circuit 19 can be configured using, for example, a band gap reference circuit. The comparison circuit CMP1 compares the power supply voltages V1 to V5 of the voltage sources 11_1 to 11_5 with the reference voltage Vref, and outputs comparison results OUT_M1 to OUT_M5.

  For example, when the power supply voltage V1 of the voltage source 11_1 is lower than the reference voltage Vref, the comparison circuit CMP1 outputs a low level signal as the comparison result OUT_M1. On the other hand, when the power supply voltage V1 of the voltage source 11_1 is equal to or higher than the reference voltage Vref, a high level signal is output as the comparison result OUT_M1.

  Comparison results OUT_M1 to OUT_M5 of the voltage monitor circuit 17 (that is, comparison results between the power supply voltages V1 to V5 of the voltage sources 11_1 to 11_5 and the reference voltage Vref) are stored in the control circuit 18. For example, the control circuit 18 includes flip-flops FF1 to FF5 (not shown) provided so as to correspond to the respective voltage sources 11_1 to 11_5, and the power supply voltages V1 to V5 and the reference voltages of the respective voltage sources 11_1 to 11_5. Comparison results OUT_M1 to OUT_M5 with Vref are stored in the corresponding flip-flops FF1 to FF5, respectively.

  The reference voltage Vref may be determined based on the input voltage Vin_1 of the voltage control circuit 14_1 and the input voltage Vin_2 of the voltage control circuit 14_2. For example, when Vin_1 <Vin_2, the reference voltage Vref may be determined so as to satisfy Vin_1 × 2 <Vref <Vin_2 × 2.

  The reference voltage Vref may be determined based on the power supply voltages V1 to V5 of the voltage sources 11_1 to 11_5. For example, when the maximum value of the power supply voltages V1 to V5 is V_max and the minimum value of the power supply voltages V1 to V5 is V_min, the reference voltage Vref may be determined to satisfy V_min <Vref <V_max. Further, the reference voltage Vref may be determined using an average value (or a value near the average value) of the power supply voltages V1 to V5.

  The control circuit 18 controls the power supply circuit 1. Specifically, the control circuit 18 controls the switches SW_M1 to SW_M5 included in the voltage source switching circuit 16. The control circuit 18 controls the plurality of switches SW1_1 to SW5_1 and SW1_2 to SW5_2 included in the voltage source connection switch 13 according to the comparison results OUT_M1 to OUT_M5 of the voltage monitor circuit 17. For example, the control circuit 18 connects a voltage source whose voltage is lower than a predetermined reference voltage Vref among the voltage sources 11_1 to 11_5 to the voltage control circuit 14_1, and the voltage of the voltage sources 11_1 to 11_5 is equal to or higher than the predetermined reference voltage Vref. Are connected to the voltage control circuit 14_2. In this way, voltage sources having comparable power supply voltages can be connected to the voltage control circuits 14_1 and 14_2. Further, the control circuit 18 controls the clock generation circuit 20. For example, the control circuit 18 can adjust the output voltages of the voltage control circuits 14_1 and 14_2 by controlling the duty ratios of the clock signals CLK_1 and CLK_2 generated by the clock generation circuit 20, respectively.

  Next, the operation of the power supply circuit according to this embodiment will be described with reference to the timing chart shown in FIG. The power supply circuit 1 according to the present embodiment includes a monitor mode and a normal mode as operation modes. In the normal mode, the voltage source connection switch 13 connects at least one of the voltage sources 11_1 to 11_5 to one of the voltage control circuit 14_1 and the voltage control circuit 14_2 to supply power to the load circuit 15. It is a mode to do. The monitor mode is a mode for monitoring the power supply voltages V1 to V5 of the voltage sources 11_1 to 11_5 using the voltage monitor circuit 17. In the monitor mode, among the voltage sources 11_1 to 11_5, voltage sources other than the voltage source that monitors the power supply voltage using the voltage monitor circuit 17 are the voltage control circuit 14_1 and the voltage control circuit, as in the normal mode. 14_2 is connected to one of them. Therefore, power is supplied to the load circuit 15 even in the monitor mode. Note that the clock signal CLK_1 having a predetermined duty ratio is supplied to the voltage control circuit 14_1, and the clock signal CLK_2 having a predetermined duty ratio is supplied to the voltage control circuit 14_2.

  As shown in FIG. 8, at time t1, the voltage source connection switch 13 transitions from the normal mode to the monitor mode. Next, at timing t2, when the control signal CTR_M1 of the switch SW_M1 (see FIG. 5) included in the voltage source switching circuit 16 becomes high level, the switch SW_M1 is turned on, and the power supply voltage V1 of the voltage source 11_1 is changed to the voltage monitor circuit 17. Is output. At this time, the voltage source connection switch 13 switches to a state where the voltage source 11_1 is not connected to any of the voltage control circuits 14_1 and 14_2.

  The voltage monitor circuit 17 compares the power supply voltage V1 of the voltage source 11_1 with the reference voltage Vref, and outputs a comparison result OUT_M1. For example, when the power supply voltage V1 of the voltage source 11_1 is lower than the reference voltage Vref, the voltage monitor circuit 17 outputs a low level signal as the comparison result OUT_M1. On the other hand, when the power supply voltage V1 of the voltage source 11_1 is equal to or higher than the reference voltage Vref, the voltage monitor circuit 17 outputs a high level signal as the comparison result OUT_M1.

  At timing t3, when the drive clock of the flip-flop FF1 storing the comparison result OUT_M1 becomes high level, the comparison result OUT_M1 (information on the voltage of the voltage source 11_1) is stored in the flip-flop FF1. Thereafter, the control signals CTR_M2 to CTR_M5 are sequentially set to the high level, and similarly to the voltage source 11_1, the power supply voltages V2 to V5 of the voltage sources 11_2 to 11_5 are compared with the reference voltage Vref, and these comparison results OUT_M2 to OUT_M5 are They are stored in flip-flops FF2 to FF5, respectively.

  Thereafter, at timing t4, the voltage source connection switch 13 changes from the monitor mode to the normal mode. At this time, the voltage source connection switch 13 determines whether the voltage sources 11_1 to 11_5 are in accordance with the comparison results OUT_M1 to OUT_M5 (that is, information on the voltages of the voltage sources 11_1 to 11_5) stored in the flip-flops FF1 to FF5. At least one of them is connected to one of the voltage control circuits 14_1 and 14_2. Thereby, the state of the power supply voltage of the voltage sources 11_1 to 11_5 monitored in the monitor mode is reflected in the connection state of the voltage source connection switch 13.

  For example, the voltage source connection switch 13 connects a voltage source whose voltage is lower than a predetermined reference voltage Vref among the voltage sources 11_1 to 11_5 to the voltage control circuit 14_1, and the voltage of the voltage sources 11_1 to 11_5 is a predetermined reference voltage. A voltage source equal to or higher than Vref is connected to the voltage control circuit 14_2. In this way, voltage sources having the same power supply voltage can be connected to the same voltage control circuit.

  At this time, a lower limit reference voltage Vref_L may be provided, and a voltage source whose power supply voltage is lower than the lower limit reference voltage Vref_L may not be connected to any of the voltage control circuits 14_1 and 14_2. Further, an upper limit reference voltage Vref_H may be provided, and a voltage source whose power supply voltage is higher than the upper limit reference voltage Vref_H may not be connected to any of the voltage control circuits 14_1 and 14_2.

  Thereafter, at timing t5, the voltage source connection switch 13 transitions again from the normal mode to the monitor mode. Thereafter, the operation described above is repeated.

  As described in the background art, when the energy harvesting technique is used, the voltage obtained by one voltage source is very small. For example, the voltage obtained using radio waves (environmental radio waves) drifting in space is very small, about 0.1 to 0.4V. Therefore, it is necessary to provide a voltage control circuit in order to boost the voltage of the voltage source to a voltage that can drive the electronic device. For example, to drive a microcomputer or the like, it is necessary to boost the voltage to about 1 V using a voltage control circuit.

  In addition, with a voltage source using energy harvesting technology, the power obtained with one voltage source is small. For this reason, it is necessary to provide a plurality of voltage sources in order to drive the electronic device, and to collect the power obtained by these voltage sources. For example, in order to drive a microcomputer, power of about several hundred μW to several mW is required.

  However, if a voltage control circuit is provided for each of the plurality of voltage sources, the circuit area of the power supply circuit increases. On the other hand, if a single voltage control circuit is shared by a plurality of voltage sources in order to reduce the circuit area, power loss occurs because the output voltage of each voltage source is not constant. There is a problem that can not be taken out. In particular, in the case of a voltage source that generates electric power using radio waves, a rectifier circuit is used. Therefore, when the generated voltage is low, it may be impossible to extract electric power from the voltage source.

  Therefore, in the power supply circuit 1 according to the present embodiment, a plurality of voltage control circuits 14_1 and 14_2 are provided for the plurality of voltage sources 11_1 to 11_5. The voltage source connection switch 13 is used to connect at least one of the voltage sources 11_1 to 11_5 to any one of the plurality of voltage control circuits 14_1 and 14_2. For example, a voltage source whose power source voltage is lower than the reference voltage is connected to the voltage control circuit 14_1, and a voltage source whose power source voltage is higher than the reference voltage is connected to the voltage control circuit 14_2. Therefore, it is possible to provide a power supply circuit that can efficiently extract power from each voltage source and a control method for the power supply circuit. Further, since the voltage control circuit is shared by a plurality of voltage sources, the circuit area of the power supply circuit can be reduced.

  FIG. 9 is a block diagram showing an example of the operation of the power supply circuit 1 according to the present embodiment. In the power supply circuit 1 shown in FIG. 9, the power supply voltage (open voltage) of the voltage source 11_1 is 0.2V, the power supply voltage of the voltage source 11_2 is 0.2V, the power supply voltage of the voltage source 11_3 is 0.3V, and the voltage source 11_4 The power supply voltage is 0.4V, and the power supply voltage of the voltage source 11_5 is 0.5V. The output impedance of each voltage source 11_1 to 11_5 is 1 kΩ.

  Then, the reference voltage Vref is set to 0.25 V, a voltage source whose power source voltage is lower than the reference voltage is connected to the voltage control circuit 14_1, and a voltage source whose voltage source is higher than the reference voltage is voltage controlled. It is assumed that the circuit 14_2 is connected. In this case, since the power supply voltage of the voltage sources 11_1 and 11_2 is 0.2V and lower than the reference voltage 0.25V, the voltage source connection switch 13 connects the voltage sources 11_1 and 11_2 to the voltage control circuit 14_1. On the other hand, the power supply voltages of the voltage sources 11_3, 11_4, and 11_5 are 0.3V, 0.4V, and 0.5V, respectively, and are higher than the reference voltage 0.25V, so the voltage source connection switch 13 is connected to the voltage sources 11_3, 11_4, 11_5 is connected to the voltage control circuit 14_2.

  Further, the output voltage Vout of the voltage control circuits 14_1 and 14_2 is 1.5V, the duty ratio of the clock signal CLK_1 supplied to the voltage control circuit 14_1 is 0.93, and the duty ratio of the clock signal CLK_2 supplied to the voltage control circuit 14_2. Is set to 0.87, the input voltage Vin_1 of the voltage control circuit 14_1 becomes 0.1V, and the input voltage Vin_2 of the voltage control circuit 14_2 becomes 0.2V.

  At this time, the power supplied from the voltage source 11_1 to the voltage control circuit 14_1 has a potential difference of 0. 0 between the power supply voltage V1 (0.2V) of the voltage source 11_1 and the input voltage Vin_1 (0.1V) of the voltage control circuit 14_1. Since it is 1 V and the current supplied to the voltage control circuit 14_1 is 100 μA (= 0.1 V / 1 kΩ), it becomes 10 μW (= 0.1 V × 100 μA). Similarly, the power supplied from the voltage source 11_2 to the voltage control circuit 14_1 is 10 μW, the power supplied from the voltage source 11_3 to the voltage control circuit 14_2 is 20 μW, and the power supplied from the voltage source 11_4 to the voltage control circuit 14_2 is 40 μW. The power supplied from the voltage source 11_5 to the voltage control circuit 14_2 is 60 μW. Therefore, the total power supplied from the voltage sources 11_1 to 11_5 to the voltage control circuits 14_1 and 14_2 is 140 μW.

  FIG. 10 is a block diagram illustrating an example of the operation of the power supply circuit according to the comparative example. In the power supply circuit shown in FIG. 10, all voltage sources 111_1 to 111_5 are connected to one voltage control circuit 114. The power supply voltage and output impedance of the voltage sources 111_1 to 111_5 are the same as those of the power supply circuit shown in FIG. When the output voltage of the voltage control circuit 114 is set to 1.5V and the duty ratio of the clock signal supplied to the voltage control circuit is set to 0.91, the input voltage of the voltage control circuit 114 becomes 0.16V.

  At this time, the power supplied from the voltage source 111_1 to the voltage control circuit 114 is 6.5 μW, the power supplied from the voltage source 111_2 to the voltage control circuit 114 is 6.5 μW, and supplied from the voltage source 111_3 to the voltage control circuit 114. The power supplied to the voltage control circuit 114 from the voltage source 111_4 is 38 μW, and the power supplied from the voltage source 111_5 to the voltage control circuit 114 is 55 μW. Therefore, the total power supplied from the voltage sources 111_1 to 111_5 to the voltage control circuit 114 is 128 μW.

  Therefore, when the power supply circuit 1 according to the present embodiment shown in FIG. 9 and the power supply circuit according to the comparative example shown in FIG. 10 are compared, the power supply circuit 1 according to the present embodiment has a power supply according to the comparative example. The input power was improved by about 10% compared to the circuit. The reason for this will be described below.

  The power input to the voltage control circuits 14_1 and 14_2 is maximized when the input voltages Vin_1 and Vin_2 of the voltage control circuits 14_1 and 14_2 are ½ of the power supply voltage (open voltage) of the voltage sources 11_1 to 11_5. In other words, as the input voltages Vin_1 and Vin_2 of the voltage control circuits 14_1 and 14_2 deviate from ½ times the power supply voltage (open voltage) of the voltage sources 11_1 to 11_5 connected to the voltage control circuits 14_1 and 14_2. The power input to the voltage control circuits 14_1 and 14_2 decreases.

  In the power supply circuit according to the comparative example shown in FIG. 10, all voltage sources 111_1 to 111_5 are connected to one voltage control circuit 114. For this reason, among the voltage sources 111_1 to 111_5, there are many voltage sources in which a voltage that is ½ times the power supply voltage and the input voltage (0.16V) of the voltage control circuit 114 are different.

  On the other hand, in the power supply circuit 1 according to the present embodiment shown in FIG. 9, a plurality of voltage control circuits 14_1 and 14_2 are provided, the input voltage Vin_1 of the voltage control circuit 14_1 is set to 0.1 V, and the voltage control circuit 14_2 The input voltage Vin_2 is set to 0.2V. Then, the reference voltage is set to 0.25 V, the voltage sources 11_1 and 11_2 whose power source voltage is lower than the reference voltage are connected to the voltage control circuit 14_1, and the voltage source 11_3 whose power source voltage is equal to or higher than the reference voltage. To 11_5 are connected to the voltage control circuit 14_2. Therefore, among the voltage sources 11_1 to 11_5, it is possible to reduce voltage sources in which a voltage that is ½ times the power supply voltage and the input voltage of the voltage control circuits 14_1 and 14_2 are deviated, and the voltage control circuits 14_1 and 14_2 can be reduced. The power input to can be improved.

  For example, in the power supply circuit according to the present embodiment, the duty ratios of the clock signals CLK_1 and CLK_2 supplied to the voltage control circuits 14_1 and 14_2 may be fixed to a predetermined value.

  In the power supply circuit according to this embodiment, the clock signals CLK_1 and CLK_2 supplied to the voltage control circuits 14_1 and 14_2 may be adjusted according to the power supply voltages of the respective voltage sources 11_1 to 11_5. In this case, the control circuit 18 supplies the clock signals CLK_1 and CLK_2 to be supplied to the voltage control circuits 14_1 and 14_2 according to the monitoring result acquired from the voltage monitor circuit 17 (that is, the power supply voltage of each of the voltage sources 11_1 to 11_5). The duty ratio of each can be adjusted.

  For example, the control circuit 18 may increase the duty ratio of the clock signal CLK_1 supplied to the voltage control circuit 14_1 when the power supply voltages of the voltage sources 11_1 and 11_2 are lowered. Thereby, it can suppress that the output voltage Vout of the voltage control circuit 14_1 falls. Conversely, the control circuit 18 may reduce the duty ratio of the clock signal CLK_1 supplied to the voltage control circuit 14_1 when the power supply voltage of the voltage sources 11_1 and 11_2 rises. Thereby, it is possible to suppress an increase in the output voltage Vout of the voltage control circuit 14_1.

  Although the case where the power supply circuit 1 includes five voltage sources has been described above, the number of voltage sources may be any number as long as it is three or more (that is, N ≧ 3 when the number of voltage sources is N). Become). In the above description, the power supply circuit 1 includes two voltage control circuits. However, the number of voltage control circuits may be any number as long as the number is two or more (that is, the number of voltage control circuits is K). K ≧ 2, where N ≧ K).

<Embodiment 2>
Next, a second embodiment will be described. FIG. 11 is a block diagram of the power supply circuit 2 according to the second embodiment. The power supply circuit 2 according to the present embodiment differs from the power supply circuit 1 described in the first embodiment in that a voltage source switch 22 is provided.

  As shown in FIG. 11, the power supply circuit 2 according to the present embodiment includes a voltage source 21_1 to 21_5, a voltage source switch 22, a voltage source connection switch 23, voltage control circuits 14_1 and 14_2, a voltage source switching circuit 16, a voltage A monitor circuit 17, a clock generation circuit 20, and a control circuit 28 are provided. The power supply circuit 2 supplies power to the load circuit 15. Note that the voltage control circuits 14_1 and 14_2, the voltage source switching circuit 16, the voltage monitor circuit 17, and the clock generation circuit 20 are the same as those in the power supply circuit 1 described in the first embodiment, and thus the same components. Are denoted by the same reference numerals, and redundant description is omitted.

  Each voltage source 21_1 to 21_5 generates power supply voltages V1 to V5. In the power supply circuit 2 according to the present embodiment, the voltage sources 21_1 to 21_5 include the voltage sources 21_2 and 21_4 directly connected to the voltage source connection switch 23 via the wirings 31 and 32, and the voltage source connection switch 23 to the voltage source. The voltage sources 21_1, 21_3, and 21_5 connected via the inter-switch 22 can be classified into two types.

  The voltage sources 21_2 and 21_4 generate power supply voltages V2 and V4, respectively, and output the generated power supply voltages V2 and V4 to the voltage source connection switch 23 and the voltage source switching circuit 16. The voltage sources 21_1, 21_3, and 21_5 generate power supply voltages V1, V3, and V5, and output the generated power supply voltages V1, V3, and V5 to the voltage source switching circuit 16. Since the other configurations and operations of the voltage sources 21_1 to 21_5 are the same as those of the voltage sources 11_1 to 11_5 described in the first embodiment, a duplicate description is omitted.

  The voltage source switch 22 includes voltage source switches SW1 to SW4. The voltage source 21_1 and the voltage source 21_2 are configured to be connectable via a voltage source switch SW1, and the voltage source 21_2 and the voltage source 21_3 are configured to be connectable via a voltage source switch SW2. The voltage source 21_3 and the voltage source 21_4 are configured to be connectable via a voltage source switch SW3, and the voltage source 21_4 and the voltage source 21_5 are configured to be connectable via a voltage source switch SW4.

  In other words, the voltage source switch 22 is configured to connect the i-th (1 ≦ i ≦ N−1) voltage source of the N voltage sources and the i + 1-th voltage source (see FIG. 11). In the example, N = 5). At this time, m voltage sources out of the N voltage sources are directly connected to the voltage source connection switch 23 (m = 2 in the example shown in FIG. 11). Further, N−m voltage sources among the N voltage sources are connected to the voltage source connection switch 23 via the voltage source switch 22.

  The inter-voltage source switch 22 connects the i-th voltage source and the i + 1-th voltage source when the voltage of the i-th voltage source and the voltage of the i + 1-th voltage source are within a predetermined range. For example, the switch 22 between voltage sources connects a voltage source whose voltage is lower than a predetermined reference voltage Vref among the N voltage sources to form a first voltage source group, and among the N voltage sources, A voltage source having a voltage equal to or higher than a predetermined reference voltage Vref is connected to each other to form a second voltage source group.

  For example, in the power supply circuit 2 shown in FIG. 11, when the power supply voltage V1 of the voltage source 21_1 and the power supply voltage V2 of the voltage source 21_2 are lower than the reference voltage Vref, the voltage source switch 22 switches the voltage source switch SW1. The first voltage source group is formed by connecting the voltage source 21_1 and the voltage source 21_2 in an on state (see FIG. 13). At this time, the first voltage source group (the voltage source 21_1 and the voltage source 21_2) is connected to the voltage source connection switch 23 via the wiring 31.

  Further, the voltage source switch 22 connects the voltage sources 21_3 to 21_5 by turning on the voltage source switches SW3 and SW4 when the power supply voltages V3 to V5 of the voltage sources 21_3 to 21_5 are equal to or higher than the reference voltage Vref. Thus, the second voltage source group is formed (see FIG. 13). At this time, the second voltage source group (voltage sources 21_3 to 21_5) is connected to the voltage source connection switch 23 via the wiring 32.

  Note that the voltage source switches SW1 to SW5 can be configured using NMOS transistors, PMOS transistors, and inverters, for example, similarly to the switch SW1_1 of the voltage source connection switch 23 shown in FIG.

  The voltage source connection switch 23 switches the connection state between the first voltage source group (wiring 31) and the second voltage source group (wiring 32) and the voltage control circuits 14_1 and 14_2. That is, in the voltage source connection switch 23, the first voltage source group (wiring 31) is connected to the voltage control circuit 14_1, and the first voltage source group (wiring 31) is connected to the voltage control circuit 14_2. State, and the first voltage source group (wiring 31) is switched between three connection states in which the voltage control circuits 14_1 and 14_2 are not connected. Similarly, in the voltage source connection switch 23, the second voltage source group (wiring 32) is connected to the voltage control circuit 14_1, and the second voltage source group (wiring 32) is connected to the voltage control circuit 14_2. The three connection states, that is, the second voltage source group (wiring 32) is not connected to any of the voltage control circuits 14_1 and 14_2. The configuration of the voltage source connection switch 23 is the same as that of the voltage source connection switch 13 described in the first embodiment (see FIG. 2 and FIG. 3), and thus a duplicate description is omitted.

  In the power supply circuit 2 according to the present embodiment, the control circuit 28 is further configured to control the voltage source switch 22. Since the other configuration and operation of the control circuit 28 are the same as those of the control circuit 18 described in the first embodiment, a duplicate description is omitted.

  Next, the operation of the power supply circuit 2 according to the present embodiment will be described with reference to the timing chart shown in FIG. The power supply circuit 2 according to the present embodiment includes a monitor mode and a normal mode as operation modes. In the normal mode, the voltage source switch 22 and the voltage source connection switch 23 are used to connect at least one of the voltage sources 21_1 to 21_5 to one of the voltage control circuit 14_1 and the voltage control circuit 14_2. In this mode, power is supplied to the load circuit 15. The monitor mode is a mode for monitoring the power supply voltages V1 to V5 of the voltage sources 21_1 to 21_5 using the voltage monitor circuit 17.

  In the monitor mode, when the power supply voltage V1 of the voltage source 21_1 is monitored using the voltage monitor circuit 17, the voltage source 21_1 and the voltage source connection switch 23 are electrically connected with the voltage source switch SW1 turned off. No state. At this time, the other voltage sources 21_2 to 21_5 are connected to any one of the voltage control circuit 14_1 and the voltage control circuit 14_2 as in the normal mode. Therefore, power is supplied to the load circuit 15 even in the monitor mode. The same applies to the voltage source 21_3 and the voltage source 21_5.

  In the monitor mode, when the power supply voltage V2 of the voltage source 21_2 is monitored using the voltage monitor circuit 17, the voltage source switches SW1 and SW2 and the voltage source connection switch are turned off, and the voltage source 21_2 is switched to the voltage monitor circuit 17. Only to be connected with. At this time, power supply to the voltage control circuit 14_1 or the voltage control circuit 14_2 through the wiring 31 is interrupted. On the other hand, power supply to the voltage control circuit 14_1 or the voltage control circuit 14_2 via the wiring 32 is continued. The same applies to the voltage source 21_4.

  Note that the clock signal CLK_1 having a predetermined duty ratio is supplied to the voltage control circuit 14_1, and the clock signal CLK_2 having a predetermined duty ratio is supplied to the voltage control circuit 14_2.

  As shown in FIG. 12, at the timing t11, the voltage source switch 22 and the voltage source connection switch 23 transition from the normal mode to the monitor mode. Next, at timing t12, when the control signal CTR_M1 of the switch SW_M1 (see FIG. 5) included in the voltage source switching circuit 16 becomes high level, the switch SW_M1 is turned on, and the power supply voltage V1 of the voltage source 21_1 is changed to the voltage monitor circuit 17. Is output. At this time, the voltage source switch SW1 is turned off, and the voltage source 21_1 and the voltage source connection switch 23 are not connected.

  The voltage monitor circuit 17 compares the power supply voltage V1 of the voltage source 21_1 with the reference voltage Vref, and outputs a comparison result OUT_M1. For example, when the power supply voltage V1 of the voltage source 21_1 is lower than the reference voltage Vref, the voltage monitor circuit 17 outputs a low level signal as the comparison result OUT_M1. On the other hand, when the power supply voltage V1 of the voltage source 11_1 is equal to or higher than the reference voltage Vref, the voltage monitor circuit 17 outputs a high level signal as the comparison result OUT_M1.

  At timing t13, when the driving clock of the flip-flop FF1 storing the comparison result OUT_M1 becomes high level, the comparison result OUT_M1 (information on the voltage of the voltage source 21_1) is stored in the flip-flop FF1. Thereafter, the control signals CTR_M2 to CTR_M5 sequentially become high level, and the power supply voltages V2 to V5 of the voltage sources 21_2 to 21_5 are compared with the reference voltage Vref as in the case of the voltage source 21_1, and these comparison results OUT_M2 to OUT_M5 are They are stored in flip-flops FF2 to FF5, respectively.

  Thereafter, at timing t14, the voltage source switch 22 and the voltage source connection switch 23 shift from the monitor mode to the normal mode. In the normal mode, the voltage source switch 22 and the voltage source connection switch 23 correspond to the comparison results OUT_M1 to OUT_M5 (that is, information on the voltages of the voltage sources 21_1 to 21_5) stored in the respective flip-flops FF1 to FF5. At least one of the voltage sources 21_1 to 21_5 is connected to one of the voltage control circuits 14_1 and 14_2. Thereby, the state of the power supply voltage of the voltage sources 21_1 to 21_5 monitored in the monitor mode is reflected in the connection state of the voltage source switch 22 and the voltage source connection switch 23.

  Specifically, the voltage source switch 22 is a comparison result between adjacent voltage sources measured by the voltage monitor circuit (that is, comparison results OUT_M1 to OUT_M5 stored in the respective flip-flops FF1 to FF5). , “0” or “1” values) are the same, the switches 22 between these voltage sources are turned on. For example, when the comparison results OUT_M1 and OUT_M2 of the voltage sources 21_1 and 21_2 are the same, the voltage source switch SW1 is turned on. For example, when the comparison results OUT_M3 to OUT_M5 of the voltage sources 21_3 to 21_5 are the same, these voltage source switches SW3 and SW4 are turned on.

  The voltage source connection switch 23 switches the connection state between the first voltage source group (wiring 31) and the second voltage source group (wiring 32) and the voltage control circuits 14_1 and 14_2. For example, the voltage source connection switch 23 connects the first voltage source group (wiring 31) whose comparison results OUT_M1 and OUT_M2 are “0” to the voltage control circuit 14_1. For example, the voltage source connection switch 23 connects the second voltage source group (wiring 32) whose comparison results OUT_M3 to OUT_M5 are “1” to the voltage control circuit 14_2. Thereby, the voltage source whose voltage is lower than the predetermined reference voltage Vref among the voltage sources 21_1 to 21_5 is connected to the voltage control circuit 14_1, and the voltage source whose voltage is equal to or higher than the predetermined reference voltage Vref among the voltage sources 21_1 to 21_5. It can be connected to the voltage control circuit 14_2. Therefore, voltage sources having the same power supply voltage can be connected to the same voltage control circuit.

  After that, at the timing t15, the voltage source switch 22 and the voltage source connection switch 23 transition from the normal mode to the monitor mode again. Thereafter, the operation described above is repeated.

  In addition, when the voltage source connected directly to the voltage source connection switch 23 is not included in the voltage source group formed using the switch 22 between the voltage sources, it is included in the adjacent voltage source group. The switch between the voltage sources with the voltage source being connected (that is, the voltage source directly connected to the voltage source connection switch 23) may be turned on.

  In other words, the switches between the voltage sources among the a-th to b-th (1 ≦ a <b ≦ N) of the N voltage sources are all in the ON state, and the a-th to b-th When the voltage source connected directly to the voltage source connection switch 23 is not included in the voltage sources up to the th, the switch between the voltage sources between the a-1th voltage source and the ath voltage source or A switch between voltage sources between the b-th voltage source and the b + 1-th voltage source may be turned on.

  FIG. 13 is a block diagram illustrating an example of the operation of the power supply circuit 2 according to the present embodiment. In the power supply circuit 2 shown in FIG. 13, the power supply voltage (open voltage) of the voltage source 21_1 is 0.2V, the power supply voltage of the voltage source 21_2 is 0.2V, the power supply voltage of the voltage source 21_3 is 0.3V, and the voltage source 21_4 The power supply voltage is 0.4V, and the power supply voltage of the voltage source 21_5 is 0.5V. The output impedance of each voltage source 21_1 to 21_5 is 1 kΩ.

  Then, the reference voltage Vref is set to 0.25 V, a voltage source whose power source voltage is lower than the reference voltage is connected to the voltage control circuit 14_1, and a voltage source whose voltage source is higher than the reference voltage is voltage controlled. It is assumed that the circuit 14_2 is connected. In this case, the power source voltage of the voltage sources 21_1 and 21_2 is 0.2V, which is lower than the reference voltage 0.25V. Therefore, the voltage source switch SW1 is turned on, and the voltage source connection switch 23 performs voltage control on the wiring 31. Connect to the circuit 14_1. As a result, the voltage sources 21_1 and 21_2 are electrically connected to the voltage control circuit 14_1.

  On the other hand, the power source voltages of the voltage sources 11_3, 11_4, and 11_5 are 0.3V, 0.4V, and 0.5V, respectively, and are higher than the reference voltage 0.25V. Therefore, the voltage source switches SW3 and SW4 are turned on. The voltage source connection switch 23 connects the wiring 32 to the voltage control circuit 14_2. Thereby, the voltage sources 21_3 to 21_5 are electrically connected to the voltage control circuit 14_2.

  Further, the output voltage Vout of the voltage control circuits 14_1 and 14_2 is 1.5V, the duty ratio of the clock signal CLK_1 supplied to the voltage control circuit 14_1 is 0.93, and the duty ratio of the clock signal CLK_2 supplied to the voltage control circuit 14_2. Is set to 0.87, the input voltage Vin_1 of the voltage control circuit 14_1 becomes 0.1V, and the input voltage Vin_2 of the voltage control circuit 14_2 becomes 0.2V.

  At this time, the power supplied from the voltage source 21_1 to the voltage control circuit 14_1 has a potential difference of 0. 0 between the power supply voltage V1 (0.2V) of the voltage source 21_1 and the input voltage Vin_1 (0.1V) of the voltage control circuit 14_1. Since it is 1 V and the current supplied to the voltage control circuit 14_1 is 100 μA (= 0.1 V / 1 kΩ), it becomes 10 μW (= 0.1 V × 100 μA). Similarly, the power supplied from the voltage source 21_2 to the voltage control circuit 14_1 is 10 μW, the power supplied from the voltage source 21_3 to the voltage control circuit 14_2 is 20 μW, and the power supplied from the voltage source 21_4 to the voltage control circuit 14_2 is 40 μW. The power supplied from the voltage source 21_5 to the voltage control circuit 14_2 is 60 μW. Therefore, the total power supplied from the voltage sources 21_1 to 21_5 to the voltage control circuits 14_1 and 14_2 is 140 μW, and the power is efficiently extracted from each of the voltage sources 21_1 to 21_5 for the same reason as in the first embodiment. be able to.

  In particular, in the power supply circuit 2 according to the present embodiment, when the power supply voltages between adjacent voltage sources are within a predetermined range, a voltage source group is formed using the voltage source switch 22 (in other words, Grouping multiple voltage sources). For this reason, the wiring (corresponding to the wirings 31 and 32) on the input side of the voltage source connection switch 23 can be reduced, and the configuration of the voltage source connection switch 23 can be simplified.

  Moreover, it is preferable that the voltage sources directly connected to the voltage source connection switch 23 are arranged equally among the plurality of voltage sources.

  Although the case where the power supply circuit 2 includes five voltage sources has been described above, the number of voltage sources may be any number as long as it is three or more (that is, N ≧ 3 when the number of voltage sources is N). Become). In the above description, the power supply circuit 2 includes two voltage control circuits. However, the number of voltage control circuits may be any number as long as the number is two or more (that is, the number of voltage control circuits is K). K ≧ 2, where N ≧ K).

  Here, assuming that m voltage sources (m is a natural number smaller than N) among N voltage sources are voltage sources directly connected to the voltage source connection switch 23, the number of switches constituting the voltage source connection switch 23 In order to reduce N, K, and m, it is preferable to satisfy (N−1) + (m × K) <N × K.

  Note that when the variation in power supply voltage between adjacent voltage sources is large, the power supply circuit 1 described in Embodiment 1 can be used.

<Embodiment 3>
Next, a third embodiment will be described. In the third embodiment, a configuration example in which the power supply circuit 1 described in the first embodiment is mounted on a semiconductor chip (hereinafter referred to as a chip) will be described. FIG. 14 is a diagram of a configuration example of the power supply circuit according to the third embodiment. As shown in FIG. 14, in the power supply circuit 3 according to the present embodiment, the switches SW1_1 to SW5_1, SW1_2 to SW5_2 (see FIG. 2) constituting the voltage source connection switch 13 on the chip 50, and the voltage source switching circuit 16 The switches SW_M1 to SW_M5 (see FIG. 5), the voltage control circuits 14_1 and 14_2, the voltage monitor circuit 17, and the pads 53 to 58 are arranged. In addition, outside the chip 50, voltage sources 11_1 to 11_5, a first wiring 51, a second wiring 52, a pad 59, and a load circuit 15 are arranged.

  The voltage source 11_1 is connected to a voltage source pad (third pad) 53 using a bonding wire 61. The voltage source pad 53 is connected to the first pad 54 via the switch SW1_1. Here, one end of the switch SW1_1 and the voltage source pad 53, and the other end of the switch SW1_1 and the first pad 54 are connected by an in-chip wiring. The first pad 54 is connected to the first wiring 51 using a bonding wire 62. The same applies to the other voltage sources 11_2 to 11_5 and the other switches SW2_1 to SW5_1. The first wiring 51 is connected to the pad 56 using a bonding wire 64. The pad 56 is connected to the voltage control circuit 14_1 using intra-chip wiring. The voltage control circuit 14_1 is connected to the pad 58 using intra-chip wiring. Here, the first pad 54 is a pad electrically connected to the voltage control circuit 14_1.

  Similarly, the voltage source pad 53 is connected to the second pad 55 via the switch SW1_2. Here, one end of the switch SW1_2 and the voltage source pad 53, and the other end of the switch SW1_2 and the second pad 55 are connected by an in-chip wiring. The second pad 55 is connected to the second wiring 52 using a bonding wire 63. The same applies to the other switches SW2_2 to SW5_2. The second wiring 52 is connected to the pad 57 using a bonding wire 65. The pad 57 is connected to the voltage control circuit 14_2 using an in-chip wiring. The voltage control circuit 14_2 is connected to the pad 58 using intra-chip wiring. Here, the second pad 55 is a pad electrically connected to the voltage control circuit 14_2.

  The voltage source pad 53 is connected to the voltage monitor circuit 17 via a switch SW_M1 constituting the voltage source switching circuit 16. The same applies to the other switches SW_M2 to SW_M5. The pad 58 is connected to the pad 59 using a bonding wire 66. The pad 59 is connected to the load circuit 15. Further, the voltage source pad 53, the first pad 54, the second pad 55, and the pads 56 and 57 are provided at the end portions of the chip 50 on the first and second wirings 51 and 52 side.

  As described above, in the power supply circuit 3 according to the present embodiment, the voltage control circuit 14_1, the voltage control circuit 14_2, and the voltage source connection switches SW1_1 to SW5_1 and SW1_2 to SW5_2 are formed on the same chip. Further, the voltage control circuit 14_1 and the voltage source connection switches SW1_1 to SW5_1 are connected via a first wiring 51 provided outside the chip 50. The voltage control circuit 14_2 and the voltage source connection switches SW1_2 to SW5_2 are connected via a second wiring 52 provided outside the chip 50. Here, the voltage source connection switches SW1_1 to SW5_1 (first switches) are switches for switching the connection between the voltage sources 11_1 to 11_5 and the voltage control circuit 14_1. The voltage source connection switches SW1_2 to SW5_2 (second switches) are switches for switching the connection between the voltage sources 11_1 to 11_5 and the voltage control circuit 14_2.

  The first wiring 51 and the second wiring 52 are wirings arranged outside the chip 50, and have a smaller resistance than wiring inside the chip 50 (in-chip wiring). Therefore, in the power supply circuit 3 according to the present embodiment, wiring for connecting the voltage control circuit 14_1 and the voltage source connection switches SW1_1 to SW5_1, and wiring for connecting the voltage control circuit 14_2 and the voltage source connection switches SW1_2 to SW5_2. Wiring resistance can be reduced.

  FIG. 15 is a diagram illustrating the power supply circuit 103 according to the comparative example. In the comparative example shown in FIG. 15, the first wiring 51 and the second wiring 52 (hereinafter also referred to as “off-chip wirings 51, 52”) shown in FIG. 14 are configured using the on-chip wirings 151, 152. Shows the case. In the power supply circuit 103 shown in FIG. 15, the same components as those of the power supply circuit 3 shown in FIG.

  As shown in FIG. 15, in the power supply circuit 103 according to the comparative example, in-chip wirings 151 and 152 are formed inside the chip 150. The voltage source 11_1 is connected to the voltage source pad 153 using a bonding wire. The voltage source pad 153 is connected to one end of the switch SW1_1, one end of the switch SW1_2, and one end of the switch SW_M1 using a wiring 161. The other end of the switch SW1_1 is connected to the intra-chip wiring 151 using the wiring 162. The other end of the switch SW1_2 is connected to the in-chip wiring 152 using the wiring 163. The other end of the switch SW_M1 is connected to the voltage monitor circuit 17. The same applies to the other voltage sources 11_2 to 11_5, the other switches SW2_1 to SW5_1, and SW_M2 to SW_M5. The voltage control circuit 14_1 is connected to the intra-chip wiring 151 using the wiring 164. The voltage control circuit 14_2 is connected to the in-chip wiring 152 using the wiring 165.

  In the comparative example shown in FIG. 15, in order to reduce the wiring resistance of the in-chip wirings 151 and 152 (in order to make the wiring resistance comparable to that of the outside-chip wirings 51 and 52 shown in FIG. 14), , 152 needs to be thick (for example, 1 mm or more). For this reason, if the in-chip wirings 151 and 152 are provided inside the chip 150, the chip area increases. Therefore, in this embodiment, as shown in FIG. 14, it is preferable to use the off-chip wirings 51 and 52, and thereby the chip area can be greatly reduced.

  In the power supply circuit 3 according to the present embodiment, the voltage source pad 53, the first pad 54, and the second pad 55 may be arranged as shown in FIG. That is, each pad is arranged in two rows so that two voltage source pads 53 are connected to one first pad 54, and two voltage source pads 53 are connected to one second pad 55. May be connected. At this time, the voltage source connection switches SW1_1 to SW5_1 and SW1_2 to SW5_2 are provided between the pads. In addition, each pad is connected using an in-chip wiring.

  Thus, by arranging each pad as shown in FIG. 16, two voltage source pads 53 share one first pad 54 and one second pad 55. Since this is possible, the number of pads can be reduced.

  Further, in the power supply circuit 3 according to the present embodiment, the voltage source pad 53, the first pad 54, and the second pad 55 may be arranged as shown in FIG. That is, each pad may be arranged in two rows and further arranged in a staggered manner. At this time, the respective voltage source pads 53 are arranged in the first row, and the first and second pads 54 and 55 are arranged in the second row. The connection state of each pad shown in FIG. 17 is the same as that shown in FIG. Also in this case, the voltage source connection switches SW1_1 to SW5_1 and SW1_2 to SW5_2 are provided between the pads. In addition, each pad is connected using an in-chip wiring.

  By arranging the pads as shown in FIG. 17, the lateral length occupied by each pad can be shortened. Further, by arranging the pads in a staggered manner, it is possible to suppress the bonding wires connected to the pads from interfering with each other.

  For example, when the number of voltage sources is large (for example, eight), each pad may be arranged as shown in FIG. That is, each pad is arranged in two rows, and further, four voltage source pads 53 are connected to one first pad 54, and four voltage source pads are connected to one second pad 55. 53 may be connected. Also in this case, the voltage source connection switch is provided between the pads. In addition, each pad is connected using an in-chip wiring.

  Thus, by arranging each pad as shown in FIG. 18, the four voltage source pads 53 share one first pad 54 and one second pad 55. As a result, an increase in the number of pads can be suppressed.

<Embodiment 4>
Next, a fourth embodiment will be described. In the fourth embodiment, a power supply system using the power supply circuits 1 to 3 described in the first to third embodiments, specifically, the power supply circuits 1 to 3 described in the first to third embodiments are mounted on a semiconductor chip. A configuration example of the energy harvesting system will be described.

  FIG. 19 is a block diagram illustrating an example of a power supply system according to the present embodiment. As illustrated in FIG. 19, the power supply system according to the present embodiment includes antennas 71_1 to 71_5, RF-DC conversion circuits 72_1 to 72_5, a power supply circuit 73, and a load circuit 15. The antennas 71_1 to 71_5 and the RF-DC conversion circuits 72_1 to 72_5 correspond to the voltage sources 11_1 to 11_5 described in Embodiments 1 to 3. The power supply circuit 73 corresponds to the power supply circuits 1 to 3 described in the first to third embodiments (except for the voltage sources 11_1 to 11_5).

  The antennas 71_1 to 71_5 receive radio waves in a predetermined frequency band, and output received AC signals to the RF-DC conversion circuits 72_1 to 72_5. The antennas 71_1 to 71_5 are configured to receive radio waves in a frequency band (that is, a frequency band with high energy) often used in an environment where the power supply system is placed. The antennas 71_1 to 71_5 may be configured to receive radio waves in a single frequency band, or may be configured to receive radio waves in a plurality of frequency bands.

  The RF-DC conversion circuits 72_1 to 72_5 are provided so as to correspond to the antennas 71_1 to 71_5, convert AC signals received by the antennas 71_1 to 71_5 into DC signals, and convert the DC signals to the power supply circuit 73. Output.

  The power supply circuit 73 generates a power supply voltage using the power supplied from the RF-DC conversion circuits 72_1 to 72_5 and supplies the power supply voltage to the load circuit 15. The power supply circuit 73 can be configured using a semiconductor chip 74. Note that the configuration and operation of the power supply circuit 73 are the same as those of the power supply circuits 1 to 3 described in the first to third embodiments, and thus detailed description thereof is omitted.

  In the energy harvesting technology, generally, not the radio wave energy transmitted toward the antennas 71_1 to 71_5, but radio wave energy radiated from a radio tower or a mobile phone base station toward an unspecified number is collected. Therefore, in order to collect more energy, radio waves in commonly used frequency bands such as radio waves in the frequency band of mobile phones, radio waves in the frequency band of wireless LAN, and radio waves in the frequency band of digital terrestrial broadcasting are used. It is preferable to use an antenna that can receive signals.

  FIG. 20 is a diagram illustrating an example of power collected by the antennas 71_1 to 71_5, and illustrates a relationship between the output voltage and the output power of the RF-DC conversion circuit. In the example illustrated in FIG. 20, a case where a 200 MHz band antenna is used as the antenna 71_1, a 500 MHz band antenna is used as the antennas 71_2 and 71_3, and an 800 MHz band antenna is used as the antennas 71_4 and 71_5.

  The intensity of radio wave energy in each frequency band varies depending on the location and time. For this reason, the situation where the intensity of the radio wave energy in each frequency band is almost the same is rare. For example, the antenna outputs for the 200 MHz band, the 500 MHz band, and the 800 MHz band are -14 dBm, -20 dBm, and -26 dBm, respectively. The relationship between the output voltage and output power of the RF-DC conversion circuit is as shown in FIG.

  For example, when the voltage control circuit has one input (see FIG. 10), the outputs of all the RF-DC conversion circuits 72_1 to 72_5 are supplied to one voltage control circuit, and the RF-DC conversion circuits 72_1 to 72_5 If all outputs are 0.2V, as shown in FIG. 20, the power that can be recovered from the RF-DC conversion circuits 72_2 and 72_3 in the 500 MHz band is maximized. However, the output power of the 200 MHz band RF-DC conversion circuit 72_1 does not become maximum (indicated by reference numeral 78). Further, in the 800 MHz band RF-DC conversion circuits 72_4 and 72_5, the output power decreases due to the influence of the leakage current (indicated by reference numeral 79). Therefore, in this case, the power supplied from the RF-DC conversion circuits 72_1 to 72_5 to one voltage control circuit is only about 14 μW.

  On the other hand, when the power supply circuits 1 to 3 described in Embodiments 1 to 3 are used, for example, the 200 MHz band RF-DC conversion circuit 72_1 is connected to the voltage control circuit 14_2 (see FIG. 1) to 0.3 V. The 500 MHz band RF-DC conversion circuits 72_2 and 72_3 are connected to the voltage control circuit 14_1 and operated at 0.2 V, and the 800 MHz band RF-DC conversion circuits 72_4 and 72_5 are connected to the voltage control circuits 14_1 and 14_2. By not connecting to either, power of about 20 μW can be recovered.

  In the power supply system shown in FIG. 19, the case where the antennas 71_1 to 71_5 and the RF-DC conversion circuits 72_1 to 72_5 are provided as voltage sources has been described. However, in this embodiment, thermoelectric elements and solar cells are used instead. It is good also as a structure provided with. Thermal energy can be recovered by using a thermoelectric element. Moreover, light energy can be recovered by using a solar cell.

  Further, as shown in FIG. 21, a plurality of types of voltage sources may be used in combination as the voltage source. FIG. 21 shows an example in which antennas 71_1 to 71_3, thermoelectric element 75, and solar cell 76 are used in combination as voltage sources. In this way, by combining multiple types of voltage sources, energy (radio wave energy and thermal energy) can be recovered from other inputs even when specific energy (light energy) cannot be recovered, such as in a dark place. can do.

  Further, when a plurality of types of voltage sources are used in combination, the output voltage varies depending on the intensity of radio wave energy, thermal energy, and light energy, for example. However, in this embodiment, a plurality of voltage control circuits 14_1 and 14_2 (see FIG. 1) are provided, and the voltage control circuits 14_1 and 14_2 to be connected are switched according to the output voltage obtained from each energy source. . Therefore, energy can be efficiently recovered from each energy source.

  Further, in the present embodiment, as shown in FIG. 22, an MCU (Micro Controller Unit) 82 driven by the power supply circuit 73 is mounted on the semiconductor chip 81, and the load circuit 15 is used using the control signal 83 output from the MCU 82. May be controlled. By adopting such a configuration, it is possible to perform finer control over the load circuit 15 such as stopping the operation of the load circuit 15 when the output voltage of the power supply circuit 73 is low.

  In this embodiment, as shown in FIG. 23, a power switch circuit 92 that controls power supply to the load circuit 15 and a switch control circuit 93 that controls the power switch circuit 92 are mounted on the semiconductor chip 91. Also good. The switch control circuit 93 outputs a control signal 94 to the power switch circuit 92 when the output voltage of the power circuit 73 is equal to or higher than a certain level (more than the operating voltage of the load circuit 15). When the control signal 94 is supplied, the power switch circuit 92 connects the power circuit 73 and the load circuit 15 so that power is supplied to the load circuit 15.

  With such a configuration, power supply to the load circuit 15 can be started after the output voltage of the power supply circuit 73 becomes equal to or higher than a certain level (more than the operating voltage of the load circuit 15). Therefore, even when the consumption current of the load circuit 15 is large below the operation guarantee voltage, the load circuit 15 can be stably started.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1, 2, 3 Power supply circuits 11_1 to 11_5 Voltage source 13 Voltage source connection switches 14_1 and 14_2 Voltage control circuit 15 Load circuit 16 Voltage source switching circuit 17 Voltage monitor circuit 18 Control circuit 19 Reference voltage generation circuit 20 Clock generation circuits 21_1 to 21_5 Voltage source 22 Voltage source switch 23 Voltage source connection switch 28 Control circuit 31, 32 Wiring 50 Chip 51 First wiring 52 Second wiring 53 Voltage source pad 54 First pad 55 Second pads 56, 57, 58, 59 Pads 61, 62, 63, 64, 65, 66 Bonding wires 71_1 to 71_5 Antennas 72_1 to 72_5 RF-DC conversion circuit 73 Power supply circuit 74 Semiconductor chip 75 Thermoelectric element 76 Solar cell 81 Semiconductor chip 82 MCU
83 control signal 91 semiconductor chip 92 power switch circuit 93 switch control circuit 94 control signal

Claims (2)

N voltage sources (N ≧ 3);
First and second voltage control circuits for boosting the input voltage;
A voltage source connection switch for connecting at least one of the N voltage sources to any one of the first and second voltage control circuits;
A switch between voltage sources capable of connecting the i-th (1 ≦ i ≦ N−1) voltage source of the N voltage sources and the i + 1-th voltage source;
A method for controlling a power supply circuit comprising:
A first step of monitoring the voltages of the N voltage sources;
According to the value of the monitored voltage, the switch between the voltage sources connects a voltage source whose voltage is lower than a predetermined reference voltage among the N voltage sources to form a first voltage source group. A second step of:
According to the value of the monitored voltage, the switch between the voltage sources connects the voltage sources having a voltage equal to or higher than a predetermined reference voltage among the N voltage sources to form a second voltage source group. A third step;
A fourth step in which the voltage source connection switch connects the first voltage source group to the first voltage control circuit and connects the second voltage source group to the second voltage control circuit;
A method for controlling a power supply circuit.   2. The method of controlling a power supply circuit according to claim 1, wherein the voltages of the N voltage sources are monitored by comparing the voltages of the N voltage sources with the predetermined reference voltage. 3.

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