JP2018046451A - Array antenna device and array antenna system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an array antenna device and array antenna system for monitoring a deviation between reception signals output from a plurality of channels.SOLUTION: An array antenna device 1 includes: a reference timing signal generation unit 50 for generating a reference timing signal; a plurality of channels for generating reception data S(Rx)-1 to N obtained by processing signals received by respective antenna elements 10-1 to N individually at signal processing units 20-1 to N before A/D conversion boards 30-1 to N performing A/D conversion and insertion of time stamps on the processed signals; a beam synthesis unit 40 for performing beam synthesis on the basis of the reception data from the plurality of channels to output a reception beam; a logical OR circuit that performs logical OR of the time stamps of the plurality of channels to generate reference signals showing time deviation amounts between the time stamps; and an input/output unit 60 for outputting a generated reference signal together with a time stamp selected by an external monitoring device 100 to the monitoring device.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to an array antenna device and an array antenna system.

  An array antenna apparatus having a plurality of channels including an antenna and a receiving circuit is known. The array antenna apparatus may include a signal generator that generates timing signals in order to synchronize received signals output from a plurality of channels. The timing signal generated by the signal generation device is supplied to each reception circuit via a signal line connecting the signal generation device and a plurality of reception circuits, and a distributor.

  In this type of array antenna apparatus, as the number of channels increases, it is necessary to distribute more timing signals to each receiving circuit, and therefore there is a tendency that the deviation between the received signals increases. In some cases, the increase in the number of channels makes it difficult to monitor the deviation between the received signals.

JP2013-242151A

  The problem to be solved by the present invention is to provide an array antenna device and an array antenna system capable of monitoring a shift between received signals output from a plurality of channels.

  The array antenna apparatus according to the embodiment includes a signal generation unit, a plurality of channels, a synthesis unit, an OR circuit, and an output unit. The signal generation unit generates a reference timing signal. The plurality of channels include an antenna, a signal processing circuit, and an A / D conversion unit. The signal processing circuit processes a reception signal generated by the antenna. The A / D conversion unit converts the signal processed by the signal processing circuit to generate a bit string of a serial signal, and based on the timing of the reference timing signal supplied from the signal generation unit to the bit string Insert time stamp and output. The synthesis unit synthesizes a reception beam based on serial signals respectively output from the plurality of channels. The logical sum circuit calculates a logical sum of the time stamps included in the plurality of serial signals output by the plurality of A / D conversion units. The output unit outputs a result calculated by the OR circuit to an external device.

The figure which shows an example of the array antenna apparatus 1 of embodiment. The figure which shows an example of the clock signal CLK and reference | standard timing signal SYSREF in embodiment. The block diagram which shows an example of the structure which distributes the clock signal CLK and the reference timing signal SYSREF which are output from the reference timing signal generation part 50 of embodiment. The block diagram which shows an example of the A / D conversion board | substrate 30 in embodiment. The figure which shows an example of the A / D converter 310 of embodiment. The figure which shows an example of the reception data S (Rx) output by the A / D converter 310 of embodiment. The figure which shows the relationship between a some reference signal and OR output output from OR circuit 102 of embodiment in embodiment. The figure which shows the relationship between several time stamp TS, OR output output from OR circuit 324a of embodiment, and the output of the multiplexer circuit 324b in embodiment. The flowchart which shows an example of the procedure of the process which determines the abnormality of the reference signal in the N A / D conversion board | substrates 30 of embodiment. 6 is an exemplary flowchart illustrating an example of a processing procedure for determining an abnormality of a time stamp TS in the M A / D converters 310 according to the embodiment.

  Hereinafter, an array antenna device and an array antenna system of an embodiment will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of an array antenna system according to an embodiment. The array antenna system includes, for example, an array antenna device 1 and a management terminal device 100. The array antenna device 1 and the management terminal device 100 are connected so as to be able to transmit and receive data. The array antenna device 1 and the monitoring device 100 are connected via a signal cable, for example. The array antenna device 1 and the monitoring device 100 may be connected via a wired communication network or a wireless communication network.

  The array antenna apparatus 1 includes, for example, a plurality of antenna elements 10-1,... 10-N, a plurality of received signal processing units 20-1,. digital) conversion boards 30-1,... 30-N, a beam synthesis unit 40, a reference timing signal generation unit 50, and a control unit 60. N is an arbitrary natural number. Hereinafter, when the antenna element is not distinguished from other antenna elements, it is described as “antenna element 10”. Further, when the received signal processing unit is not distinguished from other received signal processing units, it is described as “received signal processing unit 20”. When the A / D conversion board is not distinguished from other A / D conversion boards, it is described as “A / D conversion board 30”. In the following description, one antenna element 10, a reception signal processing unit 20 that processes a reception signal generated by the antenna element 10, and an A / D converter 310 in the A / D conversion board 30, The description will be made assuming that the channels are the same.

  In addition, the array antenna apparatus 1 of embodiment receives the electromagnetic wave radiated | emitted in space. The array antenna apparatus 1 may include a transmission / reception switch and a transmission circuit, and may have a function of radiating radio waves into space in response to a transmission signal supplied from the transmission circuit.

  The antenna element 10 receives a radio wave radiated into space and generates a reception signal. The antenna element 10 supplies the generated reception signal to the reception signal processing unit 20. The reception signal processing unit 20 includes signal processing circuits such as a limiter, a band pass filter, an amplifier, and a phase shifter. The signal processing unit 20 limits the signal level of the received signal using a limiter. The bandpass filter suppresses unnecessary signal components included in the received signal. The amplifier amplifies the amplitude of the reception signal that has passed through the reception band-pass filter. The phase shifter changes the phase of the received signal to a desired phase. The phase shift of the phase shifter is set for each antenna element 10.

  The A / D conversion board 30 performs A / D conversion processing on the reception signal supplied from the reception signal processing unit 20. The A / D conversion boards 30-1 to 30-N output the received data S (Rx) -1 to S (Rx) -N subjected to the A / D conversion process to the beam combining unit 40. The array antenna apparatus 1 may perform reception processing such as orthogonal demodulation processing and digital down conversion in addition to A / D conversion processing before beam combining.

  The beam combining unit 40 is supplied with received signals S (Rx) -1 to S (Rx) -N from a plurality of A / D conversion boards 30. The beam combining unit 40 performs beam combining based on a plurality of received data and outputs a received beam.

  The reference timing signal generator 50 generates a clock signal CLK and a reference timing signal SYSREF. FIG. 2 is a diagram illustrating an example of the clock signal CLK and the reference timing signal SYSREF in the embodiment. The clock signal CLK is a timing signal serving as a reference for operating the A / D conversion board 30. The reference timing signal SYSREF is information for outputting received data in which a plurality of A / D conversion boards 30 are synchronized, such as CPI (Coherent Processing Interval) and PRI (PRI: Pulse Repetition Interval).

  FIG. 3 is a block diagram showing an example of a configuration for distributing the clock signal CLK and the reference timing signal SYSREF output from the reference timing signal generation unit 50. A distributor 52 and N distributors 54 are connected to the reference timing signal generator 50. The distributor 52 is connected to the reference timing signal generator 50 through a signal line. The distributor 52 distributes the clock signal CLK and the reference timing signal SYSREF output from the reference timing signal generator 50 to the N A / D conversion boards 30.

  The distributor 54 is provided corresponding to each A / D conversion board 30. The N distributors 54 are connected to the distributors 52 via signal lines, respectively. The distributor 54 distributes the clock signal CLK and the reference timing signal SYSREF distributed by the distributor 52 to M A / D converters 310-1 to 310-M, respectively.

  FIG. 4 is a block diagram illustrating an example of the A / D conversion board 30 in the embodiment. The A / D conversion board 30 includes, for example, M A / D converters 310-1 to 310 -M and a serial signal processing unit 320.

  FIG. 5 is a diagram illustrating an example of the A / D converter 310 according to the embodiment. The A / D converter 310 includes, for example, an A / D conversion unit 312 and a time stamp insertion unit 314. The A / D conversion unit 312 is supplied with the reception signal from the signal processing unit 20, and converts the supplied reception signal into a bit string having a predetermined number of bits based on the clock signal CLK. The A / D conversion unit 312 generates, for example, a 16-bit bit string as the received bit string.

  FIG. 6 is a diagram illustrating an example of reception data S (Rx) output by the A / D converter 310 according to the embodiment. The time stamp insertion unit 314 inserts the time stamp TS into the received bit string converted by the A / D conversion unit 312 based on the reference timing signal SYSREF. The position where the time stamp insertion unit 314 inserts the time stamp TS is set to the bit next to the 13-bit bit string assigned to the received signal, for example, in a 16-bit bit string. The A / D converter 310 determines the timing for inserting the time stamp TS based on the clock signal CLK, and inserts the time stamp TS.

  Returning to FIG. The serial signal processing unit 320 includes, for example, M serial signal interfaces 322-1 to 322 -M and an FPGA (Field-Programmable Gate Array) 324. Hereinafter, the serial signal interface is referred to as “serial signal interface 322” when it is not distinguished from other serial signal interfaces.

  The serial signal interface 322 is an interface circuit that receives a serial signal from the A / D converter 310 and transfers the serial signal to the FPGA 324. The serial signal interface 322 is, for example, a high-speed interface circuit that operates in the GHz band. As the serial signal, an IF such as JESD 204B is often used. The serial signal interface 322 is supplied with received data S (Rx) from a plurality of A / D converters 310, respectively. For example, the serial signal interface 322 supplies the time stamp TS of the received data S (Rx) as a serial signal to the FPGA 324. Further, the M serial signal interfaces 322-1 to 322-M supply a bit string from 0 bits to 13 bits to the beam combining unit 40 as received data.

  The FPGA 324 includes, for example, an OR circuit 324a and a multiplexer circuit 324b. The OR circuit 324a and the multiplexer circuit 324b are realized by FPGA, but are not limited thereto. A part of the OR circuit 324a and the multiplexer circuit 324b may be realized by executing a program stored in a program memory by a processor such as a CPU (Central Processing Unit), for example, LSI (Large Scale Integration), ASIC (ASIC It may be realized by other hardware such as Application Specific Integrated Circuit).

  The OR circuit 324a performs an OR operation on the M time stamps TS supplied from the M serial signal interfaces 322-1 to 322-M. The OR circuit 324a outputs the calculation result to the input / output unit 60. The calculation result of the OR circuit 324a corresponds to a reference signal that represents a temporal deviation amount of the time stamp TS in the A / D conversion board 30. The reference signal is in-circuit information representing the result calculated by the OR circuit 324a in the A / D conversion board 30.

  The multiplexer circuit 324b is supplied with M time stamps TS from the M serial signal interfaces 322-1 to 322-M. The multiplexer circuit 324b selects some time stamps TS among the M time stamps TS. For example, the multiplexer circuit 324b selects some time stamps TS based on a request from the monitoring apparatus 100. The multiplexer circuit 324 b outputs the selected time stamp TS to the input / output unit 60.

  Returning to FIG. The beam combining unit 40 is supplied with N pieces of received data S (Rx) -1 to S (Rx) -N from N pieces of A / D conversion boards 30-1 to 30-N. Each received data includes M received data as serial signals. The beam combining unit 40 combines N × M received data and outputs the combined received data as a received beam to an external device. The external device is, for example, a radio wave analysis device that analyzes radio waves received by the array antenna device 1 based on a reception beam.

  The input / output unit 60 is, for example, a signal output terminal of the array antenna device 1. N reference signals are supplied from the N A / D conversion boards 30 to the input / output unit 60, and the N reference signals are output to the monitoring device 100. The monitoring device 100 is connected to the input / output unit 60. The monitoring device 100 is an information processing device such as a personal computer, for example. The monitoring device 100 is used, for example, by an administrator who manages the array antenna device 1.

  The monitoring device 100 includes, for example, an OR circuit 102, an abnormality determination unit 104, and a presentation unit 106. The OR circuit 102, the abnormality determination unit 104, and the presentation unit 106 are realized, for example, when a processor such as a CPU (Central Processing Unit) executes a program stored in a program memory. Some or all of these functional units may be realized by hardware such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array). It may be realized by cooperation of software and hardware.

  N reference signals are supplied from the input / output unit 60 to the OR circuit 102. The OR circuit 102 performs an OR operation on the N reference signals. The abnormality determination unit 104 determines the abnormality of the array antenna device 1 based on the calculation result by the OR circuit 102 and / or the N reference signals supplied from the input / output unit 60. The presentation unit 106 displays the calculation result of the OR circuit 102 and / or N reference signals using, for example, a display display.

  FIG. 7 is a diagram illustrating a relationship between N reference signals and an OR output output from the OR circuit 102 according to the embodiment. The OR circuit 102 performs an OR operation on the N reference signals (1) to (N). The OR circuit 102 outputs an operation result of “1” when at least one of the N reference signals is “1”. A period in which the output of the OR circuit 102 is “1” represents a period in which the reference signals are shifted from each other. The beginning of the period in which the N reference signals are shifted corresponds to the time when the time stamp TS is first detected in the N A / D conversion boards 30. The end of the period in which the N reference signals are shifted corresponds to the time when the time stamp TS is detected last in the N A / D conversion boards 30.

  FIG. 8 is a diagram illustrating a relationship among a plurality of time stamps TS, an OR output output from the OR circuit 324a, and an output of the multiplexer circuit 324b in the embodiment. FIG. 8 shows a change in the time stamp TS when the number M of A / D converters 310 is eight. The OR circuit 324a performs an OR operation using the N time stamps TS (1) to TS (8). The OR circuit 324a outputs a calculation result of “1” when at least one of the eight time stamps TS is “1”. A period in which the output of the OR circuit 324a is “1” represents a period in which a plurality of time stamps TS are shifted. The beginning of the period in which the eight time stamps TS are shifted corresponds to the time when the eight A / D converters 310 first detect the time stamp TS. The end of the period in which the eight time stamps TS are shifted corresponds to the last time when the eight A / D converters 310 detected the time stamp TS.

  The multiplexer circuit 324b outputs the time stamp TS (8) selected according to the request from the monitoring device 100 to the monitoring device 100. The monitoring apparatus 100 uses the presentation unit 106 to compare and present the reference signal output from the OR circuit 324a and the output of the multiplexer circuit 324b. Thereby, the array antenna apparatus 1 and the monitoring apparatus 100 can present that the time stamp TS (8) is located last in the reference signal. Further, according to the array antenna apparatus 1 and the monitoring apparatus 100, the time stamp TS (7) is positioned approximately in the middle of the reference signal by comparing and presenting the time stamp TS (7) with the reference signal. Can be presented. Furthermore, according to the array antenna device 1 and the monitoring device 100, the time stamp TS (1) is positioned first in the reference signal by comparing and presenting the time stamp TS (1) with the reference signal. Can be presented.

  FIG. 9 is a flowchart illustrating an example of a processing procedure for determining an abnormality of the array antenna device 1 according to the embodiment. First, the monitoring apparatus 100 takes in N reference signals from the N A / D conversion boards 30 (step S100). Next, the OR circuit 102 performs an OR operation on the acquired N reference signals (step S102).

  Next, the abnormality determination unit 104 determines whether or not the period in which the OR operation result is “1” is equal to or greater than the first threshold (step S104). The first threshold value is set based on the amount of deviation between a plurality of reference signals allowed in the array antenna device 1. The abnormality determination unit 104 presents the abnormality of the array antenna device 1 using the presentation unit 106 when the period of “1” of the OR operation result is equal to or greater than the first threshold (step S106). If the period for which the OR operation result is “1” is not equal to or greater than the first threshold, the abnormality determination unit 104 ends the process without presenting the abnormality of the array antenna device 1.

  FIG. 10 is a flowchart illustrating an example of a processing procedure for determining an abnormality of the A / D conversion board 30 according to the embodiment. First, the monitoring apparatus 100 designates one reference signal among N reference signals (step S200). For example, when the abnormality of the array antenna apparatus 1 is presented in the process of determining the abnormality of the array antenna apparatus 1, one reference signal is designated to identify the A / D conversion board 30 that has output the abnormal reference signal. . For example, the monitoring apparatus 100 designates one reference signal based on an operation of the administrator.

  Next, the abnormality determination unit 104 determines whether or not the period during which the value of one designated reference signal is “1” is equal to or greater than the second threshold (step S202). The second threshold value is set based on the deviation amounts of the plurality of time stamps TS allowed in each A / D conversion board 30. The abnormality determination unit 104 presents an abnormality of the A / D conversion board 30 using the presentation unit 106 when the period of “1” of the OR operation result is equal to or greater than the second threshold (step S204). If the period for which the OR operation result is “1” is not equal to or greater than the second threshold, the abnormality determination unit 104 ends the process without presenting the abnormality.

  Next, the monitoring apparatus 100 determines whether an instruction to select any one of the plurality of time stamps TS has been received (step S206). When the monitoring apparatus 100 receives an instruction to select the time stamp TS, the monitoring apparatus 100 acquires the selected time stamp TS (step S208). For example, the monitoring device 100 stores a reference signal fetched from the input / output unit 60 in a storage unit (not shown). The monitoring apparatus 100 acquires a change over a predetermined time of the selected time stamp TS among the time stamps TS from which the reference signal designated in step S200 is generated. The monitoring apparatus 100 presents the change in the acquired time stamp TS using the presenting unit 106 (step S210).

  Note that the monitoring device 100 described above determines an abnormality when the period in which the calculation result of the OR circuit 102 is “1” or the period in which the calculation result of the reference signal is “1” is equal to or greater than the threshold. It is not limited to. The monitoring device 100 may determine the abnormality of the array antenna device 1 when there is a period in which the OR circuit 102 has a calculation result of “1” for a short period of time “0”. Further, the monitoring apparatus 100 may determine the abnormality of the A / D conversion board 30 when there is a period in which the value of the reference signal is “1” and the period becomes “0” for a short time.

  According to the array antenna device 1 of the embodiment described above, the OR circuit 324a that calculates the logical sum of a plurality of time stamps output by the plurality of A / D converters 310 and the result calculated by the OR circuit 324a ( And an input / output unit 60 that outputs a reference signal) to the monitoring device 100. According to the array antenna device 1 of the embodiment, by monitoring the reference signal, it is possible to monitor the deviation between the reception signals output from a plurality of channels.

  In order to determine an abnormality of the time stamp TS, a comparative example is conceivable in which a monitor signal is input to the signal processing unit 20 and an abnormality of received data is determined. However, in this comparative example, a period for temporarily stopping the reception processing of the array antenna apparatus is provided. In contrast, the array antenna device 1 according to the embodiment can detect an abnormality of the time stamp TS without receiving a period for temporarily stopping the reception processing of the array antenna device 1, and can receive radio waves that have always arrived. Thus, radio waves can be analyzed and the reliability of the antenna device can be improved.

  According to the array antenna device 1 of the embodiment, any one of the time stamps TS from which the reference signal is generated can be selected and presented. According to the array antenna device 1 of the embodiment, the position of the time stamp TS in the reference signal can be presented, and the A / D converter 310 that outputs the time stamp TS can be grasped. it can. Thereby, according to the array antenna apparatus 1 of embodiment, it can be determined whether each channel is abnormal among many channels.

  According to the array antenna system of the embodiment, an OR circuit 102 that calculates a logical sum of a plurality of reference signals output from a plurality of A / D conversion boards 30, and a presentation unit that presents a result calculated by the OR circuit 102 106. According to the array antenna system of the embodiment, the amount of deviation between the reference signals can be monitored by monitoring the output of the OR circuit 102. Thereby, according to the array antenna system of the embodiment, it can be determined whether or not there is an abnormality in the entire array antenna apparatus 1.

  According to the array antenna system of the embodiment, it is possible to select and present one of the reference signals that is the source of the OR output of the OR circuit 102. According to the array antenna system of the embodiment, the position of the reference signal among the OR outputs of the OR circuit 102 can be presented, and the A / D conversion board 30 that outputs the reference signal can be grasped. be able to. Thereby, according to the array antenna system of the embodiment, it is possible to determine whether or not each A / D conversion board 30 is abnormal among the plurality of A / D conversion boards 30.

  Furthermore, according to the array antenna system of the embodiment, by presenting the position of the time stamp TS in the reference signal output from the A / D conversion board 30 having an abnormality, the inside of the A / D conversion board 30 having the abnormality Thus, it is possible to determine which time stamp TS the A / D converter 310 that has output is abnormal. Thereby, according to the array antenna system of an embodiment, it can be judged whether each channel is abnormal among many channels.

  Furthermore, according to the array antenna device 1 of the embodiment, based on the reference signal, it is determined whether the period in which the value of the reference signal is “1” exceeds the first predetermined period, and the value of the reference signal is When the period of “1” exceeds the first predetermined period, an abnormality is determined. Thereby, according to array antenna device 1 of an embodiment, A / D conversion board 30 provided with A / D converter 310 which has abnormality among a plurality of A / D converters 310 can be determined.

  Furthermore, according to the array antenna system of the embodiment, whether or not the period during which the OR output value is “1” exceeds the second predetermined period based on the calculation result of the OR circuit 102 for a plurality of reference signals. An abnormality is determined when the period in which the value of the OR output is “1” exceeds the second predetermined period. Thereby, according to the array antenna system of the embodiment, it is determined whether or not there is an A / D conversion board 30 including the A / D converters 310 that are abnormal in the plurality of A / D conversion boards 30. it can. In other words, according to the embodiment, it is possible to determine whether or not there is an abnormality in the received signal shift in the entire array antenna apparatus 1.

  According to at least one embodiment described above, the reference timing signal generator 50 and the received signal are converted to generate a serial signal bit string, and a time stamp is inserted into the bit string based on the timing of the reference timing signal. OR circuit 324a for calculating the logical sum of a plurality of channels including A / D converters 310 to be output and time stamps included in the plurality of serial signals output by the plurality of A / D converters 310, and an OR circuit By having the input / output unit 60 that outputs the result calculated by 324a to the monitoring device 100, the result calculated by the OR circuit 324a can be presented to the administrator of the array antenna device 1 or the like. Thereby, according to at least one embodiment, it is possible to monitor the deviation between the reception signals output from a plurality of channels by causing the manager of the array antenna apparatus 1 to present the deviation of the reception signals. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Array antenna apparatus, 10 ... Antenna element, 30 ... A / D conversion board, 40 ... Beam synthetic | combination part, 50 ... Reference | standard timing signal generation part, 52, 54 ... Divider, 60 ... Input / output part, 100 ... Monitoring apparatus DESCRIPTION OF SYMBOLS 102 ... OR circuit 104 ... Abnormality determination part 106 ... Presentation part 310 ... A / D converter 310, 312 ... A / D conversion part 312, 314 ... Time stamp insertion part, 320 ... Serial signal processing part, 322 ... Serial signal interface, 324 ... FPGA, 324a ... OR circuit, 324b ... Multiplexer circuit

Claims (9)

A signal generator for generating a reference timing signal;
A plurality of channels including an antenna, a signal processing circuit, and an A / D converter,
The signal processing circuit processes a reception signal generated by the antenna;
The A / D conversion unit converts the signal processed by the signal processing circuit to generate a bit string of a serial signal, and based on the timing of the reference timing signal supplied from the signal generation unit to the bit string Insert time stamp and output,
Multiple channels,
A combining unit that combines the received beams based on the serial signals output from the plurality of channels;
A logical sum circuit for calculating a logical sum of the time stamps included in the plurality of serial signals output by the plurality of A / D converters;
An output unit for outputting a result calculated by the OR circuit to an external device;
An array antenna apparatus comprising: The output unit outputs information indicating a temporal shift amount between the plurality of time stamps as a result of calculation by the OR circuit.
The array antenna apparatus according to claim 1. The plurality of channels include a plurality of circuit boards including a plurality of the A / D conversion units,
The OR circuit corresponds to each of the circuit boards, and performs an OR operation on the time stamps included in the plurality of serial signals respectively output from the plurality of A / D conversion units provided on the circuit board. Calculate each
The output unit includes a plurality of output terminals for outputting in-circuit information representing results calculated by the OR circuit to the external device, respectively.
The array antenna apparatus according to claim 1 or 2. And a selection unit that selects any one of the time stamps included in the plurality of serial signals output from the plurality of A / D conversion units based on a request received from the external device. ,
The output unit outputs the time stamp selected by the selection unit to the external device;
The array antenna device according to any one of claims 1 to 3. The array antenna device according to any one of claims 1 to 4,
The external device;
An array antenna system comprising: The external device includes a presentation unit that presents information representing a temporal shift amount between the plurality of time stamps based on the result output by the output unit.
The array antenna system according to claim 5. The external device determines, based on a result calculated by the OR circuit, whether or not a period in which the result calculated by the OR circuit is a first predetermined value exceeds a first predetermined period. An abnormality determination unit that determines an abnormality of the A / D conversion unit when a period in which the result calculated by the OR circuit is the first predetermined value exceeds the first predetermined period;
The array antenna system according to claim 5 or 6. The external device further includes a logical sum operation unit that performs a logical sum based on the plurality of pieces of in-circuit information output from the plurality of output terminals.
The array antenna system according to claim 5 or 6. The external device determines whether a period in which a result calculated by the OR circuit is a second predetermined value exceeds a second predetermined period, and the result calculated by the OR circuit is the first value. An abnormality determination unit that determines an abnormality of the array antenna device when a period that is a predetermined value of 2 exceeds the second predetermined period;
The array antenna system according to claim 8.

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