JP2018043485A - Laser driver and laser printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique advantageous for improvement of image quality and reduction in cost of a laser driver.SOLUTION: A laser driver is for driving a light-emitting device for generating laser beam. The laser driver includes a signal generation section which generates a signal for driving the light-emitting device as an output signal on the basis of an input signal to be an analog signal. The signal generation section has a transistor, receives the input signal at a control terminal of the transistor and amplifies the input signal. The signal generation section is configured so that the output signal includes a signal component proportional to the amplified signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a laser driver and a laser printer.

  A laser printer, which is an electrophotographic recording apparatus, includes, for example, a light emitting element that generates laser light, a photosensitive member, and a polygon mirror for causing the photosensitive member to scan the laser light. The polygon mirror is rotated at a constant rotation speed, thereby reflecting the laser beam from the light emitting element and scanning the surface of the photoreceptor. For this reason, the scanning speed (moving speed of the light spot) may differ depending on where the irradiation position of the laser beam (that is, the light spot) is located on the surface of the photosensitive member. Specifically, the scanning speed in the end area on the surface of the photoconductor is faster than the scanning speed in the center area on the surface of the photoconductor.

  Some laser printers further include an fθ lens which is a lens having fθ characteristics in order to keep the scanning speed constant regardless of the position of the light spot on the surface of the photoreceptor. However, such a laser printer causes an increase in size and cost of the apparatus. Therefore, a technique for configuring a laser printer without using an fθ lens is required.

JP-A-2006-511 JP 2005-262509 A

  When the fθ lens is not used, the scanning speed changes depending on the position of the light spot on the surface of the photoconductor. Therefore, when the light intensity of the laser light is constant (fixed value), the irradiation amount (light intensity time) of the photoconductor surface with the laser light (Integrated value) varies depending on the position of the light spot. For this reason, a non-uniform dot density distribution is formed on the surface of the photoconductor, and specifically, the dot density decreases as the distance from the center area (closer to the edge) is reached. Causes a drop.

  Here, Patent Document 1 discloses a laser driver that reduces the light intensity in the central region of the photoreceptor surface and increases the light intensity in the end region. Specifically, a preset input voltage (digital signal) is converted from digital to analog (DA conversion) to generate a current (analog signal) for driving the light emitting element. However, according to Patent Document 1, it is necessary to provide a digital / analog converter (DAC) for realizing the DA conversion with high accuracy in the laser driver, which is a cause of an increase in circuit scale and associated cost. It can be.

  Patent Document 2 discloses a laser driver that adjusts the signal level of a drive signal for driving a light emitting element by using an input signal for PWM (pulse width modulation). Specifically, by adjusting the duty ratio (H level period in the pulse cycle) of the input signal (digital signal) and generating a drive signal having a signal level based on the input signal using a low-pass filter, the drive signal The signal level can be adjusted. However, according to Patent Document 2, it is necessary to provide a high-precision low-pass filter and an adjustment circuit for adjusting the duty ratio in the laser driver, which causes an increase in circuit scale and associated cost. sell.

  An object of the present invention is to provide a technique advantageous in improving the quality of an image and reducing the cost of a laser driver.

  One aspect of the present invention relates to a laser driver, and the laser driver is a laser driver for driving a light emitting element that generates laser light, and drives the light emitting element based on an input signal that is an analog signal. A signal generation unit that generates a signal for output as an output signal, the signal generation unit including a transistor, receiving the input signal at a control terminal of the transistor, amplifying the input signal, and the signal generation unit Is characterized in that the output signal includes a signal component proportional to the amplified signal.

  According to the present invention, it is advantageous for improvement of image quality and cost reduction of a laser driver.

The figure for demonstrating an example of a structure of a laser printer. The figure for demonstrating an example of a structure of a laser driver. The figure for demonstrating an example of the circuit structure of a laser driver. The figure for demonstrating an example of the circuit structure of a laser driver. The figure for demonstrating the waveform of an input signal, and the waveform of an output signal. The figure for demonstrating an example of the circuit structure of a laser driver. The figure for demonstrating the example of a part of circuit structure of a laser driver.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Each drawing is only described for the purpose of explaining the structure or configuration, and the dimensions of the illustrated members do not necessarily reflect actual ones. Moreover, in each figure, the same reference number is attached | subjected to the same member or the same component, and description is abbreviate | omitted about the overlapping content hereafter.

  FIG. 1 is a schematic diagram for explaining a mechanism of a portion that realizes a recording function in a configuration of a laser printer (an electrophotographic recording apparatus or an apparatus that has an auxiliary electrophotographic recording function) 1. It is. The laser printer 1 includes, for example, a laser driver 100, a light emitting element 11, a photoconductor 12, a polygon mirror 13, an optical system 14, a collimator lens 15, a sensor 16, and a lens 17.

  The light emitting element 11 is a semiconductor laser (laser diode), and the laser driver 100 drives the light emitting element 11 to generate laser light L. The laser light L from the light emitting element 11 is shaped by the collimator lens 15, then reflected by the polygon mirror 13, passes through the optical system 14, and is irradiated onto the surface of the photoreceptor 12.

  The polygon mirror 13 has, for example, a hexagonal shape having six reflecting surfaces 13a on the side surfaces. The laser light L from the light emitting element 11 is reflected toward the optical system 14 on the reflection surface 13a. The polygon mirror 13 rotates in the direction D at a constant rotation speed, and the reflection direction of the reflected light L on the reflection surface 13a differs depending on the direction of the reflection surface 13a (that is, the rotation angle of the polygon mirror 13). .

  The optical system 14 includes a lens for guiding the reflected light L from the polygon mirror 13 to the photosensitive member 12, but in the present embodiment, in order to reduce the cost, a lens having an fθ characteristic (fθ lens) is not included. To do. Alternatively, in other embodiments, the optical system 14 itself may not be arranged.

  With such a configuration, the reflected light L from the polygon mirror 13 scans the surface of the photoconductor 12 along the main scanning direction MSD as the polygon mirror 13 rotates in the direction D. The polygon mirror 13 may take another polygonal shape such as a quadrangle, for example.

  Along with the scanning of the reflected light L in the main scanning direction MSD, the photoconductor 12 is rotated in the sub-scanning direction SSD, so that the surface of the photoconductor 12 has a potential distribution corresponding to the irradiation amount of the laser light L. Formed (latent image). Thereafter, colored powder adheres to the surface of the photoreceptor 12 according to the potential distribution (development), and recording (image formation, printing) is realized by transferring it to a recording medium such as paper.

  The sensor 16 and the lens 17 are elements for determining the driving start timing of the light emitting element 11 in one scan (one scan in the main scanning direction MSD). Specifically, the lens 17 condenses the reflected light L from the polygon mirror 13, and the condensed light L is detected by the sensor 16, thereby determining the driving start timing of the light emitting element 11. For example, a synchronization signal is generated in response to detection of the light L by the sensor 16, and drive control of the light emitting element 11 in one scan is started.

  The above-described elements (laser driver 100, light emitting element 11, photoconductor 12, polygon mirror 13, optical system 14, collimator lens 15, sensor 16, lens 17, etc.) for scanning the surface of the photoconductor 12 with light L are as follows. These may be collectively referred to as the optical scanning device 10 or the like.

  Here, since the fθ lens is not used in the optical system 14, the moving speed (scanning speed) of the irradiation position (that is, the light spot) of the laser light L on the surface of the photoconductor 12 in the main scanning direction MSD is not constant. That is, the scanning speed is different between the central area and the edge area in the main scanning direction MSD on the surface of the photoconductor 12, and specifically, the scanning speed in the edge area is faster than the scanning speed in the central area. Therefore, when the light intensity (light quantity per unit time) of the laser light L is constant (fixed value), the irradiation amount (time integrated value of the light intensity) of the surface of the photoconductor 12 by the laser light is the center in the end region. It will be smaller than the area. This results in a non-uniform density distribution of dots (the smallest unit area that can be expressed by recording) on the surface of the photoreceptor 12 (specifically, the density of the dots decreases as the distance from the central area decreases), and the image May cause the quality of the product to deteriorate.

here,
V _MIN : scanning speed in the central area,
P _MIN : Light intensity of the laser beam L in the central region,
V _MAX : scanning speed in the end region,
P _MAX : The light intensity of the laser beam L in the end region. At this time,
P _MAX = P _MIN × {1+ (V _MAX −V _MIN ) / V _MIN }
Is good (Formula 1). In this (Equation 1), since the scanning speed V _MAX is higher than the scanning speed V _MIN in the central region in the end region, the light intensity P _MAX of the laser light L in the end region is correspondingly increased. It shows that the light intensity P _MIN of the laser light L in the central region is made larger. In addition, this (Formula 1) considers description (for example, paragraph 0094) of patent document 1 (Unexamined-Japanese-Patent No. 2006-511) of a prior art document. In addition, the above (Equation 1) will be discussed using an equation for explanation here, but an inequality of V _MAX > V _MIN × {1+ (V _MAX −V _MIN ) / V _MIN } may be used. .

here,
θ: scanning angle (in the example of FIG. 1, the rotation angle of the polygon mirror 13),
B: Scanning characteristic coefficient (coefficient based on the configuration of the optical system 14 in the example of FIG. 1)
And θ = 0 indicates the case where the irradiation position of the laser light L is in the central region, and θ = | θ _MAX | indicates the case where the irradiation position of the laser light L is in the end region. At this time, from the above (formula 1),
P _MAX = P _MIN × (1 + tan ² (Bθ)); θ → | θ _MAX |
(Equation 2).

The development from the (formula 1) to the (formula 2) can be made in consideration of the following. First, a line (axis) coinciding with the reflected light L when θ = 0 is taken as the optical axis,
Y: Image height (amount of deviation of the light spot from the optical axis),
K: Image formation coefficient at the on-axis image height
Y = (K / B) × tan (Bθ)
It can be expressed. Differentiating both sides of this equation by θ,
(DY / dθ) = K / (cos ² (Bθ))
It can be expressed. Here, K is the velocity (dY / dθ (θ = 0)) at the on-axis image height, and when both sides of the above equation are divided by K = dY / dθ (θ = 0),
(DY / dθ) / K = 1 / (cos ² (Bθ))
It becomes. If you add “-1” to both sides,
{(DY / dθ) / K} −1 = 1 / (cos ² (Bθ)) − 1
= Tan ² (Bθ)
It becomes. Here, in θ = | θ _MAX |, (dY / dθ) = V _MAX and K = dY / dθ (θ = 0), that is, K = V _MIN .
V _MAX / V _MIN −1 = tan ² (Bθ); θ → | θ _MAX |
Thus, (Equation 1) to (Equation 2) are obtained.

Furthermore, when (Equation 2) is developed by the tailor,
P _MAX ≈P _MIN × (1+ (Bθ) ² ); θ → | θ _MAX |
(Equation 3). In this equation expansion, the terms after (Bθ) ⁴ are very small and therefore approximate to 0.

The above (Equation 3) indicates that the light intensity P _MAX of the laser light L in the end region should be increased by quadratic function approximation starting from the light intensity P _MIN of the laser light L in the central region. That is, the laser driver 100 may drive the light emitting element 11 so that the light intensity of the laser light L increases with a quadratic function approximation as the irradiation position of the laser light L becomes farther from the central region of the surface of the photoreceptor 12. Therefore, it can be said that the quality of the image can be improved.

  In the following, a laser driver 100 that is advantageous for improving image quality and reducing costs will be described with reference to several embodiments.

(First embodiment)
The laser driver 100 according to the first embodiment will be described with reference to FIGS. 2, 3 (a), and 3 (b). As shown in FIG. 2, the laser driver 100 includes a signal generation unit 110, receives an input signal SIG1 that is an analog signal, and generates an output signal SIG2 that is another analog signal based on the input signal SIG1. The output signal SIG2 is a drive signal for driving the light emitting element 11. In the present embodiment, the signal generation unit 110 includes a first circuit unit 111 and a second circuit unit 112.

  In this specification, an analog signal is a signal having any signal level (signal value) within a predetermined range, and can be fixed to any signal level within the predetermined range. Say. Therefore, the analog signal does not necessarily have to be fixed at a specific signal level, but may be fixed to the target value as necessary.

  The first circuit unit 111 has, for example, a MOS transistor, and receives the input signal SIG1 at its gate to amplify the input signal SIG1. Then, the first circuit unit 111 generates a first signal SIG1A including a signal component that is proportional to the amplified signal (may be equal to the magnification). The second circuit unit 112 superimposes the signal SIG1A and the reference signal (DC signal component) and outputs an output signal SIG2. Specifically, the second circuit unit 112 outputs a signal (or a signal corresponding thereto) having a signal level obtained by adding the signal level of the signal SIG1A and the signal level (fixed value) of the reference signal as an output signal. Output as SIG2.

  FIG. 3A shows one example of the circuit configuration of the laser driver 100 according to the present embodiment. In this example, the laser driver 100 includes a MOS transistor M11 that forms a P-type channel, and MOS transistors M12 and M13 that form an N-type channel. In the description of the circuit configuration of this example, “N-type” and “P-type” are only polarities, and these are “first conductivity type” and “second conductivity” which are opposite conductivity types. It may be described in “type”. In this specification, the first conductivity type is N-type and the second conductivity type is P-type. However, the above-described circuit may be configured so that these polarities are reversed (first conductivity type). May be P-type, and the second conductivity type may be N-type).

  The MOS transistor M11 corresponds to the first circuit unit 111, and the MOS transistors M12 and M13 correspond to the second circuit unit 112. The MOS transistors M11 and M12 are arranged in series on a path between the first power supply node (ground node) VSS and the second power supply node VDD (> VSS). Specifically, for the MOS transistor M11, the input signal SIG1 is input to the gate, the source is connected to the power supply node VDD, and the drain is connected to the node n11. In this example, the input signal SIG1 is a voltage signal.

  The source of the MOS transistor M12 is connected to the power supply node VSS, and the drain and gate are connected to the node n11. The node n11 is supplied with the reference current Iref from the current source CS0. That is, the MOS transistor M12 is arranged in series with respect to the MOS transistor M11 and the current source CS0 arranged in parallel with each other. As a result, a current obtained by superimposing the drain current Ivar of the MOS transistor M11 and the reference current Iref is supplied to the MOS transistor M12.

  In the MOS transistor M13, the gate is connected to the node n11, the source is connected to the power supply node VSS, and the drain functions as an output terminal (outputs the output signal SIG2). In this example, the output signal SIG2 is a current signal. The MOS transistor M13 forms a current mirror with the MOS transistor M12.

  Therefore, when the driving powers of the MOS transistors M12 and M13 are equal, the current I having the same amount as the current flowing through the MOS transistor M12 flows through the MOS transistor M13. Here, the driving force of a MOS transistor can be generally defined by the ease with which a drain current flows under a predetermined condition. For example, in the case of an NMOS transistor, the driving force is the magnitude of the drain current when the voltage of the power supply node VSS is applied to the source and back gate (bulk) and the voltage of the power supply node VDD is applied to the gate and drain. . Therefore, the case where the above-described MOS transistors M12 and M13 have the same driving force means that their structures are substantially the same. Specifically, the transistor size (ratio of gate width / gate length) and the gate insulating film It shows that the film thickness etc. are equal to each other.

Here, the equation for the current in the saturation region of the MOS transistor is:
I _DS ≈ (β / 2) × (V _GS −V _TH ) ²
I _DS : Drain current (current according to the number of carriers passing between the source and drain)
V _GS : _Potential difference between gate and source V _TH : MOS transistor threshold voltage (conduction voltage)
β: It can be expressed by a constant determined by the gate length, the gate width, the thickness of the gate insulating film, etc. (Formula 4). As can be seen from this (Equation 4), I _DS follows a quadratic function approximation with V _GS as a variable.

  When attention is paid to the MOS transistor M11 in FIG. 3, a drain current Ivar of an amount corresponding to the signal level of the input signal SIG1 flows through the MOS transistor M11, and the drain current Ivar is a secondary having the signal level of the input signal SIG1 as a variable. Follow function approximation. The drain current Ivar corresponds to the signal SIG1A described with reference to FIG.

  A current (Ivar + Iref) obtained by superimposing the drain current Ivar and the reference current Iref flows through the MOS transistor M12. When the driving powers of the MOS transistors M12 and M13 are equal to each other, a current (Ivar + Iref) of the same amount as that of the MOS transistor M12 flows through the MOS transistor M13.

  FIG. 3B is a diagram for explaining input / output characteristics (that is, the relationship between the input signal SIG1 and the output signal SIG2) of the circuit configuration of the laser driver 100 of FIG. As can be seen from FIG. 3B, according to this example, the signal generation unit 10 is configured such that the signal level of the output signal SIG2 follows a quadratic function approximation with the signal level of the input signal SIG1 as a variable. . That is, when the signal level of the input signal SIG1 is changed linearly with time, the signal level of the output signal SIG2 shows a waveform of a quadratic function approximation.

  In other words, focusing on the operation of the MOS transistor M11, the input signal SIG is amplified by the signal amplification action of the MOS transistor M11 capable of source follower operation. Then, the output signal SIG2 is output so as to include a signal component (in this embodiment, the signal SIG1A) that is proportional to the amplified signal (may be equal to the magnification). In this example, this is realized by superimposing the reference current Iref and the current mirror configuration of the MOS transistors M12 and M13. The output signal SIG2 may include a signal component that directly follows the signal SIG1A (that is, it may be a waveform that approximates the quadratic function), and the output signal SIG2 may be a voltage signal or a current signal. May be.

  In this specification, quadratic function approximation means that when the electrical characteristics of a MOS transistor (the same applies to other transistors) are evaluated using a predetermined approximate model, the output signal based on the model equation is used. Any signal level may be used as long as it draws a curve of a quadratic function. Therefore, the output signal is based on a quadratic function multiplied by a predetermined coefficient, a quadratic function added with a constant or a linear function, or a combination thereof.

  As described above, according to the present embodiment, for example, it is not necessary to provide a digital-analog converter in order to generate the output signal SIG2 having a quadratic function approximation waveform, and it is also necessary to use an input signal for pulse width modulation (PWM) Nor. As a result, it is possible to suppress an increase in circuit scale and an accompanying increase in cost. Therefore, according to the present embodiment, the laser driver 100 can be realized with a simple configuration, which is advantageous for cost reduction.

(Second Embodiment)
The laser driver 100 according to the second embodiment will be described with reference to FIGS. 4, 5 (a), and 5 (b). FIG. 4 illustrates an example of a circuit configuration of the signal generation unit 110 ′ included in the laser driver 100 according to the present embodiment. The signal generation unit 110 ′ includes MOS transistors M21 to M24 that form N-type channels and MOS transistors M25 to M29 that form P-type channels. The MOS transistors M21 to M24 form a first translinear circuit (first MOS translinear circuit) 111 ′ corresponding to the first circuit unit 111 described with reference to FIG. The MOS transistors M25 to M28 (and incidentally the MOS transistor M29) form a second translinear circuit (second MOS translinear circuit) 112 ′ corresponding to the second circuit unit 112.

  More specifically, the MOS transistor M21 (first MOS transistor) is arranged so that the source is connected to the power supply node VSS and the gate and drain are both connected to the source of the MOS transistor M22. The MOS transistor M22 (second MOS transistor) is arranged so that the gate and drain are both connected to the first constant current source CS1. The MOS transistor M23 (third MOS transistor) is arranged so that its drain is connected to the first node n21 and its source is connected to the second node n22. Further, a voltage obtained by superimposing the voltage ΔV on the gate voltage of the MOS transistor M22 is supplied to the gate of the MOS transistor M23. The MOS transistor M24 (fourth MOS transistor) is arranged such that the source is connected to the power supply node VSS, and the gate and drain are both connected to the node n22.

  In the present embodiment, the superimposed voltage ΔV is an external input voltage superimposed on the gate voltage of the MOS transistor M22, and corresponds to the input signal SIG1 described with reference to FIG. In other words, the gate voltage of the MOS transistor M22 is a (bias) DC component applied to the superimposed voltage ΔV. The MOS transistors M21 and M22 and the first current source CS1 form a bias circuit for operating the MOS transistor M23 in the saturation region. The size ratio of the MOS transistors M22 and M23 is m: 1 (for example, the gate width of the MOS transistor 22 is m times the gate width of the MOS transistor 23).

  The MOS transistor M25 (fifth MOS transistor) is arranged such that the source is connected to the power supply node VDD, and the gate and drain are both connected to the source of the MOS transistor M26. The MOS transistor M26 (sixth MOS transistor) is arranged so that the gate and drain are both connected to the second constant current source CS2. The MOS transistor M27 (seventh MOS transistor) is arranged so that its source is connected to the node n21, its drain is connected to the node n22, and its gate is connected to the gate and drain of the MOS transistor M26. As can be seen from the figure, the MOS transistor M26 and the MOS transistor M27 form a current mirror (the mirror ratio is m: 1, for example, the gate width of the MOS transistor 26 is m times the gate width of the MOS transistor 27). .) MOS transistor M28 (eighth MOS transistor) is arranged such that the source is connected to power supply node VDD, and the gate and drain are both connected to node n21. Note that the constant current sources CS1 and CS2 both provide a current amount Iref.

  The MOS transistor M29 (the ninth MOS transistor) is arranged so that the source is connected to the power supply node VDD, the gate is connected to the node n21, and the drain is a terminal for outputting the output current I. As can be seen from the figure, the MOS transistor M29 forms a current mirror with the MOS transistor M28 (the mirror ratio is 1: 1). In the present embodiment, the output current I is a drive signal supplied to the light emitting element 11, and corresponds to the output signal SIG2 described with reference to FIG.

  That is, in this embodiment, the current of the MOS transistor M23 that has received the voltage ΔV that is the input signal and the reference current of the MOS transistor M27 are superimposed, and the current I that is the output signal is output by the MOS transistor M29. It has become.

In the above description, the elements 111 ′ and 112 ′ are expressed as translinear circuits. However, in this specification, “translinear circuit (MOS translinear circuit)” satisfies the following two assumptions (conditions). To do.
A plurality of MOS transistors arranged so as to form a certain closed loop are arranged in the order of gate and source in the clockwise direction (CW direction) and in the order of gate and source in the counterclockwise direction (CCW direction). Are equal to each other.
The plurality of MOS transistors forming the closed loop operate in the saturation region under the condition that an appropriate voltage is applied (follow the operation region of (Equation 4) exemplified in the first embodiment). .)

  The above circuit configuration will be described in detail below.

と表せる（式５）。 First Case First, consider the case where the superimposed voltage ΔV = 0 (the case where the gate voltages of the MOS transistors M22 and M23 are equal to each other) as the first case. As described above, the V _GS -I _DS characteristic of the MOS transistor operating in the saturation region follows (Equation 4).

(Equation 5).

が得られる（式６）。上記（式６）の第１式は、トランスリニア回路１１２’のＭＯＳトランジスタＭ２５〜Ｍ２８により形成される閉ループについての関係式である。また、（式６）の第２式は、トランスリニア回路１１１’のＭＯＳトランジスタＭ２１〜Ｍ２４により形成される閉ループについての関係式である。また、定数β_Ｐは、ＰＭＯＳトランジスタについてのβを示し、定数β_Ｎは、ＮＭＯＳトランジスタについてのβを示す。 Using the above (Equation 5), according to Kirchhoff's second law, a relational expression is obtained for each of the translinear circuits 111 ′ and 112 ′.

Is obtained (Equation 6). The first expression of the above (Expression 6) is a relational expression regarding the closed loop formed by the MOS transistors M25 to M28 of the translinear circuit 112 ′. The second expression of (Expression 6) is a relational expression regarding the closed loop formed by the MOS transistors M21 to M24 of the translinear circuit 111 ′. The constant β _P represents β for the PMOS transistor, and the constant β _N represents β for the NMOS transistor.

が得られる（式７）。 Furthermore, according to (Equation 6) above,

Is obtained (Equation 7).

となる（式８）。例えばｍ＝２の場合、出力電流Ｉ＝Ｉｒｅｆである。 Here, when ΔV ′ = 0, a = 0.5, and from the above (Equation 7),

(Equation 8) For example, when m = 2, the output current I = Iref.

が得られる（式９）。なお、例えばｍ＝２の場合、出力電流Ｉ＝０．７２８×Ｉｒｅｆであり、特許文献１（例えば段落００６２〜００６６、図１３）記載の状態（即ち、最軸外像高の輝度を軸上像高の輝度の０．７４倍にした状態）と同等の状態を実現することができる。 Second Case Next, consider the case where the superimposed voltage ΔV << 0 (when the gate voltage of the MOS transistor M23 is sufficiently low and the MOS transistor M23 is off) as the second case. That is, in the second case, the translinear circuit 112 ′ is in an active state, while the translinear circuit 111 ′ is in an inactive state. In this case, since a = 0, based on the first formula of (Formula 7) above,

Is obtained (Equation 9). For example, when m = 2, the output current I = 0.728 × Iref, and the state described in Patent Document 1 (for example, paragraphs 0062 to 0066, FIG. 13) (that is, the brightness of the most off-axis image height is on the axis). A state equivalent to 0.74 times the brightness of the image height) can be realized.

Third Case Finally, consider the case where the superimposed voltage ΔV <0 (the case between the first case and the second case and the MOS transistor M23 is in a weakly on state) as the third case. In the third case, the output current I falls within the range between the above (Formula 8) and (Formula 9).

が得られる（式１０）。上記（式１０）は、出力電流ＩをΔＶ’の２次多項式で表せることを示しており、Ｉについて解くと、

となる（式１１）。ここで、ΔＶ’＝０のときに前述の（式８）が成立することを考慮すると、上記（式１１）は実際には１つの解を有し、即ち、

となる（式１２）。なお、（式１２）及び（式９）から、ΔＶ’＝−Ａ／２のときに両式は等しい。 Solving for variable a based on (Equation 7) above,

Is obtained (Equation 10). The above (Equation 10) shows that the output current I can be expressed by a quadratic polynomial of ΔV ′.

(Equation 11) Here, considering that (Equation 8) holds when ΔV ′ = 0, the above (Equation 11) actually has one solution, that is,

(Equation 12) Note that, from (Expression 12) and (Expression 9), both expressions are equal when ΔV ′ = − A / 2.

  For example, when m = 2, when ΔV ′ is linearly changed with time in the range of −A / 2 ≦ ΔV ′ ≦ 0, the output current I is in the range of 0.728 × Iref ≦ I ≦ Iref. Draw a waveform of approximate quadratic function.

FIG. 5A shows a graph in the case where the superimposed voltage ΔV is linearly changed with time (in addition, ΔV = ΔV ′ / (β _N ) ^1/2 from (Expression 7)). . In the figure, the horizontal axis indicates the time axis t, the vertical axis indicates the superimposed voltage ΔV, the period φ1 indicates a period during which ΔV is linearly reduced (0 ≦ t ≦ T), and the period φ2 indicates that ΔV is linear. Indicates a period (T ≦ t ≦ 2T) to be increased. FIG. 5B shows a waveform of the output current I corresponding to FIG. As can be seen from FIGS. 5A and 5B, when ΔV is changed linearly, the output current I draws a waveform of a quadratic function approximation.

As described above, also according to this embodiment, it is possible to generate an output signal having a waveform of a quadratic function approximation, and the same effects as those of the first embodiment described above can be obtained. Furthermore, according to the present embodiment, _VTH does not exist in (Equation 12), as can be seen by comparing with (Equation 4) shown in the first embodiment with reference to (Equation 12) above. Therefore, the fluctuation amount of the output current I caused by the _VTH fluctuation when the device temperature or the like changes is suppressed. That is, according to the present embodiment, it is less affected by temperature changes or the like than the first embodiment.

(Third embodiment)
A laser driver 100 according to the third embodiment will be described with reference to FIGS. 6 and 7. The present embodiment is mainly different in that a unit 300 that generates a superimposed voltage ΔV (corresponding to an input signal) is added to the circuit configuration of the second embodiment described above.

  FIG. 6 shows an example of the circuit configuration of the signal generation unit 110 ″ included in the laser driver 100 according to the present embodiment. The signal generation unit 110 ″ includes MOS transistors M31 to M39 corresponding to the MOS transistors M21 to M29. In addition to these, switches sw1 and sw2, a capacitor C1, N-channel MOS transistors M310 and M311 and a unit 300 are included.

  The MOS transistors M31 to M34 form a first translinear circuit 111 ". The MOS transistors M35 to M38 (and incidentally the MOS transistor M39) form a second translinear circuit 112".

  The switch sw1 is arranged between the gate of the MOS transistor M32 and the gate of the MOS transistor M33. The capacitor C1 is arranged such that one end is connected to the power supply node VSS and the other end is connected to a node n33 between the switch sw1 and the gate of the MOS transistor M33. A node connecting the gate of the MOS transistor M32 and the switch sw1 is referred to as a node n34.

Unit 300 generates a current for charging / discharging capacitor C1. In the present embodiment, the unit 300 includes a non-inverting input terminal (first input terminal indicated by “+” in the drawing) and an inverting input terminal (second input indicated by “−” in the drawing). A voltage-current converter (transconductance amplifier). The unit 300 can output a current corresponding to the potential difference V _DIFF between the non-inverting input terminal and the inverting input terminal.

Any voltage of the non-inverting input terminal (+) and the inverting input terminal (−) may be high (that is, any state of V _DIFF > 0, V _DIFF <0, and V _DIFF = 0). For example, if the gain of the unit 300 (voltage-current converter) is 1 / R, the unit 300 outputs a current of V _DIFF / R. For example, when V _DIFF > 0, a positive current is output (that is, the capacitor C1 is charged), and when V _DIFF <0, a negative current is output (that is, the capacitor C1 is discharged). To do.)

  The MOS transistor M310 (tenth MOS transistor) is arranged such that the source is connected to the power supply node VSS, and the gate and drain are both connected to the source of the MOS transistor M311. The MOS transistor M311 (eleventh MOS transistor) is arranged so that the gate and drain are both connected to the third constant current source CS3 (current amount Iref). With such a configuration, the gate and drain of the MOS transistor M311 form a reference node nref for providing a constant voltage.

  The size ratio between the MOS transistor M31 and the MOS transistor M310 is 1: 4. The size ratio between the MOS transistor M32 and the MOS transistor M311 is set to m: 4m with the MOS transistor M33 as a reference (1). The amount of current flowing through the MOS transistors M31 and M32 and the amount of current flowing through the MOS transistors M310 and M311 are both the current amount Iref and are equal to each other. On the other hand, the MOS transistors M310 and M311 have a size (that is, driving power) that is four times larger than the MOS transistors M31 and M32, respectively. Therefore, the gate voltage of MOS transistor M311 (voltage of reference node nref) and the gate voltage of MOS transistor M32 (voltage of node n34) are different from each other.

  Here, referring also to FIG. 5 described in the second embodiment, at time t <0, the switch sw1 is in a conductive state (on state), and the capacitor C1 is charged from the current source CS1 via the switch sw1. Is done. Therefore, by time t = 0, the voltage at the node n33 becomes equal to the voltage at the node n34. Thereafter (after t = 0), the switch sw1 is turned off (off state). In the period φ1 (0 ≦ t ≦ T), the switch sw2 connects the inverting input terminal (−) of the unit 300 to the node n34 and connects the non-inverting input terminal (+) to the reference node nref. On the other hand, in the period φ2 (T ≦ t ≦ 2T), the switch sw2 connects the inverting input terminal (−) to the reference node nref and connects the non-inverting input terminal (+) to the node n34. Thereby, the unit 300 can output a negative current (discharge the capacitor C1) in the period φ1 and can output a positive current (charge the capacitor C1) in the period φ2. According to such a configuration, it is possible to realize the superimposed voltage ΔV (corresponding to the input signal) exemplified in FIG.

である（式１３）。即ち、Ｖ_ＤＩＦＦ＜０である。これにより、キャパシタＣ１は放電され、ノードｎ３３の電圧は時間経過と共に線形に下がる。なお、このときの単位時間あたりの該電圧の減少量（波形の傾き）は（Ｖ_ＤＩＦＦ／Ｒ）／Ｃ１である。ここで、期間ＴをＴ＝Ｒ×Ｃ１と設定していれば、期間φ１の終了時（ｔ＝Ｔの時）、ノードｎ３３の電圧低下量（ΔＶ（Ｔ）とする。）は上記（式１３）により、

となる（式１４）。なお、この（式１４）のＡは、第２実施形態の（式１０）のＡと同じである。 More specifically, in the period φ1,

(Equation 13). That is, V _DIFF <0. As a result, the capacitor C1 is discharged, and the voltage at the node n33 decreases linearly with time. At this time, the decrease amount of the voltage per unit time (the slope of the waveform) is (V _DIFF / R) / C1. Here, if the period T is set as T = R × C1, when the period φ1 ends (when t = T), the voltage drop amount (ΔV (T)) of the node n33 is the above (formula). 13)

(Equation 14) Note that A in (Expression 14) is the same as A in (Expression 10) in the second embodiment.

In addition, referring to the rightmost side of (Expression 14) and the definition of ΔV ′ described in (Expression 7), ΔV ′ (T) at time t = T is ΔV ′ (T) = − A / 2. Become. Substituting this into (Equation 12) yields (Equation 9). That is, at t = T, the output current I is expressed by (Equation 9), which is the same as in FIG. Here, the output current I is not affected by the beta _N (see FIG. 5 (b)), specifically, even if there are variations due to the temperature change or the like in the V _TH as well beta _N, the output It can be said that the current I is hardly affected.

である（式１５）。即ち、Ｖ_ＤＩＦＦ＞０であり、これにより、キャパシタＣ１は充電され、ノードｎ３３の電圧は時間経過と共に線形に上がる。 Next, in the period φ2, the unit 300 performs an operation opposite to that in the period φ1 by switching with the switch sw2.

(Equation 15). That is, V _DIFF > 0, whereby the capacitor C1 is charged and the voltage at the node n33 increases linearly with time.

  As described above, ΔV is linearly changed (ΔV is linearly decreased when 0 ≦ t ≦ T, and ΔV is linearly increased when T ≦ t ≦ 2T), and the output current I of the waveform of the quadratic function approximation is obtained. Can be generated.

  FIG. 7 shows an example of the circuit configuration of the unit 300. The unit 300 includes N-type channel MOS transistors M312 and M313, P-type channel MOS transistors M314 and M315, and a switched capacitor SWC. The MOS transistor M312 (the twelfth MOS transistor) is arranged so that the source is connected to the fourth constant current source CS4 and the gate functions as a non-inverting input terminal (+). The MOS transistor M313 (thirteenth MOS transistor) is arranged so that the source is connected to the fifth constant current source CS5 and the gate functions as an inverting input terminal (−). The MOS transistor M314 (fourteenth MOS transistor) is arranged such that the source is connected to the power supply node VDD and the gate and drain are connected to the drain of the MOS transistor M312.

  The MOS transistor M315 (fifteenth MOS transistor) is arranged such that the source is connected to the power supply node VDD and the gate is connected to the gate and drain of the MOS transistor M314. The drain of the MOS transistor M315 is connected to the sixth constant current source CS6 and to the node n33 (the other end of the capacitor C1). Note that the current amounts of the constant current sources CS4 to CS6 are all the current amount Iref2.

The switched capacitor SWC is arranged between the source of the MOS transistor M312 and the source of the MOS transistor M313 so as to act as a load. The switched capacitor SWC includes, for example, a capacitor C2 and a switch sw3, and connects the source of the MOS transistor M312 and the source of the MOS transistor M313 alternately to the capacitor C2 at a predetermined frequency f. Effective load _{R SWC} switched capacitor SWC _is expressed as ^{_{R SWC = (f × C2)}} -1.

The difference between the gate voltage of the gate voltage and the MOS transistor M313 of the MOS transistor M312 is the voltage difference _{V DIFF,} the output current from the unit 300 at this time is _V DIFF _{/ R SWC.} Incidentally, the transconductance of the MOS transistors M312 and M313 (gm) is sufficiently large, for example, it is assumed that _{gm >> (R} ^{SWC) -1.}

The above-described setting of T = R × C1 can be expressed as T = _RSWC × C1 = C1 / (f × C2). Both the capacitors C1 and C2 can be formed on the same semiconductor substrate by a common manufacturing process, whereby the T can be set to a desired value, and the design value (target value) of the T due to manufacturing variation or the like can be set. ) Can be reduced. For example, when the time required for one scan of the laser beam L described with reference to FIG. 1 is 200 [μsec], T = 100 [μsec], and when operating at a frequency f = 1 [MHz] It may be designed so that C1: C2 = 100: 1. Needless to say, the above design example is only an example, and the values of C1, C2, and f can be changed by changing the size ratio of the MOS transistors M312 and M313 and other parameters.

(Other)
In the above, some preferred embodiments have been exemplified, but the present invention is not limited to these examples, and some of them may be changed without departing from the gist of the present invention. For example, other elements (or elements) may be added to the circuit configuration illustrated in each embodiment as necessary, or some of them may be deleted or other elements or two or more elements It may be replaced with an electronic component configured by combining. For example, in each embodiment, the circuit configuration mainly using MOS transistors has been exemplified, but the polarity and conductivity type of elements constituting them may be changed as appropriate, and other types having an amplification function may be used. Transistors (BJT, JFET, IGBT, etc.) may be used.

  For example, another transistor may be used instead of the MOS transistor M11 (FIG. 3). In that case, if the other transistor has an amplification function similar to that of the MOS transistor M11, the signal generator 110 may receive the input signal SIG1 at the control terminal corresponding to the gate of the other transistor. Then, the signal generation unit 110 may be configured to amplify the input signal SIG1 by the other transistor and generate an output signal SIG2 according to the amplified signal.

  For example, the current source CS0 (FIG. 3), the MOS transistor M27 (FIG. 4), and the like are elements (first elements) for superimposing a DC signal component. Also, the MOS transistors M12 (FIG. 3), M28 (FIG. 4), etc. add the signal component indicated by the MOS transistors M11 (FIG. 3), M23 (FIG. 4), etc. that receive the input signal and the DC signal component. Element (second element). Also, the MOS transistors M13 (FIG. 3), M29 (FIG. 4), etc. are elements (third elements) for generating an output signal of quadratic function approximation (in the configuration of the illustrated embodiment, the current is Due to the mirror structure, this output signal is proportional to the signal component represented by the second element). Further, the MOS transistor M26 (FIG. 4) or the like is an element (fourth element) that generates a reference current (DC signal component) (in the configuration of the illustrated embodiment, the first mirror described above has a current mirror structure). A signal component proportional to the DC signal component is generated in the element). Each of these elements may be replaced with other elements having the same function.

  In addition, it is needless to say that each term used in the present specification is merely used for the purpose of describing the present invention, and the present invention is not limited to the strict meaning of the term. The equivalent can also be included.

  1: laser printer, 100: laser driver, 11: light emitting element, 13: polygon mirror, 12: photoconductor.

Claims (17)

A laser driver for driving a light emitting element that generates laser light,
Based on an input signal that is an analog signal, a signal generation unit that generates a signal for driving the light emitting element as an output signal,
The signal generation unit includes a transistor, receives the input signal at a control terminal of the transistor, amplifies the input signal,
The laser driver, wherein the signal generation unit is configured so that the output signal includes a signal component proportional to the amplified signal. A laser driver for driving a light emitting element that generates laser light,
Based on an input signal that is an analog signal, a signal generation unit that generates a signal for driving the light emitting element as an output signal,
The signal driver is configured such that the signal level of the output signal follows a quadratic function approximation using the signal level of the input signal as a variable. The signal generation unit includes a transistor, receives the input signal at a control terminal of the transistor, amplifies the input signal, generates a signal component of the quadratic function approximation, and uses the generated signal component The laser driver according to claim 2, wherein the output signal is generated. The laser driver according to claim 1, wherein the transistor is a MOS transistor, and the laser driver further includes a bias circuit that operates the MOS transistor in a saturation region. The signal generation unit further includes a first element arranged in parallel with the transistor, and a second element arranged in series with the transistor and the first element,
The laser driver according to claim 1, wherein the output signal includes a signal component indicated by the second element. The laser driver according to claim 5, wherein the signal generation unit further includes a third element that generates the output signal so that the output signal is proportional to a signal component indicated by the second element. The laser according to claim 6, wherein the signal generation unit further includes a fourth element that generates a DC signal component and causes the first element to generate a signal component proportional to the DC signal component. driver. The laser driver according to claim 7, wherein each element from the first element to the fourth element is a MOS transistor. The signal generator forms a first translinear circuit composed of a plurality of MOS transistors forming a first conductivity type channel, and a second conductivity type channel having a conductivity type opposite to the first conductivity type. A second translinear circuit composed of a plurality of MOS transistors,
The first translinear circuit generates a signal of the quadratic function approximation,
2. The second translinear circuit outputs the output signal by superimposing the quadratic function approximation signal generated by the first translinear circuit and a reference signal. The laser driver according to claim 1. The signal generation unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor that form a first conductivity type channel, and a conductivity opposite to the first conductivity type. A fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor forming a second conductivity type channel that is a type;
The first MOS transistor is arranged such that a source is connected to a first power supply node, and a gate and a drain are both connected to a source of the second MOS transistor,
The second MOS transistor is arranged such that both the gate and the drain are connected to the first constant current source,
The third MOS transistor has a drain connected to the first node, a source connected to the second node, and a gate having a voltage obtained by superimposing the signal level of the input signal on the gate voltage of the second MOS transistor. Are arranged to be supplied,
The fourth MOS transistor is arranged such that a source is connected to the first power supply node, and a gate and a drain are both connected to the second node.
The fifth MOS transistor is arranged such that the source is connected to the second power supply node, and the gate and the drain are both connected to the source of the sixth MOS transistor,
The sixth MOS transistor is arranged such that the gate and the drain are both connected to the second constant current source,
The seventh MOS transistor is arranged such that a source is connected to the first node, a drain is connected to the second node, and a gate is connected to a gate and a drain of the sixth MOS transistor,
The eighth MOS transistor is arranged such that a source is connected to the second power supply node, and a gate and a drain are both connected to the first node.
The ninth MOS transistor is arranged such that a source is connected to the second power supply node, a gate is connected to the first node, and a drain is a terminal for outputting the output signal. The laser driver according to any one of claims 1 to 4. The signal generator is
A switch disposed between the gate of the second MOS transistor and the gate of the third MOS transistor;
A capacitor having one end connected to the first power supply node and the other end connected to a node between the switch and the gate of the third MOS transistor;
Further comprising
The laser driver according to claim 10, further comprising a unit that generates a current for charging and discharging the capacitor as the input signal. The unit is a voltage-current converter that has a first input terminal and a second input terminal, and outputs a current based on a potential difference between them.
The laser driver further comprises a second switch and a reference node for providing a constant voltage,
The second switch connects the first input terminal to one of the gate of the second MOS transistor and the reference node, and connects the second input terminal to the gate of the second MOS transistor and The laser driver according to claim 11, wherein the laser driver is connected to the other of the reference nodes. The laser driver further includes a tenth MOS transistor and an eleventh MOS transistor forming the first conductivity type channel,
The tenth MOS transistor is arranged such that a source is connected to the first power supply node, and a gate and a drain are both connected to a source of the eleventh MOS transistor,
The laser driver according to claim 12, wherein the eleventh MOS transistor is arranged so that a gate and a drain are both connected to the reference node and to a third constant current source. The driving power of the second MOS transistor and the driving power of the eleventh MOS transistor are different from each other, and the driving power of the first MOS transistor and the driving power of the tenth MOS transistor are different from each other. The laser driver according to claim 13. The unit which is the voltage-current converter includes a twelfth MOS transistor and a thirteenth MOS transistor forming the first conductivity type channel, a fourteenth MOS transistor and a fifteenth MOS transistor forming the second conductivity type channel. Including a MOS transistor and a switched capacitor,
The twelfth MOS transistor has a source connected to a fourth constant current source and a gate arranged to function as the first input terminal.
The thirteenth MOS transistor has a source connected to a fifth constant current source and a gate functioning as the second input terminal.
The fourteenth MOS transistor is arranged such that a source is connected to the second power supply node, and a gate and a drain are connected to a drain of the twelfth MOS transistor,
The fifteenth MOS transistor has a source connected to the second power supply node, a gate connected to the gate and drain of the fourteenth MOS transistor, a drain connected to a sixth constant current source, and the Arranged to be connected to the other end of the capacitor,
15. The switch capacitor according to claim 12, wherein the switched capacitor is arranged to act as a load between a source of the twelfth MOS transistor and a source of the thirteenth MOS transistor. The laser driver according to claim 1. The laser driver according to any one of claims 1 to 15,
The light emitting element;
A photoreceptor,
A laser printer comprising: a polygon mirror for reflecting laser light from the light emitting element driven by the laser driver and scanning the laser light with respect to the surface of the photosensitive member. The laser printer according to claim 16, wherein no fθ lens is provided.

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