JP2018041784A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with suppressed current collapse.SOLUTION: A semiconductor device comprises: a first semiconductor layer formed of a nitride semiconductor on a substrate; a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; an insulating film having an opening formed on the second semiconductor layer; a gate electrode that has a fine gate region formed at the opening of the insulating film, and an overhang region formed on the insulating film around the opening; and an impurity doped region formed at a part of the second semiconductor layer and doped with an impurity element, immediately under an end part at the drain electrode side, of the overhang region of the gate electrode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A nitride semiconductor such as GaN, AlN, InN, or a mixed crystal material thereof has a wide band gap, and is used as a high-power electronic device, a short wavelength light-emitting device, or the like. Among these, as a high-power device, a technique related to a field-effect transistor (FET), in particular, a high electron mobility transistor (HEMT) has been developed (for example, Patent Document 1). ). HEMTs using such nitride semiconductors are used in high power / high efficiency amplifiers, high power switching devices, and the like.

  As a field effect transistor using a nitride semiconductor, there is a HEMT in which GaN is used for an electron transit layer and AlGaN is used for an electron supply layer, and 2DEG (Two--) is generated in the electron transit layer by the action of piezoelectric polarization or spontaneous polarization in GaN. Dimensional Electron Gas) is generated. In such a HEMT, a so-called current collapse phenomenon can be cited as a phenomenon that deteriorates characteristics. Current collapse is a phenomenon in which the drain current decreases and the on-resistance increases in a state where a high voltage is applied. Such current collapse is supposed to occur when electrons are trapped at defects inside the nitride semiconductor, at the interface between the nitride semiconductor and the insulating film, and the concentration of 2DEG is reduced. As one method of suppressing such current collapse, a method of forming a gate electrode in a field plate structure is disclosed. When the gate electrode has a field plate structure, electric field concentration can be reduced, and electrons can be hardly trapped in the vicinity of the gate electrode.

JP 2002-359256 A JP 2010-118556 A JP 2012-231107 A

  However, the current collapse is not sufficiently suppressed only by the gate electrode having the field plate structure, and a semiconductor device having a structure in which the current collapse is further suppressed is demanded.

  According to one aspect of the present embodiment, a first semiconductor layer formed of a nitride semiconductor on a substrate and a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer. A semiconductor layer; a source electrode and a drain electrode formed on the second semiconductor layer; an insulating film having an opening formed on the second semiconductor layer; and the opening of the insulating film. A gate electrode having a fine gate region formed on the insulating film around the opening, and an end on the drain electrode side of the overhang region of the gate electrode An impurity doped region doped with an impurity element formed in a part of the second semiconductor layer is provided immediately below the portion.

  According to the disclosed semiconductor device, current collapse can be sufficiently suppressed in the semiconductor device.

Structure diagram of semiconductor device Structural diagram of semiconductor device according to first embodiment (1) Structural diagram of semiconductor device in first embodiment (2) Structural diagram of semiconductor device according to first embodiment (3) Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Structure diagram of semiconductor device according to third embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing (2) of the manufacturing method of the semiconductor device in 3rd Embodiment Process drawing of the manufacturing method of the semiconductor device in 3rd Embodiment (3) Explanatory diagram of a discretely packaged semiconductor device according to the fourth embodiment Circuit diagram of power supply device according to fourth embodiment Structure diagram of high-power amplifier in fourth embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
A current collapse in a semiconductor device in which the gate electrode has a field plate structure will be described with reference to FIG. In the semiconductor device having the structure shown in FIG. 1, a buffer layer 911, an electron transit layer 921, an electron supply layer 922, and a cap layer 923 are stacked on a substrate 910 by epitaxial growth of a nitride semiconductor. The substrate 910 is made of a semiconductor material such as SiC. The buffer layer 911 is made of AlN, GaN or the like, the electron transit layer 921 is made of i-GaN, the electron supply layer 922 is made of n-AlGaN, and the cap layer 923 is made of n- It is made of GaN. As a result, in the electron transit layer 921, 2DEG 921a is generated in the vicinity of the interface between the electron transit layer 921 and the electron supply layer 922.

  A source electrode 942 and a drain electrode 943 are formed on the electron supply layer 922, and an insulating film 930 is formed on the cap layer 923 between the source electrode 942 and the drain electrode 943. The insulating film 930 has an opening in a region where the gate electrode 941 is formed. The gate electrode 941 is formed on the cap layer 923 in the opening and on the insulating film 930 around the opening. Is formed. The gate electrode 941 is formed by a fine gate region 941a formed immediately above the cap layer 923 and an overhang region 941b called a field plate formed on the insulating film 930 around the opening. .

  In the gate electrode 941 in which such an overhang region 941b is formed, the electric field concentration is alleviated as described above, so that current collapse can be suppressed to some extent. However, the electric field tends to concentrate immediately below the end 941c on the drain electrode 943 side of the overhang region 941b of the gate electrode 941, and electrons are easily trapped in this region. Specifically, the interface between the cap layer 923 and the insulating film 930 immediately below the end 941c on the drain electrode 943 side of the overhang region 941b of the gate electrode 941, the cap layer 923, the cap layer 923, and the electron supply layer 922 Electrons are easily trapped at the interface. When electrons are trapped in these regions, the density of 2DEG 921a decreases, a current collapse phenomenon occurs, and the on-resistance increases.

(Semiconductor device)
Next, the semiconductor device in the first embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 2, a buffer layer 11, an electron transit layer 21, an electron supply layer 22, and a cap layer 23 are stacked on a substrate 10 by epitaxial growth of a nitride semiconductor. Is formed. The substrate 10 is made of a semiconductor material such as SiC. The buffer layer 11 is made of AlN, GaN or the like, the electron transit layer 21 is made of i-GaN, the electron supply layer 22 is made of i-AlGaN or n-AlGaN, and the cap layer 23 Is formed of i-GaN or n-GaN. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22. The electron supply layer 22 may be formed of InAlN or InAlGaN. In this case, a spacer layer may be formed of AlN or the like between the electron transit layer 21 and the electron supply layer 22, and the cap layer 23 may not be formed.

  A source electrode 42 and a drain electrode 43 are formed on the electron supply layer 22, and an insulating film 30 is formed on the cap layer 23 between the source electrode 42 and the drain electrode 43. The insulating film 30 has an opening formed in a region where the gate electrode 41 is formed. The gate electrode 41 is formed on the cap layer 23 in the opening and on the insulating film 30 around the opening. Is formed. The gate electrode 41 is formed by a fine gate region 41a formed immediately above the cap layer 23 and an overhang region 41b called a field plate formed on the insulating film 30 around the opening. . In the present embodiment, the electron transit layer 21 is described as a first semiconductor layer, the electron supply layer 22 is described as a second semiconductor layer, and the cap layer 23 is described as a third semiconductor layer. There is.

  In the present embodiment, a part of the cap layer 23 and the electron supply layer 22 in the region immediately below the end 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41 is doped with an impurity element at a high concentration. An impurity doped region 25 is formed. In other words, the impurity doped region 25 is formed between the gate electrode 41 and the drain electrode 43, and is one of the cap layer 23 and the electron supply layer 22 directly below the end 41 c of the overhang region 41 b of the gate electrode 41 on the drain electrode 43 side. It is formed in the part.

The impurity doped region 25 is doped with an impurity element at a concentration of 2 × 10 ¹⁸ cm ⁻³ or more, for example, 1 × 10 ¹⁹ cm ⁻³ . When the impurity element doped in the impurity doped region 25 is Si, Ge, O, etc., the impurity doped region 25 is n-type, and when it is Mg, C, it is p-type. In the present embodiment, the impurity doped region 25 is doped with an n-type impurity element.

In the case where the electron supply layer 22 is made of n-AlGaN and the cap layer 23 is made of n-GaN, Si is about 1 × 10 ¹⁸ cm ⁻ as an impurity element that becomes n-type. ³ doped. In the present embodiment, the impurity doped region 25 is doped with an impurity element at a concentration higher than the concentration of the impurity element doped in the electron supply layer 22 and the cap layer 23.

  In the region immediately below the end 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41, the impurity doped region 25 formed in a part of the cap layer 23 and the electron supply layer 22 has a high concentration of impurity elements. Conductivity is high because it is doped with. Therefore, even if electrons are trapped between the cap layer 23 and the insulating film 30 immediately below the end 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41, the electrons in the impurity doped region 25 increase or decrease. Only. Therefore, even if the electrons are trapped, the concentration of 2DEG 21a is not affected, so that the occurrence of current collapse is suppressed and an increase in on-resistance can be prevented.

  Further, when the impurity doped region 25 having high conductivity is formed in a part of the cap layer 23 and the electron supply layer 22 immediately below the end 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41, electric field concentration is caused. Since it is relaxed, the potential gradient becomes gentle. For this reason, electrons are not easily trapped.

  The impurity doped region 25 formed in this way is in a floating state because the electric field strength may increase when electrically connected to any one of the gate electrode 41, the source electrode 42, and the drain electrode 43. . The floating state means a state in which the electrode is not connected to an electrode to which a voltage is applied and is floating.

  In the present embodiment, as shown in FIG. 3A, the impurity doped region 25 is only in the cap layer 23 in the region immediately below the end 41c of the overhang region 41b of the gate electrode 41 on the drain electrode 43 side. It may be formed. In addition, as long as it is a region including the region directly under the end 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41, as shown in FIG. You may form widely in a part of layer 23 and the electron supply layer 22. FIG.

  Further, as shown in FIG. 4, the semiconductor device in the present embodiment has a structure in which the insulating film 30 and the gate electrode 41 are formed on the electron supply layer 22 without forming the cap layer 23. May be.

  Further, the substrate 10 can be a substrate formed of sapphire, Si, GaAs, or the like other than SiC. The substrate 10 has conductivity even if it has semi-insulating properties. Or either.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 5A, the buffer semiconductor layer 11, the electron transit layer 21, the electron supply layer 22, and the cap layer 23 are formed by epitaxially growing a nitride semiconductor layer on the substrate 10. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22. The nitride semiconductor layer is formed by epitaxial growth by MOVPE (Metal Organic Vapor Phase Epitaxy). These nitride semiconductor layers may be formed by MBE (Molecular Beam Epitaxy) instead of MOVPE.

  As the substrate 10, for example, a sapphire substrate, a Si substrate, a SiC substrate, or a GaN substrate can be used. In the present embodiment, a SiC substrate is used as the substrate 10. The buffer layer 11 is made of AlGaN or the like, the electron transit layer 21 is made of i-GaN having a thickness of 3 μm, and the electron supply layer 22 is made of i-AlGaN having a thickness of 20 nm. The cap layer 23 is made of i-GaN having a thickness of 5 nm.

Next, as shown in FIG. 5B, impurity doping is applied to a part of the cap layer 23 and the electron supply layer 22 in the region immediately below the end 41c of the overhang region 41b of the gate electrode 41 on the drain electrode 43 side. Region 25 is formed. Specifically, a photoresist is applied on the cap layer 23, and exposure and development are performed by an exposure apparatus to form a resist pattern (not shown) having an opening in a region where the impurity doped region 25 is formed. . Thereafter, Si ions are implanted into a part of the cap layer 23 and the electron supply layer 22 in the opening of the resist pattern. In the present embodiment, in order to form the impurity doped region 25 having a desired impurity concentration at a desired depth, Si ions are implanted while adjusting the dose and acceleration energy. Thereby, an impurity doped region 25 doped with about 1 × 10 ¹⁹ cm ^{−3 of} Si as an impurity element is formed in part of the cap layer 23 and the electron supply layer 22. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like, a protective film (not shown) is formed on the entire surface of the cap layer 23, and a temperature between 600 ° C. and 1400 ° C., for example, 1000 ° C. Then, activation annealing is performed, and thereafter a protective film (not shown) is removed. The protective film formed at this time is formed of SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ or the like.

  Thereafter, although not shown, an element isolation region for isolating elements is formed. Specifically, a photoresist is applied on the cap layer 23, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where an element isolation region is formed. Thereafter, an element isolation region is formed by implanting argon (Ar) ions into the nitride semiconductor layer in the region where the resist pattern is not formed. The element isolation region may be formed by removing a part of the nitride semiconductor layer in a region where the resist pattern is not formed by dry etching such as RIE (Reactive Ion Etching) using a chlorine-based gas. After forming the element isolation region, the resist pattern is removed with an organic solvent or the like.

  Next, as shown in FIG. 6A, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 22. Specifically, a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the cap layer 23 and performing exposure and development by an exposure apparatus. Form. Thereafter, the cap layer 23 in the opening portion of the resist pattern is removed by dry etching such as RIE using a chlorine-based gas, and the electron supply layer 22 is exposed. At this time, a part of the electron supply layer 22 may be removed. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Thereafter, a photoresist is applied on the cap layer 23 and the like again, and exposure and development are performed by an exposure apparatus, whereby a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed. Form. Thereafter, a metal laminated film formed of Ti / Al is formed by vacuum vapor deposition, and then immersed in an organic solvent, whereby the metal laminated film on the resist pattern is removed together with the resist pattern by lift-off. Thereby, the source electrode 42 and the drain electrode 43 are formed by the metal laminated film remaining on the electron supply layer 22. Thereafter, an ohmic contact is established between the source electrode 42 and the drain electrode 43 by performing heat treatment in a nitrogen atmosphere at a temperature between 400 ° C. and 1000 ° C., for example, a temperature of about 550 ° C. The metal laminated film formed of Ti / Al is a film in which a Ti film with a thickness of 20 nm and an Al film with a thickness of 200 nm are laminated, and is formed so that the Ti film is in contact with the electron supply layer 22. .

  Next, as shown in FIG. 6B, an insulating film 30 is formed on the cap layer 23 by plasma CVD (chemical vapor deposition). The insulating film 30 is formed of SiN or the like and has a film thickness of 2 nm to 1000 nm, for example, 100 nm. The insulating film 30 may be formed by ALD (Atomic Layer Deposition) or sputtering.

  Next, as shown in FIG. 7A, an opening 30 a is formed in the region where the gate electrode 41 is formed in the insulating film 30. Specifically, a resist pattern (not shown) having an opening in a region where the fine gate of the gate electrode 41 is formed by applying a photoresist on the insulating film 30 and performing exposure and development by an exposure apparatus. Form. Thereafter, the insulating film 30 in the opening of the resist pattern (not shown) is removed by dry etching such as RIE using a fluorine-based gas, and the cap layer 23 is exposed to form the opening 30a. Thereafter, the resist pattern is removed by dipping in an organic solvent or the like.

  Next, as shown in FIG. 7B, a gate electrode 41 is formed on the cap layer 23 exposed in the opening 30a of the insulating film 30 and on the insulating film 30 around the opening 30a. To do. Specifically, a photoresist is applied on the insulating film 30 and the like, and a resist pattern (not shown) having an opening in a region where the gate electrode 41 is formed is formed by performing exposure and development with an exposure apparatus. To do. Thereafter, a metal laminated film formed of Ni / Au is formed by vacuum vapor deposition, and then immersed in an organic solvent, whereby the metal laminated film on the resist pattern is removed together with the resist pattern by lift-off. Thereby, the gate electrode 41 is formed by the remaining metal laminated film. The formed gate electrode 41 has a fine gate region 41 a formed immediately above the cap layer 23 and an overhang region 41 b formed on the insulating film 30. The gate electrode 41 is formed so that the impurity doped region 25 is located immediately below the end 41c on the drain electrode 43 side of the overhang region 41b. The metal laminated film formed of Ni / Au is a film in which a Ni film having a thickness of 30 nm and an Au film having a thickness of 400 nm are laminated, and the Ni film is formed so as to be in contact with the cap layer 23.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

[Second Embodiment]
Next, a second embodiment will be described. The present embodiment is a manufacturing method for manufacturing the semiconductor device according to the first embodiment by a method different from that of the first embodiment. A method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 8A, the nitride semiconductor layer is epitaxially grown on the substrate 10 to form the buffer layer 11, the electron transit layer 21, the electron supply layer 22, and the cap layer 23. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22.

  Next, as shown in FIG. 8B, an insulating film 30 is formed on the cap layer 23 by plasma CVD. The insulating film 30 is formed of SiN or the like and has a film thickness of 2 nm to 1000 nm, for example, 100 nm.

Next, as shown in FIG. 9A, impurity doping is performed on a part of the cap layer 23 and the electron supply layer 22 in a region immediately below the end 41 c on the drain electrode 43 side of the overhang region 41 b of the gate electrode 41. Region 25 is formed. Specifically, a photoresist is applied on the insulating film 30, and exposure and development are performed by an exposure apparatus to form a resist pattern (not shown) having an opening in a region where the impurity doped region 25 is formed. . Thereafter, Si ions are implanted into a part of the cap layer 23 and the electron supply layer 22 in the opening of the resist pattern. In the present embodiment, ion implantation is performed by adjusting acceleration energy or the like so that Si passes through the insulating film 30 and is doped into part of the cap layer 23 and the electron supply layer 22. Thereby, an impurity doped region 25 doped with about 1 × 10 ¹⁹ cm ^{−3 of} Si as an impurity element is formed in part of the cap layer 23 and the electron supply layer 22. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like, and activation annealing is performed at a temperature between 600 ° C. and 1400 ° C., for example, 1000 ° C.

  Thereafter, although not shown, an element isolation region for isolating elements is formed.

  Next, as illustrated in FIG. 9B, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 22. Specifically, a resist pattern (not shown) having openings in regions where the source electrode 42 and the drain electrode 43 are formed by applying a photoresist on the insulating film 30 and performing exposure and development by an exposure apparatus. Form. Thereafter, the insulating film 30 and the cap layer 23 in the opening portion of the resist pattern are removed by dry etching such as RIE using a fluorine-based gas and a chlorine-based gas as an etching gas, and the electron supply layer 22 is exposed. Thereafter, the source electrode 42 and the drain electrode 43 are formed on the exposed electron supply layer 22.

  Next, as shown in FIG. 10A, an opening 30 a is formed in the region where the gate electrode 41 is formed in the insulating film 30.

  Next, as shown in FIG. 10B, a gate electrode 41 is formed on the cap layer 23 exposed in the opening 30a of the insulating film 30 and on the insulating film 30 around the opening 30a. To do.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

  The contents other than the above are the same as in the first embodiment.

[Third Embodiment]
(Semiconductor device)
Next, a semiconductor device according to a third embodiment will be described with reference to FIG. In the semiconductor device according to the present embodiment, a buffer layer 11, an electron transit layer 21, an electron supply layer 22, and a cap layer 23 are stacked on a substrate 10 by epitaxial growth of a nitride semiconductor. The substrate 10 is made of a semiconductor material such as SiC. The buffer layer 11 is made of AlN, GaN or the like, the electron transit layer 21 is made of i-GaN, the electron supply layer 22 is made of i-AlGaN or n-AlGaN, and the cap layer 23 Is formed of i-GaN or n-GaN. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22.

  A source electrode 42 and a drain electrode 43 are formed on the electron supply layer 22, and an insulating film 30 is formed on the cap layer 23 between the source electrode 42 and the drain electrode 43. The insulating film 30 has an opening formed in a region where the gate electrode 41 is formed. The gate electrode 41 is formed on the cap layer 23 in the opening and on the insulating film 30 around the opening. Is formed. Of the gate electrode 41, a portion formed on the insulating film 30 around the opening becomes an overhang region 41b called a field plate or the like. In the present embodiment, the electron transit layer 21 is described as a first semiconductor layer, the electron supply layer 22 is described as a second semiconductor layer, and the cap layer 23 is described as a third semiconductor layer. There is.

  In the present embodiment, the cap layer 23 and a part of the electron supply layer 22 in the region immediately below the end 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41 are made of conductive material. A portion 125 is formed. The conductive portion 125 is formed by embedding a metal or metal nitride. The metal forming the conductive portion 125 is preferably a metal having a larger work function than a metal having a small work function, such as Ni, Cu, Pt, Au, or Pd. The metal nitride is preferably a nitride of a refractory metal such as TiN, TaN, WN, etc., which is not affected even if a heat treatment or the like is performed in a later step. The melting point of Ti is about 1668 ° C., the melting point of Ta is about 2996 ° C., and the melting point of W is 3410 ° C.

  As in the first embodiment, the semiconductor device in this embodiment can suppress the occurrence of current collapse and prevent an increase in on-resistance. However, the conductive portion 125 is made of a highly conductive metal or the like. Since it is formed, this effect can be made more remarkable. That is, since the conductive portion 125 formed of metal or the like has a lower resistance and higher conductivity than the impurity doped region in which the nitride semiconductor is doped with the impurity element, the above-described effect becomes more remarkable.

  In addition, since the conductive portion 125 is buried immediately below the end portion 41c on the drain electrode 43 side of the overhang region 41b of the gate electrode 41, the thickness of the nitride semiconductor layer in this region is reduced. Few electrons are trapped in the nitride semiconductor layer. For this reason, current collapse caused by trapped electrons is suppressed.

  Further, when the conductive portion 125 is formed of a metal nitride of a refractory metal, since the electron supply layer 22 and the cap layer 23 are formed of the same nitride, the adhesive force in the conductive portion 125 is strong, Increased reliability. Further, even when heat treatment or the like for establishing ohmic contact is performed, when the conductive portion 125 is a refractory metal nitride, the metal element in the conductive portion 125 does not diffuse into the nitride semiconductor layer. And reliability are prevented.

  Note that when the conductive portion 125 is electrically connected to any one of the gate electrode 41, the source electrode 42, and the drain electrode 43, the electric field strength may be increased, and thus is in a floating state.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 12A, a buffer semiconductor layer 11, an electron transit layer 21, an electron supply layer 22, and a cap layer 23 are formed by epitaxially growing a nitride semiconductor layer on the substrate 10. Thereby, in the electron transit layer 21, 2DEG 21 a is generated in the vicinity of the interface between the electron transit layer 21 and the electron supply layer 22.

  Next, as shown in FIG. 12B, Ni is applied to a part of the cap layer 23 and the electron supply layer 22 in the region immediately below the end 41 c on the drain electrode 43 side of the overhang region 41 b of the gate electrode 41. The conductive portion 125 is formed by embedding. Specifically, a photoresist is applied on the cap layer 23, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the conductive portion 125 is formed. Thereafter, a part of the cap layer 23 and the electron supply layer 22 in the opening of the resist pattern is removed by dry etching such as RIE using a chlorine-based gas as an etching gas to form the opening. Thereafter, a Ni film is formed by vacuum deposition or the like and then immersed in an organic solvent, whereby the Ni film on the resist pattern is removed together with the resist pattern by lift-off. As a result, the conductive portion 125 that embeds the cap layer 23 and the electron supply layer 22 is formed by the remaining Ni film. Thereafter, surface polishing by CMP (Chemical Mechanical Polishing) or the like may be performed so that the surfaces of the cap layer 23 and the conductive portion 125 are the same surface. In this embodiment, since the conductive portion 125 is already conductive, activation annealing or the like as in the first embodiment is unnecessary.

  Thereafter, although not shown, an element isolation region for isolating elements is formed.

  Next, as illustrated in FIG. 13A, the source electrode 42 and the drain electrode 43 are formed on the electron supply layer 22.

  Next, as illustrated in FIG. 13B, the insulating film 30 is formed on the cap layer 23.

  Next, as illustrated in FIG. 14A, an opening 30 a is formed in the region where the gate electrode 41 is formed in the insulating film 30.

  Next, as shown in FIG. 14B, the gate electrode 41 is formed on the cap layer 23 exposed in the opening 30a of the insulating film 30 and on the insulating film 30 around the opening 30a. To do.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

  The contents other than the above are the same as in the first embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high-frequency amplifier.

  The semiconductor device according to the present embodiment is a discrete package of the semiconductor device according to the first or third embodiment. The semiconductor device thus discretely packaged will be described with reference to FIG. FIG. 15 schematically shows the inside of a discretely packaged semiconductor device. The arrangement of electrodes and the like are different from those shown in the first or third embodiment. Yes. In this embodiment, the case where one HEMT or UMOS transistor is formed in the semiconductor device in the first or third embodiment may be described.

  First, the semiconductor device manufactured in the first or third embodiment is cut by dicing or the like to form a semiconductor chip 410 such as a HEMT made of a GaN-based semiconductor material. The semiconductor chip 410 is fixed on the lead frame 420 with a die attach agent 430 such as solder. The semiconductor chip 410 corresponds to any one of the semiconductor devices in the first or third embodiment.

  Next, the gate electrode 411 is connected to the gate lead 421 by a bonding wire 431, the source electrode 412 is connected to the source lead 422 by a bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by a bonding wire 433. The bonding wires 431, 432, and 433 are made of a metal material such as Al. In the present embodiment, the gate electrode 411 is a gate electrode pad, and is connected to the gate electrode 41 of the semiconductor device in the first or third embodiment. The source electrode 412 is a source electrode pad, and is connected to the source electrode 42 of the semiconductor device in the first or third embodiment. The drain electrode 413 is a drain electrode pad, and is connected to the drain electrode 43 of the semiconductor device in the first or third embodiment.

  Next, resin sealing with a mold resin 440 is performed by a transfer molding method. In this manner, a discrete device such as HEMT using a GaN-based semiconductor material can be manufactured.

  Next, a power supply device and a high frequency amplifier in the present embodiment will be described. The power supply device and the high-frequency amplifier in the present embodiment are a power supply device and a high-frequency amplifier using any of the semiconductor devices in the first or third embodiment.

  First, the power supply device according to the present embodiment will be described with reference to FIG. The power supply device 460 in this embodiment includes a high-voltage primary circuit 461, a low-voltage secondary circuit 462, and a transformer 463 disposed between the primary circuit 461 and the secondary circuit 462. The primary circuit 461 includes an AC power supply 464, a so-called bridge rectifier circuit 465, a plurality of switching elements (four in the example shown in FIG. 16) 466, a switching element 467, and the like. The secondary side circuit 462 includes a plurality of switching elements (three in the example shown in FIG. 16) 468. In the example shown in FIG. 16, the semiconductor device according to the first or third embodiment is used as the switching elements 466 and 467 of the primary side circuit 461. Note that the switching elements 466 and 467 of the primary circuit 461 are preferably normally-off semiconductor devices. The switching element 468 used in the secondary circuit 462 uses a normal MISFET (metal insulator semiconductor field effect transistor) formed of silicon.

  Next, based on FIG. 17, the high frequency amplifier in this Embodiment is demonstrated. The high frequency amplifier 470 in the present embodiment may be applied to, for example, a power amplifier for a base station of a mobile phone. The high frequency amplifier 470 includes a digital predistortion circuit 471, a mixer 472, a power amplifier 473, and a directional coupler 474. The digital predistortion circuit 471 compensates for nonlinear distortion of the input signal. The mixer 472 mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 473 amplifies the input signal mixed with the AC signal. In the example illustrated in FIG. 17, the power amplifier 473 includes the semiconductor device according to the first or third embodiment. The directional coupler 474 performs monitoring of input signals and output signals. In the circuit shown in FIG. 17, for example, the output signal can be mixed with an AC signal by the mixer 472 and sent to the digital predistortion circuit 471 by switching the switch.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the second semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the gate electrode on the drain electrode side of the overhang region, an impurity doped region doped with an impurity element formed in a part of the second semiconductor layer;
A semiconductor device comprising:
(Appendix 2)
The semiconductor device according to appendix 1, wherein the impurity-doped region has a higher impurity element concentration than the second semiconductor layer.
(Appendix 3)
A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A third semiconductor layer formed of a nitride semiconductor on the second semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the third semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the overhang region of the gate electrode on the drain electrode side, the impurity formed in the third semiconductor layer, or a part of the third semiconductor layer and the second semiconductor layer An impurity-doped region doped with elements;
A semiconductor device comprising:
(Appendix 4)
The semiconductor device according to appendix 3, wherein the impurity doped region has a higher impurity element concentration than the second semiconductor layer and the third semiconductor layer.
(Appendix 5)
The semiconductor device according to any one of appendices 1 to 4, wherein a concentration of the impurity element in the impurity-doped region is 2 × 10 ¹⁸ cm ⁻³ or more.
(Appendix 6)
6. The semiconductor device according to any one of appendices 1 to 5, wherein the impurity element is an n-type impurity element.
(Appendix 7)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the impurity doped region is not connected to any of the gate electrode, the source electrode, and the drain electrode.
(Appendix 8)
The semiconductor device according to any one of appendices 1 to 7, wherein the impurity-doped region is formed between the gate electrode and the drain electrode.
(Appendix 9)
A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the second semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the gate electrode on the drain electrode side of the overhang region, a conductive portion embedded in a part of the second semiconductor layer;
A semiconductor device comprising:
(Appendix 10)
A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A third semiconductor layer formed of a nitride semiconductor on the second semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the third semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the gate electrode on the drain electrode side of the overhang region, the conductive material embedded in the third semiconductor layer or a part of the third semiconductor layer and the second semiconductor layer. And
A semiconductor device comprising:
(Appendix 11)
11. The semiconductor device according to appendix 9 or 10, wherein the conductive portion is made of metal or metal nitride.
(Appendix 12)
11. The semiconductor device according to appendix 9 or 10, wherein the conductive portion is formed of a nitride containing any one of Ti, Ta, and W.
(Appendix 13)
13. The semiconductor device according to any one of appendices 9 to 12, wherein the conductive portion is not connected to any of the gate electrode, the source electrode, and the drain electrode.
(Appendix 14)
14. The semiconductor device according to any one of appendices 9 to 13, wherein the conductive portion is formed between the gate electrode and the drain electrode.
(Appendix 15)
The first semiconductor layer is made of a material containing GaN,
15. The semiconductor device according to any one of appendices 1 to 14, wherein the second semiconductor layer is formed of a material containing any one of AlGaN, InAlN, and InAlGaN.
(Appendix 16)
Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the second semiconductor layer;
Forming an impurity doped region by doping an impurity element in a part of the second semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method of manufacturing a semiconductor device, wherein the impurity doped region is formed immediately below an end portion of the overhang region of the gate electrode on the insulating film on the drain electrode side.
(Appendix 17)
Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer from a nitride semiconductor on the second semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the third semiconductor layer;
Forming an impurity-doped region by doping an impurity element into the third semiconductor layer or a part of the third semiconductor layer and the second semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method of manufacturing a semiconductor device, wherein the impurity doped region is formed immediately below an end portion of the overhang region of the gate electrode on the insulating film on the drain electrode side.
(Appendix 18)
Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a conductive portion by embedding a conductive material in a part of the second semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the second semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method for manufacturing a semiconductor device, wherein the conductive portion is formed immediately below an end portion on the drain electrode side of an overhang region of the gate electrode on the insulating film.
(Appendix 19)
Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer from a nitride semiconductor on the second semiconductor layer;
Forming a conductive portion by embedding a conductive material in the third semiconductor layer or a part of the third semiconductor layer and the second semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the third semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method for manufacturing a semiconductor device, wherein the conductive portion is formed immediately below an end portion on the drain electrode side of an overhang region of the gate electrode on the insulating film.
(Appendix 20)
A power supply device comprising the semiconductor device according to any one of appendices 1 to 11.
(Appendix 21)
An amplifier comprising the semiconductor device according to any one of appendices 1 to 11.

10 substrate 11 buffer layer 21 electron transit layer (first semiconductor layer)
21a 2DEG
22 Electron supply layer (second semiconductor layer)
23 Cap layer 25 Impurity doped region 30 Insulating film 41 Gate electrode 41a Fine gate region 41b Overhang region 41c End portion 42 Source electrode 43 Drain electrode

Claims (10)

A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the second semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the gate electrode on the drain electrode side of the overhang region, an impurity doped region doped with an impurity element formed in a part of the second semiconductor layer;
A semiconductor device comprising: A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A third semiconductor layer formed of a nitride semiconductor on the second semiconductor layer;
A source electrode formed on the second semiconductor layer) and a drain electrode;
An insulating film having an opening formed on the third semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the overhang region of the gate electrode on the drain electrode side, the impurity formed in the third semiconductor layer, or a part of the third semiconductor layer and the second semiconductor layer An impurity-doped region doped with elements;
A semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein the concentration of the impurity element in the impurity-doped region is 2 × 10 ¹⁸ cm ⁻³ or more. A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the second semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the gate electrode on the drain electrode side of the overhang region, a conductive portion embedded in a part of the second semiconductor layer;
A semiconductor device comprising: A first semiconductor layer formed of a nitride semiconductor on a substrate;
A second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer;
A third semiconductor layer formed of a nitride semiconductor on the second semiconductor layer;
A source electrode and a drain electrode formed on the second semiconductor layer;
An insulating film having an opening formed on the third semiconductor layer;
A gate electrode having a fine gate region formed in the opening of the insulating film, and an overhang region formed on the insulating film around the opening;
Immediately below the end of the gate electrode on the drain electrode side of the overhang region, the conductive material embedded in the third semiconductor layer or a part of the third semiconductor layer and the second semiconductor layer. And
A semiconductor device comprising: The first semiconductor layer is made of a material containing GaN,
6. The semiconductor device according to claim 1, wherein the second semiconductor layer is formed of a material containing any one of AlGaN, InAlN, and InAlGaN. Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the second semiconductor layer;
Forming an impurity doped region by doping an impurity element in a part of the second semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method of manufacturing a semiconductor device, wherein the impurity doped region is formed immediately below an end portion of the overhang region of the gate electrode on the insulating film on the drain electrode side. Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer from a nitride semiconductor on the second semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the third semiconductor layer;
Forming an impurity-doped region by doping an impurity element into the third semiconductor layer or a part of the third semiconductor layer and the second semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method of manufacturing a semiconductor device, wherein the impurity doped region is formed immediately below an end portion of the overhang region of the gate electrode on the insulating film on the drain electrode side. Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a conductive portion by embedding a conductive material in a part of the second semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the second semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method for manufacturing a semiconductor device, wherein the conductive portion is formed immediately below an end portion on the drain electrode side of an overhang region of the gate electrode on the insulating film. Forming a first semiconductor layer from a nitride semiconductor on a substrate;
Forming a second semiconductor layer from a nitride semiconductor on the first semiconductor layer;
Forming a third semiconductor layer from a nitride semiconductor on the second semiconductor layer;
Forming a conductive portion by embedding a conductive material in the third semiconductor layer or a part of the third semiconductor layer and the second semiconductor layer;
Forming a source electrode and a drain electrode on the second semiconductor layer;
Forming an insulating film having an opening on the third semiconductor layer;
Forming a gate electrode on the opening of the insulating film and the insulating film around the opening;
Have
The method for manufacturing a semiconductor device, wherein the conductive portion is formed immediately below an end portion on the drain electrode side of an overhang region of the gate electrode on the insulating film.

Images