JP2018037441A - Three-dimensional lamination layer chain type storage device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a three-dimensional lamination layer chain type storage device and manufacturing method therefor, capable of achieving good storage operation by combining a three-dimensional lamination structure with a chain type storage structure.SOLUTION: A recessed part is formed on a plurality of gate electrodes laminated through an interlayer insulation film, using an eaves of the interlayer insulation film. A gate insulation film, a semiconductor channel layer and a memory substance film are sequentially formed at the recessed part, and the semiconductor channel layer is taken as a voltage application electrode for the memory substance film charged into the recessed part.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a three-dimensional stacked chain type memory device and a manufacturing method thereof.

  Non-volatile memories are being developed that can be rewritten at a higher speed than conventional EEPROMs and flash memories and have a significantly larger number of rewrites, aiming at a capacity and speed comparable to DRAMs. As such a nonvolatile memory, FeRAM (Ferroelectric Random Access Memory) using the residual polarization of the hysteresis of the ferroelectric, MRAM (Magnetic Random Access Memory) using the GMR effect as a principle of operation, phase change There is a PCRAM (Phase Change Random Access Memory) using a thermal change of a film, or an RRAM (registered trademark: Resistive Random Access Memory) using a resistance change film using an electric field induced giant resistance change as an operating principle.

  In order to make such a non-volatile memory cell such as PCRAM have a memory capacity comparable to that of a DRAM, it is necessary to achieve high integration. For high integration, it is necessary to miniaturize phase change elements and transistors. However, since lithography is limited, there is a limit to miniaturization. In addition, since the characteristics of the phase change element and the transistor are deteriorated with the miniaturization, there is a problem that the characteristics as designed cannot be obtained. FeRAM, RRAM (registered trademark), and the like also have similar problems.

  As FeRAM, ChainFeRAM (registered trademark) in which a plurality of cells are connected in a chain shape in the horizontal direction has been proposed (see, for example, Patent Document 1). Since the conventional FeRAM requires a plate line in addition to the word line and the bit line, a drive line for driving the plate electrode and a plate decoder circuit for driving the plate line of the selected cell are required. Therefore, miniaturization and high-speed driving are difficult.

  Therefore, in ChainFeRAM (registered trademark), one transistor and one capacitor are connected in parallel to form one cell, which is connected in series to form a chain structure, so that the plate line can be connected to a plurality of cells. Shared. As a result, the cell size can be greatly reduced and the number of plate decoder circuits can be reduced. Further, since the resistance of the shared plate line can be reduced, the time required for driving the plate line is shortened, and the speed can be increased.

  In ChainFeRAM (registered trademark), the cell transistors of the cells in the standby state are all turned on, and only the cell transistors of the cells to be accessed are turned off. When the plate line is driven in this state, a voltage is applied only to the cell to be accessed, and the ferroelectric capacitor data is read out, so that random access is performed. However, since such ChainFeRAM (registered trademark) also has a two-dimensional structure, integration is limited.

  On the other hand, as the PCRAM, a three-dimensional stacked chain type PCRAM in which memory elements are stacked three-dimensionally has been proposed (for example, see Patent Document 2). In a three-dimensional stacked chain type PCRAM, a plurality of gate electrodes are stacked via an interlayer insulating film, a through hole penetrating the stacked body is formed, and a gate insulating film, a channel layer, and a phase change film are sequentially formed on the side wall of the through hole. Laminated. When writing information to the cell, a weak current is passed through the phase change film to change the crystal state of the phase change film.

JP 2001-257320 A JP 2008-160004 A

  Even in the chain type FeRAM, it is conceivable to adopt a three-dimensional structure for higher integration. For example, it is conceivable to replace the phase change film in a three-dimensional stacked chain type PCRAM with a ferroelectric film to make it three-dimensional. However, there is a problem that it does not operate as a memory only by replacing the phase change film with a ferroelectric film, and the circumstances will be described with reference to FIGS.

  FIG. 39 is an explanatory diagram of a cell structure of a three-dimensional stacked chain type memory device, and FIG. 39 (a) is a cross-sectional view of one side of an annular gate structure sandwiching a cylindrical opening of a memory cell of a three-dimensional stacked chain type PCRAM. FIG. 39B is a cross-sectional view of one side of an annular gate structure sandwiching a cylindrical opening of a memory cell when applied to a three-dimensional stacked chain type FeRAM. As shown in FIG. 39A, in the three-dimensional stacked chain type PCRAM, a plurality of gate electrodes 101 are stacked through an interlayer insulating film 102 to form a through hole penetrating the stacked body, and on the side wall of the through hole. A gate insulating film 103, a polycrystalline silicon channel layer 104, and a phase change film 105 are sequentially stacked.

  On the other hand, when applied to a three-dimensionally stacked chain type FeRAM, a plurality of gate electrodes 111 are stacked via an interlayer insulating film 112, a through hole penetrating the stacked body is formed, and a gate insulating film is formed on a sidewall of the through hole. 113, the polycrystalline silicon channel layer 114, and the ferroelectric film 115 are sequentially stacked. Therefore, the phase change film 105 in the memory cell of the three-dimensional stacked chain type PCRAM is simply replaced with the ferroelectric film 115.

  FIG. 40 is an explanatory diagram of the bias state in the operating state of the three-dimensional multilayer chain type FeRAM, FIG. 40 (a) is an explanatory diagram of the standby state, and FIG. 40 (b) is an explanatory diagram of the active state. Note that the upper right diagram in each figure is an equivalent circuit diagram, and the lower right diagram shows the hysteresis characteristics.

As shown in FIG. 40A, in the standby state, the gates of all the transistors are turned on and the polycrystalline silicon channel layer 114 is held at the same potential. As shown in FIG. 40B, in the active state in which one cell is selected, only the transistor of the selected one cell is turned off, V _dd is applied to one end of the polycrystalline silicon channel layer 114, and the other V _ss is applied to the end. At this time, no current flows through the polycrystalline silicon channel layer 114 immediately below the gate electrode 113 of the transistor of one selected cell, so that a voltage is applied to both ends of the ferroelectric layer 115 at that location. However, as is apparent from the figure, since the ferroelectric layer 115 at that location is not sandwiched between electrodes, a sufficient voltage is not applied to both ends of the ferroelectric layer 115 at that location, so that it does not operate as a memory. There's a problem. These problems are not limited to the case where a ferroelectric film is used as a memory material. For example, when a phase change film is used as a memory material, the crystal structure cannot be changed satisfactorily, and when a resistance change film is used, there is a problem that sufficient resistance cannot be changed.

  Therefore, in the present invention, a memory element that requires a structure in which a memory material is sandwiched between opposing electrodes is effectively functioned, and at the same time, these memory elements are stacked three-dimensionally to perform a good memory operation. An object of the present invention is to realize a three-dimensional stacked chain type memory device.

  In one aspect, the three-dimensional stacked chain type memory device includes a plurality of gate electrodes stacked via an interlayer insulating film, a through hole penetrating the interlayer insulating film and the plurality of gate electrodes, and the inside of the through hole. A gate insulating film covering the interlayer insulating film and the exposed portion of the gate electrode; a semiconductor channel layer covering the gate insulating film; and a memory material film covering the semiconductor channel layer. An interlayer insulating film protrudes from the gate electrode and has a periodic recess along a stacking direction of the interlayer insulating film and the gate electrode, the memory material film is filled in the recess, and the semiconductor channel layer is It becomes a voltage application electrode for the memory material film filled in the recess.

  In another aspect, a method of manufacturing a three-dimensional stacked chain type memory device includes a step of stacking a plurality of gate electrode layers with an interlayer insulating film interposed therebetween, and an opening penetrating the interlayer insulating film and the plurality of gate electrode layers. Forming a recess, forming a recess by side etching the gate electrode layer exposed in the opening, and forming a gate insulating film on the exposed surface of the interlayer insulating film and the gate electrode layer in the opening. Forming a semiconductor channel layer on the exposed surface of the gate electrode layer so that a recess is formed in the semiconductor channel layer; and forming the semiconductor channel layer on the exposed surface of the semiconductor channel layer. Forming a memory material film so as to fill the recess.

  As one aspect, it is possible to realize a three-dimensional stacked chain type memory device that performs a good memory operation by combining a three-dimensional stacked structure and a memory structure.

1 is a configuration explanatory diagram of a three-dimensional stacked chain type memory device according to an embodiment of the present invention. It is principal part sectional drawing of the three-dimensional lamination chain type memory device of an embodiment of the invention. 1 is an equivalent circuit diagram of a three-dimensional stacked chain type memory device according to an embodiment of the present invention. It is explanatory drawing of operation | movement of the three-dimensional lamination chain type memory device of an embodiment of the invention. 1 is a schematic perspective view of a three-dimensional multilayer chain type FeRAM according to a first embodiment of the present invention. It is explanatory drawing of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the three-dimensional lamination chain type FeRAM of Example 1 of the present invention. It is explanatory drawing to the middle after FIG. 7 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 8 of the manufacturing process of the three-dimensional lamination chain type FeRAM of Example 1 of the present invention. It is explanatory drawing to the middle after FIG. 9 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after 10 of the manufacturing process of the three-dimensional lamination chain type FeRAM of Example 1 of the present invention. It is explanatory drawing to the middle after FIG. 11 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 12 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 13 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 14 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 15 of the manufacturing process of the three-dimensional lamination chain type FeRAM of Example 1 of the present invention. It is explanatory drawing to the middle of FIG. 16 or subsequent of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 17 of the manufacturing process of the three-dimensional lamination chain type FeRAM of Example 1 of the present invention. It is explanatory drawing to the middle after FIG. 18 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 19 of the manufacturing process of the three-dimensional lamination chain type FeRAM of Example 1 of the present invention. It is explanatory drawing to the middle of FIG. 20 or subsequent of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing after FIG. 21 of the manufacturing process of the three-dimensional laminated chain type FeRAM of Example 1 of this invention. It is explanatory drawing of the three-dimensional laminated chain type FeRAM of Example 2 of this invention. It is principal part sectional drawing of the memory cell part of the three-dimensional lamination chain type FeRAM of Example 3 of the present invention. It is principal part sectional drawing of the memory cell part of the three-dimensional lamination chain type FeRAM of Example 4 of the present invention. It is principal part sectional drawing of the memory cell part of the three-dimensional lamination chain type FeRAM of Example 5 of the present invention. It is a schematic sectional drawing of the three-dimensional lamination chain type FeRAM of Example 6 of the present invention. It is explanatory drawing of the manufacturing process to the middle of the three-dimensional lamination chain type FeRAM of Example 6 of the present invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 28 of the three-dimensional lamination chain type FeRAM of Example 6 of the present invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 29 of the three-dimensional lamination chain type FeRAM of Example 6 of the present invention. It is explanatory drawing of the manufacturing process after FIG. 30 of the three-dimensional lamination chain type FeRAM of Example 6 of the present invention. It is a schematic sectional drawing of the three-dimensional lamination chain type FeRAM of Example 7 of the present invention. It is explanatory drawing of the manufacturing process to the middle of the three-dimensional lamination chain type FeRAM of Example 7 of the present invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 33 of the three-dimensional lamination chain type FeRAM of Example 7 of the present invention. It is explanatory drawing of the manufacturing process until the middle of FIG. 34 or subsequent of the three-dimensional lamination chain type FeRAM of Example 7 of the present invention. It is explanatory drawing of the manufacturing process after FIG. 35 of the three-dimensional lamination chain type FeRAM of Example 7 of the present invention. It is explanatory drawing of the three-dimensional laminated chain type PCRAM of Example 8 of this invention. It is explanatory drawing of the three-dimensional lamination chain type RRAM of Example 9 of this invention. It is explanatory drawing of the cell structure of a three-dimensional lamination chain type memory device. It is explanatory drawing of the bias state in the operation state of three-dimensional laminated chain type FeRAM.

  Here, with reference to FIG. 1 thru | or FIG. 4, the three-dimensional lamination | stacking chain type memory device of embodiment of this invention is demonstrated. FIG. 1 is an explanatory diagram of a configuration of a three-dimensional stacked chain type memory device according to an embodiment of the present invention. An upper diagram is a schematic sectional view of a memory cell unit, and a lower diagram is a capacitor unit surrounded by a broken line in the upper diagram. FIG. As shown in the upper diagram, a plurality of gate electrodes 1 are stacked with an interlayer insulating film 2 interposed therebetween, and an opening 3 penetrating the interlayer insulating film 2 and the plurality of gate electrodes 1 is formed. A gate insulating film 5, a semiconductor channel layer 6, and a memory material film 7 are provided so as to cover the exposed portion of the interlayer insulating film 2 and the gate electrode 1 in the opening 3. At this time, in the opening 3, the interlayer insulating film 2 protrudes from the gate electrode 1 to form a periodic recess 4 along the stacking direction of the interlayer insulating film 2 and the gate electrode 1. The membrane 5 is filled. As a result, as shown in the figure below, in the memory cell portion, the memory material layer 7 is sandwiched by the semiconductor channel layer 6 in the stacking direction, so that the memory material film 7 in which the semiconductor channel layer 6 is filled in the recess 4 is formed. Voltage application electrode.

  FIG. 2 is a cross-sectional view of a main part of the three-dimensional stacked chain type memory device according to the embodiment of the present invention. Here, a cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG. 1 is shown. In the opening (5), the insulator film 8, the memory material film 7, the semiconductor channel layer 6, and the gate insulating film 5 are arranged in a concentric ring shape, and the other region becomes the gate electrode 1.

  FIG. 3 is an equivalent circuit diagram of the three-dimensional stacked chain type memory device according to the embodiment of the present invention. Here, a portion where four cells surrounded by a broken line in the figure are stacked is the three-dimensional stacked chain type memory device. This is an equivalent circuit of the memory block. As shown in the figure, as a circuit configuration of the three-dimensional stacked chain type memory device, one memory cell is composed of one transistor connected in parallel and one ferroelectric capacitor, and one memory block includes a plurality of memory blocks. The memory cells are connected in series, one terminal of the memory block is connected to a bit line, and the other terminal is connected to a plate line.

  FIG. 4 is an explanatory diagram of the operation of the three-dimensional stacked chain type memory device according to the embodiment of the present invention, FIG. 4 (a) is an explanatory diagram of a standby state, and FIG. 4 (b) is an explanatory diagram of an active state. FIG. 4A and 4B, the left diagram is a schematic cross-sectional view of the memory cell portion, the upper right diagram is an equivalent circuit diagram of a three-dimensional stacked chain type memory device, and the lower right diagram is hysteresis. It is explanatory drawing of a characteristic.

As shown in FIG. 4 (a), in the standby state, the transistors of all the cells are in the ON state, both ends of the semiconductor channel layer 6 becomes a state in which a voltage of V _ss via the bit line and the plate line are applied No voltage is applied to the memory material film 7 of each cell. As shown in FIG. 4B, a voltage of V _dd is applied to the plate line, and only the transistor of the selected cell is turned off. At this time, since carriers do not flow through the semiconductor channel layer 6 of the transistor of the selected cell, a voltage is applied to the memory material film 7 of the selected cell, and data is written or read.

As the gate electrode 1, polycrystalline silicon, Co silicide, Ni silicide, or the like can be used. The height of the gate electrode 1 is about 50 nm to 120 nm, and the diameter is 50 nm or more. As the interlayer insulating film 2, a TEOS (Tetraethyl Orthosilicate) film, a thermal CVD SiO ₂ film, a HDP (high density plasma) -SiO ₂ film, a SiOF film, an organic polymer-based or porous silica-based Low-k film may be used. it can. The film thickness of the interlayer insulating film 2 is about 50 nm, and the length of the flange for forming the recess 4 is about 50 nm to 150 nm. The diameter of the opening 3 is about 100 nm to 200 nm, and the diameter of the opening residual gap remaining after the formation of the memory material film 7 is, for example, 25 nm or more. However, 0 nm may be used in some cases. As the gate insulating film 5, TEOS film, thermal CVD SiO ₂ film, it is possible to use a HDP-SiO ₂ film or ALD (atomic layer deposition) -SiO ₂ film, or the like. The thickness of the gate insulating film 5 is about 5 nm to 10 nm.

  As the semiconductor channel layer 6, a silicon-based semiconductor layer such as polycrystalline silicon, amorphous silicon, or a silicon layer formed by atomic layer deposition, or an oxide-based semiconductor layer such as IGZO (In—Ga—Zn—O) is used. it can. The thickness of the semiconductor channel layer 6 is about 8 nm to 15 nm. In order to reduce the resistance of the semiconductor channel layer 6, laser annealing may be performed after the film formation.

As the memory material film 7, any one of a ferroelectric film, a phase change film, and a resistance change film is used. When the ferroelectric film is used, a three-dimensional chain type FeRAM is formed, and a phase change film is used. In this case, it becomes a three-dimensional chain type PCRAM, and when a resistance change film is used, it becomes a three-dimensional chain type RRAM (RRAM is a registered trademark). As the ferroelectric film, an HfO _X- based ferroelectric material, for example, Al: HfO ₂ , Si: HfO ₂ , Gd: HfO ₂ , Y: HfO ₂ , HfZrO, or the like, or a laminate of a barrier film and a ferroelectric film is used. Examples of the structure include HfO _X / PZT, HfO _X / SBT (SrBi ₂ Ta ₂ O ₉ ), and HfO _X / BST (Ba _x Sr _1-x TiO ₃ ). Examples of the phase change film include GST (Ge—Sb—Te), Ga—Sb, and Ga—Sb—Ge. Examples of the resistance change film include HfO _X , NiO _X , and TaO _X. The thickness of the memory material film 7 is about 5 nm to 200 nm. When the thickness of the memory substance film 7 is less than 5 nm, there is a concern that the breakdown voltage of the material is insufficient, and when it exceeds 200 nm, there is a concern that a residual charge sufficient for device operation cannot be obtained.

Face opposite to the side in contact with the semiconductor channel layer 6 of the memory material layer 7 may be covered with an insulating film 8, the insulating film 8, and the TEOS film, thermal CVD SiO ₂ film, HDP-SiO ₂ film Low- A k film can be used. Alternatively, a diffusion preventing film that prevents diffusion of hydrogen or moisture may be used as the insulator film 8, and examples of the diffusion preventing film include an Al ₂ O ₃ film and a SiN film.

  The surface of the memory material film 7 opposite to the side in contact with the semiconductor channel layer 6 may be covered with a conductive film such as TiN. By applying strain in the heat treatment process for improving crystallinity, the characteristics of the memory material film 7 are improved. improves.

  A conductor film having a higher conductivity than that of the semiconductor channel layer 6 such as TiN or W may be provided on the surface of the recess 4 except for the side surface of the semiconductor channel layer 6. By providing such a conductor film, it is possible to reduce the specific resistance of the portion of the semiconductor channel layer 6 that effectively becomes the source / drain region. In addition, since the portion sandwiching the memory material film 7 becomes a conductor film, a sufficient voltage can be applied to the memory material film 7. Note that a MOCVD (metal organic chemical vapor deposition) method may be used as a film formation method.

  You may intentionally trim and provide roundness in the corner | angular part of the edge part of the overhang | projection part which forms the collar part of the interlayer insulation film 2. FIG. Thus, by providing the roundness, the source gas for forming the gate insulating film 5, the semiconductor channel layer 6, and the memory material film 7 can easily enter the collar portion of the interlayer insulating film 2, thereby suppressing generation of voids. Can do.

  In the embodiment of the present invention, the recess 4 is formed in the portion of the memory cell portion where the gate electrode 1 and the memory material film 7 face each other in the memory cell portion, so that the recess 4 is filled. The semiconductor channel layer 6 comes into contact with the upper and lower ends of the memory material film 7 formed. As a result, the memory material film 7 is sandwiched by the semiconductor channel layer 6 from above and below in FIG. 4B, so that a sufficient voltage is applied to function as a memory element.

  Next, with reference to FIGS. 5 to 22, the three-dimensional multilayer chain type FeRAM according to the first embodiment of the present invention will be described. FIG. 5 is a schematic perspective view of the three-dimensional stacked chain type FeRAM according to the first embodiment of the present invention. Here, the drawing and input / output units of the memory cell portion of the three-dimensional stacked chain type FeRAM 20 are illustrated and described. Is omitted. As shown in FIG. 5, a plurality of plate lead lines 24 are provided in parallel on the semiconductor substrate side. A plurality of word lead lines 23 provided on the plate lead lines 24 and bit lead lines 22 provided above the memory cells are provided in parallel in a direction orthogonal to the plate lead lines 24. The n-type polycrystalline Si layer 46 that becomes the gate electrode of the transistor of the memory cell is separated by the interlayer insulating film 47, and the gate electrode lead electrode 21 is drawn in the direction opposite to the bit lead line 22. The gate electrode lead line 21, the bit lead line 22, the word lead line 23, and the plate lead line 24 are connected to the wiring layer through vias, respectively.

  FIG. 6 is an explanatory diagram of the three-dimensional stacked chain type FeRAM according to the first embodiment of the present invention. The right figure is a schematic cross-sectional view of the main part, and the right figure is a corresponding equivalent circuit diagram. Here, it is shown as a cross-sectional view along the alternate long and short dash line connecting BB 'in the explanatory view of the manufacturing process described later. Here, a case where two layers of gate electrodes are stacked is shown.

  As shown in the left figure, a vertical transistor having an n-type amorphous Si layer 37 as a gate electrode connected to a word line is formed on a Si substrate 31, and an n-type amorphous Si layer 41 serving as a channel layer is a W layer serving as a plate line. 33 is connected.

A nitride film 44 and a SiO ₂ film 45 are formed on the Si substrate 31 on which the vertical transistor is formed, and then a two-layer gate electrode composed of n-type polycrystalline Si layers 46 and 48 is formed via an interlayer insulating film 47. The SiO ₂ film 49 is provided thereon. An opening 50 penetrating the SiO ₂ film 49 to the n-type polycrystalline Si layer 46 is provided. A gate insulating film 52, an Si channel layer 53, and a ferroelectric film 54 are sequentially formed so as to cover the exposed portions of the interlayer insulating film 47 and the n-type polycrystalline Si layers 46 and 48 in the opening 50. At this time, the interlayer insulating film 47 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46 and 48 in the opening 50 so that the interlayer insulating film 47 and the n-type polycrystalline Si layers 46 and 48 are stacked. Two recesses 51 are formed along the same, and the recesses 51 are filled with the ferroelectric film 54. Further, a SiO ₂ film 55 is embedded in the gap between the opposing back surfaces of the ferroelectric film 54. As a result, a hollow cylindrical ferroelectric capacitor is formed between the n-type polycrystalline Si layers 46 and 48 facing each other.

  As shown in the right figure, a bit line 56 is connected to the upper end of the Si channel layer 53, connected to a bit line selection transistor not shown in the left figure, and a vertical transistor is connected to the lower end. A word line selection transistor (not shown in the left diagram) is connected to the gate electrode of the vertical transistor. Further, n-type amorphous Si layers 46 and 48 serving as gate electrodes of the memory cell transistors are respectively connected to gate selection transistors (not shown).

Next, with reference to FIGS. 7 to 22, a manufacturing process of the three-dimensional multilayer chain type FeRAM according to the first embodiment of the present invention will be described. In addition, the figure (a) in each figure is a top view, the figure (b) is sectional drawing along the dashed-dotted line which connects AA 'in figure (a), and figure (c) is figure (a). It is sectional drawing along the dashed-dotted line which connects BB 'in FIG. First, as shown in FIG. 7, an SiO ₂ film 32 and a W layer 33 are deposited on the Si substrate 31, and then etched in a stripe shape. At this time, the W layer 33 etched in a stripe shape becomes a plate line.

Next, as shown in FIG. 8, a SiO ₂ film is deposited on the entire surface, and then planarized by a CMP (Chemical Mechanical Polishing) method, thereby filling the space between the stripe patterns with the SiO ₂ film 34. Next, a SiN film 35, a SiO ₂ film 36, an n-type amorphous silicon layer 37, and a SiO ₂ film 38 are sequentially deposited on the entire surface.

  Next, as shown in FIG. 9, the SiO 2 film 38 to the SiN film 35 are selectively etched using a RIE (Reactive Ion Etching) method to form an opening 39 to expose the W layer 33.

  Next, as shown in FIG. 10, a gate insulating film 40 is formed on the entire surface. Next, as shown in FIG. 11, after removing the gate insulating film 40 laminated on the flat portion by anisotropic etching, an n-type amorphous Si layer 41 is deposited on the entire surface, planarized by the CMP method, and the opening 39 is formed. An n-type amorphous Si layer 41 is embedded in

Next, as shown in FIG. 12, the separation groove 42 is formed along the AA ′ direction in which the W layer 33 extends. The word line is cut out by the separation groove 42. Then, as shown in FIG. 13, after depositing the SiO ₂ film 43 on the entire surface by flattening by CMP, embedding the isolation trench 42 in the SiO ₂ film 43.

Next, as shown in FIG. 14, after an SiN film 44 and an SiO ₂ film 45 are deposited on the entire surface, for example, an interlayer composed of an n-type polycrystalline Si film 46 having a thickness of 62 nm and an SiO ₂ film having a thickness of 50 nm. An insulating film 47, an n-type polycrystalline Si film 48 having a thickness of 62 nm, and an SiO ₂ film 49 are sequentially formed. In addition, in FIG. 14, sectional drawing along BB 'is abbreviate | omitted.

  Next, as shown in FIG. 15, an opening 50 reaching the SiN film 44 is formed in a region where the n-type amorphous Si film 37 exists. Here, the diameter of the opening 50 is, for example, 100 nm. In FIG. 15 and subsequent figures, a part of the lower structure in the cross-sectional view connecting AA ′ is not shown.

Next, as shown in FIG. 16, n polycrystalline silicon layers 36 and 38 are side-etched by isotropic etching with a polycrystalline Si / SiO 2 high selection ratio, for example, a selectivity ratio of about 22, using a microwave etching apparatus. As a result, the overhanging portions of the interlayer insulating film 47 and the SiO ₂ film 49 form a recess 51 having a thickness of 120 mm. Here, as the etching gas, a mixed gas of CF ₄ at a flow rate of 80 ml / min and O ₂ at a flow rate of 20 ml / min is used, and the temperature of the wafer stage is set to 70 ° C. in an atmosphere of 0.7 Torr. A power of 1300 W is applied.

Next, as shown in FIG. 17, a SiO ₂ film having a thickness of, for example, 6 nm on the side surface portion of the opening 50 is deposited on the surface of the opening 50 using the ALD method to form the gate insulating film 52. Next, as shown in FIG. 18, the flat surface of the SiO ₂ film 49 and the gate insulating film 52 deposited on the SiN film 44 are removed by anisotropic dry etching. Next, the exposed SiN film 44 is removed, and the n-type amorphous Si film 37 is exposed in the opening 50.

Next, as shown in FIG. 19, a Si channel layer 53 having a thickness of, for example, 10 nm is deposited on the entire surface by using the ALD method. In this case, the specific resistance ρ of the Si channel layer 53 is arbitrary, but here, for example, 7.35 × 10 ⁻⁵ Ω · m.

Next, as shown in FIG. 20, the ALD method is used to fill the recess 51 by forming a ferroelectric film 54 made of HfZrO with a thickness of, for example, 30 nm. At this time, although not shown, a recess is formed on the back surface of the ferroelectric film 54 located in the recess 51 as shown in FIG. At this time, the diameter of the residual gap of the through hole formed by the opposing surfaces of the ferroelectric films 54 facing each other is 28 nm. Next, a residual gap is filled by depositing a SiO ₂ film 55 on the entire surface. The SiO ₂ film 55 is also filled in a recess formed on the back surface of the ferroelectric film 54 (not shown) located on the recess 51.

Then, as shown in FIG. 21, by CMP, by polishing until the SiO ₂ film 49 is exposed, SiO ₂ film 55 is deposited above the surface of the SiO ₂ film 49, ferroelectric film 54 and the Si channel Layer 53 is polished and planarized.

  Next, as shown in FIG. 22, by forming the bit line 56 along the extending direction of the word line cut out by the separation groove 42, the basic structure of the three-dimensional stacked chain type FeRAM according to the first embodiment of the present invention. Is completed.

In Example 1 of the present invention, a flange portion is formed in the interlayer insulating film 47 and the SiO ₂ film 49, and a recess 51 is formed on the side surface of the n-type polycrystalline silicon 46, 48 to be a gate electrode. A ferroelectric film 54 is formed so as to be embedded. As a result, in the memory cell portion, the ferroelectric film 54 is sandwiched between the Si channel layer 53 in the vertical direction in the figure, and the Si channel layer 53 serves as a voltage application electrode, so that a sufficient voltage is applied to the ferroelectric film 54. It is possible to perform writing and reading reliably.

  Next, referring to FIG. 23, the three-dimensional stacked chain type FeRAM according to the second embodiment of the present invention will be described, but is the same as the first embodiment except that the number of stacked memory cells is four. . FIG. 23 is an explanatory diagram of the three-dimensional stacked chain type FeRAM according to the second embodiment of the present invention.

  As shown in the figure, a vertical transistor having an n-type amorphous Si layer 37 as a gate electrode connected to a word line is formed on a Si substrate 31, and an n-type amorphous Si layer 41 serving as a channel layer is used as a W layer 33 serving as a plate line. Connect to.

After the SiN film 44 and the SiO ₂ film 45 are formed on the Si substrate 31 on which the vertical transistor is formed, the n-type polycrystalline Si layers 46, 48, 58, 60 are interposed via the interlayer insulating films 47, 57, 59. A four-layer gate electrode made of is laminated, and an SiO ₂ film 49 is provided thereon. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction. In the opening 50, the gate insulating film 52, the Si channel layer 53, and the ferroelectric film 54 are formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60. The film is sequentially formed so that the recess 51 is filled with the ferroelectric film 54. Further, a SiO ₂ film 55 is embedded in the gap between the opposing back surfaces of the ferroelectric film 54. As a result, a hollow cylindrical ferroelectric capacitor is formed between the n-type polycrystalline Si layers 46, 48, 58, 60 facing each other. Thus, the number of gate stacks in the case of configuring a three-dimensional stacked chain type FeRAM is arbitrary.

  Next, with reference to FIG. 24, the three-dimensional stacked chain type FeRAM according to the third embodiment of the present invention will be described. On the exposed surface other than the side surface in the recess of the Si channel layer, the conductivity of the Si channel layer having high conductivity is described. This is basically the same as Example 2 except that a body membrane is provided. FIG. 24 is a cross-sectional view of the main part of the memory cell portion of the three-dimensional multilayer chain type FeRAM according to Embodiment 3 of the present invention.

As shown in the figure, four layers of gate electrodes composed of n-type polycrystalline Si layers 46, 48, 58, 60 are stacked via interlayer insulating films 47, 57, 59. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction. In the opening 50, the gate insulating film 52 and the Si channel layer 53 are sequentially formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60.

Next, for example, a TiN film 61 is deposited as a conductor film having a higher conductivity than the Si channel layer by using MOCVD. At this time, in the MOCVD method, when the aspect ratio of the recess 51 is large, the source gas does not diffuse to the back of the recess, so the TiN film 61 is not deposited on the side surface of the recess of the Si channel layer 53, Deposit on other exposed surfaces. Next, the recess 51 is filled with the ferroelectric film 54. In addition, the gap between the opposing back surfaces of the ferroelectric film 54 is filled with the SiO ₂ film 55.

  As a result, the portion of the Si channel layer 53 that effectively becomes the source / drain region has a laminated structure with the TiN film 61, so that the overall resistance can be reduced. Further, a hollow cylindrical ferroelectric capacitor is formed between the n-type polycrystalline Si layers 46, 48, 58, 60 facing each other. The ferroelectric film 54 of the hollow cylindrical ferroelectric capacitor is formed. Since the upper and lower surfaces are in contact with the low resistance TiN film 61, a sufficient voltage is applied.

  Next, with reference to FIG. 25, the three-dimensional multilayer chain type FeRAM according to the fourth embodiment of the present invention will be described, but basically the same as the second embodiment except that PZT is used as the ferroelectric film. It is. FIG. 25 is an explanatory diagram of the memory cell portion of the three-dimensional stacked chain type FeRAM according to the fourth embodiment of the present invention. The upper diagram is a schematic cross-sectional view of the memory cell portion, and the lower diagram is surrounded by a broken line in the upper diagram. It is a principal part perspective view which shows a capacitor part.

  As shown in the figure, four layers of gate electrodes composed of n-type polycrystalline Si layers 46, 48, 58, 60 are stacked via interlayer insulating films 47, 57, 59. Next, an opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO 2 film 49 are projected from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47, Four recesses 51 are formed along the stacking direction of 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60. In the opening 50, the gate insulating film 52 and the Si channel layer 53 are sequentially formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60.

Next, a PZT film 63 is formed as a ferroelectric film, but before that, an HfO _x film 62 having a thickness of, for example, 5 nm is formed as a barrier film. Since the PZT film 63 is alloyed with the Si channel layer 53, a barrier film is formed to prevent alloying. Even when an SBT film or a BST film is used as the ferroelectric film, it is alloyed with the Si channel layer 53, so that it is necessary to provide a barrier film. Further, the gap on the opposite back surface of the PZT film 63 is filled with the SiO ₂ film 55.

  As described above, even when PZT is used as a ferroelectric film, by providing a barrier film, alloying of the PZT film and the Si channel layer can be prevented, so that transistor characteristics and ferroelectric characteristics are deteriorated. There is nothing to do.

  Next, with reference to FIG. 26, the three-dimensional stacked chain type FeRAM according to the fifth embodiment of the present invention will be described. However, the above implementation is performed except that the gap on the opposite back surface of the ferroelectric film is filled with the TiN film. Basically the same as Example 2. FIG. 26 is an explanatory diagram of the memory cell portion of the three-dimensional stacked chain type FeRAM according to the fifth embodiment of the present invention. The upper diagram is a schematic cross-sectional view of the memory cell portion, and the lower diagram is surrounded by a broken line in the upper diagram. It is a principal part perspective view which shows a capacitor part.

As shown in the figure, four layers of gate electrodes composed of n-type polycrystalline Si layers 46, 48, 58, 60 are stacked via interlayer insulating films 47, 57, 59. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction. In the opening 50, the gate insulating film 52, the Si channel layer 53, and the ferroelectric film 54 are formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60. Films are sequentially formed.

Next, the gap between the opposing back surfaces of the ferroelectric film 54 is filled with the TiN film 64. Next, the crystallinity of the ferroelectric film 54 is improved by performing heat treatment. At this time, if the TiN film 64 is provided, since the strain is applied to the ferroelectric film 54, the capacitor characteristics are improved. Such an effect is remarkable when an HfO _x -based ferroelectric film is used as the ferroelectric film.

  Next, a three-dimensional multilayer chain type FeRAM according to Example 6 of the present invention will be described with reference to FIGS. 27 to 31 except that the corners of the end portions of the overhang portions of the interlayer insulating film are rounded. This is basically the same as the second embodiment. FIG. 27 is a schematic cross-sectional view of a three-dimensional multilayer chain type FeRAM according to Embodiment 6 of the present invention.

  As shown in the figure, a vertical transistor having an n-type amorphous Si layer 37 as a gate electrode connected to a word line is formed on a Si substrate 31, and an n-type amorphous Si layer 41 serving as a channel layer is used as a W layer 33 serving as a plate line. Connect to.

After forming the nitride film 44 and the SiO ₂ film 45 on the Si substrate 31 on which the vertical transistor is formed, the n-type polycrystalline Si layers 46, 48, 58, 60 are interposed via the interlayer insulating films 47, 57, 59. A four-layer gate electrode made of is laminated, and an SiO ₂ film 49 is provided thereon. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction, and the interlayer insulating films 47, 57, 59 and SiO ₂ film 49 are stretched. A roundness 65 is provided at the corner of the end of the protruding portion.

Next, the gate insulating film 52, the Si channel layer 53, and the ferroelectric film so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60 in the opening 50. 54 are sequentially formed so that the recess 51 is filled with the ferroelectric film 54. Further, a SiO ₂ film 55 is embedded in the gap between the opposing back surfaces of the ferroelectric film 54.

Next, with reference to FIGS. 28 to 31, the manufacturing process of the three-dimensional multilayer chain type FeRAM according to the sixth embodiment of the present invention will be described. First, as shown in FIG. 28, after forming a transistor, a plate line or the like on the Si substrate 31 as in FIG. 14 described above, a polycrystalline Si / SiO ₂ high selection ratio, for example, using a microwave etching apparatus, for example, The n polycrystal Si layers 46, 48, 58, 60 are side-etched by isotropic etching with a selectivity of about 22 so that the overhanging portions of the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are 120 mm concave portions 51. Form. Here, as the etching gas, a mixed gas of CF ₄ at a flow rate of 80 ml / min and O ₂ at a flow rate of 20 ml / min is used, and the temperature of the wafer stage is set to 70 ° C. in an atmosphere of 0.7 Torr. A power of 1300 W is applied.

Next, as shown in FIG. 29, CF ₄ is etched and isotropically etched to trim the corners of the end portions of the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49. Provide roundness 65.

  Next, as shown in FIG. 30, gate insulation is performed using the ALD method so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60 in the opening 50. A film 52, a Si channel layer 53, and a ferroelectric film 54 are sequentially formed. At this time, since the rounds 65 are formed at the corners of the end portions of the interlayer insulating films 47, 57, and 59, the source gas can easily enter the collar portion, so that favorable film formation can be performed without generating voids. Become.

Next, as shown in FIG. 31, the gap on the opposite back surface of the ferroelectric film 54 is filled with the SiO ₂ film 55. Thereafter, a bit line or the like may be formed as in the manufacturing process of the first embodiment.

  Next, a three-dimensional stacked chain type FeRAM according to Example 7 of the present invention will be described with reference to FIGS. 32 to 36. A diffusion prevention film for preventing diffusion of hydrogen and moisture is provided on the back surface of the ferroelectric film. Except for the provision, the configuration is basically the same as that of the sixth embodiment. FIG. 32 is a schematic cross-sectional view of a three-dimensional multilayer chain type FeRAM according to Example 7 of the present invention.

  As shown in the figure, a vertical transistor having an n-type amorphous Si layer 37 as a gate electrode connected to a word line is formed on a Si substrate 31, and an n-type amorphous Si layer 41 serving as a channel layer is used as a W layer 33 serving as a plate line. Connect to.

After forming the nitride film 44 and the SiO ₂ film 45 on the Si substrate 31 on which the vertical transistor is formed, the n-type polycrystalline Si layers 46, 48, 58, 60 are interposed via the interlayer insulating films 47, 57, 59. A four-layer gate electrode made of is laminated, and an SiO ₂ film 49 is provided thereon. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction, and the interlayer insulating films 47, 57, 59 and SiO ₂ film 49 are stretched. A roundness 65 is provided at the corner of the end of the protruding portion.

Next, the gate insulating film 52, the Si channel layer 53, and the ferroelectric film are formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60 in the opening 50. 54 and a diffusion prevention film 66 are sequentially formed so that the recess 51 is filled with the ferroelectric film 54. Further, the gap between the opposing back surfaces of the ferroelectric film 54 is filled with the SiO ₂ film 55.

Next, with reference to FIGS. 33 to 36, a manufacturing process of the three-dimensional multilayer chain type FeRAM according to Embodiment 7 of the present invention will be described. First, similarly to FIG. 28 described above, after a transistor, a plate line or the like is formed on the Si substrate 31, a polycrystalline Si / SiO ₂ high selection ratio, for example, a selection ratio of about 22 is selected using a microwave etching apparatus. The n polycrystal Si layers 46, 48, 58, 60 are side-etched by isotropic etching to form a recess 51 in which the protruding portions of the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are 120 mm. Here, as the etching gas, a mixed gas of CF ₄ at a flow rate of 80 ml / min and O ₂ at a flow rate of 20 ml / min is used, and the temperature of the wafer stage is set to 70 ° C. in an atmosphere of 0.7 Torr. A power of 1300 W is applied.

Next, as shown in FIG. 33, CF ₄ is etched and isotropically etched to trim the corners of the end portions of the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49. Provide roundness 65.

  Next, as shown in FIG. 34, gate insulation is performed using the ALD method so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60 in the opening 50. A film 52, a Si channel layer 53, and a ferroelectric film 54 are sequentially formed. At this time, since the rounds 65 are formed at the corners of the end portions of the interlayer insulating films 47, 57, and 59, the source gas can easily enter the collar portion, so that favorable film formation can be performed without generating voids. Become.

Next, as shown in FIG. 35, an Al ₂ O ₃ film having a thickness of, for example, 20 nm is formed as the diffusion preventing film 66. Next, as shown in FIG. 36, the gap on the opposite back surface of the diffusion prevention film 66 is filled with the SiO ₂ film 55. Thereafter, a bit line or the like may be formed as in the manufacturing process of the first embodiment.

In the seventh embodiment of the present invention, since the diffusion prevention film 66 is provided on the back surface of the ferroelectric film 54, the deterioration of the ferroelectric film 54 due to the intrusion of hydrogen or moisture can be suppressed. Here, although an Al ₂ O ₃ film is used as the diffusion preventing film, a SiN film may be used. Further, when a BST film or SBT film is used as the ferroelectric film, it is deteriorated by hydrogen or moisture as in the case of the PZT film. Therefore, it is desirable to provide a diffusion prevention film. Further, in the above-described first to fifth embodiments, a diffusion preventing film may be provided.

  Next, referring to FIG. 37, the three-dimensional stacked chain type PCRAM according to the eighth embodiment of the present invention will be described. Basically, a phase change film is provided as a memory material film instead of a ferroelectric film. The structure and manufacturing process are the same as those in the second embodiment. FIG. 37 is an explanatory diagram of a three-dimensional multilayer chain type PCRAM according to an eighth embodiment of the present invention. The upper diagram is a schematic cross-sectional view of a memory cell unit, and the lower diagram shows a capacitor unit surrounded by a broken line in the upper diagram. It is a principal part perspective view.

  As shown in the figure, a vertical transistor having an n-type amorphous Si layer 37 as a gate electrode connected to a word line is formed on a Si substrate 31, and an n-type amorphous Si layer 41 serving as a channel layer is used as a W layer 33 serving as a plate line. Connect to.

After forming the nitride film 44 and the SiO ₂ film 45 on the Si substrate 31 on which the vertical transistor is formed, the n-type polycrystalline Si layers 46, 48, 58, 60 are interposed via the interlayer insulating films 47, 57, 59. A four-layer gate electrode made of is laminated, and an SiO ₂ film 49 is provided thereon. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction.

The gate insulating film 52, the Si channel layer 53, and the phase change film 67 are sequentially formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60 in the opening 50. A film is formed so that the recess 51 is filled with the phase change film 67. Further, a SiO ₂ film 55 is buried in the gap between the opposite back surfaces of the phase change film 67. As a result, a hollow cylindrical phase change material memory portion is formed between the n-type polycrystalline Si layers 46, 48, 58, 60 facing each other. Here, a GST film is used as the phase change film 67.

  Even when a phase change film is used as the memory material film as in the eighth embodiment of the present invention, in the memory cell portion, the phase change film 67 is sandwiched between the Si channel layers 53 in the vertical direction as shown below. The Si channel layer 53 serves as a voltage application electrode. Therefore, a sufficient voltage is applied to the phase change film 67 and a current flows, so that the crystal structure of the phase change film can be changed satisfactorily. In the eighth embodiment, as in the sixth embodiment, the corners of the overhang portions of the interlayer insulating film may be rounded.

  Next, referring to FIG. 38, a three-dimensional stacked chain type RRAM (RRAM is a registered trademark) according to a ninth embodiment of the present invention will be described. A resistance change film is provided instead of a ferroelectric film as a memory material film. Except for the above, the basic structure and manufacturing process are the same as those of the second embodiment. FIG. 38 is an explanatory diagram of the three-dimensional multilayer chain type RRAM according to the ninth embodiment of the present invention. The upper diagram is a schematic cross-sectional view of the memory cell unit, and the lower diagram shows a capacitor unit surrounded by a broken line in the upper diagram. It is a principal part perspective view.

  As shown in the figure, a vertical transistor having an n-type amorphous Si layer 37 as a gate electrode connected to a word line is formed on a Si substrate 31, and an n-type amorphous Si layer 41 serving as a channel layer is used as a W layer 33 serving as a plate line. Connect to.

After forming the nitride film 44 and the SiO ₂ film 45 on the Si substrate 31 on which the vertical transistor is formed, the n-type polycrystalline Si layers 46, 48, 58, 60 are interposed via the interlayer insulating films 47, 57, 59. A four-layer gate electrode made of is laminated, and an SiO ₂ film 49 is provided thereon. Next, the opening 50 is provided. In the opening 50, the interlayer insulating films 47, 57, 59 and the SiO ₂ film 49 are protruded from the n-type polycrystalline Si layers 46, 48, 58, 60, and the interlayer insulating film 47. , 57, 59 and n-type polycrystalline Si layers 46, 48, 58, 60 are formed in four recesses 51 along the stacking direction.

The gate insulating film 52, the Si channel layer 53, and the resistance change film 68 are sequentially formed so as to cover the exposed portions of the interlayer insulating films 47, 57, 59 and the n-type polycrystalline Si layers 46, 48, 58, 60 in the opening 50. A film is formed so that the recess 51 is filled with the resistance change film 68. Further, a SiO ₂ film 55 is embedded in the gap between the opposing back surfaces of the resistance change film 68. As a result, a hollow cylindrical resistance change material memory is formed between the n-type polycrystalline Si layers 46, 48, 58, 60 facing each other. Here, an HfO _x film is used as the resistance change film.

  Even when a resistance change film is used as the memory material film as in the ninth embodiment of the present invention, in the memory cell portion, the resistance change film 68 is sandwiched between the Si channel layer 53 in the vertical direction as shown in the following figure. The Si channel layer 53 serves as a voltage application electrode. Therefore, a sufficient voltage is applied to the resistance change film 68, and the resistance changes due to the electric field induced giant resistance change. In the ninth embodiment, as in the sixth embodiment, the corners of the end portions of the overhang portions of the interlayer insulating film may be rounded.

Here, the following supplementary notes are attached to the embodiments of the present invention including Examples 1 to 9.
(Supplementary Note 1) A plurality of gate electrodes stacked via an interlayer insulating film, an opening penetrating the interlayer insulating film and the plurality of gate electrodes, and an exposed portion of the interlayer insulating film and the gate electrode in the opening A gate insulating film covering the semiconductor channel layer covering the gate insulating film; and a memory material film covering the semiconductor channel layer, wherein the interlayer insulating film protrudes from the gate electrode in the opening, A voltage applied to the memory material film having a periodic recess along the stacking direction of the interlayer insulating film and the gate electrode, the memory material film filling the recess, and the semiconductor channel layer filling the recess A three-dimensional stacked chain type memory device serving as an application electrode.
(Supplementary note 2) The three-dimensional stacked chain memory device according to supplementary note 1, wherein the memory substance film is any one of a ferroelectric film, a phase change film, and a resistance change film.
(Supplementary note 3) The three-dimensional stacked chain type memory device according to supplementary note 1 or supplementary note 2, further comprising an alloying prevention layer between the semiconductor channel layer and the memory material film.
(Supplementary note 4) The three-dimensional stacked chain type memory device according to any one of supplementary notes 1 to 3, wherein a surface of the memory material film opposite to a side in contact with the semiconductor channel layer is covered with an insulator film.
(Supplementary note 5) The three-dimensional stacked chain memory device according to supplementary note 4, wherein the insulator film is a diffusion prevention film that prevents diffusion of hydrogen or moisture.
(Supplementary note 6) The three-dimensional stacked chain memory device according to supplementary note 5, wherein the diffusion prevention film is either an aluminum oxide film or a silicon nitride film.
(Supplementary note 7) The three-dimensional stacked chain memory device according to any one of supplementary notes 1 to 3, wherein a surface of the memory material film opposite to a side in contact with the semiconductor channel layer is covered with a conductor film.
(Supplementary note 8) The three-dimensional stacked chain memory device according to supplementary note 7, wherein the conductor film is a TiN film.
(Supplementary note 9) The three-dimensional laminated chain according to any one of supplementary notes 1 to 8, further comprising a conductor film having a higher conductivity than the semiconductor channel layer on an exposed surface of the semiconductor channel layer other than the side surface in the recess. Type memory device.
(Additional remark 10) The process of laminating | stacking a some gate electrode layer through an interlayer insulation film, The process of forming the opening part which penetrates the said interlayer insulation film and a some gate electrode layer, The gate electrode exposed in the said opening part Forming a recess by side etching the layer; forming a gate insulating film on the exposed surface of the interlayer insulating film and the gate electrode layer in the opening; and a semiconductor channel on the exposed surface of the gate electrode layer Forming a layer so that a recess is formed in the semiconductor channel layer; and forming a memory material film so as to embed the recess formed in the semiconductor channel layer on the exposed surface of the semiconductor channel layer. A manufacturing method of at least a three-dimensional stacked chain type memory device.
(Supplementary note 11) The method for manufacturing a three-dimensional stacked chain type memory device according to supplementary note 10, further comprising a step of forming an insulator film on an exposed surface of the memory material film opposite to the side in contact with the semiconductor channel layer.
(Supplementary note 12) The method further includes the step of forming a conductive film on the exposed surface of the memory material film opposite to the side in contact with the semiconductor channel layer, and the step of performing a heat treatment in a state where the conductive film is provided. A manufacturing method of the three-dimensional stacked chain type memory device described in 1.
(Additional remark 13) Before the film-forming process of the said gate insulating film, Trimming the corner | angular part of the edge part of the said interlayer insulating film further has the process of giving roundness, Any one of Additional remark 10 thru | or Additional remark 12 A method of manufacturing a three-dimensional stacked chain type memory device.

DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Interlayer insulating film 3 Opening part 4 Recessed part 5 Gate insulating film 6 Semiconductor channel layer 7 Memory material film 8 Insulator film 20 Three-dimensional laminated chain type FeRAM
21 gate electrode lead line 22 bit lead line 23 word lead line 24 plate lead line 31 silicon substrate 32 SiO ₂ film 33 W layer 34 SiO ₂ film 35 SiN film 36 SiO ₂ film 37 n-type amorphous Si layer 38 SiO ₂ film 39 Opening Portion 40 Gate insulating film 41 n-type amorphous Si layer 42 isolation trench 43 SiO ₂ film 44 SiN film 45 SiO ₂ films 46, 58, 58, 60 n-type polycrystalline Si layers 47, 57, 59 Inter-layer insulating film 48 n-type poly Crystal Si layer 49 SiO ₂ film 50 Opening 51 Recess 52 Gate insulating film 53 Si channel layer 54 Ferroelectric film 55 SiO ₂ film 56 Bit line 61 TiN film 62 HfO _x film 63 PZT film 64 TiN film 65 Rounding 66 Diffusion prevention Film 67 Phase change film 68 Resistance change film 101, 111 Gate electrode 102, 112 Interlayer insulating film 103, 113 Gate insulating films 104 and 114 Polycrystalline silicon channel layer 105 Phase change film 115 Ferroelectric film

Claims (8)

A plurality of gate electrodes stacked via an interlayer insulating film;
An opening penetrating the interlayer insulating film and the plurality of gate electrodes;
A gate insulating film covering the interlayer insulating film and the exposed portion of the gate electrode in the opening;
A semiconductor channel layer covering the gate insulating film;
And at least a memory material film covering the semiconductor channel layer,
In the opening, the interlayer insulating film protrudes from the gate electrode, and has a periodic recess along the stacking direction of the interlayer insulating film and the gate electrode,
A three-dimensional stacked chain memory device in which the memory material film is filled in the recess, and the semiconductor channel layer serves as a voltage application electrode for the memory material film filled in the recess.   The three-dimensionally stacked chain type memory device according to claim 1, wherein the memory material film is one of a ferroelectric film, a phase change film, and a resistance change film.   3. The three-dimensionally stacked chain type memory device according to claim 1, wherein a surface of the memory material film opposite to a side in contact with the semiconductor channel layer is covered with an insulator film.   3. The three-dimensional stacked chain memory device according to claim 1, wherein a surface of the memory material film opposite to a side in contact with the semiconductor channel layer is covered with a conductor film.   5. The three-dimensional stacked chain type according to claim 1, further comprising a conductor film having a higher conductivity than the semiconductor channel layer on an exposed surface other than a side surface of the recess of the semiconductor channel layer. Memory device. Laminating a plurality of gate electrode layers via an interlayer insulating film;
Forming an opening that penetrates the interlayer insulating film and the plurality of gate electrode layers;
Forming a recess by side-etching the gate electrode layer exposed in the opening;
Forming a gate insulating film on the exposed surface of the interlayer insulating film and the gate electrode layer in the opening;
Forming a semiconductor channel layer on the exposed surface of the gate electrode layer such that a recess is formed in the semiconductor channel layer;
Forming a memory material film so as to embed the recess formed in the semiconductor channel layer on an exposed surface of the semiconductor channel layer. Depositing a conductor film on an exposed surface of the memory material film opposite to the side in contact with the semiconductor channel layer;
The method of manufacturing a three-dimensionally stacked chain type memory device according to claim 6, further comprising a step of performing a heat treatment in a state where the conductor film is provided.   8. The three-dimensional stacked chain type memory according to claim 6, further comprising a step of trimming a corner portion of the end portion of the interlayer insulating film to make it round before the step of forming the gate insulating film. Device manufacturing method.

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