JP2018032926A - Transimpedance amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TIA compatible with high gain and broadband characteristics.SOLUTION: A transimpedance amplifier 100 includes a first terminal PIN and a second terminal POUT, an inverting amplifier 1 to which a signal from the first terminal is inputted, a voltage follower 2 to which a signal outputted from the inverting amplifier is inputted, a current generation circuit 3 generating a current according to a current flowing to the voltage follower and outputting to the second terminal, a first load Iconnected with the second terminal, a first feedback resistor Rconnected between the first terminal and the output terminal of the voltage follower, and a second feedback resistor Rconnected between the output terminal of the voltage follower and the second terminal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a transimpedance amplifier, for example, a transimpedance amplifier mounted on a receiving device of an optical communication system.

  In general, a receiving device such as an optical communication system or a wireless communication system is provided with an amplifier that amplifies a received signal. For example, in an optical receiver in an optical communication system, in addition to a photodiode (PD: Photodiode) that performs optical-current conversion on an optical signal transmitted from a transmission line (optical fiber), a current signal output from the photodiode A transimpedance amplifier (TIA) that linearly amplifies the voltage signal to a voltage amplitude at which a subsequent circuit (for example, an analog / digital converter and a digital signal processor) can operate is provided. (See Non-Patent Document 1 and Non-Patent Document 2).

FIG. 9 is a diagram showing a conventional TIA mounted on an optical receiver.
A TIA 900 shown in FIG. 9 has an inverting amplifier 91 having a gain A and a source follower 92 connected in cascade, and a feedback resistor R _FB is connected between the output terminal of the source follower 92 and the input terminal of the inverting amplifier 91. This is an example of a so-called feedback resistance type TIA (see FIG. 7 (a) of Non-Patent Document 1).

In the TIA 900, when the input impedance of the inverting amplifier 91 is sufficiently larger than the feedback resistor R _FB , all of the input current I _IN is converted into a voltage by flowing through the feedback resistor R _FB , amplified, and output.

Here, the gain (hereinafter referred to as “transimpedance gain”) Z _T of TIA 900 is expressed by Expression (1).

When the gain of the inverting amplifier 91 is “A” and the gain of the source follower 92 is “1”, “V _OUT = −AV _IN ” between the input voltage V _IN and the output voltage V _OUT of the TIA 900. Since the relationship is established and the relationship of “V _OUT = I _IN × R _FB ” is established between the output voltage V _OUT and the input current I _IN , the input impedance Z _{IN of the} TIA 900 is expressed by Expression (2). .

When the TIA 900 is used as the TIA for an optical receiver, since a photodiode (PD) is connected to the input terminal of the TIA 900, a cathode-anode capacitance of the PD is added as a parasitic capacitance to the input terminal of the TIA 900. Further, the capacitance of the electrode pad and the parasitic capacitance of the wiring connected to other input terminals are added to the input terminal of the TIA 900. Therefore, the band of the TIA 900 is a low-pass filter (time constant≈C _IN × Z _IN ) formed by the input capacitor C _IN composed of the various capacitors added to the input terminal of the TIA 900 and the input impedance Z _{IN of the} TIA 900. Limited by.

T. Takemoto et al., “A 25-to-28 Gb / s High-Sensitivity (-9.7dBm) 65nm CMOS Optical Receiver for Board-to-Board Interconnects,” JSSC, Vol. 49, No. 10, Oct. 2014. T. Masuda et al., “45GHz Transimpedance 32dB Limiting Amplifier and 40Gb / s 1: 4 High-Sensitivity Demultiplexer with Decision Circuit using SiGe HBTs for 40Gb / s Optical Receiver” IEEE International Solid-State Circuits Conference 2000.

With the recent increase in the speed of optical communication systems, it is desired to increase the bandwidth of TIA for optical receivers. As described above, in TIA900 conventional feedback resistor type, bandwidth is limited by the low-pass filter consisting of the input impedance Z _IN and the input capacitance C _IN. Therefore, in order to widen the band of TIA900, it is necessary to reduce at least one of the input capacitance C _IN and the input impedance Z _IN.

However, since the input capacitance C _IN of the TIA 900 is mainly determined by the type of PD connected to the input terminal of the TIA and the connection form between the PD and the TIA, it is easy to greatly reduce the capacitance value. is not. Further, the input impedance Z _{IN of the} TIA 900 can be reduced by making the feedback resistor R _FB a small value. However, when the feedback resistor R _FB is reduced, the transimpedance as shown in the equation (1). The gain Z _T also decreases. Therefore, in the conventional feedback resistance type TIA900, it is difficult to achieve both high gain and wideband characteristics.

  On the other hand, Non-Patent Document 2 discloses a TIA having a two-stage configuration in which a gate-grounded TIA is connected to a preceding stage of a feedback resistance type TIA. According to this, it is possible to secure a band by lowering the input impedance without lowering the transimpedance gain of the entire TIA.

  However, the present inventors have considered that a TIA having a new configuration capable of further increasing the gain and increasing the bandwidth is necessary in consideration of a further increase in the speed of the optical communication system expected in the future.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a TIA that achieves both high gain and wideband characteristics.

The transimpedance amplifier (100 to 103) according to the present invention includes a first terminal (PIN) and a second terminal (POUT), an inverting amplifier (1, 1X) for inputting a signal from the first terminal, and an output from the inverting amplifier. A voltage follower (2) for inputting the generated signal, a current generation circuit (3) for generating a current corresponding to the current flowing through the voltage follower and outputting the current to the second terminal, and a first load connected to the second terminal (I _C2 ), a first feedback resistor (R _FB1 ) connected between the first terminal and the output terminal of the voltage follower, and a second connected between the output terminal and the second terminal of the voltage follower. And a feedback resistor (R _FB2 ).

In the transimpedance amplifier, the voltage follower has one end connected to the fixed potential node (VSS) and the other end connected to the intermediate node (X) to which the first feedback resistor and the second feedback resistor are connected. A first transistor (M1) having a load (I _C1 ), a control electrode connected to the output terminal of the inverting amplifier, a first main electrode connected to the intermediate node, and a second main electrode connected to the input terminal of the current generation circuit The current generation circuit may be a current mirror circuit that outputs the current supplied from the second main electrode of the first transistor by multiplying N (N is an integer of 1 or more) to the second terminal. .

  In the transimpedance amplifier (101), the transimpedance amplifier (101) further includes an input stage amplifier (4) connected between the first terminal and the input terminal of the inverting amplifier. A second transistor (M7) that amplifies the signal of the first terminal input to the first main electrode and outputs the signal from the second main electrode to the input terminal of the inverting amplifier may be included.

  In the transimpedance amplifier, the input stage amplifier may be a grounded gate amplifier circuit.

  In the transimpedance amplifier, the input stage amplifier may be a regulated cascode amplifier circuit.

  In the transimpedance amplifier, the inverting amplifier may be a grounded source amplifier circuit (1A).

  In the transimpedance amplifier, the inverting amplifier may be a CMOS inverter circuit (1B).

  The transimpedance amplifier (102, 103) has two sets of circuit blocks each including a voltage follower, a current generation circuit, a first load, a first feedback resistor, and a second feedback resistor, and is inverted. The amplifier (1X) is a differential amplifier circuit that inverts and amplifies a pair of differential signals, and outputs the signal output from the inverted output terminal (−) of the differential amplifier circuit to one of the circuit blocks. The signal that is input and output from the non-inverting output terminal (+) of the differential amplifier circuit may be input to the other circuit block.

  In the above description, as an example, constituent elements on the drawing corresponding to the constituent elements of the invention are represented by reference numerals with parentheses.

  According to the present invention, it is possible to provide a TIA having both high gain and wideband characteristics.

FIG. 1 is a diagram illustrating a configuration of a TIA according to the first embodiment. FIG. 2A is a diagram illustrating a configuration of a common-source amplifier circuit as an inverting amplifier circuit. FIG. 2B is a diagram illustrating a configuration of a CMOS inverter circuit as an inverting amplifier circuit. FIG. 3 is a diagram illustrating frequency characteristics of the gain of the TIA according to the first embodiment. FIG. 4 is a diagram illustrating a configuration of the TIA according to the second embodiment. FIG. 5 is a diagram showing a configuration of a grounded-gate TIA as an example of an input stage amplifier. FIG. 6 is a diagram illustrating a configuration of the TIA according to the third embodiment. FIG. 7 is a diagram illustrating a configuration of the TIA according to the fourth embodiment. FIG. 8 is a diagram showing a configuration of a common-gate TIA as an example of the differential input stage amplifier. FIG. 9 is a diagram showing a configuration of a conventional feedback resistance type TIA.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals are given to components common to the respective embodiments, and repeated description is omitted.

<< Embodiment 1 >>
FIG. 1 is a diagram showing a configuration of a TIA according to an embodiment of the present invention.
A TIA 100 shown in the figure is a feedback resistance type TIA mounted on, for example, an optical receiver in an optical communication system. In an optical receiver of an optical communication system, an optical signal sent from a transmission line (optical fiber) is subjected to light-current conversion by a PD, and the current signal subjected to light-current conversion is converted to a voltage signal. The TIA 100 receives the current signal I _IN converted by the PD and converts it into a voltage signal, and amplifies it to a voltage amplitude at which a subsequent circuit (for example, an analog / digital converter and a digital signal processor) can operate. Output.

As shown in FIG. 1, the TIA 100 includes an inverting amplifier 1, a voltage follower 2, a current mirror circuit 3, a current source I _C2 as a load, feedback resistors R _FB1 and R _FB2 , and terminals PIN and POUT.

  Although not particularly limited, the TIA 100 can be realized by a semiconductor integrated circuit formed on a semiconductor substrate by a known CMOS (complementary metal oxide semiconductor) manufacturing process, for example. The TIA 100 may be realized as a one-chip semiconductor device or a multi-chip semiconductor device, and is not particularly limited.

  The inverting amplifier 1 is a circuit that amplifies and outputs a signal input to the terminal PIN. In order to increase the bandwidth of the TIA 100, it is desirable that the inverting amplifier 1 has a wide bandwidth and a high gain. Examples of the wideband and high gain inverting amplifier 1 include the common source amplifier circuit 1A shown in FIG. 2A and the CMOS inverter circuit 1B shown in FIG. 2B.

The voltage follower 2 is an amplifier circuit that amplifies the signal output from the inverting amplifier 1 and outputs the amplified signal. As shown in FIG. 1, the voltage follower 2 is exemplified by a source follower composed of one MOS transistor M1 (hereinafter referred to as “transistor M1”) and a current source I _C1 as a load. it can.

Specifically, the current source I _C1 has one end connected to the power supply line VSS as a fixed potential node and the other end connected to the intermediate node X to which the feedback resistor R _FB1 and the feedback resistor R _FB2 are connected. The transistor M1 is an N-channel MOS transistor, for example, and has a gate electrode as a control electrode connected to the output terminal S of the inverting amplifier 1, a source electrode as a first main electrode connected to the intermediate node X, The drain electrode as the two main electrodes is connected to the input terminal of the current mirror circuit 3.

  The current mirror circuit 3 is a current generation circuit that generates a current corresponding to the current flowing through the voltage follower 2 and outputs the current to the terminal POUT. Specifically, the current mirror circuit 3 multiplies the current supplied from the drain electrode of the transistor M1 by N (for example, N is an integer of 1 or more) and outputs the multiplied current to the terminal POUT.

  As shown in FIG. 1, in the current mirror circuit 3, the gate electrode and the drain electrode are commonly connected to the drain electrode of the transistor M1, and the source electrode is connected to the power supply line VDD (> VSS) as a fixed potential node. A P-channel MOS transistor M2 (hereinafter referred to as “transistor M2”), a gate electrode is connected to the gate electrode of the transistor M2, a source electrode is connected to the power supply line VDD, and a drain electrode is connected to the terminal POUT. And a P-channel MOS transistor M3 (hereinafter referred to as “transistor M3”).

The current source I _C2 has one end connected to the terminal POUT and the other end connected to the power supply line VSS.

The feedback resistor R _FB1 is connected between the terminal PIN and the output terminal (intermediate node X) of the voltage follower 2. The feedback resistor R _FB2 is connected between the output terminal (intermediate node X) of the voltage follower 2 and the terminal POUT.

Next, the operation principle of TIA 100 according to the first embodiment will be described.
In the TIA 100, since the input impedance of the inverting amplifier 1 is sufficiently large, almost all of the input current I _IN input to the terminal PIN flows into the feedback resistor R _FB1 .

Part of the input current I _IN flowing into the feedback resistor R _FB1 flows into the input terminal of the current mirror circuit 3 (the drain electrode of the transistor M2) via the output terminal of the voltage follower 2 as the current I ₁ , and the input current I _IN Since the remainder flows through the feedback resistor R _FB2 from the terminal POUT to the output terminal of the current mirror circuit 3 (the drain electrode of the transistor M3), between the input current I _IN and the currents I ₁ and I ₂ , The relations “I _IN = I ₁ + I ₂ ” and “I ₂ = N × I ₁ ” are established. Therefore, the transimpedance gain Z _T100 of the TIA ₁₀₀ is expressed by the following formula (3).

In the TIA 100, the current values of the current source I _C1 and the current source I _C2 are not particularly limited, and may be I _C1 : I _C2 ≠ 1: N. Even in this case, a direct current flows through the feedback resistor R _FB2 so that the current ratio of the transistors M2 and M3 in the current mirror circuit 3 is 1: N.

In Formula (3), when N is sufficiently large, “Z _T100 ≈R _FB1 + R _FB2 ” is satisfied, and the transimpedance gain Z _T100 of the TIA ₁₀₀ is determined by the sum of the feedback resistance R _FB1 and the feedback resistance R _FB2 .

When the gain of the inverting amplifier 1 is “A” and the gain of the voltage follower 2 is “1”, the input impedance Z _IN100 of the _{TIA 100} is expressed by the following equation (4).

For example, when the transimpedance gain Z _T100 of the TIA _{100 according} to the present embodiment is set to the same value as the transimpedance gain Z _T (= R _FB ) of the conventional TIA 900 described above, “R _FB1 < R _FB ". At this time, from the equations (2) and (4), the input impedance _ZIN100 of the _{TIA 100} is smaller than the input impedance ZIN of the conventional TIA900. As described above, in the feedback resistance type TIA, the input impedance is one of the elements that limit the band. Therefore, according to the TIA100, the transimpedance gain equivalent to that of the conventional feedback resistance type TIA is maintained. As a result, it is possible to increase the bandwidth.

On the other hand, when the input impedance Z _IN100 of the TIA _{100 according} to the present embodiment is set to the same value as the input impedance Z _IN of the conventional TIA 900, “R _FB1 = R _FB ” is obtained from the equations (1) and (4). Become. At this time, from the expressions (2) and (3), the transimpedance gain Z _T100 of the TIA ₁₀₀ is larger than the transimpedance gain Z _T of the conventional TIA 900. That is, according to the present TIA100, it is possible to increase the gain while maintaining a band (input impedance) equivalent to that of the conventional feedback resistance type TIA.

FIG. 3 is a diagram showing frequency characteristics of the gain of TIA 100 according to the first embodiment.
In the figure, the simulation result of the frequency characteristic of the feedback resistance type TIA100 gain according to the present embodiment is indicated by reference numeral 300, and the simulation result of the frequency characteristic of the gain of the conventional feedback resistance type TIA900 is indicated by reference numeral 301. It is shown in In the figure, the horizontal axis represents frequency (Hz) and the vertical axis represents gain (dBΩ).

The simulation conditions of the simulation results shown in FIG. 3 are R _FB = 6 kΩ in the conventional TIA circuit 900 (FIG. 9), and R _FB1 = 3.5 kΩ, R _FB2 = 2.5 kΩ in the TIA 100 according to the present embodiment, N = 6. The TIA circuits 100 and 900 both use 65 nm generation CMOS parameters, and the terminal PIN as the input terminal of the TIA circuits 100 and 900 has a cathode-anode capacitance of the PD and a parasitic capacitance of the electrode pad, respectively. An assumed input capacitance C _{IN of} 140 fF was connected. In addition, a common source amplifier circuit (see FIG. 2A) was used as the inverting amplifiers 1 and 91 of the TIAs 100 and 900.

  As shown in FIG. 3, when the TIA 100 according to the present embodiment and the conventional TIA 900 have the same gain condition, the TIA 100 is reduced by -3 dB from the DC gain (about 74 dB) compared to the conventional TIA 900. The frequency is about 2.1 times larger, and it is understood that a broader TIA can be realized.

As described above, according to the TIA 100 according to the first embodiment, the voltage follower 2 is connected in series to the inverting amplifier 1 that amplifies the signal input to the terminal PIN, and the current flowing through the voltage follower 2 is copied by the current mirror circuit 3. And a feedback resistor R _FB1 is connected between the terminal PIN and the output terminal of the voltage follower 2, and a feedback resistor R _FB2 is connected between the output terminal of the voltage follower 2 and the terminal POUT. Since it has a configuration, it is possible to increase the bandwidth while maintaining the transimpedance gain equivalent to that of the conventional feedback resistance type TIA, and the bandwidth (input impedance) equivalent to the conventional feedback resistance type TIA. It is possible to increase the gain while maintaining the above. That is, according to TIA 100 according to the first embodiment, it is possible to realize a TIA having both high gain and wideband characteristics.

<< Embodiment 2 >>
FIG. 4 is a diagram illustrating a configuration of the TIA according to the second embodiment.
The TIA 101 according to the second embodiment is different from the TIA 100 according to the first embodiment in that another input stage amplifier having a lower input impedance than the feedback resistance type TIA is connected between the terminal PIN and the inverting amplifier 1. The other points are the same as those of the TIA 100 according to the first embodiment.

Specifically, the TIA 101 shown in FIG. 4 further includes an input stage amplifier 4 connected between the terminal PIN and the input terminal Y of the inverting amplifier 1, and a resistor R _OUT as a load of the input stage amplifier 4. .

The input stage amplifier 4 is an amplifier circuit whose input impedance is lower than that of the feedback resistance type TIA. Specifically, the input stage amplifier 4 amplifies a signal (input current I _IN ) from the terminal PIN input to the source electrode as the first main electrode, with the gate electrode as the control electrode grounded in an alternating manner. The amplifier circuit includes a transistor that outputs to the input terminal Y of the inverting amplifier 1 from the drain electrode as the second main electrode. Examples of such an amplifier circuit include a grounded gate type TIA and a regulated cascode type (RGC type) TIA as shown in FIG.

As shown in FIG. 4, in the TIA 101, the current I _IN input to the terminal PIN branches into a current I _ROUT and a current I _INX flowing through the resistor R _OUT , and the current I _INX flows into the feedback resistance type TIA in the _subsequent stage. Thus, the TIA for converting the input current I _IN into a voltage and amplifying it has a two-stage configuration. The circuit configuration in which the TIA has a two-stage configuration shown in FIG. 4 is the same as the conventional TIA disclosed in Non-Patent Document 2 described above.

The TIA 101 is different from the conventional TIA disclosed in Non-Patent Document 2 in that the TIA 100 according to the first embodiment is used as the subsequent feedback resistance type TIA.
In the TIA 101, when the transimpedance gain of the TIA 100 in the subsequent stage is set to the same value as the gain of the feedback resistance type TIA in the subsequent stage of the TIA in Non-Patent Document 2, the impedance of the subsequent stage as viewed from the node Y (input impedance of the TIA 100) is It becomes lower than the input impedance of the feedback resistance type TIA in the latter stage of the TIA of Non-Patent Document 2. Therefore, the ratio of the current I _INX input to the TIA 100 to the current I _ROUT flowing through the resistor R _OUT is larger than that of the TIA of Non-Patent Document 2. That is, the current input to the feedback resistance type TIA in the subsequent stage is larger in the TIA 101 according to the second embodiment than in the TIA of Non-Patent Document 2. As a result, the TIA 101 according to the second embodiment can output a voltage signal larger than the TIA of the conventional non-patent document 2 from the terminal POUT.

  Further, in the TIA 101, since the input impedance viewed from the input terminal PIN is determined by the input stage amplifier 4 composed of the gate-grounded TIA (or the regulated cascode type TIA), it is compared with a circuit composed only of the feedback resistance type TIA. As a result, bandwidth degradation does not occur.

  As described above, according to the TIA 101 according to the second embodiment, in the TIA having a two-stage configuration in which the feedback resistance type TIA is combined with the grounded gate TIA or the regulated cascode type TIA having a lower input impedance than the feedback resistance type TIA. Since the TIA 100 according to the first embodiment is applied as the feedback resistance type TIA, it is possible to realize a TIA having a higher gain than the conventional two-stage TIA without degrading the band. It becomes.

<< Embodiment 3 >>
FIG. 6 is a diagram illustrating a configuration of the TIA according to the third embodiment.
A TIA 102 shown in the figure has a differential configuration of the TIA 100 according to the first embodiment. That is, the TIA 102 is a TIA having a differential configuration that converts a pair of current signals input to the terminals PINp and PINn into a pair of voltage signals and outputs them from the terminals POUTp and POUTn, respectively.

Specifically, the TIA 102 includes a differential amplifier 1X that inverts and amplifies the difference between a pair of signals input to the terminal PINp and the terminal PINn and outputs the differential signal as a differential signal. In addition, the TIA 102 has two sets of circuit blocks that are a set of a voltage follower 2, a current mirror circuit 3, a current source I _C2 as a load, a feedback resistor R _FB1, and a feedback resistor R _FB2 .

The signal output from the inverting output terminal (−) of the differential amplifier circuit 1X is one circuit block composed of transistors M1A, M2A, M3A, current sources I _{C1_A} , I _{C2_A} , and feedback resistors R _{FB1_A} , R _{FB2_A.} The signal output from the non-inverting output terminal (+) of the differential amplifier circuit 1X is composed of transistors M1B, M2B, M3B, current sources I _{C1_B} , I _{C2_B} , and feedback resistors R _{FB1_B} , R _{FB2_B.} To the other circuit block.

  According to the TIA 102 having the differential configuration according to the third embodiment, it is possible to achieve both high gain and wideband characteristics, similar to the TIA 100 according to the first embodiment.

  Further, according to the TIA 102 having a differential configuration, it is possible to remove in-phase noise, so that it is easy to design a power supply terminal and a ground terminal in a high frequency band.

<< Embodiment 4 >>
FIG. 7 is a diagram illustrating a configuration of the TIA according to the fourth embodiment.
A TIA 103 shown in the figure is a differential configuration of the TIA 101 according to the second embodiment.

Specifically, the TIA 103 includes a differential input stage amplifier 4X and two resistors R _{OUT_A} and R _{OUT_B} as loads of the differential input stage amplifier 4X in addition to the circuit configuration of the TIA 102 according to the third embodiment. Is provided. The differential input stage amplifier 4X is composed of a TIA provided for each of the terminals PINp and PINn and having an input impedance lower than that of the feedback resistance type TIA.

FIG. 8 is a diagram illustrating an example of the differential input stage amplifier 4X.
As shown in FIG. 8, the differential input stage amplifier 4X receives a signal from a terminal PINp and uses a resistor R _{OUT_A} as a load, and has a _common gate TIA composed of a transistor M7A and a current source I _{C3_A} . It includes a transistor M7B and a grounded-gate type TIA composed of a current source I _{C3 — B} that receives a signal from the terminal PINn and uses a resistor R _{OUT — B} as a load. The drain electrode of the transistor M7A constituting one gate-grounded TIA is connected to the inverting input terminal (−) of the differential amplifier circuit 1X, and the drain electrode of the transistor M7B constituting the other gate-grounded TIA is differentially connected. It is connected to the inverting input terminal (+) of the amplifier circuit 1X.

According to the TIA 103 having the differential configuration according to the fourth embodiment, it is possible to realize a high gain TIA without degrading the band, similarly to the TIA 101 according to the second embodiment.
Further, according to the TIA 103 having a differential configuration, it is possible to remove in-phase noise, so that it is easy to design a power supply terminal and a ground terminal in a high frequency band.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, in the above-described embodiment, the case where the TIAs 100 to 103 are realized by a CMOS process has been illustrated, but may be realized by other semiconductor processes such as a bipolar process or a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. For example, the voltage follower 2 may be realized by an emitter follower instead of a source follower.

  In the above embodiment, the current mirror circuit 3 is configured by two P-channel MOS transistors M2 and M3. However, if a current corresponding to the current of the voltage follower 2 can be generated, The circuit configuration of the mirror circuit 3 and the types of transistors constituting the current mirror circuit 3 are not limited to the above example.

In the above embodiment, for the sake of simplicity, the input impedance of the inverting amplifiers 1 and 1X having the gain “−A” is sufficiently high, and the current does not flow into the input terminals of the inverting amplifiers 1 and 1X. _Any configuration is acceptable as long as most of the RF component of the input current I _IN flows into the feedback resistor R _FB1 . For example, the input stage circuit of the inverting amplifier 1 has a circuit configuration using a bipolar transistor in which the base electrode is connected to the terminal PIN and the emitter electrode is grounded, and a slight base current is applied to the base electrode (the input terminal of the inverting amplifier). Even when a negative circuit flows in or when a bypass circuit for flowing a direct current component of the input current I _IN is separately provided in the input stage of the inverting amplifier 1, the same effect as in the above embodiment can be expected.

  Further, in the second and fourth embodiments, the case where the grounded gate type TIA and the regulated cascode type TIA are used as the input stage amplifiers 4 and 4X is exemplified. However, the gate electrode (base electrode) is grounded in an alternating manner, and the source electrode As long as the amplifier circuit includes a transistor that amplifies the signal input from the (emitter electrode) and outputs the signal from the drain electrode (collector electrode), the circuit example is not limited to the above example.

  Moreover, in the said embodiment, although the case where TIA100-103 were mounted in the optical receiver of an optical communication system was illustrated, it is not restricted to this, A current signal is converted into a voltage signal like receiving apparatuses, such as a radio | wireless communications system. Any device that needs to be converted into an amplifier and amplified can be similarly applied.

DESCRIPTION OF SYMBOLS 100,101,102,103 ... TIA, 1 ... inverting amplifier circuit, 1A ... common source amplifier circuit, 1B ... CMOS inverter circuit, 2 ... voltage follower, 3 ... current mirror circuit, 4 ... input stage amplifier, 4X ... differential type input stage amplifier, pIN, POUT, PINp, PINn , POUTp, POUTn ... terminal, M1~M7, M1A~M3A, M1B~M3B, M7A , M7B ... _{transistors, R FB1, R FB2, R} FB1_A, R FB1_B, R _{FB2_A} , R _{FB2_B} ... feedback resistance, R _OUT , R _{OUT_A} , R _{OUT_B} ... load resistance, I _C1 , I _C2 , I _{C1_A} , I _{C1_B} , I _{C2_A} , I _{C2_B} ... current source.

Claims (8)

A first terminal and a second terminal;
An inverting amplifier for inputting a signal from the first terminal;
A voltage follower for inputting the signal output from the inverting amplifier;
A current generation circuit that generates a current according to a current flowing through the voltage follower and outputs the current to the second terminal;
A first load connected to the second terminal;
A first feedback resistor connected between the first terminal and an output terminal of the voltage follower;
A transimpedance amplifier comprising a second feedback resistor connected between the output terminal of the voltage follower and the second terminal. The transimpedance amplifier according to claim 1,
The voltage follower is
A second load having one end connected to a fixed potential node and the other end connected to an intermediate node to which the first feedback resistor and the second feedback resistor are connected;
A first transistor having a control electrode connected to an output terminal of the inverting amplifier, a first main electrode connected to the intermediate node, and a second main electrode connected to an input terminal of the current generating circuit;
The current generation circuit is a current mirror circuit that multiplies the current supplied from the second main electrode of the first transistor by N (N is an integer of 1 or more) and outputs the current to the second terminal. Transimpedance amplifier. The transimpedance amplifier according to claim 1 or 2,
An input stage amplifier connected between the first terminal and the input terminal of the inverting amplifier;
The input stage amplifier is:
The control electrode is grounded in an AC manner, and includes a second transistor that amplifies the signal of the first terminal input to the first main electrode and outputs the signal from the second main electrode to the input terminal of the inverting amplifier. Transimpedance amplifier. The transimpedance amplifier according to claim 3,
The transimpedance amplifier, wherein the input stage amplifier is a grounded-gate amplifier circuit. The transimpedance amplifier according to claim 3,
The transimpedance amplifier, wherein the input stage amplifier is a regulated cascode amplifier circuit. The transimpedance amplifier according to any one of claims 1 to 5,
The transimpedance amplifier, wherein the inverting amplifier is a grounded source amplifier circuit. The transimpedance amplifier according to any one of claims 1 to 5,
The transimpedance amplifier, wherein the inverting amplifier is a CMOS inverter circuit. The transimpedance amplifier according to any one of claims 1 to 7,
Two sets of circuit blocks each including the voltage follower, the current generation circuit, the first load, the first feedback resistor, and the second feedback resistor;
The inverting amplifier is a differential amplifier circuit that inverts and amplifies a pair of differential signals,
The signal output from the inverting output terminal of the differential amplifier circuit is input to one of the circuit blocks,
A transimpedance amplifier, wherein a signal output from a non-inverting output terminal of the differential amplifier circuit is input to the other circuit block.

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