JP2018029285A - Communication device, semiconductor device, communication system and initialization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication device capable of reducing the number of used terminals, and of performing initialization processing by limiting a target in a case where a predetermined event occurs in a system mounting itself, and to provide a semiconductor device, a communication system and an initialization method.SOLUTION: Provided is a communication device 12 including a communication interface unit RXD/TXD that can switch between a transmission mode of transmitting communication data and a reception mode of receiving communication data. The communication device 12 includes a monitoring unit 20 that monitors the communication data received in the reception mode, and issues an initialization signal for initializing the communication device 12 in a case where a predetermined condition is satisfied in the communication data to be received.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a communication device, a semiconductor device, a communication system, and an initialization method, in particular, a serial transmission communication device, a communication system, and a semiconductor device mounted on a microcontroller unit (hereinafter referred to as “MCU”) as a semiconductor device. It relates to the initialization method.

  The MCU refers to an embedded microprocessor in which a computer system is integrated on one integrated circuit. In recent years, with the advancement and complexity of electronic devices such as game devices, car navigation systems, printers, and portable information terminals, the MCU is often incorporated into various electronic devices. Such an embedded MCU is usually mounted on a user board called a target system. One problem is how to efficiently develop software for operating the target system.

  As such a software development support tool, a debugging tool called ICE (In Circuit Emulator) has been widely used, but in recent years, an on-chip emulator has become mainstream. The on-chip emulator is a general term for devices that execute program debugging in a state where an MCU or the like is mounted on a printed circuit board.

  The on-chip emulator is connected to a microcomputer (PC), and the on-chip emulator is controlled via this PC. On the other hand, a debug circuit is mounted inside an MCU or the like to be debugged, and debugging work is performed using debug information collected by the debug circuit. The debug information is sent to the on-chip emulator via the debugging interface, and is transferred from the on-chip emulator to the PC. That is, communication via some communication means is performed between the on-chip emulator (debug tool) and the MCU (target system).

  Conventionally, Patent Document 1 is known as a document that refers to communication between a debug tool and a target system in a debug system. In the debug system disclosed in Patent Document 1, the serial data signal corresponding to the transmission data for debugging transmitted from the target system to the debug tool and the run / break state signal indicating the state of the CPU (Central Processing Unit) are merged. Thus, a circuit for generating an output signal is provided, and the output signal is output via one debug terminal. In Patent Document 1, according to such a debugging system, the transmission of a CPU run / break status signal and the transmission of debugging data can be performed in a single communication line. It is assumed that it is not necessary to provide a debugging terminal for outputting a status signal.

JP 2007-172648 A

  Here, with reference to FIG. 8, the debug system 2 according to the comparative example will be described focusing on communication between the debug tool and the target system. As shown in FIG. 8, the debug system 2 includes an on-chip emulator 100 as a debug tool and an MCU 50 as a target system. In FIG. 8, illustration of a PC connected to the on-chip emulator 100 is omitted.

  The on-chip emulator 100 includes a communication device 102, a clock source (indicated as “OSC” in FIG. 8) 104, and a CPU 106. The communication device 102 is a part that performs communication with the MCU 50. The connector CN3 connected to the communication device 102 is connected to the TXD terminal for data signal transmission, the RXD terminal for reception, the CLK terminal for clock signal transmission, and the MCU 50. A RESET terminal for transmitting a reset signal, a VCC terminal for power supply, and a VSS terminal are arranged. The clock source 104 includes an oscillation circuit and is a part that generates a clock signal CLKe having a frequency f1 supplied to the communication apparatus 102. The CPU 106 is a part that performs overall control of the on-chip emulator 100.

  On the other hand, the MCU 50 includes a communication device 52 and a CPU 54. The communication device 52 is a part that performs communication with the on-chip emulator 100 opposite to the communication device 102. The connector CN4 has an RXD terminal for receiving a data signal, a TXD terminal for transmitting, a CLK terminal for receiving a clock signal, A RESET terminal for receiving a reset signal for the MCU 50, a VCC terminal for power supply, and a VSS terminal are arranged.

  Communication between the on-chip emulator 100 and the MCU 50 in the debug system 2 is performed by synchronous communication using the clock signal CLKe from the clock source 104 as a synchronous clock. Therefore, between the on-chip emulator 100 and the MCU 50, there are two data signal lines for transmitting and receiving data signals bidirectionally, and a signal line for supplying the clock signal CLKe from the on-chip emulator 100 to the MCU 50. One signal line and one signal line for transmitting a reset signal for resetting the MCU 50 are required. As a result, the MCU 50 also needs terminals corresponding to these signal lines. However, these terminals are dedicated terminals for debugging and are not used in actual machines such as electronic devices in which the MCU 50 is incorporated.

  On the other hand, with the recent increase in functionality of MCUs and the like, the number of terminals that are actually used such as I / O terminals in electronic devices and the like tends to increase. For this reason, it can be considered that the secondary function of the I / O terminal is used for debugging, but in this case, the function as the I / O terminal of the shared I / O terminal cannot be debugged. In this way, it is required to reduce the number of terminals used for debugging as the number of terminals actually used increases. Therefore, as described above, it is required to minimize the number of terminals used only in MCU software development and system development (debugging, etc.).

  On the other hand, in the system development of the MCU 50 using the on-chip emulator 100, a process for resetting (initializing) the MCU 50 is necessary from the viewpoint of efficient debugging work and the like. Further, with respect to the reset processing in this case, there is a case where not only the entire MCU 50 but also a necessary circuit block is partially reset. The debug system 2 is also configured so that a reset signal RESET can be issued from the on-chip emulator 100 to the MCU 50 according to the determination of the CPU 106.

  However, the reset signal RESET in the debug system 2 according to the comparative example is a signal that resets the entire MCU 50. Therefore, for example, it is not possible to reset only the communication device 12 while retaining data stored in a memory or the like associated with the debug circuit of the MCU 50.

  Under the circumstances as described above, the number of terminals used for debugging is also reduced in the debug system disclosed in Patent Document 1. However, Patent Document 1 does not mention partial reset processing after reducing the number of terminals.

  The present invention has been made in order to solve the above-described problems, and reduces the number of terminals to be used and performs initialization processing by limiting a target when a predetermined event occurs in an installed system. An object of the present invention is to provide a communication device, a semiconductor device, a communication system, and an initialization method that can be performed.

  The communication device according to the present invention is a communication device including a communication interface unit capable of switching between a transmission mode for transmitting communication data and a reception mode for receiving communication data, the communication data received in the reception mode. And a monitoring unit that issues an initialization signal to initialize itself when a predetermined condition is satisfied in the communication data to be monitored and received.

  A semiconductor device according to the present invention includes the communication device described above, a device connection interface unit for connecting to another device, and a control unit for controlling the other device to be connected.

  A communication system according to the present invention is a communication system including the above-described semiconductor device and a counter device including a counter communication device connected to the communication interface unit via a communication line, wherein the counter device includes the communication device. When a predetermined event is detected in the system, communication data of the predetermined condition is transmitted from the opposite communication device to the communication device via the communication line.

  The initialization method according to the present invention includes a communication interface unit capable of switching between a transmission mode for transmitting communication data to an opposing device via a communication line and a reception mode for receiving communication data from the opposite device. A communication device including a monitoring unit that issues an initialization signal when a predetermined condition is satisfied in the communication data that monitors and receives the communication data received from the opposite device in the reception mode An initialization method using a device, wherein when the opposite device detects a predetermined event, the opposite device transmits communication data having a predetermined polarity to the communication device via the communication line. And the communication device receives the initialization signal when the communication data of the predetermined polarity is received continuously for a predetermined period. Is to send toward said initialization signal to the counter device is initialized more itself.

  According to the present invention, a communication device, a semiconductor device, and a communication device capable of performing initialization processing by limiting a target when a predetermined event occurs in an installed system while reducing the number of terminals used. A system and initialization method can be provided.

1 is a block diagram showing a debugging system according to a first embodiment. It is a figure which shows an example of the frame structure in the asynchronous communication which concerns on embodiment. It is a circuit diagram showing an example of a monitoring circuit concerning a 1st embodiment. It is a timing chart which shows the waveform of each node of the monitoring circuit concerning a 1st embodiment. It is a circuit diagram which shows an example of the pull-up circuit and pull-down circuit of the RXD / TXD terminal which concern on embodiment. It is a circuit diagram which shows an example of the monitoring circuit which concerns on 2nd Embodiment. It is a timing chart which shows the waveform of each node of the monitoring circuit concerning a 2nd embodiment. It is a block diagram which shows the debugging system which concerns on a comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
A communication device, a semiconductor device, a communication system, and an initialization method according to the present embodiment will be described with reference to FIGS. FIG. 1 shows a debugging system 1 as a communication system according to the present embodiment, and shows an MCU 10 as a semiconductor device according to the present embodiment together with an on-chip emulator 100. In the debug system 1 (communication system) according to the present embodiment, asynchronous communication (UART, asynchronous communication) is adopted for communication between the on-chip emulator 100 and the MCU 10. Using data signal lines, in addition to initialization of communication devices by hardware reset, initialization by software reset is realized.

  The on-chip emulator 100 includes a communication device 102, a clock source 104 (denoted as “OSC” in FIG. 1) having a frequency f1 (communication frequency), and a CPU.

  The communication device 102 is a communication device capable of asynchronous communication, and transmits a TXD terminal that transmits communication data arranged in the connector CN1, a RXD terminal that receives the data, a CLK terminal that transmits a clock signal, and a reset signal. It has a RESET terminal, a VCC terminal for supplying power, and a VSS terminal. In asynchronous communication, since one data signal line is shared for transmission and reception, the TXD terminal for data transmission and the RXD terminal for data reception are short-circuited by the connector CN1. In the communication device 102, the CLK terminal for transmitting the clock signal and the RESET terminal for transmitting the reset signal are further short-circuited by the connector CN1 so as to be shared.

  The clock signal CLKe generated by the clock source 104 according to the present embodiment is a clock signal (communication clock signal) used for asynchronous communication in the communication apparatus 102 and is not sent from the CLK terminal to the MCU 10. . The CPU 106 manages and manages the entire on-chip emulator 100.

  On the other hand, the MCU 10 according to the present embodiment includes a communication device 12, a clock source 14 (denoted as “OSC” in FIG. 1) that generates a clock signal CLKi having a frequency f2, a CPU 16, and a monitoring circuit 20. Yes.

  The communication device 12 is an asynchronous communication device built in the MCU 10, and the communication data transmission line and the reception line are shared, and the debugging dedicated terminals in the MCU 10 are reduced. Therefore, the communication device 12 performs communication with the on-chip emulator 100 by switching between the transmission mode and the reception mode. The communication device 12 includes an RXD / TXD terminal for data transmission / reception arranged at the connector CN2, a CLK / RESET terminal for receiving a clock signal and a reset signal (not normally used in the present embodiment), and an on-chip emulator 100. It has a VCC terminal and a VSS terminal for receiving power supply. In the present embodiment, as an example, the power supply VCC of the MCU 10 is a positive power supply, and the power supply VSS is a ground (GND). In this embodiment, each of the power supplies VCC and VSS is supplied from the on-chip emulator 100, but the power supply of the MCU 10 does not necessarily need to be supplied from the on-chip emulator 100, and directly to the MCU 10 from the outside. It may be supplied.

The clock signal CLKi generated by the clock source 14 according to the present embodiment is a communication clock signal used for asynchronous communication in the communication device 12. Therefore, in this embodiment, the frequency f2 (communication frequency) of the clock source 14 is the same as the frequency f1 (communication frequency) of the clock source 104 of the on-chip emulator 100 (f1≈f2).
Of course, the present invention is not limited to this, and the communication frequency f2 of the MCU 10 may be different from the communication frequency f1 of the clock source 104. Further, the CPU 16 manages and manages the entire on-chip emulator 100.

  The monitoring circuit 20 receives the reception data signal RD from the communication device 12, receives the clock signal CLKi from the clock source 14, monitors the reception data signal RD based on these signals, and performs communication when a predetermined condition is satisfied. A reset signal RST for resetting (initializing) the device 12 is generated. In FIG. 1, for convenience, the communication device 12 and the monitoring circuit 20 are illustrated separately, but both are circuits that operate substantially integrally, and the monitoring circuit 20 may be built in the communication device 12. . Details of the monitoring circuit 20 will be described later.

  Next, the interface of the communication device 12 in the MCU 10 will be described in more detail. In the communication device 12 according to the present embodiment, asynchronous transmission is adopted as described above to share (bidirectional) the transmission data signal line and the reception data signal line, and one data signal line is used. By doing so, the number of terminals dedicated for debugging in the MCU 10 is reduced. Hereinafter, this one data signal line may be referred to as a UART IF (Interface). The monitoring circuit 20 according to the present embodiment can reset the MCU 10 from the on-chip emulator 100 by software using the UART IF.

  In the present embodiment, the CLK terminal and the RESET terminal are further shared to save the number of debug dedicated terminals of the MCU 10 and the number of I / O (Input / Output) terminals used in the actual machine in which the MCU 10 is mounted is reduced. Increasing. However, for further reasons of saving terminals and the reasons described below, the signal lines between the on-chip emulator 100 and the MCU 10 are increased from two (RXD / TXD (UART IF) line, CLK / RESET line) to UART. Only one IF is used.

  That is, in general, a filter for noise removal or power-on reset is often inserted into the RESET terminal, and thus the speed of a signal applied to the RESET terminal is limited. As a result, if the CLK terminal and the RESET terminal are shared, the clock signal sent from the CLK terminal cannot be increased in speed, and the significance of using synchronous communication is diminished. Therefore, in this embodiment, only one UART IF that does not require transmission of a clock signal is used as a communication line, and a reset request from the on-chip emulator 100 to the MCU 10 is performed using this UART IF. ing. The MCU 10 that has recognized the reset request resets itself. Along with its own reset, the fact that the reset request has been recognized may be returned to the on-chip emulator 100.

  Next, a frame configuration used in asynchronous communication will be described with reference to FIG. FIG. 2 is a diagram showing the configuration of one frame (denoted as “serial data” in FIG. 2) adopted in asynchronous communication together with an internal clock (communication clock). As shown in FIG. 2, in asynchronous communication, the data sent at one time is 7 bits or 8 bits (in FIG. 2, it is 8 bits from D0 to D8), and the start bit and stop bit are set before and after this data. By being sandwiched, one transmission / reception is performed. A set of arrays from the start bit to the stop bit is called “1 frame” (or “1 character”).

  The start bit is fixed at 1 bit, whereas the stop bit is 1 bit or 2 bits (2 bits in the example shown in FIG. 2), and the signal has a polarity different from that of the start bit. That is, if the start bit is low level (hereinafter “L”), the stop bit is high level (hereinafter “H”), and if the start bit is H, the stop bit is L. A parity bit may be added after the data bits (D0 to D8). In the following description, the start bit is L and the stop bit is H.

  The internal clock in FIG. 2 represents the clock signal CLKi in FIG. In this embodiment, as described above, no clock signal is exchanged between the on-chip emulator 100 and the MCU 10. Therefore, as shown in FIG. 1, the on-chip emulator 100 and the MCU 10 are individually provided with clock sources (clock source 104 and clock source 14).

  In asynchronous communication, first, when the transmitting side sends a start bit, the receiving side discriminates the polarity of the received data (received data signal RD) at the cycle of the internal clock, and when it detects that it has changed from H to L, it performs a transmission / reception operation To start. The width of 1 bit of the reception data signal RD is set in advance by the number of cycles of the internal clock. The number of cycles is the transmission / reception speed, that is, the baud rate. It is necessary to match this baud rate between the transmission side and the reception side.

Next, a case where a reset (initialization) process is required in the communication device 12 will be described. In asynchronous communication, there is no transmission of a clock signal. Therefore, both devices that perform communication must have clock sources (oscillation circuits). In order for normal communication to be performed, the frequencies of both oscillation circuits need to match, so both oscillation circuits are required to have high accuracy, for example, accuracy within 5% in terms of frequency fluctuations. However, even if the accuracy of the frequency of the oscillation circuit is 5%, as shown in FIG. 2, one frame of asynchronous communication is about 10 bits. In the vicinity, it exceeds 50%.
If the frequency deviation exceeds 50%, there is a possibility that the reception side may miss the received data. Therefore, it is necessary to monitor the deviation of the clock signal and correct the baud rate whenever the deviation of the clock signal is outside the allowable range.

  Further, although the above baud rate correction may be performed in a relatively small range, there is a case where the baud rate itself needs to be reset. For example, there is a case where noise is mixed in the baud rate setting register and the register value of the baud rate setting register changes. In such a case, it is assumed that the baud rate is greatly deviated between the on-chip emulator 100 and the MCU 10 and communication between the on-chip emulator 100 and the MCU 10 is no longer possible.

  Furthermore, since the transmission line and the reception line are shared in asynchronous communication, a state (state) indicating which is being received and which is being transmitted, a BUSY (busy) state indicating that processing is being performed, It has a state such as a READY (ready) state indicating response waiting. However, if the state machine that manages this state is shifted or if the state in the state machine is unknown for some reason, the devices at both ends of the UART IF may be unable to recognize each other. is assumed.

  However, in the debug system 1 according to the present embodiment, since the connection between the on-chip emulator 100 and the MCU 10 is one UART IF, when the above situation occurs, the on-chip emulator 100 and the MCU 10 There is no means to recover communication between.

  As one of the means corresponding to the above case, it is also conceivable to use a watchdog timer which is one means for monitoring the communication state. In the monitoring using the watchdog timer, a signal having a constant cycle is transmitted from the on-chip emulator 100 to the MCU 10 in order to monitor the normal operation of the communication state, and the watchdog timer built in the MCU 10 is reset. When the communication status becomes abnormal and the MCU 10 can no longer send a signal within a certain time, the watchdog timer will time up, and when this time is up, the on-chip emulator 100 issues a reset instruction to the MCU 10 to initialize it. .

  However, in the monitoring by the watchdog timer described above, the release process must be performed by regular communication. However, the release process cannot be performed in a state where the communication means is not established. There is also a problem that the on-chip emulator 100 cannot determine where the reset is applied. Furthermore, in general, monitoring by a watchdog timer has a problem that the monitoring time is long, and only the entire MCU 10 is reset, and the process of resetting only the communication device 12 cannot be performed.

  If simply resetting, it is possible to use the CLK / RESET terminal (see FIG. 1), which is a hardware reset provided in the MCU 10. However, this hardware reset is also a reset of the entire MCU 10. For example, when an important parameter is stored in a RAM (Random Access Memory) or the like included in the MCU 10 in a debugging process involving communication via the UART IF, resetting the entire MCU 10 is effective in debugging. Is greatly impaired.

  On the other hand, in the MCU 10 according to the present embodiment, it is possible to reset only the communication device 12, so that the debugging efficiency can be improved. Further, since reset processing is performed using the UART IF, it is possible to omit connection of the reset terminal of the on-chip emulator 100. In the present embodiment, an example in which only the communication device 12 is reset in the reset process of the MCU 10 will be described. However, the present invention is not limited to this, and other circuits in the MCU 10 may be reset. A reset signal may be transmitted to the on-chip emulator 100.

  Next, the monitoring circuit 20 according to the present embodiment will be described in more detail with reference to FIGS. 3 and 4. FIG. 3 is a circuit diagram showing an example of the monitoring circuit 20, and FIG. 4 is a timing chart showing operation waveforms at each node of the monitoring circuit 20. As shown in FIG. The monitoring circuit 20 mounted on the MCU 10 monitors the reception data signal RD of the UART IF, and when an initialization (reset) instruction (reset instruction signal) is issued from the on-chip emulator 100 when a predetermined condition is satisfied. It has a function of determining and mainly initializing the communication device 12.

  As shown in FIG. 3, the monitoring circuit 20 includes a counter 22, a flip-flop 24, a comparator 26, an AND circuit 28, an inverter 30, and OR circuits 32, 34, and 36. The reception data signal RD received via the RXD / TXD terminal shown in FIG. 1 is input to the inverting input of the AND circuit 28 and the OR circuits 32 and 34. The clock signal CLKi described above is input to the counter 22 and the flip-flop 24. When a predetermined condition is satisfied in monitoring the received data signal RD, the inverter 30 outputs a reset signal RST that resets the communication device 12. In the present embodiment, the reset signal RST is valid at L (active L).

  The counter 22 is a counter that monitors a continuous period of a predetermined polarity (this polarity is L in the present embodiment) in the reception data signal RD, and is a 12-bit counter as an example in the present embodiment. In the present embodiment, this continuous period is monitored by the number of pulses of the clock signal CLKi input to the clock input of the counter 22. A reception data signal RD to be monitored is input to the UP input of the counter 22, and a clear signal for the count value of the counter 22 is input to the R (synchronization) input.

  The comparator 26 compares the count signal (a signal indicating the count value) from the counter 22 with a predetermined set value, and issues a count end signal when the count value reaches the set value. In FIG. 3, the count signal of the counter is indicated by a symbol CV, a preset set value of the count value is indicated by a symbol OFref, and the count end signal is indicated by a symbol CE. In the present embodiment, the polarity of the count end signal CE is set to H (active H). The set value OFref is set to 4096, for example. That is, in the present embodiment, the reset signal RST is issued when the L of the reception data signal RD continues for 4096 periods or more of the clock signal CLKi.

  The flip-flop 24 stores the comparison result by the comparator 26. A reset signal ICE RST input to the reset input R of the counter 22 and the reset input R of the flip-flop 24 is a signal for resetting the monitoring circuit 20.

  The AND circuit 28 sets the Q output of the flip-flop 24 to H when the reception data signal RD is L and the count end signal CE is H. A complementary signal (RST_BAR) of the reset signal RST is output from the Q output of the flip-flop 24. The Q output of the flip-flop 24 is inverted by the inverter 30 and input to the communication device 12 as the reset signal RST (see FIG. 1). The OR circuit 36 maintains H by feeding back the Q output of the flip-flop 24 and taking a logical sum with the count end signal CE.

  The OR circuit 34 calculates the logical sum of the received data signal RD and the Q output of the flip-flop 24, thereby fixing the input value of the UP input of the counter 22 when the count end signal CE becomes valid. The OR circuit 32 calculates the logical sum of the received data signal RD and the Q output of the flip-flop 24, so that when the count end signal CE becomes valid, the counter 22 clear signal is supplied to the R (synchronous) input of the counter 22. Enter.

  Next, the operation of the monitoring circuit 20 will be described in more detail with reference to the timing chart shown in FIG. As described above, the communication device 12 recognizes that the start bit is received when a transition from H to L is detected in the signal (received data signal RD) input to the RXD / TXD terminal of the UART IF. Reception processing is performed until stop bit H is detected.

  The monitoring circuit 20 monitors a signal (reset instruction signal) indicating a reset instruction from the on-chip emulator 100 while receiving the reception data signal RD. That is, when it is detected that the reception data signal RD has become L, the count value of the counter 22 is incremented by one. As described above, the counting by the counter 22 is performed by counting the number of pulses of the clock signal CLKi. In the present embodiment, the clock signal CLKi is used as a clock (communication clock such as a baud rate counter clock or a sampling clock) used for communication of the communication device 12. However, the present invention is not limited to this, and a clock by a clock source having a different frequency independent of the communication clock may be used. Since this circuit automatically stops when the clock of the communication device itself stops, a clock of another system is more preferable.

  In the operation example shown in FIG. 4, since the transition of the reception data signal RD from H to L is detected at time t1, the counter 22 starts counting and the count value CV is counted up. As long as the reception data signal RD is L, this count-up is continued. However, since the reception data signal RD transits from L to H at the time t2 during the counting, the counter 22 is reset (cleared), the count value is discarded and returned to 0 at the time t3. When a normal data signal is received by the UART IF, the counter 22 is always cleared.

  Since the reception data signal RD again changes from H to L at time t4, the counting by the counter 22 is resumed. Since the count value reaches the set value OFref = 4096 at time t5, the count end signal CE changes from L to H (is activated). In the next clock cycle, the Q output of the flip-flop 24 is set to H, the reset signal RST changes to L, and the reset signal RST becomes valid (activated). Thereafter, the counter is cleared to 0 at time t6, and the reception data signal RD becomes H at time t7. Accordingly, the reset signal RST is set to H (deactivated).

  In the present embodiment, in the received data signal RD, the reset signal RST is issued when L for 4096 periods of the clock signal CLKi is continued (indicated as the detection time Tp in FIG. 4). ing. However, the setting of the detection time Tp is not limited to this, and may be more or less than 4096 periods depending on design conditions and the like. However, the detection time Tp must be at least longer than the time of one frame of the UART IF so that it can be distinguished from a normal data signal.

  For example, when the frequency of the clock signal CLKi is set to 32768 Hz, which is the same as that of a clock or the like, for example, the detection time Tp needs to be 125 ms (millisecond) or more (4096/32768 = 125 ms). Incidentally, if the detection time Tp is one frame, one frame is 125 ms, and if one frame is 12 bits as shown in FIG. 2, the baud rate in the UART IF is 96 (= 12 / 0.125) bps (bit per second).

  As described above in detail, in the debug system 1 according to the present embodiment, the on-chip emulator 100 detects a predetermined event (for example, an event in which the MCU 10 cannot be recognized) and needs to be reset (initialized). If the determination is made, the communication device 102 forcibly fixes the transmission data signal SD of the UART IF to L and issues a reset instruction signal, so that the MCU 10 Can be reset (initialized). The initialization referred to in the present embodiment includes setting of the baud rate.

  Hereinafter, the relationship between the reset instruction signal transmitted from the on-chip emulator 100 via the UART IF and the processing in the MCU 10 will be supplemented. First, when the MCU 10 is in a reception waiting state, when receiving an L-fixed reset instruction signal from the on-chip emulator 100, the MCU 10 recognizes that the reception data signal RD has arrived, but does not receive the H stop bit (see FIG. 2). So treat it as a framing error. Therefore, the reset instruction signal is not mistaken for a data signal.

  On the other hand, when the reset instruction signal is received when the MCU 10 is in the transmission state, there is no problem if the transmission data is L, but when the transmission data is H, it collides with the reset instruction signal L. As a countermeasure in this case, as shown in FIG. 5A, it is conceivable that the RXD / TXD terminal is pulled up to a high potential side (VDD side in the present embodiment) by a pull-up resistor Ru. Since the driving capability of H by pull-up is relatively low, the L input from the on-chip emulator 100 is superior, and there is no problem in receiving the reset instruction signal.

  The processing of the RXD / TXD terminal of the MCU 10 is not limited to the above pull-up, and as shown in FIG. 5 (b), the pull-down resistance Rd may be used to pull down to the low potential side (VSS side in this embodiment). . In this case, it is possible to detect that the connection between the on-chip emulator 100 and the MCU 10 has been disconnected (disconnected) by performing pull-down processing on the RXD / TXD terminal. That is, when communication in the UART IF is in an idle state, the MCU 10 always receives H, but if the communication line between the on-chip emulator 100 and the MCU 10 is disconnected, the RXD / TXD terminal sticks to L, and the detection time Tp After the elapse, the MCU 10 is forcibly reset (initialized). By this unintended reset, the on-chip emulator 100 can recognize the possibility of disconnection in the communication line.

[Second Embodiment]
The monitoring circuit 20a according to the present embodiment will be described with reference to FIGS. FIG. 6 is a circuit diagram showing the monitoring circuit 20a, and FIG. 7 is a timing chart showing operation waveforms at each node of the monitoring circuit 20a. The monitoring circuit 20a is obtained by adding a noise canceller (disturbance canceling circuit) including a flip-flop 38 and an AND circuit 40 in order to improve resistance to disturbance (noise) in the monitoring circuit 20 described above. Accordingly, the same components as those of the monitoring circuit 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 6, the received data signal RD is input to the D input of the added flip-flop 38, and the clock signal CLKi is input to the clock input via the inverter 42. Therefore, the flip-flop 38 operates at the falling edge of the clock signal CLKi. Further, the Q output of the flip-flop 38 is input to the added AND circuit 40. The added AND circuit 40 takes the logical product of the Q output and the received data signal RD and inputs the result to the OR circuits 32 and 34. In other words, in the monitoring circuit 20 shown in FIG. 3, the reception data signal RD is directly input to the OR circuits 32 and 34, whereas in the monitoring circuit 20a, the reception data processed by the flip-flop 38 and the AND circuit 40 is displayed. The signal RD is input to the OR circuits 32 and 34.

  Next, the operation of the monitoring circuit 20a will be described in more detail with reference to FIG. First, with reference to FIG. 7A, the operation of the monitoring circuit 20 that does not have a measure against disturbance will be described. In the example shown in FIG. 7A, the counter 22 starts counting when the reception data signal RD transitions from H to L at time t8. However, a disturbance N (beard) occurs at time t10, which is the sampling timing, and the counter 22 is reset because the reception data signal RD has instantaneously returned to H, and the count is restarted from 0 when it becomes L again. ing. Thereafter, at time t11, the count value reaches the set value OFref, and the count end signal CE is generated. Subsequent operations are the same as those in FIG. That is, when no countermeasure is taken against disturbance, the counting by the counter 22 between times t8 and t10 is wasted, and extra time is required until the reset signal RST is issued.

  On the other hand, the influence of the disturbance N can be suppressed in the monitoring circuit 20a according to the present embodiment including the disturbance cancel circuit (noise canceller) including the flip-flop 38 and the AND circuit 40. That is, the flip-flop 38 takes in the received data signal RD when the clock signal CLKi falls at time t9. When the clock signal CLKi rises at time t10 after the next half cycle, the AND circuit 40 calculates the logical product of the Q output of the flip-flop 38 and the received data signal RD. With this operation, the output of the AND circuit 40 becomes H only when both inputs of the AND circuit 40 are H, and the counter 22 is cleared. That is, in the example shown in FIG. 6, L of the received data signal RD is taken in at time t9. Therefore, when the logical product with the received data signal RD is obtained at time t10, the AND circuit 40 outputs L, and as a result the counter 22 Is not cleared.

  In this embodiment, the noise countermeasure until the reset becomes effective has been described as an example. However, after the reset becomes effective by using a similar countermeasure circuit, the reset is canceled by noise. It can also be applied to noise countermeasures that suppress this.

  In the above embodiments, the polarities of various signals (for example, the reset signal RST is active L) are described. However, these polarities are merely examples and may be reversed.

1, 2 Debug system 10 MCU
12 Communication device 14 Clock source 16 CPU
20, 20a Monitoring circuit 22 Counter 24 Flip-flop 26 Comparator 28 AND circuit 30 Inverter 32, 34, 36 OR circuit 38 Flip-flop 40 AND circuit 42 Inverter 50 MCU
52 Communication Device 54 CPU
100 On-chip emulator 102 Communication device 104 Clock source 106 CPU
CLKe, CLKi Clock signal CN1, CN2, CN3, CN4 Connector RD Receive data signal Ru Pull-up resistor Rd Pull-down resistor

Claims (12)

A communication device including a communication interface unit capable of switching between a transmission mode for transmitting communication data and a reception mode for receiving communication data,
A communication apparatus including a monitoring unit that monitors the communication data received in the reception mode and issues an initialization signal that initializes itself when a predetermined condition is satisfied in the received communication data. The communication apparatus according to claim 1, wherein the predetermined condition is that communication data having a predetermined polarity is continuous for a predetermined period in the communication data received by the communication interface unit. A first clock source for generating a first clock signal of a first frequency;
The monitoring unit includes a counter for counting the number of the communication data having the predetermined polarity based on the first clock signal in the reception mode, and the number of the communication data having the predetermined polarity counted. And a comparator that compares the predetermined set value with each other, and issues the initialization signal when the counted number of the communication data of the predetermined polarity exceeds the predetermined set value. The communication device according to claim 2. The monitoring unit clears the counter when receiving the communication data having a polarity opposite to the predetermined polarity while counting the number of the communication data having the predetermined polarity by the counter. The communication device according to claim 3. The monitoring unit receives a disturbance unrelated to the communication data having a polarity opposite to the predetermined polarity while the counter is counting the number of the communication data having the predetermined polarity. The communication apparatus according to claim 4, further comprising a disturbance cancel circuit that stops the clearing operation by the counter. The communication method of the communication device is asynchronous communication,
The predetermined condition is that the communication data having a predetermined polarity in the communication data received by the communication interface unit is continuous for a predetermined period. The communication apparatus as described in. The communication apparatus according to claim 6, wherein the predetermined period is longer than a period corresponding to one unit of a frame used in the asynchronous communication. The communication apparatus according to claim 6, further comprising a second clock source that generates a second clock signal having a second frequency used in the asynchronous communication. The predetermined polarity is negative polarity;
The communication interface unit has been subjected to pull-down processing,
The monitoring unit issues the initialization signal even when a disconnection occurs in a communication line connected from the communication interface unit to an opposite communication device facing the communication device. The communication device according to item. The communication device according to any one of claims 1 to 9,
A device connection interface for connecting to other devices;
A control unit for controlling the other device to be connected;
A semiconductor device including: A communication system including the semiconductor device according to claim 10 and a counter device including a counter communication device connected to the communication interface unit via a communication line,
The said opposing apparatus transmits the communication data of the said predetermined condition to the said communication apparatus via the said communication line from the said opposing communication apparatus, when a predetermined event is detected in the said communication system. A communication device including a communication interface unit capable of switching between a transmission mode for transmitting communication data to an opposite device via a communication line and a reception mode for receiving communication data from the opposite device, wherein the reception mode In the initialization method using the communication device including a monitoring unit that monitors the communication data received from the opposite device and issues an initialization signal when a predetermined condition is satisfied in the received communication data. And
When the opposite device detects a predetermined event, the opposite device transmits communication data of a predetermined polarity to the communication device via the communication line,
When the communication device continuously receives the communication data of the predetermined polarity for a predetermined period, the communication device initializes itself with the initialization signal and sends the initialization signal to the counter device. Send to the initialization method.