JP2018026485A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce stress at the time of forming a wiring along a chip.SOLUTION: In a semiconductor device where at least a first chip and a second chip are laminated to face each other: the first chip includes a chip body, a first connection part reaching at least the chip body, a second connection part which reaches at least the chip body and serves as an electrical connection destination of the first connection part and an independent wiring which is provided on the first chip via an insulation layer in a state of sandwiching an insulation layer with the chip body and being separated from the first connection part and the second connection part; and the second chip includes a first connection wiring with one end connected to the first connection part and with the other end connected to one end of the independent wiring, and a second connection wiring with one end connected to the other end of the independent wiring and with the other end connected to the second connection part.SELECTED DRAWING: Figure 5

Description

  The invention disclosed in this specification relates to a semiconductor device.

  2. Description of the Related Art Conventionally, a semiconductor device having a multilayer wiring structure and a multilayer wiring board are known (see, for example, Patent Document 1 and Patent Document 2).

JP 2012-4505 A JP 2002-176260 A

  By the way, recently, for example, a structure in which chips of a large-scale integrated circuit (LSI) in which TSV (Through Si Via) is formed is three-dimensionally stacked is known. In such a structure, there is a region where a TSV cannot be formed due to the structure in the chip and design restrictions. In this case, for example, in order to supply power to the stacked chips, it is necessary to form a wiring along the surface of the chip. It is considered that the same problem can also occur in a structure in which a plurality of chips are three-dimensionally stacked, such as pseudo SoC (System On Chip) using TMV (Through Mold Via).

  When the wiring is formed along the chip as described above, it is considered that the chip is deformed by the stress generated in the wiring. If the deformation amount of the chip is large, it may be difficult to stack the chips three-dimensionally. When the wiring is thick or long, the stress generated increases, and the warpage of the wafer increases even if the substrate is in a thick state before being thinned into a chip. When the warpage of the wafer becomes large, it becomes difficult to form bumps on the wiring.

  Further, even when three-dimensional chip stacking is performed, internal stress is applied to the joint, which may reduce the reliability of the semiconductor device.

  Thus, it is considered that various problems occur when wiring is formed along the chip. However, none of these patent documents solves these problems.

  In one aspect, it is an object of the semiconductor device disclosed in this specification to relieve stress when a wiring is formed along a chip.

  The semiconductor device disclosed in this specification is a semiconductor device in which at least a first chip and a second chip are stacked to face each other, and the first chip reaches a chip body and at least the chip body. 1 and at least the second main body that reaches the chip body and serves as an electrical connection destination of the first connection section, and the first chip, between the chip main body and the second main body. And an independent wiring provided in a state of being separated from the first connection portion and the second connection portion via an insulating layer, and one end portion of the second chip has the first connection portion. And the other end is connected to the other end of the independent wiring and the other end is connected to the second end. Second connection wiring connected to the connection part of , And a.

  According to the semiconductor device disclosed in this specification, it is possible to relieve stress when wiring is formed along the chip.

FIG. 1 is an explanatory diagram showing a schematic configuration of the semiconductor device of the first embodiment. FIG. 2 is an explanatory diagram showing a schematic configuration of a lowermost layer chip and an intermediate layer chip included in the semiconductor device of the first embodiment. FIG. 3 is an explanatory view showing a state in which the lowermost layer chip and the intermediate layer chip provided in the semiconductor device of the first embodiment are separated. FIG. 4 is an explanatory diagram showing the area X1 in FIG. 2 in an enlarged manner. FIG. 5 is an explanatory diagram showing the area X2 in FIG. 2 in an enlarged manner. FIG. 6A to FIG. 6D are explanatory views showing a part of the manufacturing process of the semiconductor device of the first embodiment. FIG. 7A to FIG. 7C are explanatory views showing a part of the manufacturing process of the semiconductor device of the first embodiment. 8A and 8B are explanatory views showing a part of the manufacturing process of the semiconductor device of the first embodiment. 9A and 9B are explanatory views showing a part of the manufacturing process of the semiconductor device of the first embodiment. 10A to 10C are explanatory views showing a part of the manufacturing process of the semiconductor device of the first embodiment. FIG. 11A and FIG. 11B are explanatory views schematically showing how the micro bumps are displaced. FIG. 12A is an explanatory diagram showing an example of how to cope with the misalignment of the micro bumps, and FIG. 12B is an explanatory diagram showing another example of dealing with the misalignment of the micro bumps. FIG. 13 is an explanatory diagram showing a lowermost layer chip and an intermediate layer chip included in the semiconductor device of the second embodiment. FIG. 14 is an explanatory diagram showing a lowermost layer chip and an intermediate layer chip included in the semiconductor device of the third embodiment. FIG. 15 is an explanatory view showing an intermediate layer chip provided in the semiconductor device of the fourth embodiment. FIG. 16 is an explanatory diagram showing a schematic configuration of a semiconductor device of a comparative example. 17A is a cross-sectional view taken along line AA in FIG. 17B of the intermediate layer chip included in the semiconductor device of the comparative example, and FIG. 17B is a cross-sectional view of the intermediate layer chip in which the semiconductor device of the comparative example is sparse. It is a top view.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, in the drawings, the dimensions, ratios, and the like of each part may not be shown so as to completely match the actual ones. Further, depending on the drawings, components that are actually present may be omitted for convenience of explanation, or dimensions may be exaggerated from the actual drawing.

(First embodiment)
First, prior to the description of the semiconductor device 1 of the present embodiment, a semiconductor device 500 of a comparative example will be described with reference to FIGS. 16 to 17B. FIG. 16 is an explanatory diagram showing a schematic configuration of a semiconductor device of a comparative example. 17A is a cross-sectional view taken along line AA in FIG. 17B of the intermediate layer chip included in the semiconductor device of the comparative example, and FIG. 17B is a cross-sectional view of the intermediate layer chip in which the semiconductor device of the comparative example is sparse. It is a top view.

  In the semiconductor device 500, a plurality of chips are stacked. That is, the semiconductor device 500 includes a lowermost layer chip 510, an intermediate layer chip 520, and an uppermost layer chip 530 stacked. Here, attention is paid to the intermediate layer chip 520. The intermediate layer chip 520 includes a chip body 521. On one surface side of the chip body 521, a circuit forming layer 521a is provided. The intermediate layer chip 520 is provided with a plurality of TSVs 522. Micro bumps 526 made of solder are formed at the ends of each TSV 522, and are electrically connected to the lowermost layer chip 510 and the uppermost layer chip 530 through the microbumps 526.

  In addition, an electrode 521a2 is provided on the circuit formation layer 521a. The electrode 521a2 is electrically connected to one of the plurality of TSVs 522. At this time, the electrode 521a2 and the TSV 522 are connected via the wiring 525 provided along the surface of the chip body 521. The wiring 525 is provided to supply power to the circuit formation layer 521a provided in the chip body 521. Such wiring 525 is provided along the chip body 521, and both the electrodes 521 a 2 and the TSV 522 reach the chip body 521. For this reason, for example, when the wiring 525 expands and contracts due to heat, a stress is generated at the joint between the wiring 525 and the surface of the chip body 521. Such stress causes the chip body 521 to warp. For example, when the thickness of the wiring 525 is 10 μm or more, even if the thickness of the Si (silicon) substrate before thinning the chip body 521 is about 775 μm, the wafer may be warped. Such a phenomenon makes it difficult to stack the intermediate layer chip 520 and other chips, or reduces the reliability of the product. Note that, in the case where the wiring 525 is not for supplying power but is, for example, a signal line, a problem due to stress may also occur.

  In order to relieve the stress generated by providing the wiring 525 on the surface of the chip main body 521 as described above, for example, it is conceivable to adopt a structure in which an insulating film is interposed between the chip main body 521 and the wiring 525. However, since the ends of the wiring 525 are connected to the electrode 521a2 and the TSV 522 that reach the chip body 521, respectively, it is considered that the effect of suppressing the deformation of the chip body 521 cannot be expected so much.

  Further, in order to relieve stress generated by providing the wiring 525 on the surface of the chip body 521, for example, it is conceivable to provide the wiring 525 in a zigzag manner in a plane parallel to the chip body 521. However, when the wiring 525 is provided in a zigzag shape, the area occupied by the wiring 525 increases, which is not suitable for a structure in which wiring and bumps are arranged at a high density such as three-dimensional integration.

  Hereinafter, the semiconductor device 1 of the present embodiment will be described with reference to FIGS. 1 to 5 while comparing with such a comparative example. FIG. 1 is an explanatory diagram showing a schematic configuration of the semiconductor device of the first embodiment. FIG. 2 is an explanatory diagram showing a schematic configuration of a lowermost layer chip and an intermediate layer chip included in the semiconductor device of the first embodiment. FIG. 3 is an explanatory view showing a state in which the lowermost layer chip and the intermediate layer chip provided in the semiconductor device of the first embodiment are separated. FIG. 4 is an explanatory diagram showing the area X1 in FIG. 2 in an enlarged manner. FIG. 5 is an explanatory diagram showing the area X2 in FIG. 2 in an enlarged manner. In the following description, the vertical direction is described as the direction shown in each drawing.

  The semiconductor device 1 of this embodiment has a so-called 3D (three dimensions) stacked structure. The semiconductor device 1 includes a stacked lowermost layer chip 10, an intermediate layer chip 20, and an uppermost layer chip 30. The intermediate layer chip 20 and the lowermost layer chip 10 are stacked so as to face each other. The uppermost layer chip 30 and the intermediate layer chip 20 are stacked facing each other. These stacked chips are electrically connected to a substrate electrode 2a provided on the package substrate 2 through C4 bumps 3. Of the stacked chips, when the intermediate layer chip 20 is the first chip, the lowermost layer chip 10 is the second chip. When the uppermost layer chip 30 is the first chip, the intermediate layer chip 20 is the second chip. In the following description, the case where the intermediate layer chip 20 is the first chip and the lowermost layer chip 10 is the second chip will be mainly described.

  Referring to FIG. 1, the lowermost layer chip 10 includes a chip body 11. A circuit formation layer 11 a is provided on the lower surface side of the chip body 11. An electrode 11a2 is provided on the circuit forming layer 11a. Further, the chip body 11 is provided with a plurality of electrodes, that is, TSVs 12 penetrating the chip body 11. A UBM (Under Barrier Metal) 14 is provided on the lower surface side of the chip body 11. The electrode 11a2 and the TSV 12 are electrically connected to the upper surface side of the UBM 14. The lower surface side of the UBM 14 is electrically connected to the substrate electrode 2 a via the C4 bump 3. A first insulating layer 13 is provided on the lower surface side of the circuit forming layer 11 a, and a part of the UBM 14 is buried in the first insulating layer 13.

  Referring to FIG. 3 and FIG. 5, the first connection wiring 15 and the second connection wiring 16 are provided on the upper surface side of the chip body 11. A second insulating layer 17 is provided on the upper surface side of the chip body 11, and the first connection wiring 15 and the second connection wiring 16 are embedded in the second insulating layer 17. Pillar portions 15a1 and 15b1 are formed at one end 15a and the other end 15b of the first connection wiring 15, respectively. Similarly, pillar portions 16a1 and 16b1 are formed at one end portion 16a and the other end portion 16b of the second connection wiring 16, respectively.

  Referring to FIGS. 1 to 5, the intermediate layer chip 20 includes a chip body 21. A circuit formation layer 21 a is provided on the lower surface side of the chip body 21. An electrode 21a2 is provided on the circuit forming layer 21a. The chip body 21 is provided with a plurality of TSVs 22. Since the TSV 22 penetrates the chip body 21, the TSV 22 has reached the chip body 21. Although a plurality of TSVs 22 are provided, some of these correspond to the first connection portion. Since the electrode 21a2 is provided on the circuit forming layer 21a formed on the chip body 21, the electrode 21a2 reaches the chip body 21. Such an electrode 21a2 corresponds to a second connection portion.

  A first insulating layer 23 is provided on the lower surface side of the circuit forming layer 21 a of the intermediate layer chip 20. As will be described later, in the manufacturing process, first insulating layer 23 is first formed with first layer 23a in contact with circuit forming layer 21a.

  The intermediate layer chip 20 includes a pillar portion 24 provided at an end portion of the electrode 21a2 or the TSV22. Micro pillars 26 made of solder are formed on the pillar portion 24, and the intermediate layer chip 20 is electrically connected to the lowermost layer chip 10 and the uppermost layer chip 30 through the microbumps 26.

  Referring to FIG. 4, the intermediate layer chip 20 is separated from the TSV 22 corresponding to the first connection part and the electrode 21 a 2 corresponding to the second connection part via the first insulating layer 23 between the chip body 21. Independent wiring 25 provided in the state is provided. The independent wiring 25 is arranged in a state of being supported by the first layer 23 a of the first insulating layer 23 provided on the lower surface side of the chip body 21. That is, the independent wiring 25 does not reach the chip body 21 and can expand and contract on the first layer 23a. Since the independent wiring 25 is separated from the TSV 22 and the electrode 21a2, the expansion and contraction of the independent wiring 25 is not constrained by the surroundings. As a result, no stress is generated as the independent wiring 25 expands and contracts.

  A pillar portion 25 a 1 is provided at one end portion 25 a of the independent wiring 25. The other end portion 25b of the independent wiring 25 is provided with a pillar portion 25b1. The pillar portion 25 a 1 is electrically connected to the other end portion 15 b of the first connection wiring 15 through the micro bump 26. The pillar portion 25 b 1 is connected to one end portion 16 a of the second connection wiring 16.

  One end portion 15 a of the first connection wiring 15 is electrically connected to the TSV 22 through the micro bump 26. The other end 16b of the second connection wiring 16 is electrically connected to the electrode 51a2 through the micro bump 26. Thereby, TSV22 and electrode 21a2 are electrically connected. That is, the TSV 22 and the electrode 21a2 are electrically connected via the first connection wiring 15, the independent wiring 25, and the second connection wiring 16. Thus, in the semiconductor device 1, in order to electrically connect the electrode 21a2 provided in the intermediate layer chip 20 and the TSV 22, the first connection wiring provided in the lowermost layer chip 10 that is stacked to face each other. 15 and the second connection wiring 16. Thereby, when electrically connecting the 1st connection part and the 2nd connection part which are arrange | positioned in the same chip | tip, it does not receive to the influence of the stress which wiring produces. In addition, the thickness of the independent wiring 25 in this embodiment is 10 μm, and the thickness of the chip body 21 is 50 μm. That is, the thickness of the independent wiring 25 is at least one tenth of the thickness of the chip body 21. The independent wiring 25 may be required to have a thickness that is at least one tenth of the thickness of the chip body 21 in response to a request for power supply or signal transmission. Even in such a case, the semiconductor device 1 of the present embodiment is not affected by the stress caused by the expansion and contraction of the independent wiring 25. In addition, when the length of the independent wiring 25 is long, for example, the influence of stress due to the expansion / contraction of the independent wiring 25 even when the length of the TSV 22 or the electrode 21a2 provided in the intermediate layer chip 20 is three times or more the minimum pitch. Not receive.

  The intermediate layer chip 20 is provided with a second insulating layer 27 on the surface opposite to the surface on which the circuit forming layer 21a of the chip body 21 is provided, and a first connection wiring 28 and a second connection wiring 29 are provided. It has been. When the uppermost layer chip 30 is the first chip and the intermediate layer chip 20 is the second chip, the first connection wiring 28 corresponds to the first connection wiring 15 in the lowermost layer chip 10, and the second connection wiring 29 is This corresponds to the second connection wiring 16 in the lowermost layer chip 10. The first connection wiring 28 and the second connection wiring 29 are each electrically connected to an electrode 31a2 described later.

  Next, referring to FIG. 1 again, the uppermost chip 30 includes a chip body 31. A circuit formation layer 31 a is provided on the lower surface side of the chip body 31. The circuit forming layer 31a is provided with a plurality of electrodes 31a2. The top layer chip 30 includes an independent wiring 35 provided between the chip body 31 and an insulating layer 33. One end and the other end of the independent wiring 35 are electrically connected to the first connection wiring 28 and the second connection wiring 29, respectively. The independent wiring 35 functions similarly to the independent wiring 25 in the relationship between the intermediate layer chip 20 and the lowermost layer chip 10 when the uppermost layer chip 30 is the first chip and the intermediate layer chip 20 is the second chip. Have. That is, when any two electrodes 31a2 provided in the uppermost layer chip are used as the first connection portion and the second connection portion, respectively, these two electrodes 31a2 include the first connection wiring 28 and the independent wiring 35. The second connection wiring 29 is electrically connected.

  Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. 6 (A) to 10 (C). 6 (A) to 8 (B) show the manufacturing process of the intermediate layer chip 20, FIG. 9 (A) shows the manufacturing process of the lowermost layer chip 10, and FIG. 9 (B) shows the manufacturing process of the uppermost layer chip 30. The process is shown. 10A to 10B show a process of stacking the chips. In the present embodiment, a manufacturing method according to the Via Last method will be described. However, the manufacturing of the semiconductor device 1 is not limited to this method, and can be manufactured using a conventionally known method.

  First, referring to FIG. 6A, the circuit forming layer 21a is provided on the lower surface side of the Si wafer 211 before thinning. The circuit forming layer 21a is provided with electrodes 21a2 and wirings 21a1. The wiring 21a1 is for receiving a TSV 22 formed later. In this process, after the final assembly, processing is performed by installing the lower surface side as the upper surface. As an example, a pre-thinning Si wafer 211 having a thickness of 775 μm and a diameter of 300 mm is prepared.

  Next, referring to FIG. 6B, an insulating resin is applied to the lower surface of the circuit forming layer 21a to form the first layer 23a of the first insulating layer 23. Here, a material having a low elastic modulus is selected as the insulating resin. Examples of the low elastic modulus material include epoxy, silicon, urethane, and bismaleimide resin. Due to the low elastic modulus, it becomes easy to adapt to the expansion and contraction of the independent wiring 25 to be constructed later. By adapting to the expansion and contraction of the independent wiring 25, the generation of stress can be suppressed. A resin having thermoplasticity can also be selected as the insulating resin. This is because the generation of stress can be suppressed by allowing plastic deformation when the temperature becomes such that the independent wiring extends.

  In the case where the insulating resin is photosensitive, it is cured by performing a heat treatment at about 200 ° C. for 1 hour after exposure and development. The film thickness of the first layer 23a after curing is about 5 μm. In the case of a non-photosensitive resin, the resin is cured after application of the material, and the opening 23a1 is formed using dry etching, laser, or the like. In this embodiment, a non-photosensitive resin is used and dry etching is used.

  Next, referring to FIG. 6C, copper (Cu) is used to form the first layer 24a and the independent wiring 25 that are part of the pillar portion 24 by plating. In the present embodiment, the semi-additive method is used, but other methods may be used as is conventionally known. In this embodiment, specifically, after a Cu / Ti (titanium) seed layer is formed by sputtering, a plating pattern is formed using a resist. Then, Cu is deposited by, for example, 10 μm using electrolytic plating. Then, after removing the resist, the seed layer between the wirings is removed by wet etching or the like, and the pattern is electrically separated. At this time, the first layer 24a is provided on the electrode 21a2 and the wiring 21a1. On the other hand, the independent wiring 25 is provided in a mode that is supported only by the first layer 23a of the first insulating layer 23, that is, in a mode in which only the first layer 23a exists between the uninsulated Si wafer.

  Next, referring to FIG. 6D, the first insulating layer 23 is formed by applying the same material as the material forming the first layer 23a to form the second layer 23b. The film thickness of the second layer 23b after curing is about 10 μm. In the second layer 23b, an opening 23b1 is formed in the same manner as the first layer 23a.

  Next, referring to FIG. 7A, the second layer 24b of the pillar portion 24 is formed, and the pillar portions 25a1 and 25b1 connected to the independent wiring 25 are formed. The second layer 24b and the pillar portions 25a1 and 25b1 of the pillar portion 24 are formed of Cu. Then, micro bumps 26 are formed on these end portions with SnAg (tin silver). The pillar portions 25a1 and the like and the micro bumps 26 are formed using a semi-additive method. Then, after pattern separation, for example, reflow is performed at 250 ° C. for 1 minute to round the heads of the micro bumps. As for the height of the pillar portion 25a1 and the like exposed from the first insulating layer 23, the height of the micro bump 26 is about 10 μm.

  Next, referring to FIG. 7B, the Si wafer 211 before thinning is thinned. Specifically, the support wafer 41 is mounted using the temporary adhesive 42 on the surface side on which the first insulating layer 23 is provided. Then, the Si wafer 211 before thinning is thinned using back grinding and CMP (Chemical Mechanical Polishing). The thinned Si wafer 211 becomes the chip body 21. The chip body 21 has a thickness of 50 μm excluding the circuit forming layer 21a.

Next, TSV22 is formed with reference to FIG.7 (C). The TSV 22 is formed from the surface opposite to the circuit forming layer 21a. When forming the TSV 22, an insulating layer is formed on the surface of the chip body 21, and a through hole for the TSV 22 is formed by etching. Note that since the insulating layer formed at this time is very thin, it is not shown in FIG. 7C for convenience of explanation. After forming the through hole, an insulating film is also formed on the inner peripheral wall surface of the through hole. Then, Cu is embedded in the through hole using electrolytic plating. Then, Cu spreading on the surface of the chip body 21 is removed by CMP, so that each TSV 22 is separated. The insulating layer is made of SiO ₂ and is formed by CVD (chemical vapor deposition) using a thickness of 1 μm on the surface of the chip body 21 and a thickness of 100 nm on the inner peripheral wall surface of the TSV 22.

  Next, with reference to FIG. 8A, the first connection wiring 28, the second connection wiring 29, and the like are formed on the upper surface side of the chip body 21. Since the formation of the first connection wiring 28, the second connection wiring 29, and the like is common to the steps described with reference to FIGS. 6B to 7A, detailed description thereof is omitted.

  Next, referring to FIG. 8B, the support wafer 41 is removed. Then, the intermediate layer chip 20 can be obtained by dividing the chip into pieces by dicing.

  Next, processing of the lowermost layer chip 10 will be described with reference to FIG. In the lowermost layer chip 10, the first insulating layer 13 and the second insulating layer 17 are provided on a Si wafer on which the circuit forming layer 11 a is formed separately from the intermediate layer chip 20. Further, the UBM 14 for receiving the C4 bump 3 shown in FIG. 1 is formed. For example, the UBM 14 is formed as a laminated film including an Au (gold) layer having a thickness of 0.02 μm and a Ni (nickel) layer having a thickness of 4.0 μm. Then, the first connection wiring 15 and the second connection wiring 16 are formed and separated into pieces. Since these steps are common to the steps described with reference to FIGS. 7B to 8B, detailed description thereof will be omitted. The first insulating layer 13 is not required to have low elasticity, unlike the first insulating layer 23 and the like in the intermediate layer chip 20. This is because the first insulating layer 13 need not correspond to the expansion and contraction of the wiring.

  Next, processing of the uppermost layer chip 30 will be described with reference to FIG. In the uppermost layer chip 30, independent wiring 35 and the like are formed on a Si wafer on which the circuit forming layer 31 a is formed separately from the intermediate layer chip 20 and the lowermost layer chip 10. Since the formation of the independent wiring 35 and the like is common to the steps described with reference to FIGS. 6B to 7A, detailed description thereof is omitted. Then, the upper surface side of the Si wafer is thinned by back grinding and separated into individual pieces by dicing, whereby the uppermost layer chip 30 is obtained. The thickness of the chip body 31 obtained by thinning the Si wafer is 300 μm.

  Next, referring to FIG. 10A and FIG. 10B, the intermediate layer chip 20 and the uppermost layer chip 30 are stacked and bonded. Both are joined via the micro bumps 26. Bonding is performed by reflow and heat treatment at 250 ° C. for about 1 minute.

  Next, referring to FIG. 10C, the intermediate layer chip 20 and the lowermost layer chip 10 are stacked and bonded. Both are joined via the micro bumps 26. Bonding is performed by reflow and heat treatment at 250 ° C. for about 1 minute. In addition, although the lowest layer chip | tip 10, the intermediate | middle layer chip | tip 20, and the uppermost layer chip | tip 30 in this embodiment are the same magnitude | sizes, you may make it enlarge a dimension, for example in a lower layer. In the present embodiment, the number of layers is three, but the number of layers may be further increased.

  After the lowermost layer chip 10, the intermediate layer chip 20, and the uppermost layer chip 30 are stacked, these stacked chips are bonded to the package substrate 2 and the gap is filled with an underfill 50, as shown in FIG. The semiconductor device 1 of this embodiment can be obtained.

  According to the semiconductor device 1 of the present embodiment, the independent wirings 25, 35 and the like can be freely expanded and contracted, so that stress when the wiring is formed along the chip can be relieved. For example, as shown in FIGS. 11A and 11B, the independent wiring 25 of the present embodiment can be freely expanded and contracted, so that the position of the micro bump 26 is assumed to be shifted. Therefore, in order to deal with such a phenomenon, for example, as shown in FIG. 12A, the first connection wiring 15 ′ and the second connection wiring 16 ′ having dimensions that are assumed to expand and contract in advance are provided. Also good. Further, as shown in FIG. 12B, a micro bump 26 ′ having a size larger than that of other micro bumps 26 may be provided.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIG. FIG. 13 is an explanatory diagram showing a lowermost layer chip and an intermediate layer chip included in the semiconductor device of the second embodiment. In the second embodiment, one end portion 125a of the independent wiring 125 and the other end portion 115b of the first connection wiring 115 are joined via pillar portions 125a1 and 115b1. The other end 125b of the independent wiring 125 and the one end 116a of the second connection wiring 116 are joined via pillar portions 125b1 and 116a1. In other words, the micro bumps 26 are abolished at the joint, and are joined by so-called Cu-Cu direct bonding. Thereby, the thickness of the semiconductor device can be suppressed.

(Third embodiment)
Next, a third embodiment will be described with reference to FIG. FIG. 14 is an explanatory diagram showing a lowermost layer chip and an intermediate layer chip included in the semiconductor device of the third embodiment. In the third embodiment, one end 225a of the independent wiring 225 and the other end 215b of the first connection wiring 215 are directly joined. Further, the other end 225 b of the independent wiring 225 and the one end 216 a of the second connection wiring 216 are directly joined. That is, not only the micro bumps 26 are abolished but also the pillar portions are abolished in the joint portion. With such bonding, the thickness of the semiconductor device can be suppressed. In the example shown in FIG. 14, the independent wiring 225 is installed on the first insulating layer 223, and the insulating layer is abolished around the independent wiring 225. Similarly, the first connection wiring 215 and the second connection wiring 216 are disposed on the first insulating layer 213, and the insulating layer around the first connection wiring 215 and the second connection wiring 216 is abolished.

(Fourth embodiment)
Next, a fourth embodiment will be described with reference to FIG. FIG. 15 is an explanatory view showing an intermediate layer chip provided in the semiconductor device of the fourth embodiment. The fourth embodiment is an example in which the semiconductor device is a pseudo SoC. In the fourth embodiment, the intermediate layer chip 320 includes a mold part 301 as a part of the chip body 321. And unlike 1st Embodiment etc., TMV (Through Mold Via) 322 which is an electrode which penetrates the mold part 301 is provided as a 1st connection part. The chip body 321 is provided with a circuit forming layer 321a, and an electrode 321a2 is disposed. This electrode 321a2 corresponds to a second connection portion. In the fourth embodiment, as in the first embodiment, the independent wiring 325 that is separated from the TMV 322 and the electrode 321a1 is provided. The TMV 322 and the electrode 321a1 are electrically connected through a first connection wiring, a second connection wiring, and an independent wiring 325 included in another chip which is omitted in FIG. This is the same as in the first embodiment. That is, as described above, even in the semiconductor device including the TMV 322, the stress when the wiring is formed along the chip can be relieved.

  Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications, within the scope of the gist of the present invention described in the claims, It can be changed.

1 Semiconductor device 10 Bottom layer chip 12 TSV
13 First Insulating Layer 15 First Connection Wiring 16 Second Connection Wiring 20 Intermediate Layer Chip 22 TSV
24 Pillar portion 25, 35 Independent wiring 28 First connection wiring 29 Second connection wiring 30 Top layer chip

Claims (6)

A semiconductor device in which at least a first chip and a second chip are stacked facing each other,
The first chip reaches the chip main body, at least the first connection portion reaching the chip main body, and reaches at least the chip main body and becomes an electrical connection destination of the first connection portion. Independent wiring provided in a state separated from the first connection portion and the second connection portion via an insulating layer between the second connection portion and the first chip in the first chip. And comprising
The second chip has one end connected to the first connecting portion and the other end connected to one end of the independent wiring, and one end other than the independent wiring. A semiconductor device comprising: a second connection wiring which is connected to the end portion and whose other end portion is connected to the second connection portion.   The first connection part is an electrode penetrating the chip body, and the second connection part is an electrode arranged in a circuit forming layer formed on a surface of the chip body. Item 14. The semiconductor device according to Item 1.   At least the first chip includes a mold part as a part of the chip body, the first connection part is an electrode penetrating the mold part, and the second connection part is The semiconductor device according to claim 1, wherein the semiconductor device is an electrode disposed in a circuit forming layer formed on a surface of the chip body.   One end of the independent wiring and the other end of the first connection wiring are joined via a pillar portion, and the other end of the independent wiring and one end of the second connection wiring are joined via a pillar portion. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The one end part of the said independent wiring and the other end part of the said 1st connection wiring are directly joined, The other end part of the said independent wiring and the one end part of the said 2nd connection wiring are directly joined. The semiconductor device according to any one of the above.   The semiconductor device according to claim 1, wherein a thickness of the independent wiring is one tenth or more of a thickness of the chip body of the first chip.

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