TW201709324A - Semiconductor device and method for fabricating semiconductor device - Google Patents

Semiconductor device and method for fabricating semiconductor device Download PDF

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TW201709324A
TW201709324A TW105108959A TW105108959A TW201709324A TW 201709324 A TW201709324 A TW 201709324A TW 105108959 A TW105108959 A TW 105108959A TW 105108959 A TW105108959 A TW 105108959A TW 201709324 A TW201709324 A TW 201709324A
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insulating
stress relaxation
hole
semiconductor device
wiring
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TW105108959A
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TWI618143B (en
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土手暁
石剛
北田秀樹
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富士通股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that penetrates through the semiconductor substrate from a back-surface side of the semiconductor substrate and is coupled to a wire included in the wiring layer; and a stress relaxation part that protrudes toward a through-via side and is disposed on a section in the wire and coupled to the through-via, the stress relaxation part including at least one insulating portion containing an insulating material having a smaller thermal expansion coefficient than a material of the through-via.

Description

半導體裝置及半導體裝置的製造方法 Semiconductor device and method of manufacturing semiconductor device

描述於本文的具體實施例均有關於半導體裝置及半導體裝置的製造方法。 The specific embodiments described herein are directed to semiconductor devices and methods of fabricating semiconductor devices.

半導體晶片的堆疊及封裝有朝向高效能計算(HPC)、高效能伺服器及其類似者的傾向。 The stacking and packaging of semiconductor wafers has a tendency toward high performance computing (HPC), high performance servers and the like.

例如，三維(3D)封裝涉及堆疊及封裝數個半導體晶片，以及2.5維(2.5D)封裝涉及使用中介層(interposer)來堆疊及封裝半導體晶片。在3D封裝及2.5D封裝中，半導體晶片之間或半導體晶片與中介層之間的電氣連接係使用倒裝晶片黏合法。 For example, three-dimensional (3D) packaging involves stacking and packaging several semiconductor wafers, and 2.5-dimensional (2.5D) packaging involves the use of an interposer to stack and package semiconductor wafers. In 3D and 2.5D packages, electrical connections between semiconductor wafers or between semiconductor wafers and interposers use flip chip bonding.

半導體晶片及中介層設有從半導體基板之背面側穿透半導體基板的貫穿通孔(through-via)。與貫穿通孔耦合的配線被包含在設於半導體基板之正面側上的配線層中。 The semiconductor wafer and the interposer are provided with through-vias that penetrate the semiconductor substrate from the back side of the semiconductor substrate. The wiring coupled to the through via is included in the wiring layer provided on the front side of the semiconductor substrate.

第13A圖及第13B圖為半導體裝置的橫截面圖例子。第14A圖及第14B圖為半導體裝置的橫截面圖實施例。貫穿通孔有大容積以及貫穿通孔的材料有大於半 導體基板材料的熱膨脹係數。因為這樣，例如，貫穿通孔與配線之間之接面區段(junction section)的介面由於在製程期間因產生熱而重覆地膨脹及收縮而產生應力，因而接面區段的介面可能發生剝離(separation)，如第13A圖及第13B圖和第14A圖及第14B圖所示。 13A and 13B are cross-sectional views of a semiconductor device. 14A and 14B are cross-sectional views of a semiconductor device. There is a large volume through the through hole and more than half of the material penetrating the through hole The coefficient of thermal expansion of the conductor substrate material. Because, for example, the interface of the junction section between the through-hole and the wiring is stressed due to repeated expansion and contraction due to heat generation during the process, the interface of the junction section may occur. Separation, as shown in Figures 13A and 13B and Figures 14A and 14B.

例如，為了鬆弛在貫穿通孔與配線之間之接面區段之介面產生的應力以及減少接面區段之介面的剝離發生率，將會連接至貫穿通孔的配線係設有向貫穿通孔側突出的突出物。當突出物的材料有大於貫穿通孔材料的熱膨脹係數時，在貫穿通孔與配線之間之接面區段之介面產生的應力可能不被鬆弛，或接面區段之介面的剝離發生率可能不會減少。 For example, in order to relax the stress generated in the interface between the through-hole and the junction between the via and the wiring, and to reduce the incidence of the peeling of the interface of the junction, the wiring connected to the through-hole is provided to pass through. A protrusion protruding from the side of the hole. When the material of the protrusion has a coefficient of thermal expansion greater than the material of the through-hole material, the stress generated in the interface between the junction section penetrating the via hole and the wiring may not be relaxed, or the peeling rate of the interface of the junction section may be It may not be reduced.

當突出物由金屬製成以及蝕刻掉用於形成貫穿通孔的區域時，電場會集中於由金屬製成的突出物，例如，如第15圖所示，以及包括電晶體及其類似者的電路可能經由有突出物的配線而受損(充電損害)。 When the protrusion is made of metal and the region for forming the through hole is etched away, the electric field is concentrated on the protrusion made of metal, for example, as shown in Fig. 15, and including the transistor and the like. The circuit may be damaged via wiring with protrusions (charge damage).

相關技術揭示於日本早期專利公開號2014-11248以及日本早期專利公開號2010-103433。 The related art is disclosed in Japanese Laid-Open Patent Publication No. 2014-11248 and Japanese Laid-Open Patent Publication No. 2010-103433.

根據該等具體實施例的一態樣，一種半導體裝置，其係包括：半導體基板；配線層，其係設於該半導體基板之正面側上；貫穿通孔，其係從該半導體基板之背面側穿透該半導體基板且耦合至被包含於該配線層中的配線；以及應力鬆弛部，其係向貫穿通孔側突出且設置於 該配線中之區段且耦合至該貫穿通孔，該應力鬆弛部包括至少一絕緣部，該絕緣部含有熱膨脹係數小於該貫穿通孔之材料之絕緣材料。 According to one aspect of the specific embodiments, a semiconductor device includes: a semiconductor substrate; a wiring layer disposed on a front side of the semiconductor substrate; and a through hole extending from a back side of the semiconductor substrate a semiconductor chip that penetrates the semiconductor substrate and is coupled to the wiring layer; and a stress relaxation portion that protrudes toward the through hole side and is disposed on A section of the wiring is coupled to the through via, the stress relaxation portion including at least one insulating portion, the insulating portion including an insulating material having a coefficient of thermal expansion smaller than a material of the through via.

在該半導體裝置的上述組態下，減少貫穿通孔與配線之間之接面區段之介面的剝離發生率係藉由鬆弛在接面區段之介面產生的應力。結果，可增加良率及可靠性。 In the above configuration of the semiconductor device, the incidence of peeling of the interface between the through-holes and the junction between the vias is reduced by the stress generated by the interface between the junction sections. As a result, yield and reliability can be increased.

1‧‧‧半導體基板 1‧‧‧Semiconductor substrate

2‧‧‧配線層 2‧‧‧Wiring layer

2A‧‧‧配線 2A‧‧‧Wiring

2B‧‧‧絕緣薄膜(層間絕緣薄膜) 2B‧‧‧Insulating film (interlayer insulating film)

2C‧‧‧阻障層(阻障金屬) 2C‧‧‧Block barrier (barrier metal)

2X‧‧‧配線、焊墊(電極) 2X‧‧‧Wiring, pad (electrode)

2Y‧‧‧配線 2Y‧‧‧ wiring

3‧‧‧貫穿通孔 3‧‧‧through through hole

3A‧‧‧種子層 3A‧‧‧ seed layer

3B‧‧‧鍍銅層 3B‧‧‧ copper plating

3X‧‧‧貫穿孔 3X‧‧‧through holes

4‧‧‧應力鬆弛部 4‧‧‧stress relaxation department

4A、4B、4C、4D‧‧‧部份 4A, 4B, 4C, 4D‧‧‧

4X‧‧‧柱狀應力鬆弛部 4X‧‧‧ columnar stress relaxation

4Y‧‧‧板狀應力鬆弛部 4Y‧‧‧plate stress relaxation

4Z‧‧‧板狀應力鬆弛部 4Z‧‧‧plate stress relaxation

5‧‧‧電路層 5‧‧‧ circuit layer

5A‧‧‧電晶體 5A‧‧‧O crystal

5B‧‧‧元件隔離區 5B‧‧‧Component isolation area

5C‧‧‧絕緣薄膜 5C‧‧‧Insulation film

5D‧‧‧插塞 5D‧‧‧ plug

5E‧‧‧閘極絕緣薄膜 5E‧‧‧ gate insulating film

5F‧‧‧閘極 5F‧‧‧ gate

6‧‧‧微凸塊 6‧‧‧Microbumps

6A‧‧‧銅柱 6A‧‧‧Bronze Column

6B‧‧‧焊錫 6B‧‧‧ solder

7‧‧‧支撐基板(支撐晶圓) 7‧‧‧Support substrate (support wafer)

8‧‧‧暫時黏著劑 8‧‧‧ temporary adhesive

9‧‧‧絕緣層 9‧‧‧Insulation

10‧‧‧重分布配線 10‧‧‧Redistributed wiring

11‧‧‧絕緣層 11‧‧‧Insulation

12‧‧‧凸塊下金屬(UBM)部份 12‧‧‧Under bump metal (UBM) part

13‧‧‧重分布層 13‧‧‧ redistribution layer

14‧‧‧個別LSI晶片 14‧‧‧Individual LSI chips

15‧‧‧LSI晶片 15‧‧‧ LSI chip

16‧‧‧堆疊晶片 16‧‧‧Stacked wafer

17‧‧‧銲錫凸塊 17‧‧‧ solder bumps

18‧‧‧封裝基板 18‧‧‧Package substrate

19‧‧‧3D堆疊LSI封裝件 19‧‧‧3D stacked LSI package

20‧‧‧突出物 20‧‧ ‧ protrusions

第1A圖及第1B圖圖示半導體裝置之一實施例；第2A圖至第2C圖圖示具有應力鬆弛部之配線的實施例；第3圖圖示用於製造半導體裝置之方法的實施例；第4圖圖示用於製造半導體裝置之該方法實施例；第5圖圖示用於製造半導體裝置之該方法實施例；第6圖圖示用於製造半導體裝置之該方法實施例；第7A圖及第7B圖圖示用於製造半導體裝置之該方法實施例；第8A圖及第8B圖圖示用於製造半導體裝置之該方法實施例； 第9A圖及第9B圖圖示用於製造半導體裝置之該方法實施例；第10A圖及第10B圖圖示用於製造半導體裝置之該方法實施例；第11A圖及第11B圖圖示用於製造半導體裝置之該方法實施例；第12圖圖示用於製造半導體裝置之該方法實施例；第13A圖及第13B圖圖示半導體裝置的橫截面圖實施例；第14A圖及第14B圖圖示半導體裝置的橫截面圖實施例；第15圖圖示半導體裝置的橫截面圖實施例；第16圖圖示半導體裝置的橫截面圖實施例；以及第17圖圖示半導體裝置的橫截面圖實施例。 1A and 1B illustrate an embodiment of a semiconductor device; FIGS. 2A to 2C illustrate an embodiment of a wiring having a stress relaxation portion; and FIG. 3 illustrates an embodiment of a method for manufacturing a semiconductor device Figure 4 illustrates an embodiment of the method for fabricating a semiconductor device; Figure 5 illustrates an embodiment of the method for fabricating a semiconductor device; and Figure 6 illustrates an embodiment of the method for fabricating a semiconductor device; 7A and 7B illustrate an embodiment of the method for fabricating a semiconductor device; FIGS. 8A and 8B illustrate an embodiment of the method for fabricating a semiconductor device; 9A and 9B illustrate an embodiment of the method for fabricating a semiconductor device; FIGS. 10A and 10B illustrate an embodiment of the method for fabricating a semiconductor device; FIGS. 11A and 11B illustrate Embodiments of the method for fabricating a semiconductor device; FIG. 12 illustrates an embodiment of the method for fabricating a semiconductor device; FIGS. 13A and 13B illustrate a cross-sectional view of the semiconductor device; FIGS. 14A and 14B The figure illustrates a cross-sectional view of a semiconductor device; FIG. 15 illustrates a cross-sectional view of the semiconductor device; FIG. 16 illustrates a cross-sectional view of the semiconductor device; and FIG. Cross-sectional embodiment.

第1A圖及第1B圖圖示半導體裝置之一實施例。第1A圖為半導體裝置的橫截面圖，以及第1B圖為從將會裝設貫穿通孔之側面觀看具有應力鬆弛部之配線(焊墊)的平面圖。第2A圖至第2C圖圖示具有應力鬆弛部之配線(或焊墊)的實施例。第2A圖至第2C圖為從將會裝 設貫穿通孔之側面觀看具有應力鬆弛部之配線(焊墊)的平面圖。如第1A圖所示，該半導體裝置包括半導體基板1，設於半導體基板1之正面側上的配線層2，以及從半導體基板1之背面側穿透半導體基板1且耦合至包含於配線層2中之配線2X的貫穿通孔3。在第1A圖中，未圖示形成於貫穿通孔3四周的絕緣層，例如，形成於貫穿孔(through-hole)之側壁上的絕緣層。第1A圖中的元件符號5F表示閘極。 1A and 1B illustrate an embodiment of a semiconductor device. Fig. 1A is a cross-sectional view of the semiconductor device, and Fig. 1B is a plan view showing a wiring (pad) having a stress relaxation portion viewed from a side where a through hole is to be mounted. 2A to 2C illustrate an embodiment of a wiring (or pad) having a stress relaxation portion. Figure 2A to Figure 2C will be loaded from A plan view of the wiring (pad) having the stress relaxation portion is viewed from the side of the through hole. As shown in FIG. 1A, the semiconductor device includes a semiconductor substrate 1, a wiring layer 2 provided on the front side of the semiconductor substrate 1, and a semiconductor substrate 1 penetrating from the back side of the semiconductor substrate 1 and coupled to the wiring layer 2 The wiring 2X penetrates through the through hole 3. In FIG. 1A, an insulating layer formed around the through hole 3, for example, an insulating layer formed on the sidewall of the through-hole is not illustrated. The symbol 5F in Fig. 1A indicates a gate.

應力鬆弛部4形成於被包含在配線層2中之配線2X的一區段上，該區段耦合至貫穿通孔3，使得應力鬆弛部4向貫穿通孔3側突出。應力鬆弛部4包括由熱膨脹係數小於貫穿通孔3材料之絕緣材料製成的一部份。應力鬆弛部4有突出形狀(突出結構)。為此，應力鬆弛部4可稱為突出物。 The stress relaxation portion 4 is formed on a section of the wiring 2X included in the wiring layer 2, and the section is coupled to the through hole 3 such that the stress relaxation portion 4 protrudes toward the through hole 3 side. The stress relaxation portion 4 includes a portion made of an insulating material having a coefficient of thermal expansion smaller than that of the material penetrating the through hole 3. The stress relaxation portion 4 has a protruding shape (projecting structure). For this reason, the stress relaxation portion 4 can be referred to as a protrusion.

如第1A圖及第1B圖所示，提供多個應力鬆弛部4作為應力鬆弛部4。例如，在被包含於配線層2中之配線的焊墊(電極)2X上提供多個柱狀應力鬆弛部4X作為突出應力鬆弛部4，焊墊(電極)2X耦合至貫穿通孔3。應力鬆弛部4不受限於此。例如，如第2A圖所示，在貫穿通孔3徑向延伸且直角相交的板狀應力鬆弛部4Y在包含於配線層2中之配線的焊墊(電極)2X上可提供作為突出應力鬆弛部4，焊墊(電極)2X耦合至貫穿通孔3。例如，如第2B圖所示，多個柱狀應力鬆弛部4X在被包含於配線層2中之配線的多個配線2Y上可提供作為突出應力鬆弛 部4，配線2Y耦合至貫穿通孔3。例如，如第2C圖所示，延伸成與多個配線2Y直角相交的多個板狀應力鬆弛部4Z在被包含於配線層2中之配線的多個配線2Y上可提供作為突出應力鬆弛部4，配線2Y耦合至貫穿通孔3。為了得到應力鬆弛效應同時阻止電阻增加，可提供在貫穿通孔3與配線2X或配線2Y之間之接面區段之介面方向有減少尺寸(例如，直徑)的多個柱狀應力鬆弛部4X。 As shown in FIGS. 1A and 1B, a plurality of stress relaxation portions 4 are provided as the stress relaxation portion 4. For example, a plurality of columnar stress relaxation portions 4X are provided as the protruding stress relaxation portions 4 on the pads (electrodes) 2X of the wirings included in the wiring layer 2, and the pads (electrodes) 2X are coupled to the through vias 3. The stress relaxation portion 4 is not limited to this. For example, as shown in FIG. 2A, the plate-like stress relaxation portion 4Y extending radially through the through hole 3 and intersecting at right angles can be provided as a protruding stress relaxation on the pad (electrode) 2X of the wiring included in the wiring layer 2. Portion 4, a pad (electrode) 2X is coupled to the through via 3. For example, as shown in FIG. 2B, the plurality of columnar stress relaxation portions 4X can be provided as a protruding stress relaxation on the plurality of wirings 2Y of the wiring included in the wiring layer 2. In the portion 4, the wiring 2Y is coupled to the through hole 3. For example, as shown in FIG. 2C, a plurality of plate-shaped stress relaxation portions 4Z extending at right angles to the plurality of wires 2Y can be provided as a protruding stress relaxation portion on the plurality of wires 2Y of the wiring included in the wiring layer 2. 4. The wiring 2Y is coupled to the through via 3. In order to obtain the stress relaxation effect while preventing the increase in resistance, a plurality of columnar stress relaxation portions 4X having a reduced size (for example, a diameter) in the interface direction of the junction section penetrating through the via hole 3 and the wiring 2X or the wiring 2Y may be provided. .

應力鬆弛部4為鬆弛在貫穿通孔3與配線2X之間之接面區段之介面產生之應力的部份。由於應力鬆弛部4包括由熱膨脹係數小於貫穿通孔3材料之材料製成的一部份，在貫穿通孔3與配線2X之間之接面區段之介面產生的應力(熱應力)會被鬆弛。例如，可用應力鬆弛部4鬆弛由於有大容積之貫穿通孔3縱向變形而產生的應力。例如，用應力鬆弛部4沿著貫穿通孔3與配線2X之間之接面區段之介面(在面內方向)方向釋放由於有大容積之貫穿通孔3縱向變形而產生的應力，以及該應力因此被鬆弛。因此，可減少在貫穿通孔3與配線2X之間之接面區段(聯結區段)之介面的剝離發生率。 The stress relaxation portion 4 is a portion that relaxes the stress generated in the interface of the junction section between the through hole 3 and the wiring 2X. Since the stress relaxation portion 4 includes a portion made of a material having a thermal expansion coefficient smaller than that of the material penetrating through the via 3, the stress (thermal stress) generated at the interface of the junction portion penetrating between the via hole 3 and the wiring 2X is relaxation. For example, the stress relaxation portion 4 can be used to relax the stress generated by the longitudinal deformation of the through hole 3 having a large volume. For example, the stress relaxation portion 4 releases the stress generated by the longitudinal deformation of the through-hole 3 having a large volume along the interface (in the in-plane direction) of the junction section between the through-hole 3 and the wiring 2X, and This stress is thus relaxed. Therefore, the incidence of peeling of the interface between the through-sections (joining sections) between the through holes 3 and the wiring 2X can be reduced.

應力鬆弛部4包括各自由絕緣材料製成的部份4A及4B，而突出應力鬆弛部4係與配線2X電氣絕緣。因此，可減少在蝕刻用於形成貫穿通孔3之區域期間由於電場集中於突出應力鬆弛部4造成對於包括電晶體及其類似者之電路的損害。以此方式，在可減少對於電路的損害時，可鬆弛在貫穿通孔3與配線2X之間之接面區段 之介面產生的應力以及可減少在接面區段之介面產生的剝離。結果，可增加良率及可靠性。 The stress relaxation portion 4 includes portions 4A and 4B each made of an insulating material, and the protruding stress relaxation portion 4 is electrically insulated from the wiring 2X. Therefore, damage to the circuit including the transistor and the like due to the concentration of the electric field to the protruding stress relaxation portion 4 during the etching of the region for forming the through via 3 can be reduced. In this way, when the damage to the circuit can be reduced, the junction section between the through hole 3 and the wiring 2X can be relaxed. The stress generated by the interface and the peeling that occurs at the interface of the junction section. As a result, yield and reliability can be increased.

如第1A圖所示，在半導體基板1之正面側上提供電路層5。電路層5包括電晶體5A，藉由用絕緣材料填充半導體基板1中之元件隔離凹槽而形成的元件隔離區(element isolation region)5B，以及絕緣薄膜5C。應力鬆弛部4包括含有與被包含於元件隔離區5B之中者相同之絕緣材料的部份4A，以及含有與絕緣薄膜5C材料相同之絕緣材料的部份4B。應力鬆弛部4在其末端包括含有絕緣材料的部份4A。應力鬆弛部4可包括含有不同絕緣材料的部份4A及4B。應力鬆弛部4的部份4A可設在在厚度方向與元件隔離區5B相同的位置處，部份4A係由與元件隔離區5B相同的絕緣材料形成。因為這樣，向貫穿通孔3側突出且設置於被包含於配線層2中之配線2X的一區段上的應力鬆弛部4有大高度(突出物高度)，該區段耦合至貫穿通孔3。結果，可增加應力鬆弛效應。 As shown in FIG. 1A, the circuit layer 5 is provided on the front side of the semiconductor substrate 1. The circuit layer 5 includes a transistor 5A, an element isolation region 5B formed by filling an element isolation groove in the semiconductor substrate 1 with an insulating material, and an insulating film 5C. The stress relaxation portion 4 includes a portion 4A containing the same insulating material as that contained in the element isolation region 5B, and a portion 4B containing the same insulating material as that of the insulating film 5C. The stress relaxation portion 4 includes a portion 4A containing an insulating material at its end. The stress relaxation portion 4 may include portions 4A and 4B containing different insulating materials. The portion 4A of the stress relaxation portion 4 may be provided at the same position as the element isolation region 5B in the thickness direction, and the portion 4A is formed of the same insulating material as the element isolation region 5B. Because of this, the stress relaxation portion 4 which protrudes toward the through hole 3 side and is provided on a section of the wiring 2X included in the wiring layer 2 has a large height (projection height) which is coupled to the through hole 3. As a result, the stress relaxation effect can be increased.

半導體基板1可為矽(Si)基板。貫穿通孔3可為含銅(Cu)貫穿通孔(金屬貫穿通孔)。例如，貫穿通孔3的材料可為銅。貫穿通孔3因此可為穿透矽基板1的矽通孔(TSV)。貫穿通孔3可設有種子層3A，例如由例如Ti、TiN、Ta或TaN製成者。 The semiconductor substrate 1 may be a bismuth (Si) substrate. The through hole 3 may be a copper-containing (Cu) through hole (metal through hole). For example, the material penetrating the through hole 3 may be copper. The through hole 3 can thus be a through hole (TSV) penetrating the ruthenium substrate 1. The seed hole 3A may be provided through the through hole 3, for example, made of, for example, Ti, TiN, Ta or TaN.

被包含於配線層2中的配線2A(2X)可為含銅(Cu)配線(銅配線；金屬配線)。例如，配線層2有銅配線2A(2X)均埋入絕緣薄膜(層間絕緣薄膜)2B的結構。由於配 線層2具有多層配線結構，所以配線層2可稱為多層配線層。作為配線2A，例如，可使用由Cu，Al，CuAl，CuMn，W，Mo，Ru或其類似者製成的配線。配線2A可包括含有例如Ti，TiN，Ta，TaN，Co或Ru的阻障層及/或含有例如NiP，NiPW，CoW，CoWP或Ru的帽蓋層。作為對應至配線層2的絕緣薄膜2B，可使用絕緣薄膜，例如由例如氧化矽(SiO)，氮氧化矽(SiON)，矽碳氧化物(SiOC)或矽碳氮(SiCN)製成的薄膜或其多孔薄膜。 The wiring 2A (2X) included in the wiring layer 2 may be a copper-containing (Cu) wiring (copper wiring; metal wiring). For example, the wiring layer 2 has a structure in which the copper wiring 2A (2X) is buried in the insulating film (interlayer insulating film) 2B. Due to The wire layer 2 has a multilayer wiring structure, so the wiring layer 2 can be referred to as a multilayer wiring layer. As the wiring 2A, for example, a wiring made of Cu, Al, CuAl, CuMn, W, Mo, Ru or the like can be used. The wiring 2A may include a barrier layer containing, for example, Ti, TiN, Ta, TaN, Co or Ru and/or a cap layer containing, for example, NiP, NiPW, CoW, CoWP or Ru. As the insulating film 2B corresponding to the wiring layer 2, an insulating film such as a film made of, for example, cerium oxide (SiO), cerium oxynitride (SiON), cerium oxycarbide (SiOC) or cerium carbon nitride (SiCN) may be used. Or a porous film thereof.

在矽基板1的正面側上，提供包括電晶體5A及其類似者的電路，例如，LSI。藉由用為絕緣材料的氧化矽(例如，SiO2)填充半導體基板1中的元件隔離凹槽來形成元件隔離區5B。元件隔離區5B覆蓋為絕緣薄膜5C的氧化矽薄膜(例如，SiOx薄膜)。以此方式，在矽基板1的正面側上提供包括電晶體5A、元件隔離區5B及絕緣薄膜5C的電路層5。 On the front side of the ruthenium substrate 1, a circuit including a transistor 5A and the like, for example, an LSI, is provided. The element isolation region 5B is formed by filling the element isolation trench in the semiconductor substrate 1 with yttrium oxide (for example, SiO 2 ) which is an insulating material. The element isolation region 5B is covered with a hafnium oxide film (for example, a SiO x film) of the insulating film 5C. In this way, the circuit layer 5 including the transistor 5A, the element isolation region 5B, and the insulating film 5C is provided on the front side of the germanium substrate 1.

應力鬆弛部4包括含有與被包含於元件隔離區5B之中者同樣為絕緣材料之氧化矽(例如，SiO2)的部份4A，以及含有與對應至絕緣薄膜5C之氧化矽薄膜(例如，SiOx薄膜)相同之絕緣材料的部份4B。被包含於元件隔離區5B之中的絕緣材料實施例包括諸如氧化矽(SiO；例如，SiO2)及氮化矽(SiN；例如，Si3N4)之類的絕緣材料。絕緣薄膜5C的材料實施例包括諸如氧化矽(SiO；例如，SiOx)、氮化矽(SiN)、氮氧化矽(SiON)、摻氟氧化矽(例如，氟矽酸鹽玻璃(FSG))，摻磷氧化矽(例如，磷矽酸鹽玻璃 (PSG))，以及摻磷硼氧化矽(例如，摻磷硼的矽玻璃(BPSG))之類的絕緣材料。 The stress relaxation portion 4 includes a portion 4A containing ruthenium oxide (for example, SiO 2 ) which is an insulating material included in the element isolation region 5B, and a ruthenium oxide film corresponding to the insulating film 5C (for example, SiO x film) part 4B of the same insulating material. Examples of the insulating material included in the element isolation region 5B include insulating materials such as yttrium oxide (SiO; for example, SiO 2 ) and tantalum nitride (SiN; for example, Si 3 N 4 ). Examples of the material of the insulating film 5C include, for example, cerium oxide (SiO; for example, SiO x ), cerium nitride (SiN), cerium oxynitride (SiON), fluorine-doped cerium oxide (for example, fluorosilicate glass (FSG)). , phosphorus-doped cerium oxide (for example, phosphonium silicate glass (PSG)), and insulating material doped with phosphorus borofluoride (for example, boron-phosphorus-doped bismuth glass (BPSG)).

應力鬆弛部4可包括由熱膨脹係數小於貫穿通孔3材料之絕緣材料製成的一部份。例如，含有熱膨脹係數小於貫穿通孔3材料之絕緣材料的部份可由絕緣材料形成，例如Si，SiO，SiN，SiON，SiC，AlO，或C。 The stress relaxation portion 4 may include a portion made of an insulating material having a coefficient of thermal expansion smaller than that of the material penetrating the through hole 3. For example, a portion containing an insulating material having a coefficient of thermal expansion smaller than that of the material penetrating through the via 3 may be formed of an insulating material such as Si, SiO, SiN, SiON, SiC, AlO, or C.

貫穿通孔3(例如，TSV)有大容積。貫穿通孔3的材料，例如，銅，有比半導體基板1之材料(例如，Si)大的熱膨脹係數。因為這樣，例如，由於重覆地膨脹及收縮而在貫穿通孔3與配線2X之間之接面區段的介面產生應力，如第13A圖及第13B圖所示，因為在包括背面加工及後續3D堆疊黏合加工的製程期間產生熱，因而在接面區段之介面可能發生剝離。例如，如在第14B圖(其係第14A圖中被矩形包圍之部份的放大圖)中用箭頭表示的位置所示，在接面區段之介面可能發生剝離。貫穿通孔可能經歷塑性變形。結果，良率及可靠性可能降低。 The through hole 3 (for example, TSV) has a large volume. The material penetrating the through hole 3, for example, copper, has a larger coefficient of thermal expansion than the material of the semiconductor substrate 1 (for example, Si). Because of this, for example, stress is generated in the interface of the junction section penetrating between the through hole 3 and the wiring 2X due to repeated expansion and contraction, as shown in FIGS. 13A and 13B, because Heat is generated during the subsequent 3D stack bonding process, and thus peeling may occur at the interface of the junction section. For example, as shown by the position indicated by the arrow in Fig. 14B (which is an enlarged view of a portion surrounded by a rectangle in Fig. 14A), peeling may occur at the interface of the junction section. Through-holes may experience plastic deformation. As a result, yield and reliability may be reduced.

例如，當貫穿通孔用後形成通孔方法(via-last method)形成時，藉由蝕刻掉用於形成貫穿通孔的區域來形成的貫穿孔可能難以維持乾淨的底部，例如，貫穿通孔與被包含於配線層中之配線之間的接面介面。因此貫穿通孔與被包含於配線層中之配線可能難以改善在接面區段介面的黏性。結果，在貫穿通孔與配線之間之接面區段的介面可能發生剝離，如上述。 For example, when a via-last method is formed after the through hole is formed, it may be difficult to maintain a clean bottom by etching a through hole formed by forming a region for forming the through hole, for example, a through hole. A junction interface with the wiring included in the wiring layer. Therefore, it may be difficult to improve the adhesion at the interface of the junction section through the via hole and the wiring included in the wiring layer. As a result, peeling may occur at the interface of the junction section penetrating through the via and the wiring, as described above.

第15圖為半導體裝置的示範橫截面圖。例 如，為了鬆弛在貫穿通孔與配線之間之接面區段之介面產生的應力以及減少接面區段之介面的剝離發生率，將會耦合至貫穿通孔的配線2X可設有向貫穿通孔側突出的突出物20，如第15圖所示。例如，當突出物20的材料有大於貫穿通孔之材料的熱膨脹係數時，在貫穿通孔與配線之間之接面區段之介面產生的應力可能未被鬆弛，以及接面區段之介面的剝離發生率可能不會減少。就此情形而言，在突出物20產生的應力可能增加以及此應力可能誘發接面區段的介面剝離。 Figure 15 is an exemplary cross-sectional view of a semiconductor device. example For example, in order to relax the stress generated in the interface between the via section between the via and the wiring and to reduce the incidence of peeling of the interface of the junction section, the wiring 2X coupled to the through via may be provided to penetrate The protrusion 20 protruding from the through hole side is as shown in Fig. 15. For example, when the material of the protrusion 20 has a coefficient of thermal expansion greater than the material penetrating the through hole, the stress generated in the interface between the junction section penetrating the through hole and the wiring may not be slack, and the interface of the junction section The rate of peeling may not decrease. In this case, the stress generated at the protrusions 20 may increase and this stress may induce interface peeling of the junction sections.

當突出物20含有金屬材料時，在蝕刻用於形成貫穿通孔的區域期間，電場集中於由金屬材料形成的突出物20，如第15圖所示。因此，包括電晶體5A及其類似者的電路可能經由有突出物20的配線2X而受損(充電損害)，從而可能降低良率及可靠性。 When the protrusion 20 contains a metal material, the electric field concentrates on the protrusion 20 formed of a metal material during etching of the region for forming the through hole, as shown in FIG. Therefore, the circuit including the transistor 5A and the like may be damaged (charge damage) via the wiring 2X having the protrusion 20, so that the yield and reliability may be lowered.

在半導體裝置有上述組態的情況下，減少在貫穿通孔3與配線2X之間之接面區段之介面的剝離發生率係藉由鬆弛在接面區段之介面產生的應力。結果，可增加良率及可靠性。例如，應力鬆弛部4形成被於包含於配線層2中之配線2X的一區段上，該區段耦合至貫穿通孔3，使得應力鬆弛部4向貫穿通孔3側突出。應力鬆弛部4包括各自由熱膨脹係數小於貫穿通孔3材料之絕緣材料製成的部份4A及4B。 In the case where the semiconductor device has the above configuration, the occurrence rate of the peeling of the interface between the through-hole 3 and the wiring 2X is reduced by the stress generated in the interface of the junction section. As a result, yield and reliability can be increased. For example, the stress relaxation portion 4 is formed on a section of the wiring 2X included in the wiring layer 2, and the section is coupled to the through hole 3 such that the stress relaxation portion 4 protrudes toward the through hole 3 side. The stress relaxation portion 4 includes portions 4A and 4B each made of an insulating material having a coefficient of thermal expansion smaller than that of the material penetrating through the via 3.

第3圖至第12圖圖示用於製造半導體裝置之方法的一實施例。用於製造半導體裝置之該方法包括形 成貫穿孔3X(參考第4圖)的製程以及形成貫穿通孔3(參考第6圖)的製程。形成貫穿孔3X的製程包括蝕刻掉用於形成從正面側上具有配線層2的半導體基板1之背面側穿透半導體基板1之貫穿通孔3的區域，該貫穿通孔3耦合至被包含於配線層2中之配線2X。向貫穿通孔3側突出的應力鬆弛部4形成於被包含於配線層2中之配線2X的一區段上，該區段為將會耦合至貫穿通孔3者。應力鬆弛部4包括各自由熱膨脹係數小於貫穿通孔3材料之絕緣材料製成的部份4A及4B。形成貫穿通孔3的製程包括用貫穿通孔3的材料填充貫穿孔3X，貫穿孔3X形成於用於形成貫穿通孔3的區域中。 3 to 12 illustrate an embodiment of a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes a shape The process of forming the through hole 3X (refer to FIG. 4) and the process of forming the through hole 3 (refer to FIG. 6). The process of forming the through hole 3X includes etching away a region for forming the through via 3 for penetrating the semiconductor substrate 1 from the back side of the semiconductor substrate 1 having the wiring layer 2 on the front side, the through via 3 being coupled to be included in Wiring 2X in wiring layer 2. The stress relaxation portion 4 protruding toward the through hole 3 side is formed on a section of the wiring 2X included in the wiring layer 2, which is a portion to be coupled to the through hole 3. The stress relaxation portion 4 includes portions 4A and 4B each made of an insulating material having a coefficient of thermal expansion smaller than that of the material penetrating through the via 3. The process of forming the through hole 3 includes filling the through hole 3X with a material penetrating the through hole 3, and the through hole 3X is formed in a region for forming the through hole 3.

用於製造半導體裝置之該方法更包括形成電路層5於半導體基板1(參考第3圖)之正面側上的製程。電路層5包括電晶體5A、藉由用絕緣材料填充半導體基板1中之元件隔離凹槽而形成的元件隔離區5B、以及絕緣薄膜5C。當在形成電路層5的製程中形成元件隔離區5B時，形成應力鬆弛部4的部份4A(參考第3圖)，部份4A係由與被包含於元件隔離區5B之中者相同的絕緣材料製成。在形成貫穿孔3X的製程中，應力鬆弛部4包括由與包含於元件隔離區5B之中者相同之絕緣材料製成的部份4A以及由與絕緣薄膜5C相同之絕緣材料製成的部份4B(參考第4圖)。 The method for fabricating a semiconductor device further includes a process of forming the circuit layer 5 on the front side of the semiconductor substrate 1 (refer to FIG. 3). The circuit layer 5 includes a transistor 5A, an element isolation region 5B formed by filling an element isolation recess in the semiconductor substrate 1 with an insulating material, and an insulating film 5C. When the element isolation region 5B is formed in the process of forming the circuit layer 5, the portion 4A of the stress relaxation portion 4 (refer to FIG. 3) is formed, and the portion 4A is the same as that included in the element isolation region 5B. Made of insulating material. In the process of forming the through hole 3X, the stress relaxation portion 4 includes a portion 4A made of the same insulating material as that contained in the element isolation region 5B and a portion made of the same insulating material as the insulating film 5C. 4B (refer to Figure 4).

例如，用後形成通孔方法形成有TSV(貫穿通孔)的LSI晶片(半導體晶片)，以及堆疊兩個LSI晶片。 堆疊LSI晶片可裝在封裝基板上，以及可相應地製成3D堆疊LSI封裝件。如第7A圖所示，在矽晶圓(矽基板；半導體基板)1上形成包括電晶體及其類似者的(LSI)電路，以及在此電路之表面上形成配線層2。 For example, an LSI wafer (semiconductor wafer) having a TSV (through-via) is formed by forming a via method, and two LSI wafers are stacked. The stacked LSI wafer can be mounted on a package substrate, and a 3D stacked LSI package can be fabricated accordingly. As shown in FIG. 7A, an (LSI) circuit including a transistor and the like is formed on a germanium wafer (germanium substrate; semiconductor substrate) 1, and a wiring layer 2 is formed on the surface of the circuit.

如第3圖所示，在矽晶圓1的正面側上形成包括電晶體5A、插塞5D及其類似者的(LSI)電路。在矽晶圓1中形成元件隔離凹槽以及用為絕緣材料的氧化矽(例如，SiO2)填充，以形成元件隔離區5B。用為絕緣薄膜5C的氧化矽薄膜(例如，SiOx薄膜)覆蓋這些組件。結果，在矽晶圓1的正面側上形成包括電晶體5A、元件隔離區5B及絕緣薄膜5C的電路層5。插塞5D的材料可為鎢(W)。絕緣薄膜5C可具有約0.3微米的厚度。第3圖中的元件符號5F表示閘極電極。 As shown in FIG. 3, an (LSI) circuit including a transistor 5A, a plug 5D, and the like is formed on the front side of the germanium wafer 1. An element isolation trench is formed in the germanium wafer 1 and filled with germanium oxide (for example, SiO 2 ) which is an insulating material to form the element isolation region 5B. These components are covered with a hafnium oxide film (for example, a SiO x film) which is an insulating film 5C. As a result, the circuit layer 5 including the transistor 5A, the element isolation region 5B, and the insulating film 5C is formed on the front side of the germanium wafer 1. The material of the plug 5D may be tungsten (W). The insulating film 5C may have a thickness of about 0.3 μm. The symbol 5F in Fig. 3 denotes a gate electrode.

實質同時並且藉由與形成元件隔離區5B的實質相同製程在用於在晶圓1中形成TSV 3的區域中形成用於形成應力鬆弛部4的凹槽。藉由用為絕緣材料的氧化矽(例如，SiO2)填充凹槽來形成應力鬆弛部4的部份4A，部份4A包括與被包含於元件隔離區5B之中者同樣為絕緣材料的氧化矽(例如，SiO2)。以此方式，藉由用與用於元件隔離區5B者相同的方式來形成應力鬆弛部4的一部份，向TSV 3側突出且在被包含於配線層2之中的最下層設置於銅配線2X之一區段上的應力鬆弛部4有大高度(突出物高度)(參考第1A圖)，該區段為將會連接至TSV 3者。結果，可增加應力鬆弛效應。 The grooves for forming the stress relaxation portion 4 are formed substantially simultaneously and by a substantially same process as the formation of the element isolation region 5B in the region for forming the TSV 3 in the wafer 1. The portion 4A of the stress relaxation portion 4 is formed by filling the groove with yttrium oxide (for example, SiO 2 ) which is an insulating material, and the portion 4A includes oxidation as an insulating material as contained in the element isolation region 5B.矽 (for example, SiO 2 ). In this manner, a portion of the stress relaxation portion 4 is formed in the same manner as that for the element isolation region 5B, protruded toward the TSV 3 side, and is disposed on the lowermost layer included in the wiring layer 2 in the copper layer. The stress relaxation portion 4 on one of the segments 2X has a large height (projection height) (refer to FIG. 1A) which is to be connected to the TSV 3. As a result, the stress relaxation effect can be increased.

在電路層5上形成具有多層配線結構的多層配線層作為配線層2，其中包括焊墊(電極)2X的銅配線2A均埋入絕緣薄膜2B中。形成作為銅配線2A之阻障層(阻障金屬)2C的TiN/Ti堆疊薄膜。一層配線2A有約0.3微米的厚度。如第7A圖所示，形成作為配線層2上之端子的微凸塊(micro-bump)6。各個微凸塊6的形成係藉由形成銅柱6A於配線層2上以及在銅柱6A上提供焊錫6B。因此，可製備有微凸塊6的晶圓(LS1晶圓)1。 A multilayer wiring layer having a multilayer wiring structure is formed as the wiring layer 2 on the circuit layer 5, and the copper wiring 2A including the pad (electrode) 2X is buried in the insulating film 2B. A TiN/Ti stacked film as a barrier layer (barrier metal) 2C of the copper wiring 2A was formed. The one layer wiring 2A has a thickness of about 0.3 μm. As shown in FIG. 7A, a micro-bump 6 as a terminal on the wiring layer 2 is formed. Each of the microbumps 6 is formed by forming a copper post 6A on the wiring layer 2 and providing solder 6B on the copper post 6A. Therefore, a wafer (LS1 wafer) 1 having micro bumps 6 can be prepared.

矽晶圓1可具有約775微米的厚度及約300毫米的尺寸。微凸塊6可具有約40微米的直徑，以及微凸塊6之間的間距可約為80微米。在微凸塊6中，銅柱部份可具有約20微米的高度，以及焊錫部份可具有約15微米的高度。如第7B圖所示，例如，在晶圓1中設置微凸塊6的側面朝下時，有微凸塊6的晶圓1用暫時黏著劑8暫時黏上由矽、玻璃或其類似者製成的支撐基板(支撐晶圓)7。暫時黏著劑8可具有約60微米的厚度。支撐基板7可具有約775微米的厚度。 The germanium wafer 1 may have a thickness of about 775 microns and a size of about 300 mm. The microbumps 6 can have a diameter of about 40 microns, and the spacing between the microbumps 6 can be about 80 microns. In the microbumps 6, the copper pillar portion may have a height of about 20 micrometers, and the solder portion may have a height of about 15 micrometers. As shown in FIG. 7B, for example, when the side of the wafer 1 in which the microbumps 6 are disposed faces downward, the wafer 1 having the microbumps 6 is temporarily adhered by the temporary adhesive 8 by ruthenium, glass or the like. A support substrate (support wafer) 7 is produced. Temporary adhesive 8 can have a thickness of about 60 microns. The support substrate 7 may have a thickness of about 775 microns.

如第8A圖所示，藉由研磨晶圓1背面來減少晶圓1的厚度，例如，用背面研磨法(BG)或化學機械研磨法(CMP)。晶圓1的厚度可減到約100微米。如第8B圖及第4圖所示，晶圓1及絕緣薄膜5C從晶圓1的背面側蝕刻從而在用於形成TSV 3的區域中形成貫穿孔3X。在晶圓1的背面側上形成硬遮罩，圖案化一抗蝕層，以及蝕刻該硬遮罩。利用被圖案化之該硬遮罩來蝕刻晶圓1及絕緣 薄膜5C，從而在用於形成TSV 3之區域中形成貫穿孔3X。硬遮罩可為厚約1微米的SiO薄膜。在用於形成TSV 3之區域中形成的貫穿孔3X可具有約10微米的直徑。 As shown in FIG. 8A, the thickness of the wafer 1 is reduced by polishing the back surface of the wafer 1, for example, by back grinding (BG) or chemical mechanical polishing (CMP). The thickness of wafer 1 can be reduced to about 100 microns. As shown in FIGS. 8B and 4, the wafer 1 and the insulating film 5C are etched from the back side of the wafer 1 to form a through hole 3X in a region for forming the TSV 3. A hard mask is formed on the back side of the wafer 1, a resist layer is patterned, and the hard mask is etched. Etching the wafer 1 and insulating with the patterned hard mask The film 5C is formed to form a through hole 3X in a region for forming the TSV 3. The hard mask can be a SiO film that is about 1 micron thick. The through hole 3X formed in the region for forming the TSV 3 may have a diameter of about 10 μm.

在用於形成TSV 3之區域中(參考第3圖)形成應力鬆弛部4的部份4A，部份4A含有與被包含於元件隔離區5B之中者同樣為絕緣材料的氧化矽(例如，SiO2)。如第4圖所示，應力鬆弛部4的部份4A在藉由蝕刻掉用於形成TSV 3之區域來形成貫穿孔3X時因此仍未被蝕刻，部份4A含有與被包含於元件隔離區5B之中者同樣為絕緣材料的氧化矽(例如，SiO2)。此外，部份4A用來當作遮罩，以及留下為絕緣薄膜5C之氧化矽薄膜(例如，SiOx薄膜)的一部份，該部份對應至部份4A。 In the region for forming the TSV 3 (refer to FIG. 3), the portion 4A of the stress relaxation portion 4 is formed, and the portion 4A contains yttrium oxide which is also an insulating material as contained in the element isolation region 5B (for example, SiO 2 ). As shown in FIG. 4, the portion 4A of the stress relaxation portion 4 is still not etched when the through hole 3X is formed by etching away the region for forming the TSV 3, and the portion 4A contains and is included in the element isolation region. Among them, 5B is also an insulating material of cerium oxide (for example, SiO 2 ). Further, the portion 4A is used as a mask, and a portion of the ruthenium oxide film (for example, SiO x film) remaining as the insulating film 5C corresponds to the portion 4A.

因此，在用於形成TSV 3之區域中形成應力鬆弛部4，使得應力鬆弛部4由被包含於配線層2中最下層的銅配線2X突出。應力鬆弛部4包括含有與包含於元件隔離區5B之中者同樣為絕緣材料之氧化矽(例如，SiO2)的部份4A，以及含有與為絕緣薄膜5C之氧化矽薄膜(例如，SiOX薄膜)相同之絕緣材料的部份4B。在被包含於配線層2的銅配線2A中耦合至TSV 3的銅焊墊(銅電極)2X上，形成作為應力鬆弛部4的多個柱狀應力鬆弛部4X，使得柱狀應力鬆弛部4X在用於形成TSV 3之區域中(參考第1B圖)突出。 Therefore, the stress relaxation portion 4 is formed in the region for forming the TSV 3 such that the stress relaxation portion 4 protrudes from the copper wiring 2X included in the lowermost layer of the wiring layer 2. The stress relaxation portion 4 includes a portion 4A containing ruthenium oxide (for example, SiO2) which is an insulating material included in the element isolation region 5B, and a ruthenium oxide film (for example, a SiOX film) containing and insulating the film 5C. Part 4B of the same insulating material. On the copper pad (copper electrode) 2X coupled to the TSV 3 in the copper wiring 2A included in the wiring layer 2, a plurality of columnar stress relaxation portions 4X as the stress relaxation portion 4 are formed, so that the columnar stress relaxation portion 4X It is highlighted in the region for forming the TSV 3 (refer to FIG. 1B).

如第9A圖及第5圖所示，用例如CVD方法，在晶圓1的背面上形成絕緣層9。由於在晶圓1的背 面側上形成貫穿孔3X於用於形成TSV 3之區域中，所以也在貫穿孔3X的內側(側壁及底部)上形成絕緣層9(參考，第5圖的點線)。蝕刻掉形成於貫穿孔3X底部上的絕緣層9以便形成開口用於將會黏到被包含於形成於晶圓1正面側上之配線層2中之配線2X的區段。形成於貫穿孔3X側壁上的絕緣層9減少其厚度並留在貫穿孔3X的側壁上。 As shown in FIGS. 9A and 5, an insulating layer 9 is formed on the back surface of the wafer 1 by, for example, a CVD method. Due to the back of wafer 1 The through hole 3X is formed in the region on the surface side for forming the TSV 3, so that the insulating layer 9 is also formed on the inner side (side wall and bottom portion) of the through hole 3X (refer to the dotted line of Fig. 5). The insulating layer 9 formed on the bottom of the through hole 3X is etched away to form an opening for a portion to be adhered to the wiring 2X included in the wiring layer 2 formed on the front side of the wafer 1. The insulating layer 9 formed on the side wall of the through hole 3X is reduced in thickness and left on the side wall of the through hole 3X.

如第9B圖及第6圖所示，在晶圓1有貫穿孔3X形成於用於形成TSV 3之區域中的背面上形成種子層3A，例如，用濺鍍法或CVD方法。用電鍍法形成鍍銅層3B，藉此用鍍銅層3B填充形成於用於形成TSV 3之區域中的貫穿孔3X，結果，可形成TSV 3。例如，種子層3A的形成係藉由堆疊鈦層及銅層。在形成於用於形成TSV 3之區域中的貫穿孔3X的內壁上，鈦層及銅層的厚度各自可等於約50奈米及約200奈米。 As shown in FIGS. 9B and 6 , the seed layer 3A is formed on the back surface of the wafer 1 having the through holes 3X formed in the region for forming the TSV 3, for example, by a sputtering method or a CVD method. The copper plating layer 3B is formed by electroplating, whereby the through hole 3X formed in the region for forming the TSV 3 is filled with the copper plating layer 3B, and as a result, the TSV 3 can be formed. For example, the seed layer 3A is formed by stacking a titanium layer and a copper layer. The thickness of the titanium layer and the copper layer may each be equal to about 50 nm and about 200 nm on the inner wall of the through hole 3X formed in the region for forming the TSV 3.

如上述，應力鬆弛部4形成於用於形成晶圓1之TSV 3的區域中，使得應力鬆弛部4由被包含於配線層2中最下層的銅配線2X突出。應力鬆弛部4包括含有與被包含於元件隔離區5B之中者同樣為絕緣材料之氧化矽(例如，SiO2)的部份4A，以及含有與為絕緣薄膜5C之氧化矽薄膜(例如，SiOX薄膜)相同之絕緣材料的部份4B(參考第4圖)。 As described above, the stress relaxation portion 4 is formed in a region for forming the TSV 3 of the wafer 1 such that the stress relaxation portion 4 protrudes from the copper wiring 2X included in the lowermost layer of the wiring layer 2. The stress relaxation portion 4 includes a portion 4A containing ruthenium oxide (for example, SiO 2 ) which is an insulating material included in the element isolation region 5B, and a ruthenium oxide film containing the same as the insulating film 5C (for example, SiOX). Film) Part 4B of the same insulating material (refer to Figure 4).

如第6圖所示，在藉由用鍍銅層3B填充貫穿孔3X來形成TSV 3時，貫穿孔3X形成於用於形成TSV 3之區域中，應力鬆弛部4也埋入鍍銅層3B中。因此，在被包含於配線層2中之銅配線2X的一區段上形成應力鬆弛部4，該區段耦合至TSV 3，使得應力鬆弛部4向TSV 3側突出。應力鬆弛部4包括含有與被包含於元件隔離區5B之中者同樣為絕緣材料之氧化矽(例如，SiO2)的部份4A，以及含有與為絕緣薄膜5C之氧化矽薄膜(例如，SiOX薄膜)相同之絕緣材料的部份4B。 As shown in FIG. 6, when the TSV 3 is formed by filling the through hole 3X with the copper plating layer 3B, the through hole 3X is formed for forming the TSV. In the region of 3, the stress relaxation portion 4 is also buried in the copper plating layer 3B. Therefore, the stress relaxation portion 4 is formed on a section of the copper wiring 2X included in the wiring layer 2, and this section is coupled to the TSV 3 such that the stress relaxation portion 4 protrudes toward the TSV 3 side. The stress relaxation portion 4 includes a portion 4A containing ruthenium oxide (for example, SiO2) which is an insulating material included in the element isolation region 5B, and a ruthenium oxide film containing the same as the insulating film 5C (for example, a SiOX film). ) Part 4B of the same insulating material.

應力鬆弛部4在被包含於配線層2中之銅配線2X的一區段上形成，該區段耦合至TSV 3，使得應力鬆弛部4向TSV 3側突出。應力鬆弛部4包括各自由熱膨脹係數小於TSV 3之材料之絕緣材料製成的部份4A及4B。在耦合至在被包含於配線層2之銅配線2A中之TSV 3的銅焊墊(銅電極)2X上形成作為應力鬆弛部4的多個柱狀應力鬆弛部4X，使得柱狀應力鬆弛部4X向TSV 3側(參考第1B圖)突出。 The stress relaxation portion 4 is formed on a section of the copper wiring 2X included in the wiring layer 2, which is coupled to the TSV 3 such that the stress relaxation portion 4 protrudes toward the TSV 3 side. The stress relaxation portion 4 includes portions 4A and 4B each made of an insulating material of a material having a thermal expansion coefficient smaller than TSV 3. A plurality of columnar stress relaxation portions 4X as the stress relaxation portion 4 are formed on the copper pad (copper electrode) 2X coupled to the TSV 3 included in the copper wiring 2A of the wiring layer 2, so that the columnar stress relaxation portion 4X is highlighted to the TSV 3 side (refer to Figure 1B).

如第10A圖所示，例如，用CMP移除形成於表面上的鍍銅層3B及銅種子層3A，以及使TSV 3互相隔離。如第10B圖所示，形成重分布配線10以便耦合至TSV 3，以及蓋上絕緣層11。在絕緣層11中形成開口。在該等開口中形成凸塊下金屬(UBM)部份12，從而形成重分布層13。 As shown in Fig. 10A, for example, the copper plating layer 3B and the copper seed layer 3A formed on the surface are removed by CMP, and the TSVs 3 are isolated from each other. As shown in FIG. 10B, the redistribution wiring 10 is formed to be coupled to the TSV 3, and the insulating layer 11 is covered. An opening is formed in the insulating layer 11. A sub-bump metal (UBM) portion 12 is formed in the openings to form a redistribution layer 13.

例如，用半加成製程(semi-additive process；SAP)形成重分布配線10。例如，形成該種子層係藉由例如，用濺鍍法或無電解電鍍法堆疊鈦層及銅層，然後形成 有抗蝕層的圖案。例如，用電鍍法沉積銅層於沒有抗蝕層圖案的區域上，例如用濕蝕刻法剝掉抗蝕層，以及移除殘留種子層。結果，可形成重分布配線10。鈦層及銅層的厚度可各自等於約0.1微米及約5微米。絕緣層11可含有聚亞醯胺樹脂(光敏樹脂)且可具有約10微米的厚度。凸塊下金屬部份12的形成各自藉由，例如，用半加成製程堆疊鈦層、銅層、鎳層及金層。在這些層中，鈦層約有0.1微米，銅層約有2微米，鎳層約有3微米，以及金層約有0.05微米的厚度。 For example, the redistribution wiring 10 is formed by a semi-additive process (SAP). For example, the seed layer is formed by, for example, stacking a titanium layer and a copper layer by sputtering or electroless plating, and then forming There is a pattern of resist layers. For example, a copper layer is deposited by electroplating on a region having no resist pattern, such as by wet etching to remove the resist layer, and removing the residual seed layer. As a result, the redistribution wiring 10 can be formed. The thickness of the titanium layer and the copper layer can each be equal to about 0.1 microns and about 5 microns. The insulating layer 11 may contain a polyimide resin (photosensitive resin) and may have a thickness of about 10 μm. The under bump metal portions 12 are each formed by, for example, stacking a titanium layer, a copper layer, a nickel layer, and a gold layer by a semi-additive process. In these layers, the titanium layer is about 0.1 micron, the copper layer is about 2 microns, the nickel layer is about 3 microns, and the gold layer is about 0.05 microns thick.

如第11A圖所示，脫黏(debond)支撐基板7，接著是切成個別的片體。這提供具有TSV 3的LSI晶片。在切晶帶(dicing tape)放上重分布層13側以及脫黏支撐基板7後，將晶圓切成個別晶片。如第11B圖所示，將個別LSI晶片14放在獨立裝設的LSI晶片15上，以及用回焊處理(reflow treatment)使LSI晶片14及15互相黏合。結果，可製備堆疊晶片16。獨立裝設的LSI晶片15可為於背面研磨後在不形成TSV 3或重分布層13的情況下得到的晶片。獨立裝設之LSI晶片15的矽基板1可具有約300微米的厚度。 As shown in Fig. 11A, the support substrate 7 is debonded, followed by cutting into individual sheets. This provides an LSI wafer having TSV 3. After the dicing tape is placed on the side of the redistribution layer 13 and the debonded support substrate 7 is removed, the wafer is cut into individual wafers. As shown in Fig. 11B, the individual LSI wafers 14 are placed on the independently mounted LSI wafers 15, and the LSI wafers 14 and 15 are bonded to each other by reflow treatment. As a result, the stacked wafer 16 can be prepared. The independently mounted LSI wafer 15 may be a wafer obtained after back grinding without forming the TSV 3 or the redistribution layer 13. The tantalum substrate 1 of the independently mounted LSI wafer 15 may have a thickness of about 300 μm.

如第12圖所示，如上述製備的堆疊晶片16裝在有銲錫凸塊17在其間的封裝基板18上，因此製成3D堆疊之LSI封裝件19。在封裝基板18上形成銲錫凸塊17，以及將堆疊晶片16放在銲錫凸塊17上，接著是在回焊爐中的回焊處理。在堆疊晶片16黏至有銲錫凸塊17在其間 的封裝基板18之後，施加供樹脂密封用的底部填充膠(underfill)，因此製成3D堆疊之LSI封裝件19。銲錫凸塊17可具有約100微米的直徑。在回焊爐中的回焊處理可以約250℃的溫度進行約5分鐘。 As shown in Fig. 12, the stacked wafer 16 prepared as described above is mounted on the package substrate 18 with the solder bumps 17 therebetween, thereby forming a 3D stacked LSI package 19. Solder bumps 17 are formed on the package substrate 18, and the stacked wafers 16 are placed on the solder bumps 17, followed by a reflow process in the reflow oven. The stacked wafer 16 is adhered to the solder bump 17 therebetween After the package substrate 18, an underfill for resin sealing is applied, thereby forming a 3D stacked LSI package 19. Solder bump 17 can have a diameter of about 100 microns. The reflow process in the reflow oven can be carried out at a temperature of about 250 ° C for about 5 minutes.

根據該半導體裝置及該半導體裝置之製造方法，減少貫穿通孔3與配線2X之間之接面區段之介面的剝離發生率係藉由鬆弛在接面區段之介面產生的應力。結果，可增加良率及可靠性。圖示於第1A圖的半導體裝置包括在半導體基板1之正面側上的電路層5。電路層5包括電晶體5A，藉由用絕緣材料填充半導體基板1中之元件隔離凹槽而形成的元件隔離區5B，以及絕緣薄膜5C。應力鬆弛部4包括含有與被包含於元件隔離區5B之中者實質相同之絕緣材料的部份4A，以及含有絕緣材料與絕緣薄膜5C實質相同的部份4B。 According to the semiconductor device and the method of manufacturing the semiconductor device, the occurrence rate of the peeling of the interface between the through-hole 3 and the wiring 2X is reduced by the stress generated in the interface between the junction sections. As a result, yield and reliability can be increased. The semiconductor device shown in FIG. 1A includes a circuit layer 5 on the front side of the semiconductor substrate 1. The circuit layer 5 includes a transistor 5A, an element isolation region 5B formed by filling an element isolation recess in the semiconductor substrate 1 with an insulating material, and an insulating film 5C. The stress relaxation portion 4 includes a portion 4A containing an insulating material substantially the same as that included in the element isolation region 5B, and a portion 4B containing the insulating material substantially the same as the insulating film 5C.

第16圖為半導體裝置之橫截面圖的一實施例。例如，如第16圖所示，該半導體裝置可包括在半導體基板1之正面側上的電路層5。電路層5包括電晶體5A，藉由用絕緣材料填充半導體基板1中之元件隔離凹槽而形成的元件隔離區5B，耦合至電晶體5A的插塞5D，以及絕緣薄膜5C。例如，應力鬆弛部4可包括含有與被包含於元件隔離區5B之中者實質相同之絕緣材料的部份4A，含有與絕緣薄膜5C材料相同之絕緣材料的部份4B，以及含有與插塞5D材料相同之材料的部份4C。在第16圖中，元件符號5F表示閘極電極。 Figure 16 is an embodiment of a cross-sectional view of a semiconductor device. For example, as shown in FIG. 16, the semiconductor device may include the circuit layer 5 on the front side of the semiconductor substrate 1. The circuit layer 5 includes a transistor 5A, an element isolation region 5B formed by filling an element isolation groove in the semiconductor substrate 1 with an insulating material, a plug 5D coupled to the transistor 5A, and an insulating film 5C. For example, the stress relaxation portion 4 may include a portion 4A containing an insulating material substantially the same as that included in the element isolation region 5B, a portion 4B containing the same insulating material as that of the insulating film 5C, and a plug and a plug. Part 4C of the same material as the 5D material. In Fig. 16, the symbol 5F indicates a gate electrode.

就此情形而言，應力鬆弛部4也包括在末端由絕緣材料製成的部份4A。應力鬆弛部4包括由不同絕緣材料製成的部份4A及4B。插塞5D的材料為金屬材料，例如鎢(W)。由於被包含於應力鬆弛部4中之插塞5D的材料為金屬材料，接面區段與配線2X的黏性可增加。 In this case, the stress relaxation portion 4 also includes a portion 4A made of an insulating material at the end. The stress relaxation portion 4 includes portions 4A and 4B made of different insulating materials. The material of the plug 5D is a metal material such as tungsten (W). Since the material of the plug 5D included in the stress relaxation portion 4 is a metal material, the adhesion of the junction portion to the wiring 2X can be increased.

可用含有與被包含於元件隔離區5B之中者實質相同之絕緣材料的部份4A以及含有與絕緣薄膜5C材料實質相同之絕緣材料的部份4B包圍含有與插塞5D之材料實質相同之材料的部份4C。這允許突出應力鬆弛部4之正面側與含有與插塞5D材料實質相同之材料的部份4C之間的電氣絕緣。結果，可減少包括電晶體5A及其類似者之電路在蝕刻用於形成貫穿通孔3之區域期間由於電場集中於突出應力鬆弛部4所致的傷害。 The material containing substantially the same material as that of the plug 5D may be surrounded by the portion 4A containing the insulating material substantially the same as that contained in the element isolation region 5B and the portion 4B containing the insulating material substantially the same as the material of the insulating film 5C. Part of 4C. This allows electrical insulation between the front side of the stress relaxation portion 4 and the portion 4C containing material substantially the same as the material of the plug 5D. As a result, it is possible to reduce the damage caused by the electric field concentrated on the protruding stress relaxation portion 4 during the etching of the region for forming the through-hole 3 during the etching of the region including the transistor 5A and the like.

應力鬆弛部4也可包括含有與為插塞5D材料之金屬材料實質相同之金屬材料的部份4C，以及也可包括由另一金屬材料製成的一部份。例如，應力鬆弛部4可包括含有與為阻障薄膜材料之金屬材料(例如，Ti，TiN，Ta，TaN，TiW，或堆疊結構，例如TiN/Ti)實質相同之金屬材料的一部份，以及可包括含有金屬材料(例如，鉬(Mo))的一部份。 The stress relaxation portion 4 may also include a portion 4C containing a metal material substantially the same as the metal material of the plug 5D material, and may also include a portion made of another metal material. For example, the stress relaxation portion 4 may include a portion containing a metal material substantially the same as a metal material (for example, Ti, TiN, Ta, TaN, TiW, or a stacked structure such as TiN/Ti) which is a barrier film material, And may include a portion containing a metallic material (eg, molybdenum (Mo)).

如第16圖所示，在被包含於配線層2中之配線的焊墊2X上提供作為突出應力鬆弛部4的多個柱狀應力鬆弛部4X，焊墊2X耦合至貫穿通孔3。在焊墊2X上，可提供在貫穿通孔3徑向延伸且以直角相交的板狀應力鬆 弛部4Y作為突出應力鬆弛部4(參考第2A圖)。在多個配線2Y(參考第2B圖)上可提供多個柱狀應力鬆弛部4X作為突出應力鬆弛部4。在多個配線2Y(參考第2C圖)上，延伸成與多個配線2Y直角相交的多個板狀應力鬆弛部4Z可提供作為突出應力鬆弛部4。 As shown in FIG. 16, a plurality of columnar stress relaxation portions 4X as the protruding stress relaxation portions 4 are provided on the pads 2X of the wirings included in the wiring layer 2, and the pads 2X are coupled to the through vias 3. On the bonding pad 2X, a plate-like stress relaxation which extends radially through the through hole 3 and intersects at right angles can be provided. The relaxation portion 4Y serves as a protruding stress relaxation portion 4 (refer to FIG. 2A). A plurality of columnar stress relaxation portions 4X can be provided as the protruding stress relaxation portion 4 on the plurality of wirings 2Y (refer to FIG. 2B). On the plurality of wirings 2Y (refer to FIG. 2C), a plurality of plate-shaped stress relaxation portions 4Z extending to intersect with the plurality of wirings 2Y at right angles can be provided as the protruding stress relaxation portions 4.

第16圖用於製造半導體裝置之方法包括在半導體基板1之正面側上形成電路層5的製程。電路層5包括電晶體5A，藉由用絕緣材料填充半導體基板1中之元件隔離凹槽而形成的元件隔離區5B，耦合至電晶體5A的插塞5D，以及絕緣薄膜5C。當元件隔離區5B在形成電路層5的製程中形成時，可形成應力鬆弛部4的部份4A，部份4A由與被包含於元件隔離區5B之中者實質相同的絕緣材料製成。當插塞5D在形成電路層5的製程中形成時，含有與插塞5D材料實質相同之材料的部份4C可形成於應力鬆弛部4的部份4A上，部份4A含有與被包含於元件隔離區5B之中者實質相同的絕緣材料。然後，絕緣薄膜5C可覆蓋這些組件。 The method for fabricating a semiconductor device of Fig. 16 includes a process of forming a circuit layer 5 on the front side of the semiconductor substrate 1. The circuit layer 5 includes a transistor 5A, an element isolation region 5B formed by filling an element isolation groove in the semiconductor substrate 1 with an insulating material, a plug 5D coupled to the transistor 5A, and an insulating film 5C. When the element isolation region 5B is formed in the process of forming the circuit layer 5, the portion 4A of the stress relaxation portion 4 can be formed, and the portion 4A is made of an insulating material substantially the same as that contained in the element isolation region 5B. When the plug 5D is formed in the process of forming the circuit layer 5, the portion 4C containing the material substantially the same as the material of the plug 5D can be formed on the portion 4A of the stress relaxation portion 4, and the portion 4A contains and is included in The insulating material of substantially the same among the element isolation regions 5B. Then, the insulating film 5C can cover these components.

形成貫穿孔3X的製程可包括形成應力鬆弛部4(4X)，其係包括含有與被包含於元件隔離區5B之中者實質相同之絕緣材料的部份4A，含有與絕緣薄膜5C材料實質相同之絕緣材料的部份4B，以及含有與插塞5D材料實質相同之材料的部份4C。例如，形成貫穿孔3X的製程可包括形成應力鬆弛部4(4X)，其中用含有與被包含於元件隔離區5B之中者實質相同之絕緣材料的部份4A以及含 有與絕緣薄膜5C材料實質相同之絕緣材料的部份4B包圍含有與插塞5D材料實質相同之材料的部份4C。 The process of forming the through hole 3X may include forming the stress relaxation portion 4 (4X) including the portion 4A containing substantially the same insulating material as that contained in the element isolation region 5B, and containing substantially the same material as the insulating film 5C. The portion 4B of the insulating material and the portion 4C containing the material substantially the same as the material of the plug 5D. For example, the process of forming the through hole 3X may include forming the stress relaxation portion 4 (4X) in which the portion 4A containing the insulating material substantially the same as that included in the element isolation region 5B is included and The portion 4B having the insulating material substantially the same as the insulating film 5C material surrounds the portion 4C containing the material substantially the same as the material of the plug 5D.

第17圖為半導體裝置之橫截面圖的一實施例。例如，如第17圖所示，該半導體裝置可包括在半導體基板1之正面側上的電路層5。電路層5可包括絕緣薄膜5C與包括閘極絕緣薄膜5E的電晶體5A。應力鬆弛部4可包括含有與閘極絕緣薄膜5E材料實質相同之絕緣材料的部份4D以及含有與絕緣薄膜5C材料實質相同之絕緣材料的部份4B。在第17圖中，元件符號5F表示閘極電極。 Figure 17 is an embodiment of a cross-sectional view of a semiconductor device. For example, as shown in FIG. 17, the semiconductor device may include the circuit layer 5 on the front side of the semiconductor substrate 1. The circuit layer 5 may include an insulating film 5C and a transistor 5A including a gate insulating film 5E. The stress relaxation portion 4 may include a portion 4D containing an insulating material substantially the same as that of the gate insulating film 5E, and a portion 4B containing an insulating material substantially the same as the material of the insulating film 5C. In Fig. 17, the symbol 5F indicates a gate electrode.

應力鬆弛部4包括在其末端由絕緣材料製成的部份4D。應力鬆弛部4可包括由不同絕緣材料製成的部份4D及4B。閘極絕緣薄膜5E的材料實施例包括絕緣材料(金屬氧化物材料)，例如HfO2，HfSiON，HfAlO，LaO，以及ZrO2。如第17圖所示，在被包含於配線層2中之配線的焊墊2X上，可提供多個柱狀應力鬆弛部4X作為突出應力鬆弛部4，焊墊2X耦合至貫穿通孔3。 The stress relaxation portion 4 includes a portion 4D made of an insulating material at its end. The stress relaxation portion 4 may include portions 4D and 4B made of different insulating materials. Examples of the material of the gate insulating film 5E include an insulating material (metal oxide material) such as HfO 2 , HfSiON, HfAlO, LaO, and ZrO 2 . As shown in FIG. 17, a plurality of columnar stress relaxation portions 4X can be provided as the protruding stress relaxation portions 4 on the pads 2X of the wirings included in the wiring layer 2, and the pads 2X are coupled to the through vias 3.

例如，在焊墊2X上，可提供在貫穿通孔3徑向延伸且以直角相交的板狀應力鬆弛部4Y作為突出應力鬆弛部4(參考第2A圖)。在多個配線2Y(參考第2B圖)上，可提供多個柱狀應力鬆弛部4X作為突出應力鬆弛部4。在多個配線2Y(參考第2C圖)上，可提供延伸成與多個配線2Y直角相交的多個板狀應力鬆弛部4Z作為突出應力鬆弛部4。 For example, in the bonding pad 2X, a plate-shaped stress relaxation portion 4Y extending in the radial direction through the through hole 3 and intersecting at right angles can be provided as the protruding stress relaxation portion 4 (refer to FIG. 2A). In the plurality of wirings 2Y (refer to FIG. 2B), a plurality of columnar stress relaxation portions 4X can be provided as the protruding stress relaxation portions 4. In the plurality of wirings 2Y (refer to FIG. 2C), a plurality of plate-shaped stress relaxation portions 4Z extending to intersect with the plurality of wirings 2Y at right angles can be provided as the protruding stress relaxation portions 4.

第17圖用於製造半導體裝置之方法包括在 半導體基板1之正面側上形成電路層5的製程。電路層5包括絕緣薄膜5C與包括閘極絕緣薄膜5E的電晶體5A。當閘極絕緣薄膜5E在形成電路層5的製程中形成時，可形成應力鬆弛部4的部份4D，部份4D含有與閘極絕緣薄膜5E材料實質相同之絕緣材料。然後，可用絕緣薄膜5C覆蓋這些組件。 Figure 17 is a diagram of a method for fabricating a semiconductor device including A process of forming the circuit layer 5 on the front side of the semiconductor substrate 1. The circuit layer 5 includes an insulating film 5C and a transistor 5A including a gate insulating film 5E. When the gate insulating film 5E is formed in the process of forming the circuit layer 5, the portion 4D of the stress relaxation portion 4 may be formed, and the portion 4D contains an insulating material substantially the same as that of the gate insulating film 5E. Then, these components can be covered with an insulating film 5C.

形成貫穿孔3X的製程可包括形成應力鬆弛部4(4X)，其係包括含有與閘極絕緣薄膜5E材料實質相同之絕緣材料的部份4D以及含有與絕緣薄膜5C材料實質相同之絕緣材料的部份4B。 The process of forming the through hole 3X may include forming the stress relaxation portion 4 (4X) including the portion 4D containing the insulating material substantially the same as the material of the gate insulating film 5E and the insulating material substantially the same as the material of the insulating film 5C. Part 4B.

1‧‧‧半導體基板 1‧‧‧Semiconductor substrate

2‧‧‧配線層 2‧‧‧Wiring layer

2A‧‧‧配線 2A‧‧‧Wiring

2B‧‧‧絕緣薄膜(層間絕緣薄膜) 2B‧‧‧Insulating film (interlayer insulating film)

2X‧‧‧配線、焊墊(電極) 2X‧‧‧Wiring, pad (electrode)

3‧‧‧貫穿通孔 3‧‧‧through through hole

3A‧‧‧種子層 3A‧‧‧ seed layer

3B‧‧‧鍍銅層 3B‧‧‧ copper plating

3X‧‧‧貫穿孔 3X‧‧‧through holes

4‧‧‧應力鬆弛部 4‧‧‧stress relaxation department

4A、4B‧‧‧部份 4A, 4B‧‧‧Parts

4X‧‧‧柱狀應力鬆弛部 4X‧‧‧ columnar stress relaxation

5‧‧‧電路層 5‧‧‧ circuit layer

5A‧‧‧電晶體 5A‧‧‧O crystal

5B‧‧‧元件隔離區 5B‧‧‧Component isolation area

5C‧‧‧絕緣薄膜 5C‧‧‧Insulation film

5D‧‧‧插塞 5D‧‧‧ plug

5F‧‧‧閘極 5F‧‧‧ gate

Claims (15)

一種半導體裝置，其係包含：半導體基板；配線層，其係設於該半導體基板之正面側上；貫穿通孔，其係從該半導體基板之背面側穿透該半導體基板且耦合至被包含於該配線層中的配線；以及應力鬆弛部，其係向貫穿通孔側突出且設置於該配線中之一區段且耦合至該貫穿通孔，該應力鬆弛部包括至少一個絕緣部，該絕緣部含有熱膨脹係數小於該貫穿通孔之材料之絕緣材料。 A semiconductor device comprising: a semiconductor substrate; a wiring layer disposed on a front side of the semiconductor substrate; and a through hole penetrating the semiconductor substrate from a back side of the semiconductor substrate and coupled to be included in a wiring in the wiring layer; and a stress relaxation portion protruding toward the through hole side and disposed in one of the wiring and coupled to the through hole, the stress relaxation portion including at least one insulating portion, the insulation The portion contains an insulating material having a coefficient of thermal expansion smaller than that of the through-hole. 如申請專利範圍第1項所述之半導體裝置，其中，該至少一個絕緣部設在該應力鬆弛部的一端。 The semiconductor device according to claim 1, wherein the at least one insulating portion is provided at one end of the stress relaxation portion. 如申請專利範圍第1項所述之半導體裝置，更包含：電路層，其係設在該半導體基板之該正面側上且包括電晶體、元件隔離區及絕緣薄膜，該元件隔離區係藉由用絕緣材料填充在該半導體基板中的元件隔離凹槽而形成者。 The semiconductor device of claim 1, further comprising: a circuit layer disposed on the front side of the semiconductor substrate and including a transistor, an element isolation region, and an insulating film, wherein the device isolation region is Formed by filling an element isolation groove in the semiconductor substrate with an insulating material. 如申請專利範圍第3項所述之半導體裝置，其中，該應力鬆弛部包括含有被包含於該元件隔離區中之第一絕緣材料的第一絕緣部以及含有被包含於該絕緣薄膜中之第二絕緣材料的第二絕緣部。 The semiconductor device according to claim 3, wherein the stress relaxation portion includes a first insulating portion including a first insulating material included in the element isolation region, and a first portion included in the insulating film a second insulating portion of the second insulating material. 如申請專利範圍第3項所述之半導體裝置， 其中，該電路層包括耦合至該電晶體的插塞，該應力鬆弛部包括：第一絕緣部，係含有被包含於該元件隔離區中之第一絕緣材料；以及第三絕緣部，係含有被包含於該絕緣薄膜中之第二絕緣材料以及該插塞之材料。 The semiconductor device according to claim 3, Wherein the circuit layer includes a plug coupled to the transistor, the stress relaxation portion comprising: a first insulating portion containing a first insulating material included in the element isolation region; and a third insulating portion containing a second insulating material included in the insulating film and a material of the plug. 如申請專利範圍第5項所述之半導體裝置，其中，在該第三絕緣部中的該第二絕緣材料係包圍該插塞之該材料。 The semiconductor device of claim 5, wherein the second insulating material in the third insulating portion surrounds the material of the plug. 如申請專利範圍第3項所述之半導體裝置，其中，該電晶體包括閘極絕緣薄膜，該應力鬆弛部包括：第二絕緣部，係含有被包含於該絕緣薄膜中之第二絕緣材料；以及第四絕緣部，係含有該閘極絕緣薄膜之第三絕緣材料。 The semiconductor device of claim 3, wherein the transistor comprises a gate insulating film, and the stress relaxation portion comprises: a second insulating portion containing a second insulating material contained in the insulating film; And a fourth insulating portion is a third insulating material containing the gate insulating film. 一種用於製造半導體裝置之方法，該方法包含下列步驟：形成應力鬆弛部，該應力鬆弛部係由半導體基板中將會形成包含配線之配線層於其上的正面朝向該半導體基板的背面側突出，該應力鬆弛部包括至少一絕緣部，該絕緣部含有熱膨脹係數小於貫穿通孔之材料之絕緣材料；藉由蝕刻掉用於形成從半導體基板之背面側穿透 該半導體基板且耦合至該配線之該貫穿通孔的區域來形成貫穿孔；以及藉由用該貫穿通孔之該材料填充該貫穿孔來形成該貫穿通孔。 A method for manufacturing a semiconductor device, comprising the steps of: forming a stress relaxation portion protruding from a front surface of a semiconductor substrate on which a wiring layer including wiring is to be formed toward a back side of the semiconductor substrate The stress relaxation portion includes at least one insulating portion including an insulating material having a thermal expansion coefficient smaller than a material penetrating the through hole; and is formed by etching away from the back side of the semiconductor substrate The semiconductor substrate is coupled to a region of the through hole of the wiring to form a through hole; and the through hole is formed by filling the through hole with the material of the through hole. 如申請專利範圍第8項所述用於製造半導體裝置之方法，該方法更包含下列步驟：在該半導體基板之正面側上，形成包括電晶體、元件隔離區及絕緣薄膜的電路層。 The method for manufacturing a semiconductor device according to claim 8, wherein the method further comprises the step of forming a circuit layer including a transistor, an element isolation region, and an insulating film on a front side of the semiconductor substrate. 如申請專利範圍第9項所述用於製造半導體裝置之方法，該方法更包含下列步驟：當形成該元件隔離區於該半導體基板中時，形成該絕緣部；以及用該絕緣薄膜覆蓋該元件隔離區及該應力鬆弛部。 The method for manufacturing a semiconductor device according to claim 9, wherein the method further comprises the steps of: forming the insulating portion when the element isolation region is formed in the semiconductor substrate; and covering the device with the insulating film The isolation zone and the stress relaxation section. 如申請專利範圍第10項所述用於製造半導體裝置之方法，該方法更包含下列步驟：藉由蝕刻在該應力鬆弛部上的該絕緣薄膜來形成第一絕緣部及第二絕緣部，該第一絕緣部含有被包含於該元件隔離區中之第一絕緣材料，該第二絕緣部含有被包含於該絕緣薄膜中之第二絕緣材料。 The method for manufacturing a semiconductor device according to claim 10, further comprising the steps of: forming a first insulating portion and a second insulating portion by etching the insulating film on the stress relaxation portion, The first insulating portion includes a first insulating material included in the element isolation region, and the second insulating portion contains a second insulating material included in the insulating film. 如申請專利範圍第10項所述用於製造半導體裝置之方法，其中，該電路層包括形成於該絕緣薄膜中且耦合至該電晶體的插塞， 該方法更包含下列步驟：藉由蝕刻在該應力鬆弛部上的該絕緣薄膜來形成第一絕緣部及第三絕緣部，該第一絕緣部含有被包含於該元件隔離區中之第一絕緣材料，該第三絕緣部含有被包含於該絕緣薄膜中之第二絕緣材料以及被包含於該插塞中之材料。 The method for manufacturing a semiconductor device according to claim 10, wherein the circuit layer comprises a plug formed in the insulating film and coupled to the transistor, The method further includes the steps of: forming a first insulating portion and a third insulating portion by etching the insulating film on the stress relaxation portion, the first insulating portion containing a first insulating included in the element isolation region The material, the third insulating portion contains a second insulating material contained in the insulating film and a material contained in the plug. 如申請專利範圍第12項所述用於製造半導體裝置之方法，其中，在該第三絕緣部中的該第二絕緣材料係包圍被包含於該插塞中之該材料。 The method for manufacturing a semiconductor device according to claim 12, wherein the second insulating material in the third insulating portion surrounds the material contained in the plug. 如申請專利範圍第9項所述用於製造半導體裝置之方法，其中，該電晶體包括閘極絕緣薄膜，該方法更包含下列步驟：藉由蝕刻在該應力鬆弛部上的該絕緣薄膜來形成第二絕緣部及第四絕緣部，該第二絕緣部含有被包含於該絕緣薄膜中之第二絕緣材料，該第四絕緣部含有被包含於該閘極絕緣薄膜中之第三絕緣材料。 The method for manufacturing a semiconductor device according to claim 9, wherein the transistor comprises a gate insulating film, the method further comprising the step of: forming the insulating film on the stress relaxation portion by etching The second insulating portion and the fourth insulating portion include a second insulating material included in the insulating film, and the fourth insulating portion includes a third insulating material included in the gate insulating film. 如申請專利範圍第14項所述用於製造半導體裝置之方法，其中，在該應力鬆弛部的一端形成該第四絕緣部。 The method for manufacturing a semiconductor device according to claim 14, wherein the fourth insulating portion is formed at one end of the stress relaxation portion.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI761071B (en) * 2020-03-31 2022-04-11 台灣積體電路製造股份有限公司 Method of forming semiconductor structure and method of forming bonded semiconductor chip

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107887285A (en) * 2016-09-30 2018-04-06 中芯国际集成电路制造(北京)有限公司 Welding pad structure and its manufacture method and imaging sensor
WO2018088462A1 (en) 2016-11-10 2018-05-17 株式会社ラック Communication controller, communication control method, and program
KR102481818B1 (en) 2017-08-22 2022-12-28 삼성디스플레이 주식회사 Electronic component, electric device including the same
JP7182970B2 (en) * 2018-09-20 2022-12-05 東京エレクトロン株式会社 Embedding method and processing system
WO2023112689A1 (en) * 2021-12-13 2023-06-22 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device, method for producing same, and electronic device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3560810A (en) * 1968-08-15 1971-02-02 Ibm Field effect transistor having passivated gate insulator
US7692315B2 (en) * 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
JP4189198B2 (en) * 2002-10-24 2008-12-03 株式会社東芝 Semiconductor device and manufacturing method thereof
US7563714B2 (en) * 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same
JP4585561B2 (en) * 2007-09-04 2010-11-24 株式会社東芝 Manufacturing method of semiconductor device
JP5537016B2 (en) 2008-10-27 2014-07-02 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
JP5565272B2 (en) * 2010-10-29 2014-08-06 富士通株式会社 Through electrode substrate
US8900994B2 (en) * 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
JP5994167B2 (en) * 2011-11-15 2016-09-21 ローム株式会社 Semiconductor device, manufacturing method thereof, and electronic component
JP2013247139A (en) * 2012-05-23 2013-12-09 Ps4 Luxco S A R L Semiconductor device and method of manufacturing the same
JP2014011248A (en) * 2012-06-28 2014-01-20 Ps4 Luxco S A R L Semiconductor device and manufacturing method of the same
JP6160901B2 (en) * 2013-02-08 2017-07-12 ローム株式会社 Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI761071B (en) * 2020-03-31 2022-04-11 台灣積體電路製造股份有限公司 Method of forming semiconductor structure and method of forming bonded semiconductor chip
US11482506B2 (en) 2020-03-31 2022-10-25 Taiwan Semiconductor Manufacturing Company Limited Edge-trimming methods for wafer bonding and dicing

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