JP2018019337A - State detection circuit and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of detection targets with a simple configuration by solving trade-off between accuracy required by resistors and the number of detectable targets (the number of resistors connectable in parallel).SOLUTION: A state detection circuit is provided for detecting open/closed states of N switches to be opened/closed in accordance with a state of an apparatus. The state detection circuit comprises: a parallel circuit including N resistors which are connected in parallel and of which the resistance values are different from each other; and a voltage dividing circuit connected in series to one ends of the N resistors and having a fixed resistance value. The other ends of the N resistors are configured to be connectable in series to the N switches. The fixed resistance value is closer to a combined resistance value of the parallel circuit in the closed states of all the N resistors than a resistance value of a resistor of which the resistance value is minimum in the N resistors.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a state detection circuit that detects each state of a plurality of devices and an image forming apparatus having the state detection circuit.

  A typical image forming apparatus (for example, a printer, a multifunction printer, or a multifunction peripheral) has a plurality of devices inside, and a plurality of sensors (for example, a detection switch or a photo interrupter) for detecting the state of the apparatus. The state of the plurality of devices includes states such as the rotation state of the motor, the remaining state of the printing paper, the placement of the document on the automatic document feeder (ADF), and whether or not the optional device is mounted. Patent Document 1 proposes a technique in which digital output values of a plurality of sensors are D / A converted into analog voltage signals and input to an analog port of a CPU included in a control unit of the image forming apparatus. As a result, output signals from a large number of sensors can be combined into a single signal line. With realizing the simplification can reduce the number of used ports of the CPU.

JP 2008-059161 A JP 2009-278196 A JP 11-242538 A

  However, as the number of sensors to be detected increases, the number of resistors in the parallel circuit included in the D / A conversion increases, and the voltage accuracy required for the analog voltage signal becomes severe. For this reason, it has become a factor of the limit of the number of detection targets.

  The present invention has been made in view of such a situation, and provides a technique for increasing the number of detection objects with a simple configuration by solving the trade-off between the accuracy required for the resistor and the detectable number. Objective.

  The present invention provides a state detection circuit that detects the open / closed state of N switches that open and close according to the state of a device. This state detection circuit includes a parallel circuit having N resistors that are connected in parallel and having different resistance values, and a fixed resistance value that is connected in series to one end of the N resistors. Pressure circuit. The other ends of the N resistors are configured to be connected in series to the N switches. The fixed resistance value is closer to the combined resistance value of the parallel circuit in which all the N resistors are closed than the resistance value of the resistor having the smallest resistance value among the N resistors.

  In the above state detection circuit, N may be an integer of 3 or more.

  In the state detection circuit, the N is 4, the four resistors have a resistance value of a ratio of 1: 2: 4: 8, and the fixed resistance value is a ratio of the resistance value. May be 50% to 75% of the resistance value of one resistor.

  In the state detection circuit, the N is 4, the four resistors have a resistance value of a ratio of 1: 2: 4: 8, and the fixed resistance value is a ratio of the resistance value. May be 53% to 57% of the resistance value of one resistor.

  In the state detection circuit, the N is 3, the three resistors have a resistance value of a ratio of 1: 2: 4, and the fixed resistance value has a ratio of the resistance value of 1. The resistance value of the resistor may be 50% to 75%.

  In the state detection circuit, the N is 3, the three resistors have a resistance value of a ratio of 1: 2: 4, and the fixed resistance value has a ratio of the resistance value of 1. The resistance value of the resistor may be 57% to 67%.

  The present invention provides an image forming apparatus. The image forming apparatus includes the state detection circuit described above and an image forming unit having a plurality of states whose states are detected by the state detection circuit.

  According to the present invention, the number of detection targets can be increased with a simple configuration by solving the trade-off between the accuracy required for the resistors and the number of detectable elements (the number of resistors that can be paralleled).

1 is a block diagram showing a functional configuration of an image forming apparatus according to a first embodiment of the present invention. The table | surface which shows the change of the synthetic resistance and synthetic resistance of the parallel circuit which the state detection circuit which concerns on 1st Embodiment has. The graph which shows the output potential of the state detection circuit which concerns on 1st Embodiment. The table | surface which shows the change of the synthetic resistance and synthetic resistance of the parallel circuit which the state detection circuit which concerns on the modification of 1st Embodiment has. The graph which shows the output potential of the state detection circuit which concerns on the modification of 1st Embodiment. 9 is a flowchart showing a state detection procedure of the image forming apparatus according to the second embodiment of the present invention. The table | surface which normalizes and shows the change of the output electric potential of the state detection circuit which concerns on 2nd Embodiment, and an output electric potential. The table | surface which normalizes and shows the change of an output potential and output potential when the option apparatus of the state detection circuit which concerns on 2nd Embodiment is not mounted | worn. The table | surface which normalizes and shows the change of an output electric potential when the optional apparatus of the state detection circuit which concerns on 2nd Embodiment is mounted | worn, and an output electric potential. The table | surface which normalizes and shows the change of the correction | amendment output potential of the state detection circuit which concerns on 2nd Embodiment, and a correction | amendment output potential.

  Hereinafter, modes for carrying out the present invention (hereinafter referred to as “embodiments”) will be described with reference to the drawings.

A. First embodiment:
FIG. 1 is a block diagram showing a functional configuration of an image forming apparatus 1 according to an embodiment of the present invention. The image forming apparatus 1 includes a control unit 10, an automatic document feeder (ADF) 21, a conveyance unit 22, a motor 23, an optional device 24, a state detection circuit 30, and a storage unit 40, and is used for printing. It functions as an image forming unit that forms an image. The state detection circuit 30 detects the states of the automatic document feeder (ADF) 21, the conveyance unit 22, the motor 23, and the optional device 24, and controls the detection result from the output terminal 36 as an analog voltage value Sa as an output potential. Input to section 10.

  The control unit 10 includes main storage means such as RAM and ROM, and control means such as MPU (Micro Processing Unit) and CPU (Central Processing Unit). The control unit 10 also has controller functions related to various I / O, USB (Universal Serial Bus), bus, and other hardware such as hardware, and controls the entire image forming apparatus 1.

  The storage unit 40 is a storage device including a hard disk drive or a flash memory that is a non-temporary recording medium, and stores a control program and data for processing executed by the control unit 10.

  The ADF 21 can detect the placed state of the printed document by a photo interrupter. The photo interrupter includes a light emitting diode 21L as a light source and a light receiving element SW1 (also simply referred to as a switch). When the printed document is placed, the light of a light emitting diode (not shown) is shielded by the printed document, the switch SW1 is opened (Open), and when the printed document disappears, the switch SW1 is irradiated with light and closed ( (Low) state.

  The transport unit 22 has a paper feed tray (not shown). Printing paper is stored in the paper feed tray, and its remaining state can be detected by a photo interrupter. The photo interrupter includes a light emitting diode 22L as a light source and a light receiving element SW2 (also referred to as a switch). When the printing paper remains, light from a light emitting diode (not shown) is blocked by the printing paper, the switch SW2 is opened (Open), and when the printing paper runs out, the switch SW2 is irradiated with light and closed (Low). Transition to. The switches SW1 and SW2 may be mechanical switches.

  The motor 23 has an open collector specification that is closed (Low) only when the operation is in a steady rotation state. The motor 23 has an NPN transistor SW3 (also referred to as a switch) for outputting the operation state of the motor 23 as an open collector output. The motor 23 shifts to a closed (Low) state when the switch SW3 is in an open (Open) state at the time of start-up and the operation is in a steady rotation state.

  The optional device 24 has a connector (not shown) for electrical connection with the control unit 10. The connector has a jumper line SW4 (also called a switch). The switch SW4 is in a closed (Low) state when the optional device 24 is electrically connected to the control unit 10, and transitions to an open (Open) state when the optional device 24 is removed from the control unit 10.

  The state detection circuit 30 has the following configuration as a D / A conversion circuit. The state detection circuit 30 includes a first resistor 31, a second resistor 32, a third resistor 33, a fourth resistor 34, and a voltage dividing resistor 35. One end of the voltage dividing resistor 35 is connected to the positive power supply potential Vcc. The other end of the voltage dividing resistor 35 is connected in series to one end of a parallel circuit of the first resistor 31, the second resistor 32, the third resistor 33, and the fourth resistor 34. The resistance values of the first resistor 31, the second resistor 32, the third resistor 33, and the fourth resistor 34 are resistors having a ratio of R, 2R, 4R, and 8R (ratio of resistance values is 1: 2: 4: 8), respectively. Has a value.

  The other end (terminal 31t) of the first resistor 31 is connected to one end of the switch SW1 of the ADF 21. The other end of the switch SW1 is grounded. The other end (terminal 32t) of the second resistor 32 is connected to one end of the switch SW2 of the transport unit 22. The other end of the switch SW2 is grounded. The other end (terminal 33t) of the third resistor 33 is connected to one end of the switch SW3 of the motor 23. The other end of the switch SW3 is grounded. The other end (terminal 34t) of the fourth resistor 34 is connected to one end of the switch SW4 of the option device 24. The other end of the switch SW4 is grounded.

  FIG. 2 is a table showing a change in the combined resistance value Z and the combined resistance value Z of the parallel circuits 31, 32, 33, and 34 included in the state detection circuit 30 according to the first embodiment. This table shows the open / closed states of the four switches SW1, SW2, SW3, SW4 and the combined resistance value Z at that time. The change in the combined resistance value Z indicates the minimum change amount in the change in the open / closed state of the four switches SW1, SW2, SW3, SW4.

Specifically, for example, when the plurality of devices (ADF 21, transport unit 22, motor 23, and optional device 24) are in the following state, the combined resistance value Z is 2.67R (nominal value).
(1) ADF 21: Print document is placed, switch SW1 is open (Open) (2) Conveying unit 22: print paper exists, switch SW2 is open (Open)
(3) Motor 23: Switch SW3 is closed (Low) because it is in a steady rotation state.
(4) Optional device 24: electrically connected to the control unit 10 and the switch SW4 is closed (Low)

  As can be seen from FIG. 2, conversely, the state where the combined resistance value Z is in the vicinity of 2.67 is only the above state. Thus, since each state of each device and the combined resistance value Z correspond one-to-one, the state of each device can be detected based on the combined resistance value Z. As described above, the state of each device is detected based on a change in the combined resistance value Z corresponding to the open / closed states of the four switches SW1, SW2, SW3, SW4.

  However, the amount of change in the combined resistance value Z decreases as each of the four switches SW1, SW2, SW3, SW4 is closed and the combined resistance value Z decreases. Specifically, the amount of change in the combined resistance value Z due to the opening and closing of the switch SW4 is as large as 1.33R when the two switches SW1 and SW2 are open and the switch SW3 is closed, but the three switches When all of SW1, SW2, and SW3 are closed, the value is as small as 0.04R.

  When the amount of change in the combined resistance value Z is excessively small, the detection reliability is lowered, and a reverse phenomenon occurs depending on manufacturing tolerances of the first resistor 31, the second resistor 32, the third resistor 33, and the fourth resistor 34. Cases are also envisaged.

  FIG. 3 is a graph showing the output potential of the state detection circuit 30 according to the first embodiment. In designing a D / A conversion circuit, according to conventional common general knowledge, a parallel circuit (a parallel connection of a first resistor 31, a second resistor 32, a third resistor 33, and a fourth resistor 34) connected to a voltage dividing resistor 35 is used. The resistance value X of the voltage dividing resistor 35 is set so that the amount of change in the output potential increases in accordance with the change in the combined resistance value Z).

  Specifically, the resistance value X of the voltage dividing resistor 35 is the resistance value R of the first resistor 31 having the smallest resistance value among the first resistor 31, the second resistor 32, the third resistor 33, and the fourth resistor 34. The same resistance value is set (X = R). Thereby, as can be seen from FIG. 3, a change amount of the potential corresponding to 65% of the positive power supply potential Vcc can be generated. Such an idea forms common technical knowledge of those skilled in the art in designing a D / A conversion circuit (see, for example, the selection diagram of Patent Document 1).

  However, the inventor has created a technical idea for designing a D / A conversion circuit from a different point of view. As described above, the conventional technical idea is that the D / A converter circuit is configured such that the amount of change in the output potential increases in accordance with the change in the combined resistance value Z of the parallel circuit connected to the voltage dividing resistor 35. doing. On the other hand, this technical idea configures the D / A converter circuit so that the minimum change amount of the combined resistance value Z in the change of the open / close state of the four switches SW1, SW2, SW3, SW4 is increased. Yes.

  The minimum change amount of the combined resistance value Z in the change in the open / closed state of the four switches SW1, SW2, SW3, SW4 is that the three switches SW1, SW2, SW3 are in the closed state and the switch SW4 is in the closed state. This is the amount of change (0.04R) at the time of transition (see FIG. 2).

  The inventor of the present application configures the resistance value X of the voltage dividing resistor 35 to coincide with the combined resistance value Z of the parallel circuit when the three switches SW1, SW2, and SW3 are in the closed state and the switch SW4 is in the open state. Thus, it has been found that even if the change amount of the combined resistance value Z is small, the change amount of the output potential of the voltage dividing circuit can be increased. By so doing, the combined resistance value Z (0.57R) of the parallel circuit before the switch SW4 transitions from the open state to the closed state and the resistance value X of the voltage dividing resistor 35 are divided to an intermediate potential of the positive power supply potential Vcc. (X = 0.57R).

  Thereby, as can be seen from FIG. 3, the amount of change when the three switches SW1, SW2 and SW3 are in the closed state and the switch SW4 transitions from the open state (state 14) to the closed state (state 15) is 0. It increases from 0158 (X = R) to 0.0172 (X = 0.57R). On the other hand, the total change amount of the combined resistance value Z in the change in the open / close state of the four switches SW1, SW2, SW3, SW4 is reduced from 65% to 52%.

  The technical idea is that the combined resistance value in a state where the amount of change in the combined resistance value Z is small (a state in the vicinity of state 14), compared to a state where the amount of change in the combined resistance value Z is large (a state in the vicinity of state 1) It is characterized in that the resistance value X of the voltage dividing resistor 35 is set so as to allocate a region where the sensitivity of the potential change with respect to the Z change is large. In a state where the amount of change in the combined resistance value Z is large, even if the sensitivity of the potential change with respect to the change in the combined resistance value Z is relatively small, there is no problem because the amount of change in the combined resistance value Z is large. Resource allocation.

  This point can also be confirmed from the fact that the plot (X = 0.57R) is on a straight line compared to the plot (X = R) in FIG. In the plot (X = R), the overall potential change is relatively large (65%), but the potential change is excessively large in states 1 to 8, and the potential change is saturated in states 9 to 15. On the other hand, in the plot (X = 0.57R), although the overall potential change is relatively small (52%), the potential change in the states 1 to 8 is suppressed, and in the states 9 to 15, the potential change is saturated. Is suppressed.

  FIG. 4 is a table showing the combined resistance of the parallel circuit included in the state detection circuit according to the modification of the first embodiment. FIG. 5 is a graph showing the output potential of the state detection circuit 30 according to a modification of the first embodiment. The modification has a configuration in which the switch SW4 is deleted from the configuration of the first embodiment, and is common to other configurations.

  Similar effects can be obtained in the modification. That is, in the plot (X = R), the overall potential change is relatively large (64%), but the potential change is excessively large in states 1 to 4, and the potential change is saturated in states 5 to 7. Yes. On the other hand, in the plot (X = 0.67R), the overall potential change is relatively small (54%), but the potential change in the states 1 to 4 is suppressed, and in the states 5 to 7, the potential change is saturated. Is suppressed.

  As described above, the first embodiment uses a novel technical idea that is essentially different from the conventional technical idea, and reduces the change in the combined resistance value Z of the parallel circuit of the D / A converter circuit. The problem is solved by increasing the sensitivity of the potential change to the change in the combined resistance value Z with a simple configuration in which the resistance value X of the voltage dividing resistor 35 is appropriately set. As a result, the trade-off between the accuracy required for the resistor and the detectable number (the number of resistors that can be paralleled) can be solved and the number of detection targets can be increased.

  In the first embodiment, the resistance value X of the voltage dividing resistor 35 matches the combined resistance value Z of the parallel circuit when the three switches SW1, SW2, and SW3 are closed and the switch SW4 is open. Although not necessarily required to match, the resistance value R of the first resistor 31 having the smallest resistance value among the first resistor 31, the second resistor 32, the third resistor 33, and the fourth resistor 34 is configured. Rather than the combined resistance value Z of the parallel circuit when all four switches SW1, SW2, SW3, SW4 are closed, or the three switches SW1, SW2, SW3 are closed and the switch SW4 is open. It is sufficient if it is close to the combined resistance value Z of the parallel circuit. This is because the effect of the present embodiment can be achieved.

  In the present embodiment, the upper limit may be set to be less than 0.785R (or less than 0.75R). On the other hand, since the technical effect of the present invention does not increase even if the lower limit is 0.53 R or less, it has been confirmed by simulation of the present inventor that the lower limit is preferably 0.5 R or more. In the present embodiment, the voltage dividing resistor 35 is configured as a single resistor having a resistance value X. However, the voltage dividing circuit (for example, configured by a plurality of resistors) having a fixed resistance value for voltage division. Circuit). In the present embodiment, the most preferable region of the resistance value X is a range in which the three switches SW1, SW2, and SW3 are closed and the switch SW4 is opened and closed, that is, between 0.53R and 0.57R. Range.

  In the modified example, the most preferable region of the resistance value X is a range where the two switches SW1 and SW2 are closed and the switch SW3 is opened / closed, that is, a range between 0.57R and 0.67R. is there. However, if it is in the range between 0.5R and 0.75R, the effect of the present invention can be obtained as in the first embodiment.

B. Second embodiment:
FIG. 6 is a flowchart showing a state detection procedure of the image forming apparatus 1 according to the second embodiment of the present invention. The image forming apparatus 1 according to the second embodiment has the same configuration as the image forming apparatus 1 according to the first embodiment. In step S10, the image forming apparatus 1 is activated, for example, when the power is turned on. In step S20, the image forming apparatus 1 performs an initial operation. The initial operation includes a startup process of the control unit 10, a startup process of the photo interrupter (light emitting diode 21L, light receiving element SW1), and a startup process of the motor 23.

  The control unit 10 reads out a control program and data for processing executed by the control unit 10 from the storage unit 40 and executes activation processing. When the activation is completed, the control unit 10 starts supplying power to the photo interrupter (light emitting diode 21L, light receiving element SW1) and the state detection circuit 30. However, the control unit 10 waits for the light emission of the light emitting diode 21L for a predetermined time set in advance from activation. Thereby, the light emitting diode 21L does not emit light for a predetermined time set in advance from activation. A circuit for delaying the light emission of the light emitting diode 21L for a predetermined time set in advance from the start may be provided.

  The control unit 10 further executes a startup process of the motor 23. As described above, since the motor 23 is an open collector specification that is closed (Low) only when the operation is in a steady rotation state, the switch SW3 is open (Open) at the time of startup. As described above, the image forming apparatus 1 knows in advance that the two switches SW1 and SW3 are in the open state for a certain period of time during the startup process.

  FIG. 7 is a table showing normalized output potentials and changes in output potentials of the state detection circuit 30 according to the second embodiment. The image forming apparatus 1 knows in advance that the two switches SW1 and SW3 are open for a certain period of time during the startup process. As described above, the control unit 10 waits for the light emission of the light emitting diode 21L for a predetermined time from the start-up, and the motor 23 enters a steady rotation state after a predetermined time from the start-up. is there. Accordingly, the switch SW4 of the option device 24 in the open state (Open) is switched to the open (Open) state (State 0) and the closed (Low) state (State 1), and the switch SW2 of the transport unit 22 is switched. Only four states are assumed, in which the switch SW4 of the option device 24 in the closed (Low) state is in an open (Open) state (State 4) and a closed (Low) state (State 5).

  In step S <b> 30, the image forming apparatus 1 detects the connection state of the optional device 24. The detection of the connection state of the option device 24 is detection of either state 0 or state 1 (output difference = 0.0667) or detection of either state 4 or state 5 (output difference = 0.0409). Since any detection has a sufficient output difference, it can be detected without any problem.

  In step S <b> 40, the control unit 10 advances the process to step S <b> 50 after elapse of a predetermined time set in advance as a time for detecting the connection state of the option device 24.

  In step S50, the image forming apparatus 1 stores the detection result of the connection state of the optional device 24 in the storage unit 40, and starts the light emission of the light emitting diode 21L. The optional device 24 is permitted to be removed and connected only when the power of the image forming apparatus 1 is off. Therefore, if the connection state of the optional device 24 is detected only once when the image forming apparatus 1 is started and stored in the storage unit 40, it is not necessary to detect it again.

  In step S <b> 60, the control unit 10 determines a table to be read based on the detection result of the connection state of the optional device 24. If the optional device 24 is not connected, that is, if the switch SW4 is in the open (Open) state, the process proceeds to step S70, and if the optional device 24 is connected, that is, the switch SW4 is closed. If it is in the (Low) state, the process proceeds to step S80.

  In step S70, the control unit 10 selects and reads the opening table. The opening table is a table used when the optional device 24 is not connected, that is, when the switch SW4 is in the open (Open) state.

  FIG. 8 is a table showing normalized output potentials and changes in output potentials when the optional device 24 of the state detection circuit 30 according to the second embodiment is not attached. The changes in the output potential and the output potential are shown as “Vout / Vcc” and “Vout change / Vcc” by normalizing the output potential Vout and the change in output potential (change in Vout) with the positive power supply potential Vcc, respectively. . In the table of FIG. 8, when the optional device 24 is attached, that is, when the switch SW4 is in the closed (Low) state, the data is deleted, and the change in the normalized output potential (change in Vout / Vcc) Is calculated.

  In step S80, the control unit 10 selects and reads the closing table. The closing table is a table used when the optional device 24 is connected, that is, when the switch SW4 is in the closed (Low) state.

  FIG. 9 is a table showing normalized output potentials and changes in output potentials when the optional device 24 of the state detection circuit 30 according to the second embodiment is mounted. The output potential and the change in the output potential are normalized by the positive power supply potential Vcc as in FIG. In the table of FIG. 9, the data when the optional device 24 is not attached, that is, when the switch SW4 is in the open (Open) state is deleted, and the change in the normalized output potential (change in Vout / Vcc ) Is calculated.

  In step S90, the control unit 10 starts continuous state detection. The targets for continuous state detection are the ADF 21 (switch SW1), the transport unit 22 (switch SW2), and the motor 23 (switch SW3). The connection state of the optional device 24 (switch SW4) is detected within a predetermined time set in advance from the time of starting the image forming apparatus 1, stored in the storage unit 40, and not detected thereafter.

  The control unit 10 uses the table of FIG. 8 or FIG. 9 according to the connection state of the optional device 24, and opens / closes the three switches SW1, SW2, SW3 based on the output potential Vout of the state detection circuit 30. Can be detected. As a result, whether or not a print document is placed on the ADF 21, whether or not printing paper remains on the paper feed tray of the transport unit 22 (light emission of the light emitting diode 21 </ b> L starts in step S <b> 50), and the motor 23 It can be continuously detected whether or not it is in a steady rotation state.

  As described above, in the second embodiment, the connection state (switch SW4) of the option device 24 is determined using the open state of the two switches SW1 and SW3 that are known when the image forming apparatus 1 is started. Can be detected. In the second embodiment, when the three switches SW1, SW2, and SW3 are in the closed (Low) state, the change in the output potential of the state 14 and the state 15 is small in the detection of the connection state (switch SW4) of the option device 24. The feature is that the connection state of the optional device 24 is detected at a known timing at which this state does not occur.

  In the second embodiment, the table of FIG. 8 or FIG. 9 is selected according to the connection state of the option device 24. However, for example, the table of FIG. 10 is used regardless of the connection state of the option device 24. You may do it. The table of FIG. 10 is configured as a combination of the table of FIG. 8 (option device 24 is not connected) and the table of FIG. 9 (option device 24 is connected) corrected.

  In this correction, the amount of change in the output potential between the state 14 and the state 15 (0.0172, see FIG. 7) is changed to the states 1, 3, 5, 7, 9, and 9 in the table of FIG. The content is added to 11, 13, 15 (switch SW4 is closed). Thereby, the state of the three switches SW1, SW2, and SW3 can be detected regardless of the connection state of the option device 24.

  In the above embodiment, it is assumed that the two switches SW1 and SW3 are in an open state at a known timing (within a predetermined time set in advance from the time of activation). The effect of the present invention can be obtained as long as at least one switch of a resistor other than the specific resistor having the largest resistance value among the plurality of resistors is open.

Specifically, the switch that is known to be in the open state most preferably includes the switch SW1, and then preferably includes the switch SW2 and then the switch SW3. The ease of detection of the switch SW4 is as follows in detail.
(1) When it is known that SW1 + SW2 + SW3 is open (2) When it is known that SW1 + SW2 is open (3) When it is known that SW1 + SW3 is open (embodiment)
(4) When only SW1 is known to be open (5) When SW2 + SW3 is known to be open (6) When only SW2 is known to be open (7) Only SW3 is known to be open Time

C. Variations:
The present invention can be implemented not only in the above embodiments but also in the following modifications.

  Modification 1: In the above-described embodiment, in the image forming apparatus, the placed state of the printed document of the automatic document feeder (ADF), the remaining state of the printing paper in the paper feed tray of the transport unit, and the operating state of the motor Although it is applied to the detection of the connection state of the optional device, it can also be applied to detection of other binary states such as the open / close state of the document table cover.

  Modification 2: In the above embodiment, the resistance values of the first resistor 31, the second resistor 32, the third resistor 33, and the fourth resistor 34 are ratios of R, 2R, 4R, and 8R, respectively (the ratio of the resistance values is 1). : 2: 4: 8), but is not limited to this ratio, and the resistance values are different from each other (not including the same resistance value) connected in parallel. If it is. Note that the number of resistors may be three or more.

  Modification 3: In the above embodiment, each device has one switch, but may have two or more. It is sufficient that at least one or more devices have N (N is an integer of 3 or more) switches that open and close according to one state.

  Modified example 4: In the above embodiment, the second example is configured in combination with the first example, but the first example and the second example can be configured individually.

  Modification 5: The present invention is applied to an image forming apparatus, but is not limited to an image forming apparatus, and can be applied to other types of devices.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 10 Control part 21 ADF
21L Light-emitting diode 22L Light-emitting diode 22 Transport unit 23 Motor 24 Optional device 30 State detection circuit 31 First resistor 32 Second resistor 33 Third resistor 34 Fourth resistor 35 Voltage dividing resistor 40 Storage unit

Claims (7)

A state detection circuit that detects the open / closed state of N switches that open and close according to the state of the device,
A parallel circuit having N resistors which are connected in parallel and have different resistance values;
A voltage dividing circuit having a fixed resistance value connected in series to one end of the N resistors;
With
The other ends of the N resistors are configured to be connected in series to the N switches, respectively.
The fixed resistance value is closer to the combined resistance value of the parallel circuit in which all of the N resistors are closed than the resistance value of the resistor having the smallest resistance value among the N resistors. . The state detection circuit according to claim 1,
The state detection circuit in which N is an integer of 3 or more. The state detection circuit according to claim 1,
N is 4;
The four resistors have a resistance ratio of 1: 2: 4: 8,
The state detection circuit in which the fixed resistance value is 50% to 75% of a resistance value of a resistor having a ratio of the resistance value of 1. The state detection circuit according to claim 1,
N is 4;
The four resistors have a resistance ratio of 1: 2: 4: 8,
The state detection circuit in which the fixed resistance value is 53% to 57% of the resistance value of the resistor whose resistance value is 1. The state detection circuit according to claim 1,
N is 3;
The three resistors have a resistance ratio of 1: 2: 4,
The state detection circuit in which the fixed resistance value is 50% to 75% of a resistance value of a resistor whose resistance value is 1. The state detection circuit according to claim 1,
N is 3;
The three resistors have a resistance ratio of 1: 2: 4,
The state detection circuit in which the fixed resistance value is 57% to 67% of a resistance value of a resistor whose resistance value is 1. An image forming apparatus,
The state detection circuit according to any one of claims 1 to 6,
An image forming unit having a plurality of states whose states are detected by the state detection circuit;
An image forming apparatus comprising: