JP2018018954A - Led package nd manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LED package capable of ensuring compaction and reliability of a package, and to provide a manufacturing method thereof.SOLUTION: An LED package includes a board 1 mainly composed of an intrinsic semiconductor material of single crystal having a principal surface 11 and a mounting surface 12 facing oppositely to each other in a thickness direction Z, and a recess 14 formed in the principal surface 11, an internal terminal 21 arranged in the recess 14, an external terminal 22 arranged on the mounting surface 12 of the surface 11, and an LED chip 31 accommodated in the recess 14 and conducting to the internal terminal 21. The board 1 has a doping layer 15 formed between the principal surface 11 and mounting surface 12, and conducting the internal terminal 21 and external terminal 22 with each other.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an LED package having a single crystal intrinsic semiconductor material as a main component and an LED chip mounted on a finely processed substrate and a method for manufacturing the same.

  In recent years, by applying LSI manufacturing technology, so-called micro electro mechanical systems (MEMS) in which various semiconductor elements are mounted on a finely processed silicon substrate are becoming widespread. In manufacturing the micromachine, anisotropic etching is used as a microfabrication technique for a silicon substrate. By anisotropic etching, a fine recess can be accurately formed in the silicon substrate, and various semiconductor elements are mounted on the silicon substrate so as to be accommodated in the recess.

  For example, Patent Document 1 discloses an LED package based on such a micromachine manufacturing technique. In the LED package, a horn (recess) is formed on a silicon substrate by anisotropic etching, and an LED chip is mounted on the bottom surface of the recess. Since the horn is formed so as to be recessed from the (100) plane of the silicon substrate, it has an inclined surface that is a (111) plane. In addition, an electrode for mounting the LED package is formed by the following two methods.

  The first method is a method in which a contact hole penetrating in the thickness direction is formed in the silicon substrate at the outer peripheral portion of the concave portion in plan view, and an electrode is formed in the contact hole by sputtering. Since the contact hole is formed by anisotropic etching in the same manner as the horn, it is constituted by an inclined surface that is a (111) plane. For this reason, since the opening area of a contact hole becomes larger than the cross-sectional area required for conduction | electrical_connection with a circuit board and an LED chip, there exists a problem that formation of a contact hole causes the enlargement of a LED package.

  The second method is a method in which a contact edge having an inclined side portion of a silicon substrate is formed, and an electrode is formed on the surface of the contact edge by a sputtering method. Since the contact edge is formed by anisotropic etching in the same manner as the horn, the surface of the contact edge is an inclined surface (111 plane). In this case, when the LED package is mounted, no electrode is formed on the back surface of the silicon substrate facing the circuit board, so that the circuit board is electrically connected to the electrode formed on the surface of the contact edge via the solder. For this reason, the solder adhesion area with respect to the electrode tends to be smaller than before, and conduction may be hindered when cracks occur in the solder due to factors such as temperature stress, which reduces the reliability of the LED package. There's a problem.

Japanese Patent No. 4572121

  In view of the above circumstances, it is an object of the present invention to provide an LED package and a method for manufacturing the same that can reduce the size of the package and ensure reliability.

  The LED package provided by the first aspect of the present invention has a main surface and a mounting surface that face each other in the thickness direction, and a single crystal intrinsic semiconductor having a recess recessed from the main surface A substrate mainly composed of a material; an internal terminal disposed in the recess; an external terminal disposed on the mounting surface of the substrate; an LED chip housed in the recess and electrically connected to the internal terminal; The substrate includes a doping layer formed between the main surface and the mounting surface and electrically conducting the internal terminal and the external terminal.

  In the practice of the present invention, the doping layer preferably contains an ionized group V element.

  In the practice of the present invention, the group V element is preferably P.

  In the embodiment of the present invention, preferably, the substrate is formed with an insulating wall that divides the doping layer in a thickness direction of the substrate and is an electrical insulator, and the doping layer is electrically connected to each other by the insulating wall. It has the 1st doping part which is an insulated anode, and the 2nd doping part which is a cathode.

  In the embodiment of the present invention, preferably, the insulating wall surrounds each of the first doping portion and the second doping portion in a plan view.

  In an embodiment of the present invention, preferably, the recess has a bottom surface on which the internal terminal is disposed, and a communication surface that connects the bottom surface and the main surface of the substrate, and the bottom surface is a thickness of the substrate. It is orthogonal to the vertical direction, and the connecting surface is inclined with respect to the bottom surface.

  Preferably, in the implementation of the present invention, the shape of the bottom surface in plan view is a rectangular shape, and the plurality of connecting surfaces are formed along the four sides of the bottom surface.

  In the implementation of the present invention, it is preferable that the inclination angles of the plurality of connecting surfaces with respect to the bottom surface are the same.

  In the practice of the present invention, preferably, the intrinsic semiconductor material is Si.

  In the practice of the present invention, preferably, the main surface of the substrate is a (100) plane.

In the practice of the present invention, preferably, the insulating wall contains SiO ₂ as a main component.

  In the embodiment of the present invention, preferably, the first doping portion and the second doping portion are located between the bottom surface of the recess and the mounting surface.

  In the implementation of the present invention, preferably, a part of the insulating wall protrudes from the bottom surface of the recess.

  In the embodiment of the present invention, preferably, a reflection film that covers the communication surface of the concave portion and reflects light emitted from the LED chip is formed.

  In the practice of the present invention, preferably, the reflective film includes an Au layer.

  In the embodiment of the present invention, preferably, the reflective film has the same configuration as the internal terminal.

  Preferably, the present invention preferably includes a first insulating film formed to cover the mounting surface of the substrate, and the first insulating film is formed with a communication hole for exposing the doping layer. A part of the external terminal is inserted through the hole.

  In the embodiment of the present invention, preferably, the composition of the first insulating film is the same as the composition of the insulating wall.

  Preferably, the present invention includes a second insulating film that covers a part of the external terminal and the first insulating film.

  In the practice of the present invention, the second insulating film is preferably made of photosensitive polyimide.

  Preferably, the present invention includes an electrode pad that covers the external terminal exposed from the second insulating film.

  Preferably, in the practice of the present invention, the electrode pad is composed of a Ni layer, a Pd layer, and an Au layer stacked on each other.

  Preferably, the present invention includes a bonding layer interposed between the internal terminal and the LED chip.

  In the practice of the present invention, the bonding layer is preferably composed of an Ni layer and an alloy layer containing Sn stacked on each other.

  Preferably, in the embodiment of the present invention, the substrate is formed with a groove that is recessed from the bottom surface of the recess and surrounds the periphery of the internal terminal.

  In the implementation of the present invention, it is preferable to include a sealing resin that covers the LED chip and is filled in the recess.

  In the practice of the present invention, preferably, the sealing resin is made of a synthetic resin containing a phosphor and having translucency.

  According to a second aspect of the present invention, there is provided a method for manufacturing an LED package, comprising: ionizing a substrate having a front surface and a back surface facing away from each other in a thickness direction and made of a single crystal intrinsic semiconductor material; Forming a doped layer containing the group V element by ion implantation; forming an external conductive layer electrically connected to the doping layer so that a part thereof is in contact with the back surface of the substrate; A step of forming a recess recessed from the surface of the material in the substrate, a step of forming an internal conductive layer conducting to the doping layer in the recess, and an LED chip to be accommodated in the recess. And a step of mounting on the internal conductive layer.

  In the practice of the present invention, the group V element is preferably P.

  Preferably, in the practice of the present invention, the doping layer is divided in the thickness direction of the base material between the step of forming the doping layer and the step of forming the external conductive layer, and an electric insulator is used. A step of forming an insulating wall on the substrate;

  Preferably, in the implementation of the present invention, the step of forming the insulating wall includes a step of forming a groove portion recessed from the back surface of the base material by deep RIE.

  In the embodiment of the present invention, preferably, in the step of forming the insulating wall, a first insulating film in contact with the back surface of the base material is formed together with the insulating wall by a thermal oxidation method.

  Preferably, in the embodiment of the present invention, the step of forming the external conductive layer includes a step of forming a communication hole for exposing the doping layer from the first insulating film.

  Preferably, in the embodiment of the present invention, a second insulating film that covers a part of the external conductive layer and the first insulating film is formed between the step of forming the external conductive layer and the step of forming the recess. A step of forming by lithography.

  In the practice of the present invention, preferably, in the step of forming the recess, the recess is formed by anisotropic etching.

  In the practice of the present invention, preferably, the intrinsic semiconductor material is Si, and the surface of the substrate is a (100) plane.

  In the embodiment of the present invention, preferably, in the step of forming the internal conductive layer, a reflection film that reflects light is formed in the concave portion together with the internal conductive layer by sputtering and electrolytic plating.

  Preferably, in the embodiment of the present invention, the step of forming the internal conductive layer includes a step of forming a bonding layer for mounting the LED chip on the internal conductive layer by electrolytic plating.

  Preferably, the present invention includes a step of covering the external conductive layer and forming a pad layer as a conductor by electroless plating.

  In the implementation of the present invention, preferably, after the step of mounting the LED chip, a step of forming a sealing resin covering the LED chip and filling the concave portion is provided.

  According to the LED package of the present invention, the substrate has a doping layer that allows the internal terminals disposed in the recesses and the external terminals disposed on the mounting surface of the substrate to be electrically connected to each other. By adopting such a configuration, it is possible to ensure conduction between the internal terminal and the external terminal without forming a contact hole or a contact edge. Further, the area of the solder attached to the external terminal can be made comparable to the conventional one. Therefore, it is possible to reduce the size of the package and ensure reliability.

  According to the method for manufacturing an LED package of the present invention, the doping layer is formed by containing an ionized group V element in a base material made of a single crystal intrinsic semiconductor material by ion implantation. Since ion implantation is a common method in the manufacture of semiconductor devices, it is not necessary to provide special equipment for manufacturing the LED package according to the present invention.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a top view of the LED package concerning 1st Embodiment of this invention. FIG. 2 is a plan view of the LED package shown in FIG. 1 (LED chip and sealing resin are omitted). It is a bottom view of the LED package shown in FIG. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is a bottom view explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is a bottom view explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing which follows the XX line of FIG. It is a bottom view explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is a top view explaining the manufacturing process of the LED package shown in FIG. It is a top view explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing which follows the XVII-XVII line of FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is sectional drawing explaining the manufacturing process of the LED package shown in FIG. It is a top view explaining the manufacturing process of the LED package shown in FIG. It is a top view (a LED chip and sealing resin are abbreviate | omitted) of the LED package concerning 2nd Embodiment of this invention. It is sectional drawing which follows the XXVIII-XXVIII line of FIG. It is sectional drawing which follows the XXIX-XXIX line | wire of FIG.

  A mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described with reference to the accompanying drawings.

[First Embodiment]
Based on FIGS. 1-5, LED package A10 concerning 1st Embodiment of this invention is demonstrated. The LED package A10 includes a substrate 1, an internal terminal 21, an external terminal 22, a first insulating film 23, a second insulating film 24, an electrode pad 25, a reflective film 29, an LED chip 31, a bonding layer 32, and a sealing resin 4. .

  FIG. 1 is a plan view of the LED package A10. FIG. 2 is a plan view of the LED package A10, and the LED chip 31 and the sealing resin 4 are omitted for convenience of understanding. FIG. 3 is a bottom view of the LED package A10. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4 and 5 show the LED chip 31 and the sealing resin 4 without being omitted.

  The LED package A10 shown in these drawings is of a type that is surface-mounted on a circuit board such as a portable electronic terminal. Here, for convenience of explanation, the left and right directions of the plan view perpendicular to the thickness direction Z of the substrate 1 are perpendicular to the first direction X, and the thickness direction Z and the first direction X of the substrate 1 are both perpendicular. Are defined as a second direction Y, respectively. As shown in FIG. 1, in the present embodiment, the shape of the substrate 1 of the LED package A10 in a plan view (hereinafter simply referred to as “plan view”) in the thickness direction Z is a rectangular shape. At this time, the first direction X is the long side direction of the LED package A10.

  As shown in FIGS. 1 to 5, the substrate 1 is a member for housing the LED chip 31 and mounting the LED package A <b> 10 on the circuit substrate. The substrate 1 has a single crystal intrinsic semiconductor material as a main component, and in the present embodiment, Si has a main component. The shape of the substrate 1 in plan view is a rectangular shape. The substrate 1 has a main surface 11, a mounting surface 12, a first side surface 131, a second side surface 132, a recess 14, a doping layer 15, and an insulating wall 16.

  As shown in FIGS. 1 to 5, the main surface 11 and the mounting surface 12 are surfaces facing opposite sides in the thickness direction Z of the substrate 1. Both the main surface 11 and the mounting surface 12 are flat surfaces orthogonal to the thickness direction Z of the substrate 1. The main surface 11 is a surface facing upward in FIGS. 4 and 5. The substrate 1 according to the present embodiment has a recess 14 that is recessed from the main surface 11. By forming the recess 14 in the substrate 1, the shape of the main surface 11 is a frame shape surrounding the periphery of the recess 14. The main surface 11 according to the present embodiment is a (100) surface. The mounting surface 12 is a surface facing downward in FIGS. 4 and 5. The mounting surface 12 is a surface used when mounting the LED package A10. The mounting surface 12 has a rectangular shape. In the present embodiment, the external terminal 22, the first insulating film 23, the second insulating film 24, and the electrode pad 25 are disposed on the mounting surface 12.

  As shown in FIGS. 1 to 4, the first side surface 131 is a pair of surfaces that are sandwiched between the main surface 11 and the mounting surface 12 and are spaced apart in the first direction X. In addition, as shown in FIGS. 1 to 3 and FIG. 5, the second side surface 132 is sandwiched between the main surface 11 and the mounting surface 12 and is a pair of surfaces that are arranged apart from each other in the second direction Y. It is. Each of the pair of first side surfaces 131 and the pair of second side surfaces 132 has a rectangular shape and is a flat surface, and is orthogonal to the main surface 11 and the mounting surface 12.

  As shown in FIGS. 1, 2, 4, and 5, the concave portion 14 is a portion that is formed to be recessed from the main surface 11 and has a rectangular shape in plan view. In the present embodiment, the internal terminal 21 is disposed in the recess 14 and the LED chip 31 is accommodated in the recess 14. The recess 14 has a bottom surface 141 and a communication surface 142.

  As shown in FIGS. 2, 4, and 5, the bottom surface 141 is located between the main surface 11 and the mounting surface 12 in the thickness direction Z of the substrate 1, and with respect to the thickness direction Z of the substrate 1. It is an orthogonal flat surface. The shape of the bottom surface 141 in plan view is a rectangular shape. In the present embodiment, the internal terminal 21 is disposed on the bottom surface 141.

  As shown in FIGS. 2, 4, and 5, the communication surface 142 is a flat surface that connects the bottom surface 141 and the main surface 11 of the substrate 1. The communication surface 142 is inclined with respect to the bottom surface 141. The contact surface 142 according to the present embodiment includes four or more surfaces, and the plurality of contact surfaces 142 are formed along the four sides of the bottom surface 141. Here, in this embodiment, since the main surface 11 of the substrate 1 is the (100) surface, the plurality of connecting surfaces 142 are all (111) surfaces. For this reason, the inclination angles of the plurality of communication surfaces 142 with respect to the bottom surface 141 are all the same. The magnitude of the tilt angle is 54.74 °.

  As shown in FIGS. 4 and 5, the doping layer 15 is a portion that is formed between the main surface 11 of the substrate 1 and the mounting surface 12 and that electrically connects the internal terminal 21 and the external terminal 22 to each other. The doping layer 15 contains an ionized group V element. For this reason, since the doping layer 15 contains the free electrons resulting from the ionized group V element, the doping layer 15 exhibits properties close to those of a conductor. The group V element according to this embodiment is P. The doping layer 15 is uniformly formed between the main surface 11 of the substrate 1 and the mounting surface 12.

As shown in FIGS. 4 and 5, the insulating wall 16 is a part that divides the doping layer 15 in the thickness direction Z of the substrate 1. Insulating wall 16 according to this embodiment is an electrical insulator composed mainly of SiO _2. Therefore, the doping layer 15 includes a first doping part 151 and a second doping part 152 that are electrically insulated from each other by the insulating wall 16. In the present embodiment, the first doping unit 151 is an anode (anode), and the second doping unit 152 is a cathode (cathode). As shown in FIG. 2, the insulating wall 16 surrounds the first doping portion 151 and the second doping portion 152 in a plan view. As shown in FIGS. 2, 4, and 5, the insulating wall 16 is formed in a region occupied by the bottom surface 141 of the recess 14 in a plan view, and a part of the insulating wall 16 protrudes from the bottom surface 141. . For this reason, in the present embodiment, the first doping portion 151 and the second doping portion 152 are located between the bottom surface 141 of the recess 14 and the mounting surface 12 of the substrate 1.

  As shown in FIGS. 2, 4 and 5, the internal terminal 21 is disposed on the bottom surface 141 of the recess 14 and has the LED chip 31 mounted thereon, and a circuit board on which the LED chip 31 and the LED package A10 are mounted. Is a conductor constituting the conductive path. The internal terminal 21 according to the present embodiment is composed of a Cu layer, a Ni layer, and an Au layer stacked on each other. The internal terminal 21 includes a first internal terminal 211 and a second internal terminal 212. Both the first internal terminal 211 and the second internal terminal 212 according to the present embodiment have a rectangular shape in plan view and the same size. The first internal terminal 211 is an anode (anode) and is electrically connected to the first doping unit 151. The second internal terminal 212 is a cathode (cathode) and is electrically connected to the second doping unit 152. In the present embodiment, the first internal terminal 211 and the second internal terminal 212 are separated from each other in the first direction X.

  As shown in FIGS. 3 to 5, the external terminal 22 is a conductor that is disposed on the mounting surface 12 of the substrate 1 and constitutes a conductive path between the LED chip 31 and the circuit board on which the LED package A <b> 10 is mounted. . The external terminal 22 according to the present embodiment is made of Al. The external terminal 22 includes a first external terminal 221 and a second external terminal 222. Both the first external terminal 221 and the second external terminal 222 according to the present embodiment have a rectangular shape in plan view and the same size. The first external terminal 221 is an anode (anode) and is electrically connected to the first doping unit 151. The second external terminal 222 is a cathode (cathode) and is electrically connected to the second doping unit 152. In the present embodiment, the first external terminal 221 and the second external terminal 222 are separated from each other in the first direction X. Both the first external terminal 221 and the second external terminal 222 are in contact with the first insulating film 23. The first external terminal 221 is electrically connected to the first doping portion 151 through one communication hole 231 of the first insulating film 23 described later. Similarly, the second external terminal 222 is electrically connected to the second doping part 152 through the other communication hole 231 of the first insulating film 23.

As shown in FIGS. 3 to 5, the first insulating film 23 is a portion that is disposed on the mounting surface 12 of the substrate 1 and covers the mounting surface 12. The composition of the first insulating film 23 is the same as the composition of the insulating wall 16. For this reason, the first insulating film 23 according to the present embodiment is an electrical insulator mainly composed of SiO ₂ . One end of the insulating wall 16 is connected to the first insulating film 23 in the thickness direction Z of the substrate 1. The first insulating film 23 has a communication hole 231 that exposes the mounting surface 12 of the substrate 1 and the doping layer 15. The communication holes 231 according to the present embodiment are a pair of holes having a rectangular shape in plan view and are separated from each other in the first direction X. A part of the external terminal 22 is inserted into each communication hole 231.

  As shown in FIGS. 3 to 5, the second insulating film 24 is a part that is disposed on the mounting surface 12 of the substrate 1 and covers a part of the external terminal 22 and the first insulating film 23. The second insulating film 24 according to this embodiment is an electrical insulator made of photosensitive polyimide. A portion of the external terminal 22 that is not covered with the second insulating film 24 is covered with the electrode pad 25. Therefore, as shown in FIG. 3, when the LED package A10 is viewed from the mounting surface 12 of the substrate 1, only the second insulating film 24 and the electrode pad 25 are visible.

  As shown in FIGS. 3 to 5, the electrode pad 25 is a conductor that is disposed on the mounting surface 12 of the substrate 1 and covers the external terminal 22 exposed from the second insulating film 24. The electrode pad 25 is electrically connected to the external terminal 22, and together with the internal terminal 21 and the external terminal 22, constitutes a conductive path between the LED chip 31 and the circuit board on which the LED package A10 is mounted. The electrode pad 25 is a portion to which cream solder or the like adheres when the LED package A10 is mounted on a circuit board. The electrode pad 25 according to the present embodiment is composed of a Ni layer, a Pd layer, and an Au layer that are stacked on each other. The electrode pad 25 includes a first electrode pad 251 and a second electrode pad 252. Both the first electrode pad 251 and the second electrode pad 252 according to the present embodiment have a rectangular shape in plan view and the same size. The first electrode pad 251 is an anode (anode) and is electrically connected to the first external terminal 221. The second electrode pad 252 is a cathode (cathode) and is electrically connected to the second external terminal 222. In the present embodiment, the first electrode pad 251 and the second electrode pad 252 are separated from each other in the first direction X.

  As shown in FIGS. 2, 4, and 5, the reflection film 29 is formed so as to cover the connection surface 142 of the recess 14 and reflects the light emitted from the LED chip 31. In the present embodiment, the reflective film 29 is formed so as to cover the main surface 11 of the substrate 1. The reflective film 29 has the same configuration as the internal terminal 21. For this reason, the reflective film 29 according to the present embodiment is composed of a Cu layer, a Ni layer, and an Au layer that are laminated together. Therefore, the reflective film 29 includes an Au layer. However, the reflective film 29 and the internal terminal 21 are electrically insulated from each other. For this reason, the reflective film 29 does not constitute a conductive path between the LED chip 31 and the circuit board on which the LED package A10 is mounted.

  The LED chip 31 is a light emitting unit that serves as a light source of the LED package A10, and is a semiconductor element in which a plurality of semiconductor layers are stacked together by, for example, a pn junction. When a current flows through the LED package A10, the LED chip 31 emits light. The LED chip 31 emits blue light, red light, green light, or the like depending on the material constituting the semiconductor layer. The LED chip 31 according to the present embodiment is a so-called flip chip type element. A light emitting unit (not shown) is formed at the upper end of the LED chip 31 shown in FIGS. 4 and 5, and the LED chip 31 emits light from the light emitting unit. In addition, an electrode bump 311 is formed at the lower end of the LED chip 31 shown in FIGS. The electrode bump 311 according to this embodiment is made of, for example, Al. The electrode bump 311 includes a first electrode bump 311a and a second electrode bump 311b. The first electrode bump 311 a is a p-side electrode (anode) of the LED chip 31 and is electrically connected to the first internal terminal 211 via the bonding layer 32. The second electrode bump 311 b is an n-side electrode (cathode) of the LED chip 31 and is electrically connected to the second internal terminal 212 through the bonding layer 32.

  As shown in FIGS. 2, 4, and 5, the bonding layer 32 is a conductor interposed between the internal terminal 21 and the electrode bump 311 of the LED chip 31. By the bonding layer 32, the LED chip 31 is fixedly mounted on the internal terminal 21, and conduction between the internal terminal 21 and the LED chip 31 is ensured. The bonding layer 32 according to the present embodiment is composed of an Ni layer and an alloy layer containing Sn stacked on each other. The alloy layer is a lead-free solder such as a Sn—Sb alloy or a Sn—Ag alloy.

  The sealing resin 4 is a member that covers the LED chip 31 and is filled in the recess 14 as shown in FIGS. 1, 4, and 5. The sealing resin 4 covers the internal terminal 21 and the reflective film 29 in addition to the LED chip 31. The sealing resin 4 according to the present embodiment is made of a synthetic resin containing a phosphor and having translucency. The synthetic resin is, for example, an epoxy resin. For example, when the LED chip 31 emits blue light, white light is emitted from the LED package A10 by using the sealing resin 4 containing a yellow phosphor. In addition, when the LED chip 31 emits purple near-ultraviolet light, the white color in which the color rendering property is further secured from the LED package A10 by using the sealing resin 4 containing phosphors of three colors of red, blue and green. Light is emitted.

  Next, based on FIGS. 6-26, an example of the manufacturing method of LED package A10 is demonstrated.

  6, FIG. 8, FIGS. 12 to 14 and FIGS. 18 to 25 are cross-sectional views illustrating the manufacturing process of the LED package A10, and the cross-sectional positions thereof are the same as those in FIG. 7, 9 and 11 are bottom views for explaining the manufacturing process of the LED package A10. 10 is a cross-sectional view taken along line XX of FIG. 15, 16 and 26 are plan views for explaining the manufacturing process of the LED package A10. 17 is a cross-sectional view taken along line XVII-XVII in FIG. The definition of the thickness direction Z, the first direction X, and the second direction Y of the base material 81 shown in FIGS. 6 to 26 is defined as the thickness direction Z of the substrate 1 shown in FIGS. This corresponds to the definition of the direction X and the second direction Y.

  First, as shown in FIG. 6, a doping layer 815 is formed on the substrate 81. The base material 81 is an assembly of the substrates 1 of the LED package A10, and a substrate region 89 surrounded by an imaginary line (two-dot chain line) shown in FIG. The substrate 81 has a front surface 811 and a back surface 812 that face opposite sides in the thickness direction Z, and is made of a single crystal intrinsic semiconductor material. The intrinsic semiconductor material according to the present embodiment is Si. Both the front surface 811 and the back surface 812 are flat surfaces, and the front surface 811 is a (100) surface. For this reason, the base material 81 is a silicon wafer, for example. Further, the doping layer 815 is a portion containing a group V element ionized in the base material 81. The doping layer 815 corresponds to the doping layer 15 of the LED package A10. The group V element according to this embodiment is P. The doping layer 815 is formed by ion implantation, which is one of general methods for manufacturing semiconductor devices. At this time, the doping layer 815 is uniformly formed over the entire surface between the front surface 811 and the back surface 812 of the base material 81. Since the doping layer 815 contains free electrons attributed to the ionized group V element, the doping layer 815 exhibits properties close to those of a conductor.

  Next, as shown in FIGS. 7 to 10, an insulating wall 816 that divides the doping layer 815 in the thickness direction Z of the base material 81 is formed on the base material 81. The insulating wall 816 corresponds to the insulating wall 16 of the LED package A10. The insulating wall 816 is formed by the following process.

First, as shown in FIG. 7, a first mask layer 851 is formed on the back surface 812 of the substrate 81. The first mask layer 851 according to this embodiment is a layer mainly composed of, for example, Si ₃ N ₄ and is formed by plasma CVD. The back surface 812 of the base material 81 is in a state where the entire surface is covered with the first mask layer 851. Then, after forming a mask on the first mask layer 851 by photolithography, the first mask layer 851 is partially removed by reactive ion etching (RIE), which is a typical example of dry etching. Here, if the first mask layer is a layer mainly composed of Si ₃ N ₄ , for example, CF ₄ is used as an etching gas. As a result, the first mask layer 851 is formed with an opening 851a having a frame shape in plan view and continuing in the first direction X. In the present embodiment, the two openings 851a are continuous in the first direction X. From the opening 851a, the back surface 812 of the base material 81 and the doping layer 815 are exposed.

Next, as shown in FIG. 8, in the base material 81 exposed from the opening 851 a of the first mask layer 851, a groove 816 a recessed from the back surface 812 of the base material 81 is formed. The groove 816a is formed by deep RIE (Reactive Ion Etching). An example of the Fukahori RIE is the Bosch process. The groove 816 a is formed along the thickness direction Z of the substrate 81. After forming the groove 816a, the first mask layer 851 is completely removed. If the first mask layer 851 is a layer mainly composed of Si ₃ N ₄ , for example, reactive ion etching using CF ₄ as an etching gas or wet etching using a heated phosphoric acid solution is used as the first mask layer 851. Removed.

Next, as shown in FIGS. 9 and 10, an insulating wall 816 that fills the groove 816 a formed in the substrate 81 is formed. The insulating wall 816 is formed by a thermal oxidation method. Therefore, the insulating wall 816 is an electrical insulator mainly composed of SiO ₂ . At this time, a first insulating film 823 that is in contact with the back surface 812 of the base material 81 together with the insulating wall 816 is formed by a thermal oxidation method. For this reason, the composition of the first insulating film 823 is the same as the composition of the insulating wall 816. The first insulating film 823 corresponds to the first insulating film 23 of the LED package A10. The back surface 812 of the base material 81 is in a state where the entire surface is covered with the first insulating film 823. Through the above steps, the insulating wall 816 is formed. In the thickness direction Z of the substrate 81, the doping layers 815 separated by the insulating wall 816 are in a state of being electrically insulated from each other.

  Next, as shown in FIGS. 11 and 12, an external conductive layer 822 that conducts to the doping layer 815 is formed so that a part thereof is in contact with the back surface 812 of the substrate 81. The external conductive layer 822 formed inside the substrate region 89 corresponds to the external terminal 22 of the LED package A10. Here, the step of forming the external conductive layer 822 includes the step of forming the communication hole 823a exposing the back surface 812 of the base material 81 and the doping layer 815 from the first insulating film 823. The external conductive layer 822 is formed by the following process.

First, as shown in FIG. 11, a communication hole 823 a is formed in the first insulating film 823. The communication hole 823a corresponds to the communication hole 231 of the LED package A10. In the present embodiment, the communication holes 823a are a pair, and each communication hole 823a is formed so as to be surrounded by the insulating wall 816 in plan view. The communication hole 823a is formed by reactive ion etching using CF ₄ as an etching gas after a mask is formed on the first insulating film 823 by photolithography. From each connection hole 823a, the back surface 812 of the base material 81 and the doping layer 815 are exposed.

  Next, as illustrated in FIG. 12, an external conductive layer 822 that partially contacts the back surface 812 of the substrate 81 is formed. The external conductive layer 822 according to this embodiment is made of Al. The external conductive layer 822 is formed by a sputtering method after a mask is formed on the first insulating film 823 by photolithography. At this time, the external conductive layer 822 is formed so as to cover a part of the first insulating film 823 and fill the pair of communication holes 823 a, and is in contact with the back surface 812 of the base material 81 and the doping layer 815. Through the above steps, the external conductive layer 822 is formed.

  Next, as shown in FIG. 13, a second insulating film 824 that covers a part of the external conductive layer 822 and the first insulating film 823 is formed. The second insulating film 824 corresponds to the second insulating film 24 of the LED package A10. The second insulating film 824 according to the present embodiment is made of photosensitive polyimide. The second insulating film 824 is formed by photolithography. Specifically, a photosensitive polyimide is applied by a spin coater (rotary coating apparatus) so as to cover the entire outer conductive layer 822 and the first insulating film 823, and then formed by photolithography exposure and development. A pair of openings 824a are formed in the second insulating film 824 by exposure / development so as to correspond to the pair of communication holes 823a. The shape of the opening 824a according to this embodiment in a plan view is a rectangular shape (not shown). The external conductive layer 822 is exposed from each opening 824a.

  Next, as shown in FIG. 14, a pad layer 825 that covers the external conductive layer 822 exposed from the opening 824a of the second insulating film 824 and is a conductor is formed. The pad layer 825 corresponds to the electrode pad 25 of the LED package A10. The pad layer 825 according to the present embodiment is composed of a Ni layer, a Pd layer, and an Au layer that are stacked on each other. The pad layer 825 is formed by depositing an Ni layer, a Pd layer, and an Au layer in this order by electroless plating.

  Next, as shown in FIGS. 15 to 17, a recess 814 that is recessed from the surface 811 of the substrate 81 is formed in the substrate 81. The recess 814 corresponds to the recess 14 of the LED package A10. The recess 814 is formed by the following process.

First, as shown in FIG. 15, a second mask layer 852 is formed on the surface 811 of the substrate 81. Similar to the first mask layer 851, the second mask layer 852 according to the present embodiment is a layer containing, for example, Si ₃ N ₄ as a main component, and is formed by plasma CVD. The surface 811 of the base material 81 is in a state where the entire surface is covered with the second mask layer 852. Then, after forming a mask on the second mask layer 852 by photolithography, the second mask layer 852 is partially removed by reactive ion etching. Here, if the second mask layer is a layer mainly composed of Si ₃ N ₄ , for example, CF ₄ is used as an etching gas. Thereby, an opening 852a having a rectangular shape in plan view is formed in the second mask layer 852. The surface 811 of the base material 81 and the doping layer 815 are exposed from the opening 852a.

Next, as shown in FIGS. 16 and 17, a recess 814 that is recessed from the surface 811 of the base material 81 exposed from the opening 852 a of the second mask layer 852 is formed in the base material 81. The recess 814 has a bottom surface 814 a having a rectangular shape in plan view, and a connecting surface 814 b that connects the bottom surface 814 a and the surface 811 of the base material 81. The doping layer 815 and the insulating wall 816 are exposed from the bottom surface 814a. The communication surface 814b is four inclined surfaces formed along the four sides of the bottom surface 814a. The recess 814 is formed by anisotropic etching using an alkaline solution. The solution is, for example, a KOH (potassium hydroxide) solution or a TMAH (tetramethylammonium hydroxide) solution. In the present embodiment, since the surface 811 of the base material 81 is the (100) plane, all the four connecting surfaces 814b are the (111) plane. After forming the recess 814, the entire second mask layer 852 is removed. If the second mask layer 852 is a layer mainly composed of Si ₃ N ₄ , for example, reactive ion etching using CF ₄ as an etching gas or wet etching using a heated phosphoric acid solution is used as the second mask layer 852. Removed. The recess 814 is formed by the above process.

  Next, as shown in FIGS. 18 to 23, an internal conductive layer 821 that conducts to the doping layer 815 is formed in the recess 814. The internal conductive layer 821 formed inside the substrate region 89 corresponds to the internal terminal 21 of the LED package A10. Here, the step of forming the internal conductive layer 821 includes a step of forming a bonding layer 832 for mounting the LED chip 831 described later on the internal conductive layer 821. The internal conductive layer 821 according to this embodiment includes a base layer 821a and a plating layer 821b that are stacked on each other. The internal conductive layer 821 is formed by the following process.

  First, as shown in FIG. 18, a base layer 821a is formed. The formation range of the foundation layer 821a is the entire surface of the surface 811 of the base material 81, the bottom surface 814a of the recess 814, and the connecting surface 814b. The base layer 821a is formed by a sputtering method. The underlayer 821a according to this embodiment is made of Cu.

  Next, a mask is formed on the base layer 821a by photolithography. As shown in FIG. 19, after the first resist layer 861 is formed on the base material 81 so as to cover the base layer 821a, the first resist layer 861 is exposed and developed, whereby the base layer 821a is exposed. A mask is formed. The first resist layer 861 is formed by applying a photosensitive resist with a spin coater in the same manner as the first insulating film 823 described above. Since the first resist layer 861 according to this embodiment is a positive type, the exposed portion of the first resist layer 861 is removed by the developer, and the underlying layer 821a is exposed from the removed portion.

  Next, as shown in FIG. 20, a plating layer 821b covering the base layer 821a is formed. The plating layer 821b is formed in a portion where the first resist layer 861 is removed by exposure / development and the underlying layer 821a is exposed. The plating layer 821b according to the present embodiment includes a Cu layer, a Ni layer, and an Au layer that are stacked on each other. The plating layer 821b is formed by depositing the Cu layer, the Ni layer, and the Au layer in this order by electrolytic plating. After forming the plating layer 821b, the first resist layer 861 formed on the base material 81 is all removed.

  Next, as illustrated in FIGS. 21 and 22, a bonding layer 832 for mounting an LED chip 831 described later is formed on the internal conductive layer 821. First, a mask is formed on the plating layer 821b by photolithography. As shown in FIG. 21, after the second resist layer 862 is formed on the substrate 81 so as to cover the plating layer 821b, the second resist layer 862 is exposed to light and developed, whereby the plating layer 821b is exposed. A mask is formed. The formation range, material, and formation method of the second resist layer 862 are the same as those of the first resist layer 861. At this time, an opening 862 a is formed in the second resist layer 862. The shape of the opening 862a according to the present embodiment in a plan view is a rectangular shape (not shown).

  Next, as illustrated in FIG. 22, the bonding layer 832 is formed on the internal conductive layer 821. The bonding layer 832 corresponds to the bonding layer 32 of the LED package A10. In the present embodiment, the bonding layer 832 is formed so as to fill the opening 862a of the second resist layer 862 by electrolytic plating utilizing the base layer 821a covering the surface 811 and the recess 814 of the substrate 81. The bonding layer 832 according to the present embodiment is composed of an Ni layer and an alloy layer containing Sn stacked on each other. The alloy layer is a lead-free solder such as a Sn—Sb alloy or a Sn—Ag alloy. After forming the bonding layer 832, the entire second resist layer 862 formed on the base material 81 is removed.

Next, as shown in FIG. 23, all unnecessary base layers 821a not covered with the plating layer 821b are removed from the base material 81. The underlayer 821a is removed by wet etching, for example. In the wet etching, for example, a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) is used. The bottom surface 814a of the recess 814 and the doping layer 815 are exposed from the portion where the underlayer 821a is removed. At this time, in the recess 814, the base layer 821a and the plating layer 821b formed so as to cover the bottom surface 814a and the base layer 821a and the plating layer 821b formed so as to cover the connecting surface 814b are electrically insulated from each other. . In this case, the base layer 821a and the plating layer 821b formed to cover the bottom surface 814a are the internal conductive layers 821. In addition, the base layer 821a and the plating layer 821b formed so as to cover the communication surface 814b are a reflective film 829 that reflects light. The reflective film 829 corresponds to the reflective film 29 of the LED package A10. As described above, in the step of forming the internal conductive layer 821, the reflective film 829 is formed on the connecting surface 814 b of the recess 814 together with the internal conductive layer 821. Through the above steps, the internal conductive layer 821 is formed.

  Next, as shown in FIG. 24, the LED chip 831 is mounted on the internal conductive layer 821 so as to be accommodated in the recess 814. The LED chip 831 corresponds to the LED chip 31 of the LED package A10. The LED chip 831 according to this embodiment is mounted by FCB (Flip Chip Bonding). After flux (not shown) is applied to the electrode bump 831a of the LED chip 831, the LED chip 831 is temporarily attached to the bonding layer 832 using, for example, a flip chip bonder (not shown). At this time, the bonding layer 832 is sandwiched between the internal conductive layer 821 and the LED chip 831. Next, after the bonding layer 832 is melted by reflow, the bonding layer 832 is solidified by cooling. Through the above steps, the LED chip 831 is mounted on the internal conductive layer 821.

  Next, as illustrated in FIG. 25, a sealing resin 84 that covers the LED chip 831 and is filled in the recess 814 is formed. The sealing resin 84 corresponds to the sealing resin 4 of the LED package A10. The sealing resin 84 according to the present embodiment is made of a synthetic resin that contains a phosphor and has translucency. The synthetic resin is, for example, an epoxy resin. The sealing resin 84 is formed by injecting the fluid synthetic resin into the recess 814 and curing the synthetic resin. In the present embodiment, the sealing resin 84 does not cover the plating layer 821b formed on the surface 811 of the substrate 81, but the sealing resin 84 may be formed so as to cover it.

  Next, the base material 81 is cut along the first direction X and the second direction Y to be divided into individual pieces for each substrate region 89. In cutting, the base material 81 is cut along a cutting line CL shown in FIG. 26, for example, by plasma dicing. The individual pieces divided in the process become the LED package A10. The LED package A10 is manufactured through the above steps.

  Next, the effect of LED package A10 and its manufacturing method is demonstrated.

  The LED package A10 includes a substrate 1 having a recess 14 that is recessed from the main surface 11, an internal terminal 21 disposed in the recess 14, an external terminal 22 disposed on the mounting surface 12 of the substrate 1, and an internal terminal 21. The LED chip 31 is provided. Here, the substrate 1 is mainly composed of a single crystal intrinsic semiconductor material. Further, the substrate 1 has a doping layer 15 formed between the main surface 11 and the mounting surface 12 and electrically connecting the internal terminal 21 and the external terminal 22 to each other. By forming the doping layer 15 on the substrate 1, the contact hole or the contact edge disclosed in Patent Document 1 is not formed, but the inner terminal 21 disposed in the recess 14 and the mounting surface 12 of the substrate 1 are disposed. In addition, electrical connection with the external terminal 22 can be ensured. In this case, when the LED package A10 is mounted, the external terminals 22 are arranged on the mounting surface 12 of the substrate 1 facing the circuit board. When this occurs, there is no possibility that conduction will be hindered. Therefore, it is possible to reduce the size of the package and ensure reliability.

  The doping layer 15 contains an ionized group V element. For this reason, since the doping layer 15 contains a free electron, it shows the property approximated to the conductor. Therefore, mutual conduction between the internal terminal 21 and the external terminal 22 through the doping layer 15 is possible.

  In addition, according to the manufacturing method of the LED package A10, the doping layer 815 (doping layer 15) is obtained by ionizing a group V element ionized into the base material 81 (substrate 1) made of a single crystal intrinsic semiconductor material by ion implantation. It is formed by containing. Since ion implantation is a common method in the manufacture of semiconductor devices, it is not necessary to provide special equipment for manufacturing the LED package A10.

  The substrate 1 is formed with an insulating wall 16 that divides the doping layer 15 in the thickness direction Z of the substrate 1. The doping layer 15 includes a first doping portion 151 that is an anode electrically insulated from each other and a first doping portion 151 that is a cathode. 2 doping section 152. Therefore, the doping layer 15 functions normally without short-circuiting as a conductive path between the LED chip 31 and the circuit board on which the LED package A10 is mounted.

  By providing the first insulating film 23 covering the mounting surface 12 of the substrate 1, the effect of electrical insulation between the first doping unit 151 and the second doping unit 152 is improved, and leakage to the outside of the LED package A 10 is prevented. can do. Here, according to the manufacturing method of the LED package A10, the first insulating film 823 (first insulating film 23) is formed at the same time as the insulating wall 816 (insulating wall 16) by the thermal oxidation method. The first insulating film 23 can be formed without any problem.

  The first doping portion 151 and the second doping portion 152 are located between the bottom surface 141 of the recess 14 and the mounting surface 12 of the substrate 1. By adopting such a configuration, since the conductive path between the LED chip 31 and the circuit board on which the LED package A10 is mounted is minimized, the package can be reduced in size while suppressing power loss due to the resistance of the doping layer 15. Can be achieved.

  A reflection film 29 that reflects light emitted from the LED chip 31 is formed on the bottom surface 141 of the recess 14. The reflective film 29 exhibits the function as a secondary light source in order to emit the reflected light to the outside of the LED package A10. For this reason, the reflective film 29 can improve the luminance of the LED package A10. Here, according to the manufacturing method of the LED package A10, the reflective film 829 (reflective film 29) is formed simultaneously with the internal conductive layer 821 (internal terminal 21) by the sputtering method and electrolytic plating. Thus, the reflective film 29 can be formed.

  When the LED package A10 is mounted while protecting the external terminal 22 from the outside by providing the second insulating film 24 that covers a part of the external terminal 22 and the first insulating film 23, the first external terminal 221 and the second external terminal 22 A short circuit of the external terminal 222 can be prevented.

  By providing the bonding layer 32 interposed between the internal terminal 21 and the LED chip 31, the flip chip type LED chip 31 can be mounted on the internal terminal 21. By adopting such a configuration, the opening area of the recess 14 in a plan view can be reduced as compared with the case where the internal terminal 21 and the LED chip 31 are connected by a bonding wire, thereby reducing the size of the package. It becomes possible to plan.

  By providing the sealing resin 4 that covers the LED chip 31 and is filled in the recess 14, the LED chip 31 and the internal terminal 21 can be protected from the outside. Moreover, various materials can be emitted from LED package A10 by making the material of the sealing resin 4 into the synthetic resin which contains fluorescent substance and has translucency.

[Second Embodiment]
Based on FIGS. 27-29, LED package A20 concerning 2nd Embodiment of this invention is demonstrated. In these drawings, the same or similar elements as those of the LED package A10 described above are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 27 is a plan view of the LED package A20, and for convenience of understanding, the LED chip 31 and the sealing resin 4 are omitted. 28 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG. 28 and 29 show the LED chip 31 and the sealing resin 4 without being omitted.

  The LED package A20 according to the present embodiment is different from the LED package A10 in the configuration of the substrate 1. As shown in FIG. 27, the shape of the LED package A20 according to this embodiment in a plan view is a rectangular shape.

  As shown in FIGS. 27 to 29, the substrate 1 is formed with a groove portion 17 that is recessed from the bottom surface 141 of the recess 14 and surrounds the periphery of the internal terminal 21. The groove portion 17 surrounds each of the first internal terminal 211 and the second internal terminal 212 of the internal terminal 21. The groove portion 17 is formed along the inner periphery of the insulating wall 16 in plan view and is connected to the insulating wall 16.

  Next, the function and effect of the LED package A20 will be described.

  The LED package A20 is similar to the LED package A10 in that the substrate 1 in which the recess 14 that is recessed from the main surface 11 is formed, the internal terminals 21 that are disposed in the recess 14, and the external that is disposed on the mounting surface 12 of the substrate 1. A terminal 22 and an LED chip 31 conducting to the internal terminal 21 are provided. The substrate 1 is mainly composed of a single crystal intrinsic semiconductor material. Further, the substrate 1 has a doping layer 15 formed between the main surface 11 and the mounting surface 12 and electrically connecting the internal terminal 21 and the external terminal 22 to each other. Therefore, it is possible to reduce the size of the package and ensure reliability.

  The substrate 1 is formed with a groove 17 that is recessed from the bottom surface 141 of the recess 14 and surrounds the periphery of the internal terminal 21. For example, in the manufacturing process of the LED package A10 shown in FIG. 24, even when the LED chip 831 is mounted on the internal conductive layer 821, even if the bonding layer 832 melted by reflow protrudes from the internal terminal 21, the bonding layer 832 Flows down into the groove 17. For this reason, the bonding layer 832 can be prevented from adhering to the reflective film 829 across the insulating wall 816. Since the reflective film 29 has the same configuration as that of the internal terminal 21, the groove portion 17 can prevent an unintended conductive path from being formed in the LED package A <b> 20 by the bonding layer 32.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways.

A10, A20: LED package 1: Substrate 11: Main surface 12: Mounting surface 131: First side surface 132: Second side surface 14: Recessed surface 141: Bottom surface 142: Communication surface 15: Doping layer 151: First doping portion 152: First 2 doping part 16: insulating wall 17: groove part 21: internal terminal 211: first internal terminal 212: second internal terminal 22: external terminal 221: first external terminal 222: second external terminal 23: first insulating film 231: Contact hole 24: second insulating film 25: electrode pad 251: first electrode pad 252: second electrode pad 29: reflective film 31: LED chip 311: electrode bump 311a: first electrode bump 311b: second electrode bump 32: Bonding layer 4: Sealing resin 81: Base material 811: Front surface 812: Back surface 814: Recessed portion 814a: Bottom surface 814b: Contact surface 815: Doe 816: Insulating wall 816a: Groove 821: Internal conductive layer 821a: Underlayer 821b: Plating layer 822: External conductive layer 823: First insulating film 823a: Connecting hole 824: Second insulating film 824a: Opening 825: Pad Layer 831: LED chip 831a: Electrode bump 832: Bonding layer 84: Sealing resin 851: First mask layer 851a: Opening 852: Second mask layer 852a: Opening 861: First resist layer 862: Second resist layer 862a: Opening 89: Substrate region Z: Thickness direction X: First direction Y: Second direction CL: Cutting line

Claims (40)

A substrate mainly composed of a single-crystal intrinsic semiconductor material having a main surface and a mounting surface facing each other in the thickness direction and having a recess recessed from the main surface;
An internal terminal disposed in the recess;
An external terminal disposed on the mounting surface of the substrate;
An LED chip that is housed in the recess and is electrically connected to the internal terminal,
The LED package, wherein the substrate has a doping layer formed between the main surface and the mounting surface and electrically conducting the internal terminal and the external terminal.   The LED package according to claim 1, wherein the doping layer contains an ionized group V element.   The LED package according to claim 2, wherein the group V element is P. The substrate is provided with an insulating wall that divides the doping layer in the thickness direction of the substrate and is an electrical insulator,
4. The LED package according to claim 1, wherein the doping layer includes a first doping part that is an anode and a second doping part that is a cathode, which are electrically insulated from each other by the insulating wall. 5.   The LED package according to claim 4, wherein the insulating wall surrounds each of the first doping part and the second doping part in a plan view. The recess has a bottom surface on which the internal terminal is disposed, and a communication surface that connects the bottom surface and the main surface of the substrate,
The LED package according to claim 4, wherein the bottom surface is orthogonal to a thickness direction of the substrate, and the communication surface is inclined with respect to the bottom surface.   The shape of the bottom view in plan view is a rectangular shape, and the LED package according to claim 6, wherein the plurality of connecting surfaces are formed along four sides of the bottom surface.   The LED package according to claim 7, wherein the inclination angles of the plurality of communication surfaces with respect to the bottom surface are all the same.   The LED package according to claim 8, wherein the intrinsic semiconductor material is Si.   The LED package according to claim 9, wherein the main surface of the substrate is a (100) surface. The LED package according to claim 9 or 10, wherein the insulating wall contains SiO ₂ as a main component.   12. The LED package according to claim 6, wherein the first doping portion and the second doping portion are located between the bottom surface of the recess and the mounting surface.   The LED package according to claim 12, wherein a part of the insulating wall protrudes from the bottom surface of the recess.   The LED package according to any one of claims 6 to 13, wherein a reflection film that covers the communication surface of the recess and reflects light emitted from the LED chip is formed.   The LED package according to claim 14, wherein the reflective film includes an Au layer.   The LED package according to claim 14 or 15, wherein the reflective film has the same configuration as the internal terminal. A first insulating film formed to cover the mounting surface of the substrate;
17. The LED package according to claim 6, wherein a communication hole exposing the doping layer is formed in the first insulating film, and a part of the external terminal is inserted through the communication hole.   The LED package according to claim 17, wherein a composition of the first insulating film is the same as a composition of the insulating wall.   The LED package according to claim 17 or 18, further comprising a second insulating film that covers a part of the external terminal and the first insulating film.   The LED package according to claim 19, wherein the second insulating film is made of photosensitive polyimide.   The LED package according to claim 19 or 20, further comprising an electrode pad that covers the external terminal exposed from the second insulating film.   The LED package according to claim 21, wherein the electrode pad is composed of a Ni layer, a Pd layer, and an Au layer stacked on each other.   The LED package according to any one of claims 6 to 22, further comprising a bonding layer interposed between the internal terminal and the LED chip.   The LED package according to claim 23, wherein the bonding layer includes an Ni layer and an alloy layer containing Sn stacked on each other.   25. The LED package according to claim 23 or 24, wherein a groove portion that is recessed from the bottom surface of the recess and surrounds the periphery of the internal terminal is formed in the substrate.   The LED package according to claim 1, further comprising a sealing resin that covers the LED chip and is filled in the recess.   27. The LED package according to claim 26, wherein the sealing resin is made of a synthetic resin containing a phosphor and having translucency. Forming a doped layer containing an ionized group V element by ion implantation on a base material having a front surface and a back surface facing each other in the thickness direction and made of a single crystal intrinsic semiconductor material; ,
Forming an external conductive layer conducting to the doping layer such that a part thereof is in contact with the back surface of the substrate;
Forming a recess recessed from the surface of the substrate on the substrate;
Forming an internal conductive layer in conduction with the doping layer in the recess;
And a step of mounting the LED chip on the internal conductive layer so as to be accommodated in the concave portion.   30. The method of manufacturing an LED package according to claim 28, wherein the group V element is P.   Between the step of forming the doping layer and the step of forming the external conductive layer, the doping layer is divided in the thickness direction of the base material, and an insulating wall that is an electrical insulator is formed on the base material. The manufacturing method of the LED package of Claim 28 or 29 provided with the process formed in.   31. The method for manufacturing an LED package according to claim 30, wherein the step of forming the insulating wall includes a step of forming a groove portion recessed from the back surface of the base material by deep RIE.   32. The method of manufacturing an LED package according to claim 30 or 31, wherein, in the step of forming the insulating wall, a first insulating film in contact with the back surface of the base material is formed together with the insulating wall by a thermal oxidation method.   33. The method of manufacturing an LED package according to claim 32, wherein the step of forming the external conductive layer includes a step of forming a communication hole that exposes the doping layer from the first insulating film.   A step of forming, by photolithography, a second insulating film covering a part of the external conductive layer and the first insulating film between the step of forming the external conductive layer and the step of forming the recess; The manufacturing method of the LED package of Claim 33.   35. The method for manufacturing an LED package according to claim 32, wherein in the step of forming the recess, the recess is formed by anisotropic etching.   36. The method of manufacturing an LED package according to claim 35, wherein the intrinsic semiconductor material is Si, and the surface of the base material is a (100) plane.   37. The LED package according to claim 28, wherein in the step of forming the internal conductive layer, a reflection film that reflects light to the concave portion is formed together with the internal conductive layer by sputtering and electrolytic plating. Production method.   38. The method of manufacturing an LED package according to claim 37, wherein the step of forming the internal conductive layer includes a step of forming a bonding layer for mounting the LED chip on the internal conductive layer by electrolytic plating.   The method for manufacturing an LED package according to any one of claims 28 to 38, comprising a step of covering the external conductive layer and forming a pad layer as a conductor by electroless plating.   40. The method for manufacturing an LED package according to any one of claims 28 to 39, further comprising a step of forming a sealing resin covering the LED chip and filling the concave portion after the step of mounting the LED chip.

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