JP2018013434A - Function reliability confirmation circuit for built-in ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an unnecessary operation stop period for a semiconductor integrated circuit device including a circuit having an arbitrary function.SOLUTION: A reliability confirmation circuit includes a test pattern generation unit, a test result comparison unit, and a failure prediction/inspection unit that predicts a period left before a failure occurs for a test target. The failure prediction/inspection unit includes: a counter circuit that receives an input of determination information for a test result from the test result comparison unit, and controls a count operation; a counter circuit result storage unit that stores a result value of the counter circuit; a comparison circuit that compares the result value stored in the counter circuit result storage unit and a counter expected value stored in a counter expected value storage unit; and a comparison result determination unit that determines a comparison result of the comparison circuit. The comparison result determination unit confirms that the counter value measured by testing is larger than a counter lower-limit expected value or that the counter value measured by testing is smaller than a counter upper-limit expected value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device including a failure prediction BIST (Failure Prediction BIST) in which a failure prediction function is added to a BIST circuit that self-inspects the quality of a circuit having an arbitrary function in an internal circuit.

  Semiconductor integrated circuit devices that require high reliability, such as in-vehicle applications, have a fail-safe function and a fault-tolerance function. These measures are taken to ensure safety after a semiconductor integrated circuit device fails. Do. If safety is ensured after the semiconductor integrated circuit device has failed, an operation stop period such as stopping the control device on which the semiconductor integrated circuit device is mounted is necessary, and the period does not function as a system.

  Therefore, by periodically testing and predicting failure of the semiconductor integrated circuit device and taking measures such as replacing the semiconductor integrated circuit device before the failure of the semiconductor integrated circuit device, the operation of the control device is stopped due to the failure. Eliminate the period.

  The present invention realizes failure prediction by adding a failure prediction inspection function to a BIST circuit that self-inspects the quality of a circuit having an arbitrary function inside a semiconductor integrated circuit device.

  FIG. 2 shows an example of the configuration of a BIST circuit that self-inspects the quality of a conventional circuit having an arbitrary function. A BIST circuit 1 for self-inspecting the quality of a circuit having an arbitrary function shown in FIG. 2 is a test pattern generation unit 2 for testing a circuit having an arbitrary function, and a circuit having an arbitrary function for storing a test result is normal. A test result comparison circuit 3 is provided for determining whether it is operating or malfunctioning.

  The test pattern generator 2 generates a test pattern 4 for generating a test pattern for actually testing a circuit having an arbitrary function. An arbitrary test pattern generated by the test pattern generator 4 by cutting off the system input A selector circuit 5 for transmitting a circuit having a function is provided.

  A test method using a BIST circuit that self-inspects the quality of a circuit having an arbitrary function is to send a test pattern generated by the test pattern generation circuit 4 to a circuit having an arbitrary function via the selector circuit 5, Test the functional circuit.

  The test result is sent from the circuit having an arbitrary function to the test result comparison circuit 3 and compared with an expected value generated by the test pattern generation circuit 4. Using the comparison result, it is determined whether a circuit having an arbitrary function is operating normally or has failed.

  However, the BIST circuit that self-inspects the quality of the conventional circuit having an arbitrary function in FIG. 2 can only determine whether the circuit having the arbitrary function is operating normally or has failed. After the semiconductor integrated circuit device mounting the device fails, the control device mounting the semiconductor integrated circuit device is stopped and the semiconductor integrated circuit device is replaced. For this reason, an operation stop period such as stopping the control device on which the semiconductor integrated circuit device is mounted is necessary, and there is a problem that the control device on which the semiconductor integrated circuit device is mounted does not function as a system during that period. .

In order to solve the above-described problems, the present invention adds a failure prediction inspection function to a BIST circuit that self-inspects the quality of a circuit having an arbitrary function. The failure prediction inspection function is configured by a circuit using a counter circuit, A circuit with an arbitrary function by measuring the time required to test a circuit with an arbitrary function implemented in the circuit, comparing the measurement result with the expected value of the counter, and investigating the difference between the expected value of the counter It becomes possible to grasp the normal operation period.

  By sending information that a semiconductor integrated circuit device equipped with a circuit having an arbitrary function may fail in the near future, the control device equipped with this semiconductor integrated circuit device is Thus, the semiconductor integrated circuit device can be replaced before failure.

  This improves the reliability of the control device equipped with a semiconductor integrated circuit device equipped with a circuit having an arbitrary function, and also prevents functional malfunction and runaway of the control device, thereby improving functional safety. Is possible.

It is a block diagram of the test result comparison circuit which showed the 1st Embodiment of this invention. It is a conventional basic configuration diagram.

  Hereinafter, embodiments will be described with reference to the drawings.

  As means for solving the above-mentioned problems, an example of the present invention is shown below.

  FIG. 1 shows a basic configuration of a circuit in which a failure prediction inspection function is added to a BIST circuit that self-inspects the quality of a circuit having an arbitrary function in the present invention. The test pattern generator 2 shown in FIG. 2 is omitted because it uses the same circuit in the present invention.

  A test result comparison circuit 1 shown in FIG. 1 stores a test result mounted on a conventional BIST circuit, and determines whether a circuit having an arbitrary function is operating normally or has a failure. A failure prediction inspection unit 3 for calculating a normal operation period of a circuit having an arbitrary function and predicting a period until failure is provided.

  The failure prediction inspection unit 3 receives the test result determination information from the test result comparison unit 2 and controls the count operation, the FF group 5 that stores the result of the counter circuit 4, and the counter that is input from the test pattern generation unit The FF group 6 that stores the lower limit expected value and the counter upper limit expected value, the comparison circuit 7 that compares the values stored in the FF group 5 and the FF group 6, the lower limit expected value and the upper limit expected value of a circuit having an arbitrary function It has FF8 which judges a comparison result.

  Based on the operation of the conventional BIST circuit, it is determined from the signal output by the circuit having an arbitrary function whether the circuit is operating normally or has failed. At the same time, the counter circuit 4 mounted on the failure prediction inspection unit 3 performs a counting operation, and the counter circuit 4 stops the counting operation when it is determined that the determination result from the test result comparison unit 2 is not abnormal. The count value of the counter circuit 4 at this time is stored in the FF group 5.

  The expected counter lower limit value and the expected counter upper limit value input from the test pattern generation unit are stored in the FF group 6 while testing a circuit having an arbitrary function.

  The count value stored in the FF group 5, the expected counter lower limit value and the expected counter upper limit value stored in the FF group 6 are transferred to the comparison circuit 7 for comparison processing. First, the count value from the FF group 5 and the counter lower limit expected value from the FF group 6 are compared, and it is confirmed that the count value from the FF group 5 is larger than the counter lower limit expected value from the FF group 6. If the comparison result is large, it is determined that there is no abnormality, and if the comparison result is small, it is determined that the semiconductor integrated circuit device has failed. Next, it is confirmed that the count value from the FF group 5 is smaller than the counter upper limit expected value from the FF group 6. If the comparison result is small, it is determined that there is no abnormality, and if the comparison result is large, it is determined that the semiconductor integrated circuit device has failed. From these determination results, it is determined whether a circuit having an arbitrary function has a normal operation period or not, and the result is stored in the FF 8.

  Finally, the FF group 5, the FF group 6, and the FF 8 are read from the semiconductor integrated circuit device, and it is confirmed from the read result of the FF 8 that a normal operation period exists, and the read result of the FF group 5 and the read result of the FF group 6 are The degree of difference is calculated, and the normal operation period of a circuit having an arbitrary function is calculated. If the count value read from the FF group 5 is close to the expected counter lower limit value read from the FF group 6, the circuit having an arbitrary function has a sufficient normal operation period, so that the semiconductor integrated circuit device is replaced. Is not necessary. Conversely, if the count value read from the FF group 5 is close to the counter upper limit expected value read from the FF group 6, it is determined that the replacement period of the semiconductor integrated circuit device is near because the normal operation period is short. This test and failure prediction can be carried out at the time of regular system inspection and startup.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  In addition, control lines and signal lines are those that are considered necessary for the explanation, and not all control lines and signal lines are necessarily shown.

1 Test result comparison circuit 2 Test result comparison unit 3 Failure prediction inspection unit 3
4 Counter circuit with count control 4
5 FF group 6 for storing the result of the counter circuit 4 FF group 7 for storing the counter lower limit expected value and the counter upper limit expected value The comparison circuit 8 for comparing the values stored in the FF group 5 and the FF group 6 Normal operation period of the circuit FF that determines whether or not there is

Claims (4)

A test pattern generation unit, a test result comparison unit, and a failure prediction inspection unit for predicting the period until a test target fails,
The failure prediction inspection unit receives a test result determination information from the test result comparison unit and controls a counter operation, a counter circuit result storage unit that stores a result value of the counter circuit, and the test pattern generation Expected counter value storage unit that stores the expected counter value input from the comparator, and a comparison circuit that compares the result value stored in the counter circuit result storage unit with the expected counter value stored in the expected counter value storage unit And a comparison result determination unit for determining a comparison result in the comparison circuit,
The comparison result determination unit is a reliability confirmation circuit for confirming that the count value measured in the test is larger than the counter lower limit expected value or smaller than the counter value measured in the test and the counter upper limit expected value.   The reliability check circuit according to claim 1, wherein the failure time is predicted from a difference between the counter lower limit expected value and the counter upper limit expected value. In the reliability confirmation circuit according to claim 1 or 2,
A circuit for reliability confirmation, wherein the counter lower limit expected value or the counter upper limit expected value can be arbitrarily set. In the reliability confirmation circuit according to claim 1,
A reliability confirmation circuit for determining whether or not the test target has a normal operation period from the determination result of the comparison result determination unit.

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