JP2018011220A - Communication apparatus and transmission control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication apparatus capable of suppressing transmission delay of a transmitter signal included in a radio signal to a radio unit.SOLUTION: A communication apparatus 1 having a radio controller unit 3 which includes: a signal generation part 41 that generates a transmitter signal; a transmission control unit 42 that transmits the transmitter signal to a radio unit 2 according to transmission timing when the radio unit 2 transmits the radio signal including the transmitter signal; and a switch 43 connecting the signal generation part 41 and the transmission control unit 42, which transmits the transmitter signal in a first route connecting the signal generation part 41 and the transmission control unit 42 prior to the transmission of a signal in other route according to the transmission timing.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a communication device having, for example, a wireless device and a wireless control device, and a transmission signal transmission control method used in such a communication device.

  In a mobile communication system, a base station may have at least one radio device (Radio Equipment, RE) and a radio controller (Radio Equipment Controller, REC). The RE has a wireless processing unit and an antenna. Then, the RE generates a radio signal by superimposing the downlink signal received from the REC on a carrier wave, and transmits the radio signal to the mobile station. In addition, the RE extracts an uplink signal having a baseband frequency from a radio signal received from a mobile station via an antenna and transmits it to the REC. Meanwhile, the REC performs processing such as connection control with a mobile station, scheduling, generation of in-phase / quadrature phase (IQ) data of a downlink signal, and extraction of a data signal and a control signal from the received uplink signal. . The RE and REC are connected by a signal line such as an optical fiber cable, for example, and can communicate with each other in accordance with the Common Public Radio Interface (CPRI) (see, for example, Non-Patent Document 1). The IQ data of the downlink signal transmitted from the REC to the RE is transmitted after being stored in a predetermined position of the CPRI frame, for example.

  In addition, long term evolution (Long Term Evolution, LTE), which is a communication standard standardized by the Third Generation Partnership Project (3GPP), and LTE-Advanced, which is currently under consideration, are based on time division duplex. (Time Division Duplex, TDD) is adopted. For example, in LTE employing TDD, a frame is divided into 10 subframes along the time direction. Each subframe has two slots along the time direction, and each slot has seven symbols along the time direction and a predetermined number of subcarriers along the frequency direction. Each combination of symbols and subcarriers is called a radio resource used for radio communication with a mobile station. A radio resource is allocated to a mobile station selected by scheduling in a resource block (Resouce Block) unit having 7 symbols in the time direction and 12 subcarriers in the frequency direction (for example, non-patent) Reference 2).

CPRI Specification V6.0, August 30, 2013 3GPP TS36.211 V11.1.0, December 2012

  In the base station having the RE and the REC, a delay corresponding to the distance between the RE and the REC occurs in the transmission of the downlink signal from the REC to the RE. Therefore, the IQ data of the downlink signal is generated before the transmission timing in consideration of the delay so as to be in time for the transmission timing specified by the assigned radio resource, and is transmitted to the RE. Is required.

  In REC, when a module that generates IQ data and a module that generates a CPRI frame are directly connected, the time required from when IQ data is generated until it is stored in the CPRI frame is substantially constant. Therefore, the timing at which IQ data is generated may be adjusted in consideration of the required time. However, in REC, a module that generates IQ data and a module that generates a CPRI frame may be connected via a transmission path. In such a case, a delay may occur due to congestion or the like in the IQ data transmission path (hereinafter also referred to as a route) from the module that generates IQ data to the module that generates the CPRI frame. When a delay occurs, IQ data to be transmitted using a predetermined radio resource does not meet the timing at which the corresponding position of the CPRI frame is output to the RE, and as a result, a desired downlink signal is transmitted with the radio resource. May not be sent.

  In one aspect, an object of the present invention is to provide a communication device capable of suppressing transmission delay of a transmission signal included in a wireless signal to the wireless device.

  According to one embodiment, a communication device is provided that includes a wireless control device that generates a transmission signal and a wireless device that is connected to the wireless control device and transmits a wireless signal including the transmission signal. In this communication device, the wireless control device includes a signal generation unit that generates a transmission signal, a transmission control unit that transmits the transmission signal to the wireless device according to a transmission timing at which the wireless device transmits a wireless signal including the transmission signal, A switch that connects the signal generation unit and the transmission control unit, and prioritizes transmission of the transmission signal in the first route over the transmission of the other route in accordance with the transmission timing between the signal generation unit and the transmission control unit; Have

  According to another embodiment, there is provided a transmission control method in a communication apparatus having a radio control apparatus that generates a transmission signal and a radio apparatus that is connected to the radio control apparatus and transmits a radio signal including the transmission signal. This transmission control method uses a radio controller to transmit a signal generating unit that generates a transmission signal and a switch that connects a transmission controller that transmits a transmission signal to the radio device according to a transmission timing transmitted by the radio device. In accordance with the timing, it is set that the transmission of the transmission signal in the first route connecting the signal generation unit and the transmission control unit is given priority over the transmission of the signal in the other route. And transmitting from the signal generation unit to the transmission control unit.

  Transmission delay of the transmission signal included in the wireless signal to the wireless device can be suppressed.

It is a schematic block diagram of the base station by one Embodiment. It is a schematic block diagram of a radio | wireless control apparatus. It is a schematic block diagram of the control part of a radio | wireless control apparatus regarding the production | generation of IQ data, and transmission of IQ data to a radio | wireless apparatus. It is a schematic block diagram of a CPRI function part. It is a schematic block diagram of a switch. (A) is a figure which shows an example of the structure of a priority route setting request packet. (B) is a figure which shows an example of the structure of IQ data packet. It is a sequence diagram of a transmission control process. It is explanatory drawing of the outline | summary of the transmission process of a control packet at the time of transmission interruption of a control packet.

Hereinafter, a base station according to an embodiment of a communication device will be described with reference to the drawings.
This base station has at least one RE and REC. The RE and REC are connected via an optical fiber cable or the like, and the downlink signal and the uplink signal are between RE and REC in accordance with CPRI. It is transmitted with. The REC has a module that generates IQ data and a module that generates a CPRI frame, and these modules are connected via switches that are also connected to other modules (for example, modules that generate control signals). . Then, the REC sets the IQ data transmission path so that the IQ data is stored in the corresponding position of the CPRI frame transmitted from the REC to the RE according to the timing when the radio signal including the IQ data is transmitted from the RE. Control the switch to give priority.

  In the present embodiment, the communication device is a base station compliant with LTE or LTE-Advanced. However, the communication device may be compliant with various other wireless communication standards that can include REC and RE.

  FIG. 1 is a schematic configuration diagram of a base station according to one embodiment. The base station 1 includes a radio device (RE) 2 and a radio control device (REC) 3. RE2 and REC3 are connected to each other by an optical fiber cable 4. Then, the downlink signal and the uplink signal are transmitted between the RE and the REC through the optical fiber cable 4 according to a CPRI-compliant method. In the present embodiment, the base station 1 has one RE, but the base station 1 may have a plurality of REs. Also in this case, each RE is connected to the REC 3 by an optical fiber cable, and signal transmission between each RE and the REC 3 may be performed according to a CPRI-compliant system.

  The RE 2 includes an antenna 21 and a wireless processing unit 22. The antenna 21 transmits a radio signal including a downlink signal transmitted via the radio processing unit 22. The antenna 21 receives a radio signal from a mobile station (not shown), converts it into an electric signal, and transmits it to the radio processing unit 22. Note that the antenna 21 may have a transmitting antenna and a receiving antenna separately.

  The radio processing unit 22 is formed by, for example, one or a plurality of integrated circuits, converts the IQ data of the downlink signal received from the REC 3 via the optical fiber cable 4 into an analog signal, and then sets the radio frequency specified by the REC 3. A radio signal is superimposed on the carrier wave. Then, the wireless processing unit 22 amplifies the wireless signal to a desired level by a high power amplifier (not shown) and transmits the wireless signal to the antenna 21.

  The wireless processing unit 22 amplifies the wireless signal received from the antenna 21 by a low noise amplifier (not shown). The radio processing unit 22 extracts an uplink signal carried by the radio signal by multiplying the amplified radio signal by a periodic signal having an intermediate frequency. The wireless processing unit 22 performs analog / digital conversion on the uplink signal and then transmits the uplink signal to the REC 3 via the optical fiber cable 4.

  FIG. 2 is a schematic configuration diagram of the REC 3. The REC 3 includes a wired interface unit 31, a storage unit 32, and a control unit 33. The wired interface unit 31, the storage unit 32, and the control unit 33 are formed as separate circuits. Alternatively, each of these units may be mounted on the REC 3 as one or a plurality of integrated circuits in which circuits corresponding to the respective units are integrated.

  The wired interface unit 31 includes a communication interface circuit for connecting the REC 3 to an upper node (not shown) and another base station (not shown). Then, the wired interface unit 31 analyzes the signal received from the upper node according to the S1 interface, and extracts the downlink signal and the control signal included in the signal. Further, the wired interface unit 31 analyzes a signal received from another base station in accordance with the X2 interface, and extracts a control signal included in the signal. Then, the wired interface unit 31 passes the extracted downlink signal and control signal to the control unit 33.

  On the other hand, the wired interface unit 31 converts the uplink signal received from the control unit 33 into a signal in a format according to the S1 interface, and then outputs the signal to the upper node. The wired interface unit 31 converts a control signal to be transmitted to another base station into a format according to the X2 interface. The wired interface unit 31 outputs the control signal to another base station.

  The storage unit 32 includes, for example, a rewritable nonvolatile semiconductor memory or volatile semiconductor memory. The storage unit 32 stores various information for communicating with the mobile station, various information transmitted or received by the REC 3 via the RE 2, and various programs operating on the REC 3.

  The control unit 33 includes, for example, a plurality of integrated circuits and switches that connect the integrated circuits. Then, the control unit 33 executes various processes for executing wireless communication such as resource allocation to mobile stations, transmission power control, call control, retransmission control, and handover-related processes.

  Furthermore, the control unit 33 generates downlink IQ data by modulating the downlink signal according to the modulation and multiplexing method adopted in the communication standard that the base station 1 complies with. Then, the control unit 33 transmits the generated IQ data to the RE 2 via the optical fiber cable 4.

  On the other hand, the control unit 33 separates the uplink signal received from the RE 2 via the optical fiber cable 4 in accordance with the modulation and multiplexing method adopted by the communication standard that the base station 1 complies with, and separates the received signals respectively. Demodulate. Then, the control unit 33 outputs the demodulated uplink signal to the wired interface unit 31. Further, the control unit 33 extracts uplink control information and the like referred to by the REC 3 from the demodulated uplink signal.

  FIG. 3 is a schematic configuration diagram of the control unit 33 relating to generation of IQ data and transmission of IQ data to the RE 2. The control unit 33 includes a control signal generation unit 40, an IQ data generation unit 41, a CPRI function unit 42, and a switch 43. The switch 43 is a multi-input multi-output (MPMT) type switch, and the control signal generation unit 40, IQ data generation unit 41, and CPRI function unit 42 are connected via the switch 43. In the present embodiment, the switch 43 has three input ports # 1 to # 3 and three output ports # 1 to # 3. The control signal generator 40 is connected to the input port # 2 and the output port # 2 of the switch 43. The IQ data generation unit 41 is connected to the input port # 1 and the output port # 1 of the switch 43. The CPRI function unit 42 is connected to the input port # 3 and the output port # 3 of the switch 43. Accordingly, in the present embodiment, a priority route is appropriately set between the input port # 1 connected to the IQ data generation unit 41 and the output port # 3 connected to the CPRI function unit 42.

  In the present embodiment, the signal transmitted via the switch 43 is transmitted in the form of a packet conforming to a predetermined communication standard. The predetermined communication standard can be, for example, Ethernet (registered trademark). Further, the switch 43 determines the output port of the packet by referring to the destination information stored in the header of the packet. For example, the packet output from the IQ data generation unit 41 and the packet output from the control signal generation unit 40 are transmitted to the CPRI function unit 42 via the switch 43. A packet transmitted from the CPRI function unit 42 to the control signal generation unit 40 or the IQ data generation unit 41 is also transmitted via the switch 43. An error detection code is attached to the packet. For example, Frame Check Sequence (FCS) is used as the error detection code.

  Note that the number of input ports included in the switch 43 is not limited to three, and may be four or more, for example. Similarly, the number of output ports included in the switch 43 is not limited to three, and may be four or more. Further, the number of control signal generation units 40 connected to the switch 43 is not limited to one, and may be plural. Similarly, the number of IQ data generation units 41 connected to the switch 43 is not limited to one and may be plural. Furthermore, the control unit 33 may include the same number of CPRI function units 42 as the number of REs 2 included in the base station 1. Furthermore, the switch 43 may be connected to a device that generates signals other than IQ data packets and control packets.

  The control signal generation unit 40 generates a control signal for controlling the RE2. The control signal includes, for example, information specifying the frequency of the carrier wave. Then, the control signal generation unit 40 generates a packet including the control signal and outputs the packet to the switch 43. Hereinafter, a packet including a control signal is referred to as a control packet.

  The IQ data generation unit 41 is an example of a signal generation unit, and generates IQ data by modulating a downlink signal in accordance with a modulation scheme selected by scheduling. IQ data is an example of a transmission signal. At that time, the IQ data generation unit 41 generates IQ data a predetermined time before the transmission timing so that the IQ data is in time for the transmission timing of the radio signal, and a buffer (not shown) included in the IQ data generation unit 41. ). When the IQ data generation unit 41 receives a transmission request packet requesting transmission of IQ data from the switch 43, the IQ data generation unit 41 packetizes the IQ data stored in the buffer and outputs the packet to the switch 43. Hereinafter, a packet including IQ data is referred to as an IQ data packet.

  The CPRI function unit 42 is an example of a transmission control unit, and transmits IQ data, a control signal, and the like received from the IQ data generation unit 41 to the RE 2 via the optical fiber cable 4 in conformity with CPRI.

  FIG. 4 is a schematic configuration diagram of the CPRI function unit 42. The CPRI function unit 42 includes a timing determination unit 421, a packet generation unit 422, an error check unit 423, a buffer 424, and a frame generation unit 425. Each of these units included in the CPRI function unit 42 is realized by, for example, one or a plurality of integrated circuits.

  The timing determination unit 421 determines the timing (hereinafter simply referred to as output instruction timing) for instructing the IQ data generation unit 41 to start the output of IQ data for each IQ data in the downlink signal. For example, IQ data located at the beginning of a frame of a radio signal is required to be stored at a position of hyperframe number = 0 and basic frame number = 0 of the CPRI frame. Thus, each delivery position in the CPRI frame is determined for each IQ data. A plurality of IQ data can be stored in the IQ data packet. Therefore, it is required that an appropriate output instruction timing is determined for each set of IQ data transmitted in one IQ data packet.

  Therefore, the timing determination unit 421 determines the output instruction timing for each IQ data packet by subtracting a predetermined required time from the transmission timing of the radio signal including the IQ data transmitted by the IQ data packet. The required time includes, for example, the time required for transmission of the IQ data packet from the IQ data generation unit 41 to the RE 2 and the time required for the transmission instruction to reach the IQ data generation unit 41 from the CPRI function unit 42. Measured in advance. The required time is stored in a nonvolatile memory circuit (not shown) included in the timing determination unit 421.

  The timing determination unit 421 determines an output instruction timing for each IQ data packet with reference to a clock synchronized with the timing of each frame of the radio signal. The timing determination unit 421 notifies the packet generation unit 422 that the output instruction timing has been reached each time the output instruction timing is reached.

  Furthermore, when the timing at which the IQ data stored in the buffer 424 is transmitted to the RE 2 is reached, the timing determination unit 421 notifies the frame generation unit 425 to that effect.

  When notified from the timing determination unit 421 that the output instruction timing has been reached, the packet generation unit 422 generates a priority route setting request packet that instructs the switch 43 to prioritize the IQ data transmission path. At that time, the packet generation unit 422 includes the identification number of the input port and the identification number of the output port of the switch 43 located on the priority route in the priority route setting request packet. The input port identification number and the output port identification number of the switch 43 located on the priority route may be stored in advance in a memory circuit included in the CPRI function unit 42. Then, the packet generation unit 422 outputs a priority route setting request packet to the switch 43. As a result, the CPRI function unit 42 can cause the switch 43 to set a priority route at an appropriate timing.

  When the error check unit 423 is instructed to request retransmission, the packet generation unit 422 generates a retransmission request packet that requests the packet transmission source, for example, the IQ data generation unit 41 to retransmit the packet. Then, the packet generation unit 422 transmits the retransmission request packet to the transmission source via the switch 43.

  The error check unit 423 determines whether there is an error in the packet based on the error detection code included in the packet received from the switch 43. When there is no error in the packet, the error check unit 423 extracts data stored in the packet, for example, IQ data, and stores it in the buffer 424. On the other hand, when there is an error in the packet, the error check unit 423 discards the packet. Then, the error check unit 423 notifies the packet generation unit 422 of the information on the transmission source of the packet, and instructs to request retransmission of the packet.

The buffer 424 temporarily stores IQ data, control signals, and the like received by the CPRI function unit 42. The IQ data stored in the buffer 424 is read by the frame generation unit 425 according to the timing at which the IQ data is transmitted to the RE 2. Thereby, even when the timing at which a packet including IQ data arrives at the CPRI function unit 42 fluctuates, the CPRI function unit 42 corrects the fluctuation of the timing and stores the IQ data at the corresponding position in the CPRI frame. Can do.
Similarly, the control signal stored in the buffer 424 is also read by the frame generation unit 425 according to the timing at which the control signal can be transmitted, and transmitted to the RE 2.

  The frame generation unit 425 generates a CPRI frame and transmits the CPRI frame to the RE 2 via the optical fiber cable 4. Therefore, when notified from the timing determination unit 421 that it is the timing to transmit the IQ data to the RE 2, the frame generation unit 425 reads the corresponding IQ data from the buffer 424 and places the IQ data at the corresponding position on the CPRI frame. Store the data.

  In addition, the frame generation unit 425 reads the control signal from the buffer 424, stores the control signal in the control signal transmission area in the CPRI frame, and transmits the control signal to the RE2. As for the control signal, the transmission timing of IQ data does not have to be set strictly. Therefore, the frame generation unit 425 may transmit the IQ data to the RE 2 with priority over the control signal.

  The CPRI function unit 42 may extract uplink IQ data transmitted from the RE 2 via the optical fiber cable 4 and output the IQ data to a circuit that processes the uplink signal.

Next, details of the switch 43 will be described.
FIG. 5 is a schematic configuration diagram of the switch 43. In the present embodiment, the switch 43 has three input ports # 1 to # 3 and three output ports # 1 to # 3. The switch 43 includes a selector 431, a buffer 432, and a sending unit 433 at input ports # 1 and # 2 connected to the IQ data generating unit 41 or the control signal generating unit 40, respectively. In addition, in the input port # 3 connected to the CPRI function unit 42, the switch 43 has a packet analysis unit 434. Further, the switch 43 includes a request packet generation unit 435 and a transmission packet selection unit 436 at the output ports # 1 and # 2 connected to the IQ data generation unit 41, respectively. Furthermore, the switch 43 includes an error check unit 437, a buffer 438, and a selector 439 at the output port # 3 connected to the CPRI function unit 42. Further, the switch 43 includes a switch control unit 440.

  The selector 431 selects either the buffer 432 or the transmission unit 433 as the transmission destination of the packet received from the outside. In the present embodiment, the selector 431 directly outputs the IQ data packet to the transmission unit 433 at the input port # 1 connected to the IQ data generation unit 41. On the other hand, at the input port # 2 connected to the control signal generation unit 40, the selector 431 writes the control packet in the buffer 432.

  The buffer 432 includes, for example, a first-in first-out memory circuit, and temporarily stores the control packet received from the control signal generation unit 40 via the selector 431. Then, the buffer 432 sequentially outputs the control packet received earlier to the transmission unit 433. The output control packet may be deleted from the buffer 432.

  In the input port # 1 connected to the IQ data generation unit 41, the transmission unit 433 inputs the IQ data packet received from the selector 431 to the main body 441 of the switch 43. On the other hand, in the input port # 2 connected to the control signal generation unit 40, the transmission unit 433 sequentially reads out the packets stored in the buffer 432 to the main body 441 of the switch 43 while the priority route is not set. input. As described above, at the input port # 1 connected to the IQ data generation unit 41, the IQ data packet is directly transferred from the selector 431 to the transmission unit 433, so that a delay in transmission of the IQ data packet is suppressed. Further, at the input port # 2, the sending unit 433 stops reading out the control packet from the buffer 432 and sending out the control packet while the priority route passing through the other input port is set. This prevents congestion at the switch 43 during the setting of the priority route.

  In addition, in the input port # 2 connected to the control signal generation unit 40, the transmission unit 433 reads out the control packet when any priority route is set while the control packet is being transmitted from the transmission unit 433. And stop sending. The sending unit 433 attaches an interruption signal indicating that reading is interrupted to the portion of the control packet read from the buffer 432 until reading and sending are interrupted.

  In the present embodiment, a signal obtained by converting an error detection code according to a predetermined conversion rule is used as the interruption signal. For example, the sending unit 433 calculates the FCS for the portion of the control packet read from the buffer 432 until the sending is interrupted, and inverts the value of each bit of the obtained FCS. It is attached to that part as an interruption signal. Alternatively, the transmission unit 433 may use a bit obtained by inverting the value of one or two predetermined bits of each bit of the obtained FCS as an interruption signal. By using such an interruption signal, it becomes easy to determine whether or not the control packet is interrupted. Then, the sending unit 433 sends a part of the control packet with the interruption signal to the main body 441 of the switch 43. The sending unit 433 stores the position where sending is interrupted in the control packet and the header information of the control packet.

  Thereafter, when the setting of the priority route is canceled, the sending unit 433 reads the remaining part of the control packet after the position where the sending is interrupted from the buffer 432, and controls the remaining part of the control packet. Attaches packet header information. Further, the sending unit 433 gives an interruption signal to the remaining part. Similarly to the above, this interruption signal can be obtained by converting the error detection code according to a predetermined conversion rule.For example, the value of each bit of the FCS calculated for the remaining portion or the predetermined bit The value can be inverted. The sending unit 433 sends the remaining part of the control packet to which the interruption signal is added to the main body 441 of the switch 43. Note that the buffer 432 may be erased with respect to the portion read until the transmission is interrupted. In this case, since the head position of the control packet read after canceling the setting of the priority route is the interruption position, the transmission unit 433 does not need to store the interruption position.

  Thereby, even when the control packet is being transmitted through the switch 43, the switch 43 can set the priority route and give priority to the transmission of the IQ data packet.

  The packet analysis unit 434 provided in the input port # 3 connected to the CPRI function unit 42 analyzes the packet received from the CPRI function unit 42 and determines whether or not the packet is a priority route setting request packet. For example, the packet analysis unit 434 can determine whether the received packet is a priority route setting request packet by referring to the header information of the received packet.

  When the received packet is a priority route setting request packet, the packet analysis unit 434 switches the setting of the input port number and output port number set as the priority route and the priority route included in the packet. Notify the controller 440.

  On the other hand, when the received packet is not a priority route setting request packet (for example, when it is a retransmission request packet), the packet analysis unit 434 outputs the received packet to the main body 441 of the switch 43. In this case, the packet is transmitted based on the destination information included in the packet.

  When the request packet generator 435 provided in the output port # 1 connected to the IQ data generator 41 is notified from the switch controller 440 that the priority route is set to the IQ data generator 41, the IQ packet generator 435 A transmission request packet for requesting transmission of a data packet is generated. Then, the request packet generation unit 435 outputs the transmission request packet to the transmission packet selection unit 436. Thus, the switch 43 can cause the IQ data generation unit 41 to start sending IQ data packets without delay in accordance with the setting of the priority route.

  The transmission packet selection unit 436 provided in the output port # 1 receives the packet (for example, retransmission request packet) output from the output port # 1 or the transmission request packet from the request packet generation unit 435. Then, the transmission packet selection unit 436 outputs the received packet to the IQ data generation unit 41. Also, the transmission packet selection unit 436 provided in the output port # 2 connected to the control signal generation unit 40 transmits the packet (for example, retransmission request packet) output from the output port # 2 to the control signal generation unit 40. Output.

  The error check unit 437 provided in the output port # 3 connected to the CPRI function unit 42 is an example of an interruption detection unit. If a priority route via the output port is not set, the error check unit 437 determines whether or not the packet is a control packet for which transmission has been interrupted based on whether or not the packet has been interrupted. judge. For example, the error check unit 437 determines whether or not the value of the error detection code attached to the packet matches the value of the error detection code converted according to a predetermined conversion rule corresponding to the interruption signal. If the two match, the error check unit 437 determines that the packet is a control packet for which transmission has been interrupted. If the two do not match, the error check unit 437 determines that the packet is not a control packet for which transmission has been interrupted. . For example, as described above, it is assumed that the error detection code converted according to a predetermined conversion rule is an FCS in which the value of each bit or a predetermined bit is inverted. In this case, when the value of each bit or predetermined bit of the FCS attached to the packet is the one obtained by inverting the value of each bit of the FCS calculated for the packet, the error check unit 437 Is determined to be a control packet whose transmission has been interrupted.

  If the received packet is a control packet for which transmission has been interrupted, the error check unit 437 removes the interruption signal from the packet and stores it in the buffer 438. Then, when the error check unit 437 next receives a control packet for which transmission has been interrupted, the error check unit 437 removes the header information and the interruption signal from the control packet for which transmission has been interrupted. Then, the error check unit 437 combines the remaining part of the control packet that is received later and whose transmission is interrupted with the part of the control packet that is stored in the buffer 438 and is previously transmitted and whose transmission is interrupted. By doing so, the control packet is restored. Then, the error check unit 437 stores the restored control packet in the buffer 438. As a result, even if the transmission of the control packet is interrupted due to the setting of the priority route, the error check unit 437 can restore the control packet whose transmission has been interrupted without retransmitting.

  In addition, when the received packet is a control packet whose transmission is not interrupted, the error check unit 437 stores the packet itself in the buffer 438.

  Further, while the priority route is set for the output port provided with the error check unit 437, the error check unit 437 directly passes the packet (that is, the IQ data packet) received from the output port to the selector 439.

  The buffer 438 temporarily stores the control packet written by the error check unit 437 and a part of the control packet whose transmission has been interrupted. The buffer 438 deletes the read control packet every time the control packet is read from the selector 439. Note that the buffer 438 may separately include a memory circuit that stores the control packet and a memory circuit that stores a part of the control packet whose transmission is interrupted.

  The selector 439 directly receives the IQ data packet from the error check unit 437 while the priority route passing through the output port (in this example, output port # 3) provided with the selector 439, and receives the packet. Output to the CPRI function unit 42. On the other hand, the selector 439 stops reading the control packet from the buffer 438. When the selector 439 confirms that the IQ data packet has passed through the selector 439 by analyzing the header information of each packet output to the CPRI function unit 42, the selector 439 notifies the switch controller 440 of that fact. On the other hand, if the priority route via the output port provided with the selector 439 is not set, the selector 439 reads the control packet from the buffer 438 and outputs the packet to the CPRI function unit 42.

  When notified from the packet analysis unit 434 that the priority route is set, the switch control unit 440 refers to the input port number and the output port number to be set as the priority route included in the priority route setting request packet. , Set the preferred route. Then, the switch control unit 440 determines that the transmission route 433 provided in the input port on the priority route and the error check unit 437 and selector 439 provided in the output port on the priority route become the priority route. Notice. In addition, the switch control unit 440 sets other priority routes in the sending unit 433 provided in the input port outside the priority route, and in the error check unit 437 and the selector 439 provided in the output port outside the priority route. Notify that.

  In addition, the switch control unit 440 is notified that a packet including IQ data has passed from the selector 439 on the priority route after the priority route is set, or the priority is given when a predetermined period elapses after the priority route is set. Cancel the route setting. At that time, the switch control unit 440 notifies the sending unit 433 of each input port and the error check unit 437 and the selector 439 of each output port that the setting of the priority route is cancelled.

  FIG. 6A is a diagram illustrating an example of the structure of a priority route setting request packet. In this example, the priority route setting request packet 600 is a packet compliant with Ethernet (registered trademark), and includes a source port number 601 and a destination port number 602 in the UDP header, and a data area 603. The combination of the value of the source port number 601 (in this example, “60000”) and the value of the destination port number 602 (in this example, “60001”) identifies the priority route setting request packet. The data area 603 includes an output port identification number set for the priority route and an input port identification number set for the priority route.

  FIG. 6B is a diagram illustrating an example of the structure of the IQ data packet. In this example, the IQ data packet 610 is a packet compliant with Ethernet (registered trademark), and includes a transmission source port number 611 and a destination port number 612 in the UDP header, and a data area 613. The combination of the value of the source port number 611 (in this example, “60000”) and the value of the destination port number 612 (in this example, “60003”) identifies the IQ data packet. The data area 613 includes a predetermined number (for example, 8 chips) of IQ data.

  FIG. 7 is a sequence diagram of transmission control processing according to this embodiment. In this example, it is assumed that a route connecting the input port # 1 and the output port # 3 is set as the priority route.

  At the output instruction timing, the CPRI function unit 42 generates a priority route setting request packet and transmits the priority route setting request packet to the input port # 3 of the switch (step S101). The packet analysis unit 434 provided for the input port # 3 sets the input port identification number and the output port identification number on the priority route and the priority route included in the received priority route setting request packet. The switch control unit 440 is notified (step S102).

  The switch control unit 440 notifies the sending unit 433 provided in the input port # 1 on the priority route, the error check unit 437 provided in the output port # 3, and the selector 439 that the route is preferred. (Step S103). In addition, the switch control unit 440 notifies the sending unit 433 provided in the input port # 2 outside the priority route that another priority route has been set (step S104).

  Further, the switch control unit 440 instructs the request packet generation unit 435 of the output port # 1 connected to the IQ data generation unit 41 to generate a transmission request packet (step S105). When requested to generate a transmission request packet, the request packet generation unit 435 of the output port # 1 generates a transmission request packet and transmits the transmission request packet to the IQ data generation unit 41 (step S106).

  When receiving the transmission request packet, the IQ data generating unit 41 connected to the input port # 1 generates an IQ data packet and sends the IQ data packet to the input port # 1 (step S107). The IQ data packet input to the input port # 1 is transmitted from the output port # 3 to the CPRI function unit 42 (step S108).

  The CPRI function unit 42 stores each IQ data included in the received IQ data packet in the corresponding position on the CPRI frame and sends it to the RE 2 (step S109).

  Further, when the IQ data packet is output to the CPRI function unit 42, the selector 439 of the output port # 3 notifies the switch control unit 440 to that effect (step S110). Then, the switch control unit 440 notifies the cancellation of the setting of the priority route to each port (step S111). Then, the control unit 33 ends the transmission control process.

  FIG. 8 is an explanatory diagram of an outline of control packet transmission processing when control packet transmission is interrupted. In FIG. 8, the left side represents processing at the input port, and the right side represents processing at the output port. The vertical axis represents the processing procedure.

  Assume that a priority route is set for the input port # 1 at the time when a part 800a of the control packet 800 is read from the buffer 432 at the input port # 2. In this case, the sending unit 433 calculates an FCS for a part 800a of the control packet 800, and an interruption signal 801 obtained by inverting the value of each bit of the FCS or a predetermined bit is a part 800a of the control packet 800. And sent to output port # 3. In the output port # 3, the interruption signal 801 is removed by the error check unit 437, and a part 800a of the control packet is stored in the buffer 438.

  Thereafter, while the priority route is set, the IQ data packet is transmitted from the IQ data generation unit 41 to the CPRI function unit 42 via the priority route. When the setting of the priority route is canceled, the transmission unit 433 reads the remaining 800 b of the control packet 800 from the buffer 432. Then, the sending unit 433 calculates the FCS for the remaining 800 b of the control packet 800. Then, an interruption signal 802 obtained by inverting the value of each bit of the FCS or a predetermined bit and the same header 803 as the header of the control packet 800 are attached to the remaining 800b of the control packet 800 and transmitted to the output port # 3. .

  At the output port # 3, the interruption signal 802 and the header 803 are removed by the error check unit 437, and the remaining 800b of the control packet 800 is extracted. The control packet 800 is output after the part 800a of the previously transmitted control packet 800 and the rest 800b are combined to restore the control packet 800.

  As described above, in the radio controller of the base station, while the IQ data packet is being transmitted, the path through which the IQ data packet is transmitted in the switch connecting the IQ data generation unit and the CPRI function unit has priority. Set to root. While the priority route is set, transmission of other packets is stopped. As a result, this base station can prevent congestion during IQ data transmission in the IQ data transmission path, and can reliably store IQ data at the corresponding position of the CPRI frame. Therefore, this base station can make the IQ data reach the radio apparatus by the transmission timing of the radio signal including the IQ data.

  According to the modification, the switch 43 may transfer the received priority route setting request packet to the IQ data generation unit 41 connected to the input port specified by the priority route setting request packet. Then, the IQ data generating unit 41 may generate an IQ data packet upon receiving the priority route setting request packet and send the IQ data packet to the switch 43. In this case, the request packet generation unit 435 and the transmission packet selection unit 436 may be omitted. Therefore, the configuration of the switch 43 is simplified.

  According to another modification, the IQ data generation unit 41 may determine the timing for generating and sending the IQ data packet. In this case, for example, the same clock signal may be supplied to the IQ data generation unit 41 and the CPRI function unit 42 so that the IQ data generation unit 41 is synchronized with the CPRI function unit 42. The IQ data generation unit 41 stores in advance the time required from IQ data packet generation to IQ data storage in the CPRI frame. Then, the IQ data generation unit 41 may start the generation of the IQ data packet when the required timing is earlier than the timing at which the CPRI frame is transmitted to the RE 2. In this case, a priority route setting request packet may be transmitted from the IQ data generation unit 41 to the switch 43 immediately before generation of an IQ data packet is started. In this case, a packet analysis unit 434 is provided between the selector 431 and the IQ data generation unit 41 at the input port connected to the IQ data generation unit 41. Then, the packet analysis unit 434 may determine whether the packet received from the IQ data generation unit 41 is a priority route setting request packet.

  According to still another modification, the switch 43 may be synchronized with the IQ data generation unit 41 and the CPRI function unit 42 in advance. The switch controller 440 of the switch 43 may store in advance the time required from the generation of the IQ data packet to the storage of the IQ data in the CPRI frame. Then, the switch control unit 440 sets a priority route for the route through which the IQ data packet is transmitted, as in the above-described embodiment, when the CPRI frame is sent to the RE 2 by the required time. May be.

  According to another modification, whether the error check unit 423 of the CPRI function unit 42 is a control packet in which transmission is interrupted is the same as the error check unit 437 provided in the output port # 3 of the switch 43. In addition, processing related to restoration of the interrupted control packet may be executed. In this case, the error check unit 437 only performs a process of switching the output destination of the packet received from the switch body 441 between the buffer 438 and the selector 439 depending on whether or not a priority route is set. Good.

  According to yet another modification, the selector 439 may interrupt reading of the control packet from the buffer 438 when the priority route is set. Similarly to the transmission unit 433, the selector 439 may output the control packet that has been read halfway, after giving an interruption signal. Further, the selector 439 may read the remaining part of the control signal from the buffer 438 after the priority route setting is cancelled, and output the remaining part with an interruption signal. In this case, the error check unit 423 of the CPRI function unit 42 determines whether or not the control packet has been interrupted and determines whether the interrupted packet has been interrupted in the same manner as the error check unit 437 provided at the output port of the switch 43. Processing related to restoration may be executed. Then, the error check unit 423 may store a part of the control packet whose transmission is interrupted in the buffer 424. Alternatively, a buffer for storing a part of the control packet whose transmission is interrupted may be provided in the CPRI function unit 42 separately from the buffer 424.

  According to still another modified example, the request packet generation unit 435, the transmission packet selection unit 436, and the error check unit 437 are connected to each output port so that both the IQ data generation unit 41 and the CPRI function unit 42 can be connected. All of the buffer 438 and the selector 439 may be provided. Similarly, each input port may be provided with all of the selector 431, the buffer 432, the transmission unit 433, and the packet analysis unit 434 so that any of the IQ data generation unit 41 and the CPRI function unit 42 can be connected. .

  According to still another modification, the IQ data generation unit and the control signal generation unit may be formed integrally (hereinafter, the IQ data generation unit and the control signal generation unit are formed integrally. For the sake of convenience). In this case, the data generation unit generates not only the IQ data packet but also a control packet as necessary. Therefore, the selector provided in the input port of the switch connected to the data generation unit may dynamically change the output destination of the packet received from the data generation unit. That is, if the input port connected to the data generation unit is not set to the priority route, the selector 431 outputs the packet received from the data generation unit to the buffer 432. On the other hand, when the input port connected to the data generation unit is set as the priority route, the selector 431 directly outputs the packet received from the data generation unit to the transmission unit 433. Thereby, even when the data generation unit connected to the input port generates not only the IQ data packet but also other packets, the switch can appropriately set the priority route.

  All examples and specific terms listed herein are intended for instructional purposes to help the reader understand the concepts contributed by the inventor to the present invention and the promotion of the technology. It should be construed that it is not limited to the construction of any example herein, such specific examples and conditions, with respect to showing the superiority and inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made thereto without departing from the spirit and scope of the present invention.

1 Base station 2 Radio equipment (RE)
3 Radio control equipment (REC)
DESCRIPTION OF SYMBOLS 4 Optical fiber cable 21 Antenna 22 Wireless processing part 31 Wired interface part 32 Memory | storage part 33 Control part 40 Control signal generation part 41 IQ data generation part 42 CPRI function part 43 Switch 421 Timing determination part 422 Packet generation part 423 Error check part 424 Buffer 425 Frame generation unit 431 Selector 432 Buffer 433 Transmission unit 434 Packet analysis unit 435 Request packet generation unit 436 Transmission packet selection unit 437 Error check unit 438 Buffer 439 Selector 440 Switch control unit 441 Switch body

Claims (9)

A communication device comprising: a wireless control device that generates a transmission signal; and a wireless device that is connected to the wireless control device and transmits a wireless signal including the transmission signal,
The wireless control device
A signal generator for generating the transmission signal;
A transmission control unit that transmits the transmission signal to the wireless device in accordance with a transmission timing at which the wireless device transmits the wireless signal including the transmission signal;
Transmission of the transmission signal in a first route connecting the signal generation unit and the transmission control unit and connecting the signal generation unit and the transmission control unit according to the transmission timing is performed in another route. With priority over the switch,
A communication device.   The switch is from a time required until the radio signal is generated after the transmission signal is output from the signal generation unit before the transmission timing until the transmission signal passes through the switch. The communication apparatus according to claim 1, wherein transmission of a signal in the other route is stopped.   The transmission control unit instructs the switch to prioritize transmission of the transmission signal in the first route over transmission of the signal in the other route according to the transmission timing. Or the communication apparatus of 2.   When the switch is instructed to prioritize the transmission of the transmission signal in the first route over the transmission of the signal in the other route, the switch generates the transmission signal to the signal generation unit. The communication device according to claim 3, wherein the communication device instructs to start the output. The switch includes a selector in each of a first input port to which the signal generation unit is connected and a second input port to which a second signal generation unit that generates a signal transmitted through the other route is connected. And a buffer and a sending unit,
In the first input port, the selector outputs the transmission signal received from the signal generation unit to the transmission unit without passing through the buffer, and the transmission unit outputs the transmission signal to the first input port. Type in the port
In the second input port, the selector stores the signal received from the second signal generation unit in the buffer, and the transmission unit transmits the transmission signal in the first route to the other While prioritizing the transmission of signals in the route is not set, the signal stored in the buffer is read out and input to the second input port;
The communication apparatus as described in any one of Claims 1-4.   In the second input port, the transmission unit reads the signal from the buffer and inputs the signal to the second input port, and the transmission of the transmission signal in the first route is the other input port. When priority is given to signal transmission in the route, the reading of the signal from the buffer is interrupted, and a first interruption signal is added to the portion of the signal read up to the interruption. When the input to the second input port is finished and the transmission of the transmission signal in the first route is prioritized over the transmission of the signal in the other route, the remaining portion of the signal is read from the buffer 6. The communication apparatus according to claim 5, wherein a second interruption signal is added to the remaining portion and input to the second input port.   The switch determines whether the first interruption signal or the second interruption signal is attached to a signal output from the output port at an output port connected to the transmission control unit. The communication apparatus according to claim 6, further comprising an interruption detection unit that detects the part of the signal and the remaining part, and combines and outputs the detected part and the remaining part.   The first interruption signal is a value obtained by converting an error detection code calculated from the part of the signal according to a predetermined conversion rule, and the second interruption signal is obtained from the remaining part of the signal. 8. The communication apparatus according to claim 6, wherein the calculated error detection code is a value obtained by converting according to the predetermined conversion rule. A transmission control method in a communication apparatus comprising: a radio control apparatus that generates a transmission signal; and a radio apparatus that is connected to the radio control apparatus and transmits a radio signal including the transmission signal,
In the wireless control device,
For a switch that connects a signal generation unit that generates the transmission signal and a transmission control unit that transmits the transmission signal to the wireless device according to the transmission timing transmitted by the wireless device, the signal according to the transmission timing Setting that the transmission of the transmission signal in the first route connecting the generation unit and the transmission control unit has priority over the transmission of the signal in the other route;
After the setting, the transmission signal is transmitted from the signal generation unit to the transmission control unit via the first route.
A transmission control method.

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