JP2017511654A - システムオンチップデバイスの無効なデバッグ機能を再有効化するためのリモート局および方法 - Google Patents

システムオンチップデバイスの無効なデバッグ機能を再有効化するためのリモート局および方法 Download PDF

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JP2017511654A
JP2017511654A JP2016559869A JP2016559869A JP2017511654A JP 2017511654 A JP2017511654 A JP 2017511654A JP 2016559869 A JP2016559869 A JP 2016559869A JP 2016559869 A JP2016559869 A JP 2016559869A JP 2017511654 A JP2017511654 A JP 2017511654A
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Prior art keywords
debug
token
integrated circuit
revalidation
party
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Pending
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JP2016559869A
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English (en)
Japanese (ja)
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JP2017511654A5 (enExample
Inventor
イヴァン・ヒュー・マクリーン
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クアルコム，インコーポレイテッド
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Publication of JP2017511654A publication Critical patent/JP2017511654A/ja
Publication of JP2017511654A5 publication Critical patent/JP2017511654A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G06F21/33—User authentication using certificates
    • G06F21/335—User authentication using certificates for accessing specific resources, e.g. using Kerberos tickets
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/08—Network architectures or network communication protocols for network security for authentication of entities
    • H04L63/0807—Network architectures or network communication protocols for network security for authentication of entities using tickets, e.g. Kerberos
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3263—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials involving certificates, e.g. public key certificate [PKC] or attribute certificate [AC]; Public key infrastructure [PKI] arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Storage Device Security (AREA)
JP2016559869A 2014-04-04 2015-03-31 システムオンチップデバイスの無効なデバッグ機能を再有効化するためのリモート局および方法 Pending JP2017511654A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/245,661 2014-04-04
US14/245,661 US9942049B2 (en) 2014-04-04 2014-04-04 Remote station and method for re-enabling a disabled debug capability in a system-on-a-chip device
PCT/US2015/023518 WO2015153562A1 (en) 2014-04-04 2015-03-31 A remote station and method for re-enabling a disabled debug capability in a system-on-a-chip device

Publications (2)

Publication Number Publication Date
JP2017511654A true JP2017511654A (ja) 2017-04-20
JP2017511654A5 JP2017511654A5 (enExample) 2018-04-26

Family

ID=52823889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016559869A Pending JP2017511654A (ja) 2014-04-04 2015-03-31 システムオンチップデバイスの無効なデバッグ機能を再有効化するためのリモート局および方法

Country Status (6)

Country Link
US (1) US9942049B2 (enExample)
EP (1) EP3127031A1 (enExample)
JP (1) JP2017511654A (enExample)
KR (1) KR20160140666A (enExample)
CN (1) CN106133737A (enExample)
WO (1) WO2015153562A1 (enExample)

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US10091079B2 (en) * 2015-05-06 2018-10-02 Marvell World Trade Ltd. Apparatus and method for remotely testing memory-mapped devices of a system-on-chip via an ethernet interface
US9995789B2 (en) 2015-12-22 2018-06-12 Intel IP Corporation Secure remote debugging of SoCs
CN107734569B (zh) * 2016-08-11 2021-02-05 华为技术有限公司 通信方法和装置
CN109818742B (zh) * 2017-11-22 2023-04-25 中兴通讯股份有限公司 一种设备调试方法、装置及存储介质
CN111813614B (zh) * 2020-09-03 2020-12-15 湖北芯擎科技有限公司 调试处理方法、装置与调试处理系统
US11665002B2 (en) 2020-12-11 2023-05-30 International Business Machines Corporation Authenticated elevated access request
WO2022132184A1 (en) 2020-12-20 2022-06-23 Intel Corporation System, method and apparatus for total storage encryption
US20210319138A1 (en) * 2021-06-25 2021-10-14 Intel Corporation Utilizing logic and serial number to provide persistent unique platform secret for generation of soc root keys
US11874776B2 (en) 2021-06-25 2024-01-16 Intel Corporation Cryptographic protection of memory attached over interconnects
US12455701B2 (en) 2021-07-27 2025-10-28 Intel Corporation Scalable access control checking for cross-address-space data movement
US12487762B2 (en) 2022-05-10 2025-12-02 Intel Corporation Flexible provisioning of coherent memory address decoders in hardware
KR20250102999A (ko) * 2023-12-28 2025-07-07 (주)애크멕스알마즈 전력반도체 SoC 및 전력반도체 SoC의 운영방법
US12323503B1 (en) * 2024-10-10 2025-06-03 Moengage Inc. Method for transmitting notification to target device via hierarchy of communication channels

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WO2005091143A1 (ja) * 2004-03-24 2005-09-29 Matsushita Electric Industrial Co., Ltd. 情報処理装置及びプログラムファイル生成装置
JP2007502462A (ja) * 2003-08-11 2007-02-08 フリースケール セミコンダクター インコーポレイテッド デバッグ回路のセキュリティを確保する方法及び装置
US20070039054A1 (en) * 2005-08-01 2007-02-15 Intel Corporation Computing system feature activation mechanism
WO2008117340A1 (ja) * 2007-03-27 2008-10-02 Fujitsu Limited デバッグ対象機器、該認証プログラム、及びデバッグ認証方法
US20090165111A1 (en) * 2007-12-21 2009-06-25 General Instrument Corporation Method and apparatus for secure management of debugging processes within communication devices
US20140044265A1 (en) * 2012-08-10 2014-02-13 Cryptography Research, Inc. Secure feature and key management in integrated circuits

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US20070094507A1 (en) 2005-10-21 2007-04-26 Rush Frederick A Method and system for securing a wireless communication apparatus
US7921303B2 (en) 2005-11-18 2011-04-05 Qualcomm Incorporated Mobile security system and method
WO2007123896A2 (en) 2006-04-18 2007-11-01 The Trustees Of The University Of Pennsylvania Mutated acvr1 for diagnosis and treatment of fibrodyplasia ossificans progressiva (fop)
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US8060748B2 (en) * 2007-12-21 2011-11-15 Telefonaktiebolaget Lm Ericsson (Publ) Secure end-of-life handling of electronic devices
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Publication number Priority date Publication date Assignee Title
JP2007502462A (ja) * 2003-08-11 2007-02-08 フリースケール セミコンダクター インコーポレイテッド デバッグ回路のセキュリティを確保する方法及び装置
WO2005091143A1 (ja) * 2004-03-24 2005-09-29 Matsushita Electric Industrial Co., Ltd. 情報処理装置及びプログラムファイル生成装置
US20070039054A1 (en) * 2005-08-01 2007-02-15 Intel Corporation Computing system feature activation mechanism
WO2008117340A1 (ja) * 2007-03-27 2008-10-02 Fujitsu Limited デバッグ対象機器、該認証プログラム、及びデバッグ認証方法
US20090165111A1 (en) * 2007-12-21 2009-06-25 General Instrument Corporation Method and apparatus for secure management of debugging processes within communication devices
US20140044265A1 (en) * 2012-08-10 2014-02-13 Cryptography Research, Inc. Secure feature and key management in integrated circuits

Also Published As

Publication number Publication date
WO2015153562A1 (en) 2015-10-08
CN106133737A (zh) 2016-11-16
US9942049B2 (en) 2018-04-10
US20150288526A1 (en) 2015-10-08
KR20160140666A (ko) 2016-12-07
EP3127031A1 (en) 2017-02-08

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