JP2017219703A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of actualizing display characteristics of high quality for a liquid crystal display device having its frame made narrow.SOLUTION: A liquid crystal display device comprises a plurality of gate connection wirings which electrically connect a plurality of gate wirings to a gate wiring drive part. The gate connection wirings include a plurality of first partial gate connection wirings arranged apart in a frame region of a first substrate, and a second partial gate connection wiring which is arranged on a black matrix of a second substrate, and electrically connects the plurality of first partial gate connection wirings through respective conductive members.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a liquid crystal display device including a first substrate and a second substrate disposed to face the first substrate.

  In general, an active matrix liquid crystal display device includes a liquid crystal panel including two insulating glass substrates facing each other. A TFT substrate, which is one glass substrate of the liquid crystal panel, is provided with a grid-like wiring composed of a gate wiring and a source wiring which are insulated from each other, and a TFT (thin film transistor) is provided at each intersection of the gate wiring and the source wiring. ) Is arranged. The TFT includes a gate electrode connected to the gate wiring, a source electrode connected to the source wiring, a drain electrode, and the like. The drain electrode is connected to pixel electrodes arranged in a matrix on the TFT substrate in order to display an image. In the case of a TN (Twisted Nematic) type liquid crystal panel, a common electrode for applying a voltage to a pixel electrode via a liquid crystal layer is provided on a CF (Color Filter) substrate which is the other glass substrate of the liquid crystal panel. It is arranged. In the case of an IPS (In Plane Switching) (registered trademark) type liquid crystal panel, a common electrode for applying a voltage to the liquid crystal layer is disposed on the TFT substrate instead of the CF substrate.

  When the gate electrode of each TFT receives a scanning signal for turning on the TFT from the gate wiring, the potential of the video signal is applied to the common electrode based on the video signal received by the source electrode of the TFT from the source wiring. A voltage that is a difference from the potential is applied to the liquid crystal layer. As a result, the liquid crystal is driven in units of pixels, and a desired image is displayed on the screen.

  In the active matrix liquid crystal display device configured as described above, in recent years, a narrow frame has been demanded. On the other hand, the number of gate wirings is increasing in number, for example, on the scale of 1000 with the increase in resolution of liquid crystal display devices. For this reason, the width of the frame area outside the display area in which the gate connection wiring for supplying the scanning signal from the gate IC (Integrated Circuit) to the gate wiring is arranged is enlarged, and it is difficult to realize a narrow frame. It has become.

  As a technique for solving this problem, Patent Document 1 proposes a technique in which a gate connection wiring is composed of a wiring disposed on a TFT substrate and a wiring disposed on a CF substrate.

JP2015-55712A

  However, in the technique of Patent Document 1, a black matrix (hereinafter sometimes referred to as “BM”) is used as a wiring disposed on the CF substrate among the gate connection wirings. In such a configuration, in order to electrically isolate each wiring disposed on the CF substrate, it is necessary to provide a cut such as a slit in the black matrix, and there is a problem that light leaks from the cut.

  Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a technology capable of realizing high-quality display characteristics in a narrow frame liquid crystal display device.

  A liquid crystal display device according to the present invention includes a first substrate in which a display area and a frame area adjacent to the display area are defined, and a plurality of source wirings arranged in the display area and intersecting each other in plan view And a plurality of gate wirings, a plurality of thin film transistors disposed in the display region and connected to the plurality of source wirings and the plurality of gate wirings, and the frame region on one end side of the plurality of source wirings A source line driving unit capable of supplying a video signal to the plurality of source lines disposed in the one end frame region, and a scanning signal to the plurality of gate lines disposed in the one end frame region. Possible gate wiring driving units, a plurality of source connection wirings arranged in the frame region and electrically connecting the plurality of source wirings and the source wiring driving unit, and the plurality of gate wirings. And a plurality of gate connection wirings that electrically connect the gate wiring driving unit and the first substrate, and an insulating black matrix is disposed on a surface facing the first substrate. A plurality of first partial gate connection wirings spaced apart from each other in the frame region of the first substrate and the black matrix of the second substrate. And a second partial gate connection wiring that electrically connects the plurality of first partial gate connection wirings through each conductive member.

  According to the present invention, the gate connection wiring is disposed on the plurality of first partial gate connection wirings spaced apart in the frame region of the first substrate and the black matrix of the second substrate, and each conductive member. And a second partial gate connection wiring that electrically connects the plurality of first partial gate connection wirings. According to such a configuration, high quality display characteristics can be realized in a liquid crystal display device with a narrow frame.

4 is a plan view showing a schematic configuration of a TFT substrate in the liquid crystal panel according to Embodiment 1. FIG. 4 is a plan view showing a schematic configuration of a CF substrate in the liquid crystal panel according to Embodiment 1. FIG. 1 is a cross-sectional view showing a schematic configuration of a liquid crystal panel according to Embodiment 1. FIG. 3 is an enlarged plan view showing a schematic configuration of a CF substrate according to Embodiment 1. FIG. 6 is a plan view showing an example of an output sequence of gate ICs according to the first embodiment. FIG. 5 is a plan view showing a schematic configuration of a TFT substrate in a liquid crystal panel according to Embodiment 2. FIG. 6 is a plan view showing a schematic configuration of a CF substrate in a liquid crystal panel according to Embodiment 2. FIG. 5 is a cross-sectional view illustrating a schematic configuration of a liquid crystal panel according to Embodiment 2. FIG. FIG. 10 is a plan view illustrating an example of an output sequence of gate ICs according to the second embodiment. 5 is a plan view showing a schematic configuration of a TFT substrate in a liquid crystal panel according to Embodiment 3. FIG. 6 is a plan view showing a schematic configuration of a CF substrate in a liquid crystal panel according to Embodiment 3. FIG. 6 is a cross-sectional view illustrating an example of a schematic configuration of a liquid crystal panel according to Embodiment 3. FIG. 12 is a cross-sectional view showing another example of the schematic configuration of the liquid crystal panel according to Embodiment 3. FIG. 6 is a plan view showing a schematic configuration of a TFT substrate in a liquid crystal panel according to Embodiment 4. FIG. 6 is a plan view showing a schematic configuration of a CF substrate in a liquid crystal panel according to Embodiment 4. FIG. 10 is a plan view showing a schematic configuration of a TFT substrate in a liquid crystal panel according to Embodiment 5. FIG. 10 is a plan view showing a schematic configuration of a CF substrate in a liquid crystal panel according to Embodiment 5. FIG. FIG. 10 is a cross-sectional view illustrating a schematic configuration of a liquid crystal panel according to Embodiment 5.

<Embodiment 1>
1 and 2 are plan views showing schematic configurations of a TFT substrate and a CF substrate that constitute a liquid crystal panel included in the liquid crystal display device according to Embodiment 1 of the present invention. FIG. 3 is a cross-sectional view showing a schematic configuration of a liquid crystal panel along a gate connection wiring described later.

  As shown in FIG. 3, the CF substrate 2 in FIG. 2 is disposed to face the TFT substrate 1 in FIG. 1 and 2 are both plan views as viewed from the upper side of FIG. 3, that is, from the side opposite to the TFT substrate 1 with respect to the CF substrate 2. Originally, the wiring such as the opaque film and the partial gate connection wiring 64 is sequentially arranged on the other side with respect to the CF substrate 2 in FIG. 2, so that the wiring cannot be seen by the opaque film. However, in FIG. 2, for convenience of explanation, the schematic configuration of the wiring is illustrated in a manner as if the opaque film is transparent. This also applies to plan views showing the CF substrate 2 in FIG.

  The TFT substrate 1 and the CF substrate 2 are transparent insulating substrates, and for example, a glass substrate or the like is applied. The first substrate according to the present invention can be called a TFT substrate 1, and the second substrate according to the present invention can be called a CF substrate 2. The TFT substrate 1 and the CF substrate 2 are not limited to glass substrates, and may be glass substrates on which films are formed, for example.

  Next, the configuration on the TFT substrate 1 side will be described in detail. In the TFT substrate 1, a display area 3 and a frame area adjacent to the display area 3 are defined. In the example of FIG. 1, frame areas 41, 42, 43, and 44 are applied as frame areas adjacent to the display area 3. However, the frame area adjacent to the display area 3 is not limited to this. For example, only the frame areas 41 and 42 may be applied. In the following description, the constituent elements are arranged in the display area when the constituent elements are arranged directly on the display area 3 or the constituent elements are indirectly arranged on the display area 3. It is meant to be arranged. Similarly, the component being disposed in the frame region means that the component is disposed directly on the frame region or that the component is indirectly disposed on the frame region. Shall mean.

  In the display area 3, a plurality of source lines 5 and a plurality of gate lines 6 are disposed so as to intersect with each other in plan view. The plurality of source wirings 5 and the plurality of gate wirings 6 are electrically insulated by an insulating film (not shown) disposed between them.

  In the display area 3, a plurality of TFTs 71 connected to the plurality of source lines 5 and the plurality of gate lines 6 are disposed. For example, the plurality of TFTs 71 are disposed corresponding to the plurality of intersections of the plurality of source lines 5 and the plurality of gate lines 6. The drain electrodes of the plurality of TFTs 71 are connected to a plurality of pixel electrodes (not shown here) arranged in a matrix in the display region 3.

  Note that the above-described frame region on one end side of the plurality of source wirings 5 may be referred to as a one-end frame region 41.

  A source IC 500 and a gate IC 600 are disposed in the one-end frame region 41. The source IC 500 can supply driving video signals to the plurality of source lines 5. The gate IC 600 can supply scanning signals to the plurality of gate wirings 6. The source line driver according to the present invention can be called a source IC 500, and the gate line driver according to the present invention can be called a gate IC 600.

  In one end frame region 41 of the frame region, a plurality of source connection wirings 51 for electrically connecting the plurality of source wirings 5 and the source IC 500 are disposed. The source connection wiring 51 may be formed by extending the source wiring 5, or may be formed by another conductive film formed on the TFT substrate 1. For example, the source connection wiring 51 may be formed of a conductive film that forms at least one of the source wiring 5 and the gate wiring 6. In this case, the source connection wiring 51 may be connected in series or in parallel with at least one of the source wiring 5 and the gate wiring 6.

  Note that the liquid crystal display device according to the first embodiment includes a plurality of gate connection lines that electrically connect the plurality of gate lines 6 and the gate IC 600 in the same manner as the plurality of source connection lines 51. However, the plurality of gate connection wirings will be described in detail later.

  Next, the configuration on the CF substrate 2 side will be described in detail. In the following description, it is assumed that the CF substrate 2 also has a display area 3 and a frame area adjacent to the display area 3, as in the TFT substrate 1.

  As shown in FIG. 3, a resin BM 201 made of a black resin for suppressing light leakage is disposed on the surface of the CF substrate 2 that faces the TFT substrate 1. The resin BM 201 is disposed not only in the display area 3 of FIG. 2 but also in the frame area. The insulating black matrix according to the present invention can be referred to as a resin BM201.

  FIG. 4 is an enlarged plan view showing a schematic configuration inside the display region 3 of the CF substrate 2. As shown in FIG. 4, a lattice-shaped resin BM 201 is disposed inside the display region 3, and coloring materials 210, 211, and 212 are periodically disposed in the openings of the resin BM 201. For the color materials 210, 211, and 212, for example, three kinds of resins whose transmitted light has main wavelengths of red (R), green (G), and blue (B) are used. However, the color material is not limited to this. For example, one kind of colorless material may be used, or red (R), yellow (Y), green (G) and blue (B), or white ( Four colors such as W), red (R), green (G), and blue (B) may be used.

  As shown in FIG. 3, the TFT substrate 1 and the CF substrate 2 are bonded together by a sealing material 91 disposed in the frame regions 41 to 44. Although not shown in FIG. 3, the liquid crystal is sealed between the display region 3 of the TFT substrate 1 and the display region 3 of the CF substrate 2 by a sealing material 91.

  Next, the plurality of gate connection wirings that electrically connect the plurality of gate wirings 6 and the gate IC 600 will be described in detail. In the first embodiment, the plurality of gate connection wirings include two types of gate connection wirings. Specifically, the gate connection wiring 61 (hereinafter also referred to as “one substrate gate connection wiring 61”) disposed in the frame region of the TFT substrate 1 without being disposed on the CF substrate 2, and the TFT substrate 1 And a gate connection wiring (hereinafter also referred to as “two-substrate gate connection wiring”) disposed across the CF substrate 2. The two-substrate gate connection wiring includes partial gate connection wirings 62, 63, 64.

  In the example of FIGS. 1 and 2, the single substrate gate connection wiring 61 disposed on the TFT substrate 1 is the gate wiring 6 from G541 to G1080 among the gate wirings 6 from G1 to G1080 having a total number of 1080. That is, one end is connected to half of the gate wirings 6 disposed relatively close to the frame region 41. The one-substrate gate connection wiring 61 may be formed by extending the gate wiring 6 or may be formed by another conductive film formed on the TFT substrate 1. For example, the one-substrate gate connection wiring 61 may be formed of a conductive film that forms at least one of the source wiring 5 and the gate wiring 6.

  On the other hand, the two-substrate gate connection wirings disposed across the TFT substrate 1 and the CF substrate 2 are the gate wirings 6 from G1 to G540, that is, half of the gate wirings disposed relatively far from the one end frame region 41. 6 is connected. As described above, the two-substrate gate connection wiring includes the partial gate connection wirings 62, 63 and 64.

  The partial gate connection wirings 62 and 63 are spaced apart in the frame region of the TFT substrate 1. Among these, the end of the partial gate connection wiring 62 is connected to the gate IC 600, and the end of the partial gate connection wiring 63 is connected to one of the gate wirings 6 from G1 to G540. The plurality of first partial gate connection lines according to the present invention can be referred to as partial gate connection lines 62 and 63. However, the plurality of first partial gate connection wirings is not limited to this, and may include, for example, a wiring that is not connected to either the gate IC 600 or the gate wiring. These partial gate connection wirings 62 and 63 may be formed from a conductive film for forming the gate wiring 6, or may be formed from another conductive film formed on the TFT substrate 1. For example, the partial gate connection wirings 62 and 63 may be formed of a conductive film that forms at least one of the source wiring 5 and the gate wiring 6.

  On the other hand, the partial gate connection wiring 64 is disposed not on the TFT substrate 1 but on the resin BM 201 of the CF substrate 2 as shown in FIG. 2 and 3, the partial gate connection wiring 64 electrically connects the partial gate connection wiring 62 and the partial gate connection wiring 63 via the conductive particles 92a and 92b mixed in the sealing material 91. Connected. The second partial gate connection wiring according to the present invention can be referred to as a partial gate connection wiring 64, and the respective conductive members according to the present invention can be referred to as conductive particles 92a and 92b.

  In the first embodiment, as shown in FIGS. 1 and 2, the conductive particles 92a and 92b are arranged in the frame region. In the first embodiment, as shown in FIGS. 2 and 3, the partial gate connection wiring 64 is disposed to face the one-substrate gate connection wiring 61 connected to the gate wiring 6 in the vicinity of the one end frame region 41. Has been.

  Next, electrical connection between the partial gate connection wirings 62 and 63 and the partial gate connection wiring 64 will be described in detail.

  As shown in FIGS. 1 and 2, a contact 62 a for connecting to a partial gate connection wiring 64 disposed on the CF substrate 2 is connected to one end of the partial gate connection wirings 62 and 63 disposed on the TFT substrate 1. 63a are disposed. As shown in FIG. 3, the contacts 62 a and 63 a are exposed from the insulating film 101 through openings of the insulating film 101 disposed on the partial gate connection wirings 62 and 63. These openings may be covered with a transparent conductive film such as ITO (Indium Tin Oxide) that forms pixel electrodes and the like. Thereby, the connection resistance with the conductive particles 92a and 92b is stabilized.

  As shown in FIG. 1 and FIG. 2, the contacts 64a and 64b are located at both ends of the partial gate connection wiring 64 disposed on the CF substrate 2 in the same manner as the partial gate connection wirings 62 and 63. Are arranged in correspondence with each other. As shown in FIG. 3, the contacts 64 a and 64 b are exposed from the insulating film 202 through the opening of the insulating film 202 disposed on the partial gate connection wiring 64. These openings may be covered with the transparent conductive film when the conductive film 203 is a transparent conductive film such as ITO. Thereby, the connection resistance with the conductive particles 92a and 92b is stabilized.

  The contact 62a is electrically connected to the contact 64a by the conductive particle 92a, and the contact 63a is electrically connected to the contact 64b by the conductive particle 92b. The contacts 62a, 63a, 64a, and 64b are electrically connected when the step of bonding the TFT substrate 1 and the CF substrate 2 is performed in the step of forming the liquid crystal panel. Thus, after the liquid crystal panel bonding step is completed, the gate wirings 6 from G1 to G540 are electrically connected to the gate IC 600 through the partial gate connection wirings 62, 63, 64 and the like.

Now, as shown in FIG. 3, the partial gate connection wiring 64 is disposed on the resin BM 201. Since the resin BM201 is a black opaque layer, it is possible to prevent the partial gate connection wiring 64 from being viewed from the observation direction when operating as a liquid crystal display device. Further, in the first embodiment, since it is not necessary to provide a cut in the resin BM 201, a uniform black frame can be formed in the display area 3 and the frame area, and an uncomfortable appearance can be maintained. The sheet resistance of the resin BM 201 is preferably 1 × 10 ¹¹ Ω / □ or more from the viewpoint of suppressing leakage between the partial gate connection wirings 64.

  As shown in FIG. 3, in the first embodiment, a conductive film 203 is disposed on at least a part of the partial gate connection wiring 64 with an insulating film 202 interposed therebetween. According to such a conductive film 203, the scanning signal applied to the partial gate connection wiring 64 can be prevented from interfering with the liquid crystal in the vicinity of the partial gate connection wiring 64. Can be suppressed. In the first embodiment, at least a part of the partial gate connection wiring 64 is disposed to face the frame region of the TFT substrate 1. However, the present invention is not limited to this. As in the third embodiment, the display area 3 of the TFT substrate 1 may be disposed to face the display area 3.

  FIG. 5 shows an example of the arrangement of the outputs of the gate IC 600 when the total number of the gate wirings 6 is 1080. In this example, outputs from G1 to G540 are arranged from the central part in the longitudinal direction of the gate IC 600 toward one end, and outputs from G541 to G1080 are arranged from the central part to the other end. Yes. By using a gate IC 600 having an output arrangement as shown in FIG. 5, the one-substrate gate connection wiring 61 is connected to the gate wiring 6 relatively close to the gate IC 600, and the two-substrate gate connection wiring is compared with the gate IC 600. It can be connected to the gate wiring 6 that is far away. As a result, crossing between the gate connection wirings can be avoided, and as a result, it is not necessary to use a complicated combination of conductive films, so that the configuration of the liquid crystal panel can be simplified.

<Summary of Embodiment 1>
According to the liquid crystal display device according to the first embodiment as described above, the gate connection wiring for transmitting the scanning signal output from the gate IC 600 to the gate wiring 6 is the partial gate disposed on the CF substrate 2. Connection wiring 64 is included. For this reason, since a wiring area required for the gate connection wiring can be reduced, a frame area such as the frame area 42 can be reduced. The partial gate connection wiring 64 disposed on the CF substrate 2 is disposed on the resin BM 201. Thereby, when operating as a liquid crystal display device, it is possible to prevent the partial gate connection wiring 64 from being viewed from the observation direction. In addition, since it is not necessary to provide a cut in the resin BM 201, a uniform black frame can be formed in the display area 3 and the frame area, and an uncomfortable appearance can be maintained. As described above, according to the first embodiment, high quality display characteristics can be realized in a liquid crystal display device with a narrow frame.

  In the first embodiment, the conductive film 203 is disposed above the partial gate connection wiring 64. Accordingly, it is possible to suppress the scanning signal applied to the partial gate connection wiring 64 from interfering with the liquid crystal in the vicinity of the partial gate connection wiring 64 during the display operation of the liquid crystal panel. Abnormalities can be suppressed.

  In the above description, the ratio between the number of gate wirings 6 electrically connected to one substrate gate connection wiring 61 and the number of gate wirings 6 electrically connected to two substrate gate connection wirings is 1: 1 However, this ratio is not limited to this, and other ratios may be used as long as the effect of minimizing the frame area can be obtained.

  Further, according to the first embodiment, the gate IC 600 is disposed in the end region of the one-end frame region 41, and the gate connection wiring is disposed on the end side where the gate IC 600 is disposed. It was. However, the present invention is not limited to this, and the gate IC 600 is arranged in the central region of the one-end frame region 41, and the gate connection wiring is divided into right and left from the central portion as in the third embodiment to be described later. Even if it is the structure arrange | positioned in this way, the effect similar to the above-mentioned can be acquired.

<Embodiment 2>
6 and 7 are plan views showing a schematic configuration of a TFT substrate and a CF substrate constituting a liquid crystal panel included in the liquid crystal display device according to Embodiment 2 of the present invention. FIG. 8 is a cross-sectional view showing a schematic configuration of the liquid crystal panel along the gate connection wiring. Hereinafter, among the constituent elements described in the second embodiment, the same or similar constituent elements as those in the first embodiment are denoted by the same reference numerals, and different constituent elements will be mainly described.

  In the first embodiment, as shown in FIG. 3, the partial gate connection wiring 63 is disposed on the frame region of the TFT substrate 1. On the other hand, in the second embodiment, as shown in FIG. 8, the partial gate connection wiring 63 is disposed on the frame region of the TFT substrate 1 via the insulating film 101. That is, the partial gate connection wiring 63 is disposed above the frame region of the TFT substrate 1. Insulating films 101 and 102 are disposed on the partial gate connection wiring 62, and an insulating film 102 is disposed on the partial gate connection wiring 63.

  The contact 62 a is exposed from the insulating films 101 and 102 through the openings of the insulating films 101 and 102 disposed on the partial gate connection wiring 62. The contact 63 a is exposed from the insulating film 102 through an opening of the insulating film 102 disposed on the partial gate connection wiring 63. These openings may be covered with a transparent conductive film such as ITO forming a pixel electrode or the like. Thereby, the connection resistance with the conductive particles 92a and 92b is stabilized.

  Similarly to the first embodiment, the contact 62a is electrically connected to the contact 64a by the conductive particles 92a mixed in the sealing material 91, and the contact 63a is conductive particles mixed in the sealing material 91. 92b is electrically connected to contact 64b.

  With the above configuration, as shown in FIG. 6, even if the partial gate connection wiring 63 and the one substrate gate connection wiring 61 intersect each other in plan view, the partial gate connection wiring 63 and the one substrate gate connection wiring 61 are connected. The insulating film 101 can be electrically insulated.

  FIG. 9 shows an example of the arrangement of the outputs of the gate IC 600 when the total number of the gate wirings 6 is 1080. In this example, outputs of G1 and G1080 are arranged at one end of the gate IC 600 in the longitudinal direction, and outputs of G2 and G1079 are arranged at the other end of the gate IC 600 in the longitudinal direction. G3 and G1078 are arranged at one end portion in the longitudinal direction of the gate IC 600 and closer to the center portion than the outputs from G1 and G1080, and at the other end portion in the longitudinal direction of the gate IC 600, the outputs from the G2 and G1079 are centered. G4 and G1077 are disposed on the part side.

  By using the gate IC 600 having the output arrangement as shown in FIG. 9, the gate wiring 6 connected to the one-substrate gate connection wiring 61 and the gate wiring 6 connected to the two-substrate gate connection wiring are displayed in the display region. 3 can be alternately arranged along the arrangement direction. Here, generally, a difference in the connection resistance from the gate IC 600 to the gate wiring 6 occurs due to a difference in the path length of the gate connection wiring, and a difference in the scanning signal due to the difference in the connection resistance results in a dull operation signal. Differences in display performance occur due to differences in On the other hand, according to the liquid crystal display device according to the second embodiment as described above, the difference in display performance can be distributed alternately in the same manner as the arrangement period of the gate wirings 6. 3 can be made uniform.

<Summary of Embodiment 2>
According to the liquid crystal display device according to the second embodiment as described above, the partial gate connection wiring 63 and the one-substrate gate connection wiring 61 are arranged by arranging the partial gate connection wiring 63 above the frame region of the TFT substrate 1. They can be crossed in a plan view while being electrically insulated from each other. For this reason, when the gate IC 600 having the output arrangement as shown in FIG. 9 is used, the steep display characteristic difference in the display region 3 can be made uniform, so that a high-quality liquid crystal display device can be obtained. Can be provided.

<Embodiment 3>
10 and 11 are plan views showing a schematic configuration of a TFT substrate and a CF substrate constituting a liquid crystal panel included in the liquid crystal display device according to Embodiment 3 of the present invention. 12 and 13 are cross-sectional views showing an example and another example of the schematic configuration of the liquid crystal panel along the line AA ′ in FIG. 11. 12 is a cross-sectional view when the liquid crystal panel according to the third embodiment is a TN type liquid crystal panel, and FIG. 13 is a sectional view when the liquid crystal panel according to the third embodiment is an IPS (registered trademark) type liquid crystal. It is sectional drawing in the case of being a panel. Hereinafter, among the constituent elements described in the third embodiment, constituent elements that are the same as or similar to those in the first embodiment are denoted by the same reference numerals, and different constituent elements are mainly described.

  In the first embodiment, as shown in FIGS. 2 and 3, at least a part of the partial gate connection wiring 64 covered with the conductive film 203 is disposed to face the frame region of the TFT substrate 1. On the other hand, in the third embodiment, as shown in FIGS. 11 to 13, at least a part of the partial gate connection wiring 64 covered with the conductive film 203 faces the display region 3 of the TFT substrate 1. It is arranged. As a result, the partial gate connection wiring 64 is disposed so as to pass through the display region 3.

  With the above configuration, as shown in FIG. 10, the gate IC 600 is disposed in the central region of the one-end frame region 41, and the plurality of gate connection wirings are one-substrate gate connection wirings in FIG. 1. 61 is not included, but a two-substrate gate connection wiring is included.

  Hereinafter, a configuration when the liquid crystal panel is a TN liquid crystal panel will be described with reference to FIG.

  The partial gate connection wiring 64 disposed on the CF substrate 2 is disposed on the lattice-shaped resin BM 201 disposed in the display region 3. Since the resin BM201 is a black opaque layer, when operating as a liquid crystal display device, the partial gate connection wiring 64 can be prevented from being visually recognized from the observation direction, and display without a sense of incongruity can be performed. it can.

  In the configuration of FIG. 12, the conductive film 203 is disposed on the color materials 210 to 212 with the insulating film 202 interposed therebetween. The conductive film 203 is used as a common electrode for applying a voltage to the pixel electrode 72 on the TFT substrate 1 through the liquid crystal layer 8. Note that the conductive film 203 used as a common electrode is disposed in a planar shape in the display region 3. Therefore, the conductive film 203 also functions as a shield that suppresses interference of the liquid crystal layer 8 with the liquid crystal due to the scanning signal of the partial gate connection wiring 64.

  In the configuration of FIG. 12, an insulating film 202 is provided between the color materials 210 to 212 and the conductive film 203. However, the present invention is not limited to this, and when the color material 210 to 212 can sufficiently ensure the insulation performance between the partial gate connection wiring 64 and the conductive film 203, the insulation film 202 is omitted and the color material is omitted. 210 to 212 can be used as the insulating film. Further, the insulating film 202 may be disposed between the partial gate connection wiring 64 and each of the color materials 210 to 212 instead of being disposed at the above-described position.

  Next, a configuration when the liquid crystal panel is an IPS (registered trademark) liquid crystal panel will be described with reference to FIG. In such a liquid crystal panel, a common electrode 73 that applies a voltage to the pixel electrode 72 is disposed on the TFT substrate 1.

  The partial gate connection wiring 64 disposed on the CF substrate 2 is disposed on the lattice-shaped resin BM 201 disposed in the display region 3. Since the resin BM201 is a black opaque layer, when operating as a liquid crystal display device, the partial gate connection wiring 64 can be prevented from being visually recognized from the observation direction, and display without a sense of incongruity can be performed. it can.

  In the configuration of FIG. 13, a conductive film 203 is disposed on the color materials 210 to 212 with an insulating film 202 interposed therebetween. According to such a conductive film 203, it is possible to prevent the scanning signal applied to the partial gate connection wiring 64 from interfering with the liquid crystal of the liquid crystal layer 8 in the vicinity of the partial gate connection wiring 64. Display abnormality can be suppressed. Note that, in order to avoid the non-uniform operation of the liquid crystal due to the presence or absence of the conductive film 203, the upper part of the portion where the partial gate connection wiring 64 is not provided so that the conductive film 203 is provided uniformly in the display region 3. It is also preferable to be disposed in the case. As such a pattern of the conductive film 203, for example, a lattice pattern similar to the resin BM201 is effective. In this case, the conductive film 203 is disposed between the pixel electrodes 72 in plan view.

  In the configuration of FIG. 13, an insulating film 202 is disposed between the color materials 210 to 212 and the conductive film 203. However, the present invention is not limited to this, and when the color material 210 to 212 can sufficiently ensure the insulation performance between the partial gate connection wiring 64 and the conductive film 203, the insulation film 202 is omitted and the color material is omitted. 210 to 212 can be used as the insulating film. Further, the insulating film 202 may be disposed between the partial gate connection wiring 64 and each of the color materials 210 to 212 instead of being disposed at the above-described position.

<Summary of Embodiment 3>
According to the liquid crystal display device according to the third embodiment as described above, at least a part of the partial gate connection wiring 64 covered with the conductive film 203 is disposed to face the display region 3 of the TFT substrate 1. The Thus, as in the first embodiment, the wiring area necessary for the gate connection wiring can be reduced, so that the frame area such as the frame area 42 can be reduced. Further, since all the outputs of the gate IC 600 can be uniformly connected to the gate wiring 6 via the partial gate connection wiring 64 disposed on the CF substrate 2, a liquid crystal display device having high quality display characteristics can be obtained. It becomes possible to provide.

  In the third embodiment, in the liquid crystal display device including the horizontal electric field type liquid crystal panel as shown in FIG. 13, the conductive film 203 is disposed between the pixel electrodes 72 in a plan view. According to such a configuration, the conductive film 203 for avoiding uneven operation of the liquid crystal can be reduced as much as possible.

  In the above description, the liquid crystal panel is an IPS (registered trademark) type liquid crystal panel. However, the liquid crystal panel is not limited to this. For example, a horizontal electric field type liquid crystal panel such as an FFS (fringe field switching) type liquid crystal panel is used. If it is.

<Embodiment 4>
14 and 15 are plan views showing schematic configurations of a TFT substrate and a CF substrate that constitute a liquid crystal panel included in the liquid crystal display device according to Embodiment 4 of the present invention. Hereinafter, among the constituent elements described in the fourth embodiment, constituent elements that are the same as or similar to those in the third embodiment are denoted by the same reference numerals, and different constituent elements are mainly described.

  As shown in FIGS. 14 and 15, the outline shape of the TFT substrate 1, the CF substrate 2, and the display region 3 in a plan view has a linear shape on the one end frame region 41 side, and is opposite to the one end frame region 41. Has a curved shape. As described above, in the fourth embodiment, the outline shape of the TFT substrate 1, the CF substrate 2, and the display region 3 in plan view includes a curved shape.

  In the partial gate connection wirings 62 and 63, contacts 62a and 63a which are parts connected to the conductive particles 92a and 92b, and in the partial gate connection wiring 64, parts connected to the conductive particles 92a and 92b. The contacts 64a and 64b are arranged along the curved shape of the display area 3 in plan view.

<Summary of Embodiment 4>
According to the liquid crystal display device according to the fourth embodiment as described above, the frame area can be reduced in the liquid crystal display device having an outer shape that is not a linear shape as in the first embodiment.

<Embodiment 5>
16 and 17 are plan views showing schematic configurations of a TFT substrate and a CF substrate that constitute a liquid crystal panel included in the liquid crystal display device according to Embodiment 5 of the present invention. FIG. 18 is a cross-sectional view showing a schematic configuration of a liquid crystal panel along a connecting line between gate lines to be described later. Hereinafter, among the constituent elements described in the fifth embodiment, the same or similar constituent elements as those in the third embodiment are denoted by the same reference numerals, and different constituent elements will be mainly described.

  As shown in FIGS. 16 and 17, the outline shape of the TFT substrate 1, the CF substrate 2, and the display region 3 in a plan view has a linear shape on one end frame region 41 side and a curve on the opposite side to the one end frame region 41. It has a shape and a concave shape.

  As shown in FIG. 16, each of the several gate wirings 6 includes partial gate wirings 6a and 6b spaced apart in the display region 3 of the TFT substrate 1, and the partial gate wirings 6a and 6b are described above. Are disposed with a concave portion therebetween. That is, the partial gate wirings 6a and 6b are divided by the concave shape. The plurality of partial gate wirings according to the present invention can be referred to as partial gate wirings 6a and 6b.

  Here, in addition to the configuration of the third embodiment, the liquid crystal display device according to the fifth embodiment includes inter-gate wiring connection wirings that electrically connect the partial gate wirings 6a and 6b. The inter-gate wiring connection wiring includes partial gate wiring connection wirings 67, 68 and 69.

  The connection wirings 67 and 68 between the partial gate wirings are spaced apart in the frame region of the TFT substrate 1. Among these, the end portion of the connection line 67 between the partial gate lines is connected to the partial gate line 6a, and the end part of the connection line 68 between the partial gate lines is connected to the partial gate line 6b. The plurality of first inter-partial interconnect lines can be referred to as inter-partial interconnect lines 67 and 68. However, the plurality of connection lines between the first partial gate lines are not limited to this, and may include, for example, a line that is not connected to any of the partial gate lines 6a and 6b.

  On the other hand, the connection wiring 69 between the partial gate wirings is disposed on the resin BM 201 of the CF substrate 2 as shown in FIG. As shown in FIGS. 17 and 18, the inter-partial gate connection line 69 is connected between the inter-partial gate connection line 67 and the partial gate line via the conductive particles 92c and 92d mixed in the sealing material 91. The connection wiring 68 is electrically connected. The second partial gate wiring connection wiring according to the present invention can be referred to as a partial gate wiring connection wiring 69, and the respective conductive members according to the present invention can be referred to as conductive particles 92c and 92d. In the fifth embodiment, as shown in FIGS. 16 and 17, the conductive particles 92c and 92d are arranged in the frame region.

  When the number of gate wirings 6 divided by the concave shape is small, the two-substrate gate connection wiring described in the first embodiment or the like electrically connects between the partial gate wiring 6a or the partial gate wiring 6b and the gate IC 600. It is possible to connect to. However, when the number of gate lines 6 divided by the concave shape is large, it is difficult to dispose the two-substrate gate connection lines in the display area 3 or the frame area. It is difficult to electrically connect the partial gate wiring 6a and the partial gate wiring 6b and the gate IC 600 while maintaining the above.

  On the other hand, according to the fifth embodiment, even when the number of gate wirings 6 divided by the concave shape is large, the partial gate wiring 6a and the partial gate wiring 6a and the part are maintained while maintaining the required outer shape of the liquid crystal panel. The gate wiring 6b and the gate IC 600 can be electrically connected. As a result, the necessary display area 3 can be secured.

  As shown in FIG. 16 and FIG. 17, one end of connection wiring 67 and 68 between the partial gate wirings disposed on the TFT substrate 1 is connected to a connection wiring 69 between the partial gate wirings disposed on the CF substrate 2. For this purpose, contacts 67a and 68a are provided. As shown in FIG. 18, the contacts 67 a and 68 a are exposed from the insulating film 101 through the openings of the insulating film 101 disposed on the partial inter-gate wiring connecting wirings 67 and 68. These openings may be covered with a transparent conductive film such as ITO forming a pixel electrode or the like. Thereby, the connection resistance with the conductive particles 92c and 92d is stabilized.

  As shown in FIGS. 16 and 17, contacts 69a and 69b are provided at both ends of the connection gate 69 between the partial gate wirings disposed on the CF substrate 2 in the same manner as the connection wiring 67 and 68 between the partial gate wirings. , 68a, respectively. As shown in FIG. 18, the contacts 69 a and 69 b are exposed from the insulating film 202 through openings of the insulating film 202 disposed on the inter-part gate wiring connection wiring 69. These openings may be covered with the transparent conductive film when the conductive film 203 is a transparent conductive film such as ITO. Thereby, the connection resistance with the conductive particles 92c and 92d is stabilized.

  Contact 67a is electrically connected to contact 69a by conductive particle 92c, and contact 68a is electrically connected to contact 69b by conductive particle 92d.

  As shown in FIG. 18, the partial inter-gate wiring connection wiring 69 is disposed on the resin BM 201. Since the resin BM201 is a black opaque layer, it is possible to prevent the partial inter-gate wiring connection wiring 69 from being viewed from the observation direction when operating as a liquid crystal display device. Further, in the fifth embodiment, since it is not necessary to provide a cut in the resin BM 201, a uniform black frame can be formed in the display area 3 and the frame area, and an uncomfortable appearance can be maintained.

  As shown in FIG. 18, in the fifth embodiment, a conductive film 203 is disposed on at least a part of the inter-partial gate line connection wiring 69 via an insulating film 202. According to such a conductive film 203, it is possible to suppress the scanning signal applied to the inter-partial gate connection line 69 from interfering with the liquid crystal of the liquid crystal layer 8 in the vicinity of the inter-partial gate connection line 69. Display abnormalities such as light leakage can be suppressed.

<Summary of Embodiment 5>
According to the liquid crystal display device according to the fifth embodiment as described above, the wiring region necessary for the gate connection wiring can be reduced even when the gate wiring 6 is divided by the concave shape of the display region 3. The frame area can be reduced. Further, since the connection wiring 69 between the partial gate wirings disposed on the CF substrate 2 is disposed on the resin BM 201, the connection wiring 69 between the partial gate wirings is viewed from the observation direction when operating as a liquid crystal display device. It can be prevented from being visually recognized.

  In the fifth embodiment, the conductive film 203 is disposed above the connection wiring 69 between the partial gate wirings. Thereby, during the display operation of the liquid crystal panel, it is possible to suppress the scanning signal applied to the connection wiring 69 between the partial gate wirings from interfering with the liquid crystal in the vicinity of the connection wiring 69 between the partial gate wirings. Display abnormality such as leakage can be suppressed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 TFT substrate, 2 CF substrate, 3 display area, 5 source wiring, 6 gate wiring, 6a, 6b partial gate wiring, 41, 42, 43, 44 frame area, 51 source connection wiring, 62, 63, 64 partial gate connection Wiring, 62a, 63a, 64a, 64b Contact, 67, 68, 69 Partial gate wiring connection wiring, 71 TFT, 72 Pixel electrode, 92a, 92b, 92c, 92d Conductive particles, 201 Resin BM, 202 Insulating film, 203 Conductive film, 500 source IC, 600 gate IC.

Claims (8)

A first substrate in which a display area and a frame area adjacent to the display area are defined;
A plurality of source lines and a plurality of gate lines arranged in the display region and intersecting each other in plan view;
A plurality of thin film transistors disposed in the display region and connected to the plurality of source lines and the plurality of gate lines;
A source line driving unit capable of supplying a video signal to the plurality of source lines, the frame area being arranged in one end frame area that is an area on one end side of the plurality of source lines;
A gate line driving unit arranged in the one end frame region and capable of supplying a scanning signal to the plurality of gate lines;
A plurality of source connection wirings disposed in the frame region for electrically connecting the plurality of source wirings and the source wiring driving unit;
A plurality of gate connection lines for electrically connecting the plurality of gate lines and the gate line driving unit;
A second substrate disposed opposite to the first substrate and having an insulating black matrix disposed on a surface facing the first substrate;
The gate connection wiring is
A plurality of first partial gate connection wirings spaced apart in the frame region of the first substrate;
And a second partial gate connection wiring disposed on the black matrix of the second substrate and electrically connecting the plurality of first partial gate connection wirings through the conductive members. The liquid crystal display device according to claim 1,
The liquid crystal display device further comprising a conductive film disposed on at least a part of the second partial gate connection wiring via an insulating film. The liquid crystal display device according to claim 2,
The liquid crystal display device, wherein the at least part of the second partial gate connection wiring is disposed to face the display region. The liquid crystal display device according to claim 3,
A plurality of pixel electrodes disposed in the display region and connected to the plurality of thin film transistors;
The liquid crystal display device is a horizontal electric field type liquid crystal display device,
The liquid crystal display device, wherein the conductive film is disposed between the pixel electrodes in a plan view. The liquid crystal display device according to any one of claims 1 to 4,
The outline shape in plan view of the display area includes a curved shape,
A portion of the first partial gate connection wiring that is connected to the conductive members is disposed along the curved shape of the display region in plan view. The liquid crystal display device according to claim 1,
The gate wiring is
A plurality of partial gate wirings spaced apart in the display area of the first substrate;
Further comprising an inter-gate wiring connection wiring for electrically connecting the plurality of partial gate wirings,
The gate wiring connection wiring is
A plurality of first partial gate-wiring connection wirings spaced apart in the frame region of the first substrate;
A liquid crystal, which is disposed on the black matrix of the second substrate, and includes a second inter-partial gate line connection wiring that electrically connects the plurality of first partial gate-line connection lines via each conductive member. Display device. The liquid crystal display device according to claim 6,
The outline shape in plan view of the display area includes a concave shape,
The liquid crystal display device, wherein the plurality of partial gate lines are arranged with the concave portion interposed therebetween. The liquid crystal display device according to claim 6 or 7, wherein
A liquid crystal display device, further comprising: a conductive film disposed on at least a part of the second partial gate-wiring connection wiring via an insulating film.

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