JP2017208634A - Op amplifier and electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low output impedance of a buffer circuit using an OP amplifier, and expansion of output voltage range.SOLUTION: An OP amplifier (1A) for buffer circuit has a first input terminal (INn) and a second input terminal (INp), a differential amplifier circuit (10) generating a differential output signal based on the difference between a signal inputted to the first input terminal and a signal inputted to the second input terminal, a first output circuit (11) including a source follower circuit or an emitter follower circuit having a first conductivity type transistor (MN1) as an output transistor, a second output circuit (12) including a source follower circuit or an emitter follower circuit having a second conductivity type transistor (MP1) as an output transistor, an output terminal (OUT) connected with the output node of the first output circuit and output node of the second output circuit, and a selection circuit (13) for inputting a differential output signal to any one of the first output circuit and second output circuit.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an OP amplifier and an electronic circuit using the OP amplifier. For example, an analog / digital conversion circuit that converts an analog signal from a sensor into a digital signal in an instrument such as a temperature controller or a flow controller. The present invention relates to an OP amplifier for a buffer circuit used as an input interface of the buffer circuit.

  Instrumentation equipment such as temperature controllers and flow controllers installed in plant and building air-conditioning equipment, etc. can be controlled by detecting temperature, flow rate, etc. with sensors and performing feedback control based on the detection results from the sensors. Control is performed so that the target temperature and flow rate become target values.

  In general, instrumentation equipment includes an analog / digital conversion circuit (hereinafter also referred to as an “A / D conversion circuit”) that converts an analog signal into a digital signal. The detection signal in the format is converted into a digital signal, and various data processing is executed using the digital signal. As an A / D conversion circuit mounted on an instrumentation device, a ΔΣ type A / D conversion circuit using a switched capacitor circuit is known (for example, see Patent Document 1).

In instrumentation equipment, feedback control is performed based on the sensor detection results acquired as described above. Therefore, in order to control the temperature and flow rate of the controlled object with high accuracy, the sensor detection results are reliably acquired. In addition, it is necessary to perform A / D conversion with high accuracy.
For example, in the case of a ΔΣ type A / D converter circuit using a switched capacitor circuit, the sensor detection result is sampled by accumulating charges corresponding to the sensor output signal in the input capacitance, and the sampling result is used. A / D conversion is performed. However, in the case of an A / D conversion circuit using such a switched capacitor circuit, if the sensor output signal is directly input to the input capacitor, the output impedance of the sensor is large, so that the input capacitor cannot be charged sufficiently. The detection result of the sensor cannot be captured accurately.

  Therefore, in the conventional instrumentation equipment, a buffer circuit composed of an OP amplifier is provided between the sensor and the switched capacitor circuit at the input stage of the A / D conversion circuit, and the output signal of the sensor is switched via the buffer circuit. I was entering the circuit.

JP 2011-188089 A

  An OP amplifier used as an input stage buffer circuit of an A / D conversion circuit of an instrumentation device is required to have a smaller output impedance and a wider output voltage range in order to reliably capture the detection result of the sensor.

  However, in the case of a general CMOS process OP amplifier, as an output circuit, a source follower circuit having a small output impedance but a narrow output voltage range, or a wide output voltage range but a large output impedance (a source using transistors of the same size) The source grounded circuit) is employed, and it is not easy to realize a buffer circuit that achieves both a small output impedance and a wide output voltage range.

  The present invention has been made in view of the above problems, and an object of the present invention is to realize a low output impedance of a buffer circuit using an OP amplifier and an expansion of an output voltage range.

  The OP amplifier (1, 1A) according to the present invention includes a first input terminal (INn), a second input terminal (INp), a signal input to the first input terminal, and a signal input to the second input terminal. A differential amplifier circuit (10) for generating a differential output signal based on the difference, and a first output circuit (11) including a source follower circuit or an emitter follower circuit using the first conductivity type transistor (MN1) as an output transistor; A second output circuit (12) including a source follower circuit or an emitter follower circuit using the second conductivity type transistor (MP1) as an output transistor, and an output node of the first output circuit and an output node of the second output circuit And a selection circuit (13) for inputting a differential output signal to one of the first output circuit and the second output circuit.

  In the OP amplifier, the selection circuit may switch the input destination of the differential output signal according to the magnitude of the DC component of the signal input to the first input terminal or the second input terminal.

  An electronic circuit according to the present invention includes an OP amplifier (1A) in which a first input terminal and an output terminal are connected, and a switched capacitor circuit (2) that samples a signal output from the output terminal of the OP amplifier. It is characterized by.

In the electronic circuit, the switched capacitor circuit is charged in the capacitor during the sampling period (T _Φ1 ) for charging the capacitor (Cin) with the charge based on the signal (Vout) output from the output terminal of the OP amplifier. The holding circuit (T _Φ2 ) for holding the _stored charge alternately repeats, and the selection circuit performs differential when the DC component of the signal input to the first input terminal is smaller than the threshold value (VT) during the holding period. When the output node (n0) of the amplifier circuit is connected to the input node (n1) of the first output circuit and the DC component of the signal input to the first input terminal is larger than the threshold value, the output of the differential amplifier circuit The node is connected to the input node (n2) of the second output circuit, and in the sampling period, the output node and the first output circuit of the differential output circuit in the immediately preceding hold period The connection relationship between the input node of the path and the input node of the first output circuit may be maintained.

  In the above description, as an example, reference numerals on the drawings corresponding to the constituent elements of the invention are shown in parentheses.

  As described above, according to the present invention, it is possible to reduce the output impedance and expand the output voltage range of the buffer circuit using the OP amplifier.

FIG. 1 is a diagram showing a configuration of an OP amplifier according to an embodiment of the present invention. FIG. 2 is a diagram showing an example when a buffer circuit is configured by an OP amplifier according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a circuit configuration of the OP amplifier. FIG. 4 is a diagram for explaining an output voltage range of an OP amplifier as a buffer circuit. FIG. 5 is a diagram showing an electronic circuit using the OP amplifier according to one embodiment of the present invention as an input buffer circuit of a switched capacitor circuit. FIG. 6 is a diagram illustrating a circuit configuration of the selection signal generation circuit. FIG. 7 is a timing chart of an OP amplifier using the selection signal generation circuit of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

≪OP amplifier≫
FIG. 1 is a diagram showing a configuration of an OP amplifier according to an embodiment of the present invention.
As shown in FIG. 1, the OP amplifier 1 has input terminals INn and INp, a differential amplifier circuit 10, a selection circuit 13, output circuits 11 and 12, and an output terminal OUT.

  The differential amplifier circuit 10 is a circuit that generates a differential output signal based on a difference between a signal input to the input terminal INn and a signal input to the input terminal INp.

  The output circuit 11 is a circuit including a source follower circuit that uses a first conductivity type (for example, N-channel type) transistor as an output transistor. The output circuit 12 is a circuit including a source follower circuit in which a transistor of a second conductivity type (for example, a P channel type) is used as an output transistor. The output node of the output circuit 11 and the output node of the output circuit 12 are connected to the output terminal OUT, respectively.

  The selection circuit 13 is a circuit that inputs the differential output signal generated by the differential amplifier circuit 10 to one of the output circuit 11 and the output circuit 12.

FIG. 2 is a diagram illustrating an example in which a buffer circuit is configured by the OP amplifier 1.
As shown in FIG. 2, the OP amplifier 1 short-circuits the inverting input terminal (INn, −) of the differential amplifier circuit 10 and the output node of the OP amplifier 1, thereby providing a non-inverting input terminal of the differential amplifier circuit 10. It can function as a buffer circuit (voltage follower) that inputs the signal Vin to (INp, +). Hereinafter, a circuit in which the inverting input terminal and the output node of the differential amplifier circuit 10 are short-circuited is referred to as “voltage follower 1A”.

  The voltage follower 1A shown in FIG. 2 determines which of the output circuit 11 and the output circuit 12 is used as the output circuit of the OP amplifier according to the magnitude of the DC component of the input signal Vin input to the input terminal INp. It has a function to switch.

  Hereinafter, a specific circuit configuration of the OP amplifier 1 will be described. Here, description will be made assuming that the OP amplifier 1 is realized as a semiconductor integrated circuit formed on a semiconductor substrate by a known CMOS process, for example.

FIG. 3 is a diagram showing a circuit configuration of the OP amplifier 1.
As shown in FIG. 3, the differential amplifier circuit 10 includes, for example, P channel type MOS transistors (hereinafter referred to as “PMOS transistors”) MP3, MP4, MP5, and N channel type MOS transistors (hereinafter referred to as “PMOS transistors”). This is referred to as an “NMOS transistor”.) A cascode amplifier circuit composed of a differential input circuit 110 composed of MN3, MN4 and MN5, PMOS transistors MP6, MP7, MP8 and MP9, and NMOS transistors MN6, MN7, MN8 and MN9. 111 and a common source amplifier circuit 112 including a PMOS transistor MP10, an NMOS transistor MN10, a capacitor C, and a resistor R.

  An output node n0 of the differential amplifier circuit 10 is connected to a terminal A of a switch circuit 130 described later.

  The selection circuit 13 includes a switch circuit 130 and a selection signal 131. The switch circuit 130 is provided between the output node n 0 of the differential amplifier circuit 10, the output node n 1 of the output circuit 11, and the output node n 2 of the output circuit 12, and receives the selection signal SEL provided from the selection signal generation circuit 131. Based on this, the connection destination of the output node n0 of the differential amplifier circuit 10 is switched to the output node n1 of the output circuit 11 or the output node n2 of the output circuit 12.

The selection signal generation circuit 131 is a circuit that generates a selection signal SEL for switching the connection destination of the switch circuit 130.
For example, when the OP amplifier 1 is used as the voltage follower 1A shown in FIG. 2, the selection signal generation circuit 131 is based on the magnitude of the DC component of the signal input to the input terminal INp or the input terminal INn. A selection signal SEL is generated. The selection signal SEL is, for example, a binary signal.

  More specifically, the selection signal generation circuit 131 provides the selection signal SEL of the first logic level (for example, Low level) to the switch circuit 130 when the DC component of the signal Vin is lower than the predetermined threshold value VT. When the output node n0 of the differential amplifier circuit 10 and the input node n1 of the output circuit 11 are connected (the terminal a and the terminal b of the switch circuit 130 are connected), and the DC component of the signal Vin is higher than the predetermined threshold VT Is supplied with a selection signal SEL of a second logic level (for example, High level) to the switch circuit 130, thereby connecting the output node n0 of the differential amplifier circuit 10 and the input node n2 of the output circuit 12 (terminals of the switch circuit 130). a and terminal c are connected).

  As described above, the output circuit 11 is a source follower circuit using an NMOS transistor as an output transistor, and includes, for example, an NMOS transistor MN1 and an NMOS transistor MN2.

  The NMOS transistor MN1 is an output transistor, its drain electrode is connected to a power supply line Vdd to which a fixed voltage Vdd as a power supply voltage is supplied, its source electrode is connected to the output terminal OUT, and its gate electrode is the switch circuit 130. Are connected to the terminal B.

  The NMOS transistor MN2 is a load of the NMOS transistor MN1, its drain electrode is connected to the output terminal OUT, its source electrode is connected to a power supply line Vss to which a fixed voltage Vss (<Vdd) as a power supply voltage is supplied, A bias voltage Vb1 is applied to the gate electrode.

  As described above, the output circuit 12 is a source follower circuit using a PMOS transistor as an output transistor, and includes, for example, a PMOS transistor MP1 and a PMOS transistor MP2.

  The PMOS transistor MP1 is an output transistor, its drain electrode is connected to the power supply line Vss, its source electrode is connected to the output terminal OUT, and its gate electrode is connected to the terminal C of the switch circuit 130.

  The PMOS transistor MP2 is a load of the PMOS transistor MP1, its drain electrode is connected to the output terminal OUT, its source electrode is connected to the power supply line Vdd, and its gate electrode is applied with the bias voltage Vb2.

  According to the voltage follower 1A having the circuit configuration described above, when the DC component of the input signal Vin is lower than the threshold value VT, an N-channel low output impedance source follower circuit having a wide output voltage range on the low potential side. When the output signal 11 is used and the DC component of the input signal Vin is higher than the threshold value VT, a P-channel low output impedance source follower circuit (output circuit 12) having a wide output voltage range on the high potential side. ), The output voltage range of the voltage follower 1A can be increased in a pseudo manner as shown in FIG. As a result, the output impedance of the buffer circuit can be reduced and the output voltage range can be expanded.

  The output circuit that is not selected connects the output transistor gate electrode to the power supply line Vdd or the power supply line Vss by connecting the gate electrode of the output transistor and the gate electrode of the load transistor that constitutes the active load. A high impedance state may be set. For example, when the output circuit 11 is selected, the gate electrodes of the PMOS transistors MP1 and MP2 of the output circuit 12 that are not selected may be connected to the power supply line VDD.

≪Application examples≫
Next, an application example of the above-described OP amplifier 1 will be shown.
FIG. 5 is a diagram showing an electronic circuit using the OP amplifier 1 according to one embodiment of the present invention as an input buffer circuit of a switched capacitor circuit.

  The electronic circuit 100 shown in FIG. 5 includes an integration circuit 2 as a switched capacitor circuit and a voltage follower 1A as an input buffer circuit of the integration circuit 2. Here, it is assumed that the integrating circuit 2 and the voltage follower 1A are realized as one IC chip formed on a semiconductor substrate by a known CMOS process, for example.

  The integrating circuit 2 is a switched capacitor circuit that samples and integrates the signal Vout output from the output terminal OUT of the voltage follower 1A. For example, the integrating circuit 2 constitutes a part of an input circuit of a ΔΣ type A / D conversion circuit. .

Specifically, the integrating circuit 2, a sampling period T _.phi.1 of electric charge corresponding to the signal Vout output from the output terminal OUT of the voltage follower 1A to the input capacitor Cin, the charges charged in the input capacitance Cin during the sampling period The signal Vout is integrated by alternately repeating the hold period _TΦ2 for holding the signal Vout.

  More specifically, the integrating circuit 2 is stored in the input capacitor Cin, the output capacitor Cint, the sampling switches SW1 and SW3 for charging the input capacitor Cin with charges corresponding to the signal Vout, and the input capacitor Cin. Hold switches SW2 and SW4 for holding the stored charges and transferring them to the output capacitor Cin in the subsequent stage, and a differential amplifier circuit 20.

  Sampling switches SW1 and SW3 are controlled to be turned on / off by a signal Φ1, and holding switches SW2 and SW4 are controlled to be turned on / off by a signal Φ2.

In the integrating circuit 2, turns off the hold switch SW2, SW4 causes turn on the sampling switches SW1, SW3 to the sampling period T _.phi.1, hold switch SW2 causes turn on the sampling switches SW1, SW3 to hold period T _.phi.2, The signals Vout are integrated by inputting the signals Φ1 and Φ2 to the respective switches so as to turn off the SW4.

  As described above, the OP amplifier 1 is a voltage follower and outputs a signal Vout corresponding to the input signal Vin to be integrated.

In OP amplifier 1 shown in FIG. 5, the selection circuit 13, the hold period T _.phi.2 of the integrating circuit 2, determines the magnitude of the input signal Vin supplied to the input terminal INp, determination result to the OP amplifier 1 according One of the output circuit 11 and the output circuit 12 is selected as the output circuit, and the selection result of the output circuit in the immediately preceding hold period _TΦ2 is maintained in the sampling period _TΦ1 of the integration circuit 2.

Specifically, the selection circuit 13 connects the output node n0 of the differential amplifier circuit 10 to the input node n2 of the output circuit 11 when the DC component of the input signal Vin is smaller than the threshold value VT in the hold period _TΦ2 . When the DC component of the input signal Vin is larger than the threshold value VT, the output node n0 of the differential amplifier circuit 10 is connected to the input node n2 of the output circuit 12, and the previous hold period T in the sampling period _TΦ1 . The connection relationship between the output node n0 of the differential output circuit 10 and the input node n2 of the output circuit 12 and the input node n1 of the output circuit 11 at _Φ2 is maintained.

  More specifically, the selection signal generation circuit 131 of the selection circuit 13 is configured by using a latched comparator CMP that operates at the rising edge (or falling edge) of the signal Φ2 as shown in FIG. The circuit 13 can be operated as described above.

FIG. 7 is a timing chart of the OP amplifier 1 using the selection signal generation circuit 131 of FIG. In the figure, the period in which the signal Φ1 is High is defined as a sampling period _TΦ1, and the period in which the signal Φ2 is High is defined as a hold period _TΦ2 . Also, the corresponding switch is turned on when the signals Φ1 and Φ2 are at the high level, and the corresponding switch is turned off when the signals Φ1 and Φ2 are at the low level.

As shown in FIG. 7, by configuring the selection signal generation circuit 131 with a latched comparator CMP that operates at the rising edge of the signal Φ2, the timing between the input signal Vin and the threshold VT at the timing when the hold period _TΦ2 is started. The logic level of the selection signal SEL is updated according to the comparison result, and the logic level of the selection signal SEL is held in the sampling period _TΦ1 .

According to this, since the output circuit of the OP amplifier 1 is not switched in the sampling period _TΦ1 in which the _subsequent integration circuit 2 takes in the signal Vout, adverse effects on the integration circuit 2 can be suppressed. For example, even if there is an instantaneous fluctuation of the signal Vout when the output circuit of the OP amplifier 1 is switched, the sampling switch SW1 of the integration circuit 2 is turned off at the switching timing, so that the signal Vout instantaneously changes. The influence of such fluctuations on the integrating circuit 2 is limited.

  As described above, according to the OP amplifier according to the present invention, by using the OP amplifier as a buffer circuit, it is possible to reduce the output impedance of the buffer circuit and expand the output voltage range.

  In particular, by applying the OP amplifier 1 according to the above embodiment as an input buffer circuit of a switched capacitor circuit, the performance of the switched capacitor circuit can be sufficiently exhibited without adversely affecting the operation of the subsequent switched capacitor circuit. Can do.

  That is, when the integration circuit 2 is a part of the input circuit of the ΔΣ type A / D conversion circuit mounted on the instrumentation device, the low output impedance OP amplifier 1 is used as the input buffer circuit of the integration circuit 2. As a result, the input capacitance Cin can be sufficiently charged by the signal from the sensor, so that the signal from the sensor can be reliably captured.

  Further, since the output voltage range of the OP amplifier 1 can be increased in a pseudo manner, the input voltage range of the ΔΣ A / D conversion circuit is limited by the output voltage range of the OP amplifier 1 as the input buffer circuit. This can be prevented, and the input voltage range of the ΔΣ A / D conversion circuit can be expanded.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, in the above-described embodiment, the case where the OP amplifier 1 is realized by a known CMOS process is exemplified. However, a bipolar process, a Bi-CMOS process, a heterojunction bipolar transistor (HBT) process, or the like is used. It may be realized by other semiconductor manufacturing processes. For example, when the OP amplifier 1 is realized by a bipolar process, the output circuit 11 is configured by an emitter follower circuit in which the NMOS transistors MN1 and MN2 are changed to NPN transistors, and the PMOS transistors MP1 and MP2 are changed to PNP transistors, respectively. The output circuit 12 may be configured by an emitter follower circuit.

  In the above embodiment, the active load (NMOS transistor MN2, PMOS transistor MP2) is exemplified as the load of the output transistors (NMOS transistor MN1, PMOS transistor MP1) of the output circuits 11, 12, but the output circuits 11, 12 are exemplified. As long as a source follower circuit is configured, the configuration is not limited to the above. For example, a resistor may be used instead of the active load.

  In the above embodiment, the integration circuit 2 constituting the input circuit of the ΔΣ type A / D conversion circuit is exemplified as the switched capacitor circuit to which the OP amplifier 1 as the input circuit is connected. The integrated circuit 2 is not limited to the above-described integration circuit 2 as long as it is a switched capacitor circuit that stores a corresponding charge in a capacitor at regular intervals. For example, instead of the integration circuit 2, a switched capacitor type comparator, a switched capacitor filter, or the like may be used.

  2 and 5, in order for the OP amplifier 1 to function as a buffer circuit (voltage follower), the inverting input terminal (−) of the differential amplifier circuit 10 and the output terminal OUT of the OP amplifier 1 are connected to the outside of the IC chip. However, the present invention is not limited to this, and the input terminal INn and the output terminal OUT may be short-circuited inside the IC chip.

  DESCRIPTION OF SYMBOLS 1 ... OP amplifier, 1A ... Voltage follower, INn, INp ... Input terminal, OUT ... Output terminal, 10 ... Differential amplifier circuit, 11, 12 ... Output circuit, 13 ... Selection circuit, 130 ... Switch circuit, 131 ... Selection signal Generation circuit, n0, n1, n2 ... node, SW1, SW3 ... sampling switch, SW2, SW4 ... hold switch, Vin, Vout, [Phi] 1, [Phi] 2 ... signal, MN1-MN10 ... NMOS transistor, MP1-MP10 ... PMOS transistor .

Claims (5)

A differential amplifier circuit for generating a differential output signal based on a difference between a first input terminal and a second input terminal; a signal input to the first input terminal; and a signal input to the second input terminal;
A first output circuit including a source follower circuit having a first conductivity type transistor as an output transistor;
A second output circuit including a source follower circuit having a second conductivity type transistor as an output transistor;
An output terminal connected to an output node of the first output circuit and an output node of the second output circuit;
An OP amplifier, comprising: a selection circuit that inputs the differential output signal to one of the first output circuit and the second output circuit. A differential amplifier circuit for generating a differential output signal based on a difference between a first input terminal and a second input terminal; a signal input to the first input terminal; and a signal input to the second input terminal;
A first output circuit including an emitter follower circuit having a first conductivity type transistor as an output transistor;
A second output circuit including an emitter follower circuit having a second conductivity type transistor as an output transistor;
An output terminal connected to an output node of the first output circuit and an output node of the second output circuit;
An OP amplifier, comprising: a selection circuit that inputs the differential output signal to one of the first output circuit and the second output circuit. The OP amplifier according to claim 1 or 2,
The OP amplifier is characterized in that the selection circuit switches an input destination of the differential output signal in accordance with a magnitude of a DC component of a signal input to the first input terminal or the second input terminal. The OP amplifier according to any one of claims 1 to 3, wherein the second input terminal and the output terminal are connected;
An electronic circuit comprising: a switched capacitor circuit that samples a signal output from the output terminal of the OP amplifier. The electronic circuit according to claim 4.
The switched capacitor circuit alternately includes a sampling period for charging a capacitor based on a signal output from the output terminal of the OP amplifier and a hold period for holding the charge charged in the capacitor during the sampling period. repetition,
The selection circuit connects an output node of the differential amplifier circuit to an input node of the first output circuit when a DC component of a signal input to the first input terminal is smaller than a threshold during the hold period. When the direct current component of the signal input to the first input terminal is larger than the threshold, the output node of the differential amplifier circuit is connected to the input node of the second output circuit, and in the sampling period, An electronic circuit characterized by maintaining a connection relationship between an output node of the differential output circuit, an input node of the first output circuit, and an input node of the first output circuit in the immediately preceding hold period.

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