JP2017208377A - High-frequency semiconductor device and electronic equipment - Google Patents

High-frequency semiconductor device and electronic equipment Download PDF

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JP2017208377A
JP2017208377A JP2016097860A JP2016097860A JP2017208377A JP 2017208377 A JP2017208377 A JP 2017208377A JP 2016097860 A JP2016097860 A JP 2016097860A JP 2016097860 A JP2016097860 A JP 2016097860A JP 2017208377 A JP2017208377 A JP 2017208377A
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lead portion
frequency semiconductor
region
output
input
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一考 高木
Kazutaka Takagi
一考 高木
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a high-frequency semiconductor device having excellent heat dissipation and capable of easily achieving surface mounting, and electronic equipment.SOLUTION: A high-frequency semiconductor device 5 comprises an input lead part 10, an output lead part 20, a high frequency semiconductor element 30, a ground lead part 40, and a sealing resin layer 60. The ground lead part comprises first and second regions 42 to 45, and a die pad part 46. The sealing resin layer covers an input inner lead part 11, an output inner lead part 21, a high-frequency semiconductor element, and a mount surface 46a. A first surface 70 includes an exposed surface of the die pad part and a surface of the sealing resin layer. A second surface 72 includes a surface of the input inner lead part, a surface of the output inner lead part, a flat part of an inner lead part of the first region, and a flat part of an inner lead part of the second region. A third surface 74 includes a flat part of an input outer lead part 12, a flat part of an output outer lead part 22, a flat part of an output outer lead part of the first region, and a flat part of an outer lead part of the second region.SELECTED DRAWING: Figure 1

Description

本発明の実施形態は、高周波半導体装置および電子機器に関する。   Embodiments described herein relate generally to a high-frequency semiconductor device and an electronic apparatus.

回路基板上に高周波半導体装置を表面実装すると、電子機器を小型化するとともに量産性を高めることができる。   When a high-frequency semiconductor device is surface-mounted on a circuit board, the electronic equipment can be downsized and mass productivity can be improved.

この場合、リードが設けられた面から実装基板を経由して放熱すると、半導体装置とヒートシンク間の熱抵抗が高くなる。このため、高出力化にとって不利となる。   In this case, if heat is radiated from the surface where the leads are provided via the mounting substrate, the thermal resistance between the semiconductor device and the heat sink increases. This is disadvantageous for high output.

特開２０１２−１８２３０６号公報JP 2012-182306 A

放熱性が良好で表面実装が容易な高周波半導体装置およびこれを用いた電子機器を提供する。   A high-frequency semiconductor device having good heat dissipation and easy surface mounting and an electronic apparatus using the same are provided.

実施形態の高周波半導体装置は、入力リード部と、出力リード部と、高周波半導体素子と、接地リード部と、封止樹脂層と、を有する。前記入力リード部は、入力インナーリード部と入力アウターリード部とを有し、第１の直線に沿って延在する。前記出力リード部は、出力インナーリード部と出力アウターリード部とを有し、前記第１の直線に沿って延在する。前記高周波半導体素子は、前記入力インナーリード部および前記出力インナーリード部にそれぞれ接続される。前記接地リード部は、前記入力リード部に平行な第１領域と、前記出力リード部に平行な第２領域と、前記高周波半導体素子が接合されるマウント面を有するダイパッド部と、を有し、前記高周波半導体素子の接地電極に電気的に接続される接地リード部であって、前記第１領域と前記第２領域とは、前記第１の直線に平行な第２の直線に沿って延在する。前記封止樹脂層は、前記入力インナーリード部と、前記出力インナーリード部と、前記高周波半導体素子と、前記ダイパッド部のうちの前記マウント面の側と、を覆う封止樹脂層であって、前記入力アウターリード部と前記出力アウターリード部とは互いに反対の方向に突出し、前記接地リードの前記第１領域と前記第２領域とは互いに反対方向に突出する。実施形態の高周波半導体装置は３層からなり、１層目の第１の面は、前記マウント面とは反対の側となる前記ダイパッド部の露出面と、前記露出面の周囲に設けられた前記封止樹脂層の表面と、を含む。すなわち、前記ダイパッド部の前記マウント面とは反対の側となる面は前記封止樹脂層の表面から露出している。２層目の第２の面は、前記第１の面から後退した入力インナーリード部の表面と、前記第１の面から後退した出力インナーリード部の表面と、前記第１の面から後退した前記第１領域のインナーリード部の平坦部の表面と、前記第１の面から後退した前記第２領域のインナーリード部の平坦部の表面と、を含む。３層目の第３の面は、前記封止樹脂層の外部において、前記第２の面から前記第１の面とは反対の側に向かって折り曲げられた前記入力アウターリード部の平坦部の表面と、前記第２の面から前記第１の面とは反対の側に向かって折り曲げられた出力アウターリード部の平坦部の表面と、前記第１領域のアウターリード部の平坦部の表面と、前記第２領域のアウターリード部の平坦部の表面と、を含み、実装基板への取り付け面とされる。   The high-frequency semiconductor device according to the embodiment includes an input lead portion, an output lead portion, a high-frequency semiconductor element, a ground lead portion, and a sealing resin layer. The input lead portion has an input inner lead portion and an input outer lead portion, and extends along a first straight line. The output lead portion has an output inner lead portion and an output outer lead portion, and extends along the first straight line. The high-frequency semiconductor element is connected to the input inner lead portion and the output inner lead portion, respectively. The ground lead portion includes a first region parallel to the input lead portion, a second region parallel to the output lead portion, and a die pad portion having a mount surface to which the high-frequency semiconductor element is bonded, A ground lead portion electrically connected to a ground electrode of the high-frequency semiconductor element, wherein the first region and the second region extend along a second straight line parallel to the first straight line To do. The sealing resin layer is a sealing resin layer that covers the input inner lead portion, the output inner lead portion, the high-frequency semiconductor element, and the mount surface side of the die pad portion, The input outer lead portion and the output outer lead portion protrude in opposite directions, and the first region and the second region of the ground lead protrude in opposite directions. The high-frequency semiconductor device according to the embodiment includes three layers, and the first surface of the first layer is the exposed surface of the die pad portion on the side opposite to the mount surface and the periphery of the exposed surface. And a surface of the sealing resin layer. That is, the surface of the die pad portion that is opposite to the mount surface is exposed from the surface of the sealing resin layer. The second surface of the second layer is retracted from the first surface, the surface of the input inner lead portion retracted from the first surface, the surface of the output inner lead portion retracted from the first surface, and the first surface. The surface of the flat part of the inner lead part of the first region and the surface of the flat part of the inner lead part of the second region receding from the first surface. The third surface of the third layer is a flat portion of the input outer lead portion that is bent from the second surface toward the side opposite to the first surface outside the sealing resin layer. A surface, a surface of the flat portion of the output outer lead portion bent from the second surface toward the side opposite to the first surface, and a surface of the flat portion of the outer lead portion of the first region And a surface of the flat portion of the outer lead portion in the second region, and is a mounting surface to the mounting board.

図１（ａ）は第１の実施形態にかかる高周波半導体装置の模式平面図、図１（ｂ）はＡ−Ａ線に沿った模式断面図、図１（ｃ）はＢ−Ｂ線に沿った模式断面図、図１（ｄ）は模式側面図、である。1A is a schematic plan view of the high-frequency semiconductor device according to the first embodiment, FIG. 1B is a schematic cross-sectional view along the line AA, and FIG. 1C is along the line BB. FIG. 1D is a schematic side view. 図２（ａ）は第１の実施形態にかかる高周波半導体装置に用いるリードフレームの模式平面図、図２（ｂ）はＡ−Ａ線に沿った模式断面図、図２（ｃ）はＢ−Ｂ線に沿った模式断面図、である。2A is a schematic plan view of a lead frame used in the high-frequency semiconductor device according to the first embodiment, FIG. 2B is a schematic cross-sectional view along the line AA, and FIG. It is a schematic cross section along the B line. 図３は第１の実施形態にかかる高周波半導体装置の製造工程を説明する模式図であり、図３（ａ）はリードフレームの模式断面図、図３（ｂ）は高周波半導体素子をダイパッド部に接合した後の模式断面図、図３（ｃ）は高周波半導体素子電極とリード部とをワイヤボンディングした後の模式断面図、図３（ｄ）は樹脂モールド後の模式断面図、図３（ｅ）はリード曲げ加工を行った後の模式断面図、である。3A and 3B are schematic views for explaining a manufacturing process of the high-frequency semiconductor device according to the first embodiment. FIG. 3A is a schematic cross-sectional view of a lead frame, and FIG. 3B is a high-frequency semiconductor element as a die pad portion. 3C is a schematic cross-sectional view after bonding the high-frequency semiconductor element electrode and the lead portion, FIG. 3D is a schematic cross-sectional view after resin molding, and FIG. ) Is a schematic cross-sectional view after lead bending. 図４（ａ）は第１の実施形態にかかる高周波半導体装置が搭載された電子機器の模式断面図、図４（ｂ）はＣ−Ｃ線に沿った模式平面図、である。FIG. 4A is a schematic cross-sectional view of an electronic apparatus on which the high-frequency semiconductor device according to the first embodiment is mounted, and FIG. 4B is a schematic plan view taken along the line CC. 図５（ａ）は比較例にかかる高周波半導体装置が搭載された電子機器の模式断面図、図５（ｂ）はＤ−Ｄ線に沿った模式断面図、である。FIG. 5A is a schematic cross-sectional view of an electronic apparatus on which the high-frequency semiconductor device according to the comparative example is mounted, and FIG. 5B is a schematic cross-sectional view taken along the line DD.

以下、図面を参照しつつ、本発明の実施形態について説明する。
図１（ａ）は第１の実施形態にかかる高周波半導体装置の模式平面図、図１（ｂ）はＡ−Ａ線に沿った模式断面図、図１（ｃ）はＢ−Ｂ線に沿った模式断面図、図１（ｄ）は模式側面図、である。
高周波半導体装置５は、入力リード部１０と、出力リード部２０と、高周波半導体素子３０と、接地リード部４０と、封止樹脂層６０と、を有する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1A is a schematic plan view of the high-frequency semiconductor device according to the first embodiment, FIG. 1B is a schematic cross-sectional view along the line AA, and FIG. 1C is along the line BB. FIG. 1D is a schematic side view.
The high-frequency semiconductor device 5 includes an input lead portion 10, an output lead portion 20, a high-frequency semiconductor element 30, a ground lead portion 40, and a sealing resin layer 60.

入力リード部１０は、入力インナーリード部１１と入力アウターリード部１２とを有し、第１の直線９０に沿って延在する。   The input lead portion 10 has an input inner lead portion 11 and an input outer lead portion 12 and extends along a first straight line 90.

出力リード部２０は、出力インナーリード部２１と出力アウターリード部２２とを有し、第１の直線９０に沿って延在する。   The output lead portion 20 has an output inner lead portion 21 and an output outer lead portion 22, and extends along the first straight line 90.

高周波半導体素子３０は、ボンディングワイヤＢＷ１、ＢＷ２を介して、入力インナーリード部１１および出力インナーリード部２１にそれぞれ接続される。   The high-frequency semiconductor element 30 is connected to the input inner lead portion 11 and the output inner lead portion 21 via bonding wires BW1 and BW2.

接地リード部４０は、入力リード部１０に平行な第１領域４２と、出力リード部２０に平行な第２領域４４と、高周波半導体素子３０が接合されるマウント面４６ａを有するダイパッド部４６と、を有し、高周波半導体素子３０の接地電極に接続される。第１領域４２と第２領域４４とは、第１の直線９０に平行な第２の直線９１に沿って互いに反対方向に向かって延在する。なお、平面視において、第１領域４２の幅および第２領域４４の幅を、入力リード部１０の幅および出力リード２０の幅よりも広くすることにより、接地インダクタンスが低減される。このため、周波数帯域をマイクロ波まで広げることができる。   The ground lead portion 40 includes a first region 42 parallel to the input lead portion 10, a second region 44 parallel to the output lead portion 20, a die pad portion 46 having a mount surface 46 a to which the high-frequency semiconductor element 30 is bonded, And is connected to the ground electrode of the high-frequency semiconductor element 30. The first region 42 and the second region 44 extend in directions opposite to each other along a second straight line 91 parallel to the first straight line 90. In the plan view, the ground inductance is reduced by making the width of the first region 42 and the width of the second region 44 wider than the width of the input lead portion 10 and the width of the output lead 20. For this reason, a frequency band can be extended to a microwave.

封止樹脂層６０は、入力インナーリード部１１と、出力インナーリード部２１と、高周波半導体素子３０と、ダイパッド部４６のうちのマウント面４６ａの側と、を覆う。入力アウターリード部１２と、出力アウターリード部２２と、は互いに反対の方向に封止樹脂層６０から外側に向かって突出する。接地リード部４０の第１領域４２と第２領域４４とは互いに反対方向に突出する。   The sealing resin layer 60 covers the input inner lead portion 11, the output inner lead portion 21, the high-frequency semiconductor element 30, and the mount surface 46 a side of the die pad portion 46. The input outer lead portion 12 and the output outer lead portion 22 protrude outward from the sealing resin layer 60 in opposite directions. The first region 42 and the second region 44 of the ground lead part 40 protrude in opposite directions.

高周波半導体装置５の第１層は高周波半導体素子３０が接合されるマウント面４６ａと封止樹脂層の表面から露出しヒートシンクに放熱する露出面４６ｂとを有する。高周波半導体装置５の第１の面７０は、マウント面４６ａとは反対の側となるダイパッド部４６の露出面４６ｂと、露出面４６ｂの周囲に設けられた封止樹脂層６０の表面と、を含む。   The first layer of the high-frequency semiconductor device 5 has a mount surface 46a to which the high-frequency semiconductor element 30 is bonded and an exposed surface 46b that is exposed from the surface of the sealing resin layer and radiates heat to the heat sink. The first surface 70 of the high-frequency semiconductor device 5 includes an exposed surface 46b of the die pad portion 46 on the side opposite to the mount surface 46a, and a surface of the sealing resin layer 60 provided around the exposed surface 46b. Including.

高周波半導体装置５の第２層は第１の面７０から後退しかつ入力リード部１０のうち封止樹脂層６０に埋め込まれた入力インナーリード部１１と、第１の面７０から後退しかつ出力リード部２０のうち封止樹脂層６０に埋め込まれた出力インナーリード部２１と、第１の面７０から後退しかつ第１領域４２の接地インナーリード部４２ａ、４２ｂ、第２領域４４の接地インナーリード部４４ａ、４４ｂを有する。高周波半導体装置５の第２の面７２は、第１の面７０から後退しかつ入力リード部１０のうち封止樹脂層６０に埋め込まれた入力インナーリード部１１の表面と、第１の面７０から後退しかつ出力リード部２０のうち封止樹脂層６０に埋め込まれた出力インナーリード部２０の表面と、第１の面７０から後退しかつ第１領域４２の接地インナーリード部４２ａ、４２ｂの表面と、第２領域４４の接地インナーリード部４４ａ、４４ｂの表面と、を含む。   The second layer of the high-frequency semiconductor device 5 recedes from the first surface 70 and the input inner lead portion 11 embedded in the sealing resin layer 60 in the input lead portion 10 and recedes from the first surface 70 and outputs. The output inner lead portion 21 embedded in the sealing resin layer 60 in the lead portion 20, the ground inner lead portions 42 a and 42 b in the first region 42 that are retracted from the first surface 70, and the ground inner in the second region 44. Lead portions 44a and 44b are provided. The second surface 72 of the high-frequency semiconductor device 5 recedes from the first surface 70 and the surface of the input inner lead portion 11 embedded in the sealing resin layer 60 in the input lead portion 10 and the first surface 70. Of the output inner lead portion 20 embedded in the sealing resin layer 60 of the output lead portion 20 and the ground inner lead portions 42a and 42b of the first region 42 and the first inner surface 42. And the surface of the ground inner lead portions 44 a and 44 b in the second region 44.

高周波半導体装置５の第３層は高周波半導体装置５の封止樹脂層６０の外部において、第１の面７０とは反対の側に向かって折り曲げられた入力アウターリード部１２と、第１の面７０とは反対の側に向かって折り曲げられた出力アウターリード部２２と、第１領域４２の接地アウターリード部４２ｃ、４２ｄと、第２領域４４の接地アウターリード部４４ｃ、４４ｄを有する。第３の面７４は、封止樹脂層６０の外部において、第１の面７０とは反対の側に向かって折り曲げられた入力アウターリード部１２の表面と、第１の面７０とは反対の側に向かって折り曲げられた出力アウターリード部２２の表面と、第１領域４２の接地アウターリード部４２ｃ、４２ｄと、第２領域４４の接地アウターリード部４４ｃ、４４ｄの表面と、を含み、実装基板への取り付け面とされる。   The third layer of the high-frequency semiconductor device 5 includes an input outer lead portion 12 bent toward the side opposite to the first surface 70 outside the sealing resin layer 60 of the high-frequency semiconductor device 5, and a first surface. The output outer lead portion 22 is bent toward the opposite side of 70, the ground outer lead portions 42 c and 42 d in the first region 42, and the ground outer lead portions 44 c and 44 d in the second region 44. The third surface 74 is outside the sealing resin layer 60 and is opposite to the first surface 70 and the surface of the input outer lead portion 12 that is bent toward the side opposite to the first surface 70. A surface of the output outer lead portion 22 bent toward the side, ground outer lead portions 42c and 42d in the first region 42, and surfaces of the ground outer lead portions 44c and 44d in the second region 44. A mounting surface to the substrate.

入力アウターリード部１２、出力アウターリード部２２、接地リード部４０の第１領域４２、接地リード部４０の第２領域４４は、第３の面７４において実装基板に半田材などを用いて表面実装が可能である。他方、第１の面７０はダイパッド部４６の露出面４６ｂを含むので、放熱板に接合できる。すなわち、第１の実施形態にかかる高周波半導体装置５は、第２の面７２に関して、実装基板を介することなく放熱板を経由して発生熱を外部に排出できる。   The input outer lead portion 12, the output outer lead portion 22, the first region 42 of the ground lead portion 40, and the second region 44 of the ground lead portion 40 are surface-mounted using a solder material or the like on the mounting substrate on the third surface 74. Is possible. On the other hand, since the first surface 70 includes the exposed surface 46b of the die pad portion 46, it can be joined to the heat sink. That is, the high-frequency semiconductor device 5 according to the first embodiment can discharge generated heat to the outside via the heat dissipation plate without passing through the mounting substrate with respect to the second surface 72.

また、接地リード部４０は、第１の直線９０に関して、第１領域４２に対称に設けられた第１領域４３、および第２領域４４に対称に設けられた第２領域４５をさらに有することができる。   The ground lead portion 40 may further include a first region 43 provided symmetrically in the first region 42 and a second region 45 provided symmetrically in the second region 44 with respect to the first straight line 90. it can.

また、高周波半導体装置５は、第１の直線９０に対して平行に設けられ、インナーリード部とアウターリード部とを有するバイアスリード部５０、５１、５２、５３をさらに有することができる。バイアスインナーリード部の平坦部５０ａ、５１ａ、５２ａ、５３ａの一方の端部は、電界効果トランジスタなどの高周波半導体素子３０の電極に接続され電圧または電流をする。バイアスアウターリード部の平坦部５０ｂ、５１ｂ、５２ｂ、５３ｂは、封止樹脂層６０から外部に向かって突出する。   The high-frequency semiconductor device 5 can further include bias lead portions 50, 51, 52, and 53 that are provided in parallel to the first straight line 90 and have inner lead portions and outer lead portions. One end of the flat portions 50a, 51a, 52a, and 53a of the bias inner lead portion is connected to an electrode of the high-frequency semiconductor element 30 such as a field effect transistor to generate voltage or current. The flat portions 50b, 51b, 52b, and 53b of the bias outer lead portion protrude outward from the sealing resin layer 60.

たとえば、高周波半導体素子３０がＨＥＭＴ（High Electron Mobility Transistor）などの能動素子、キャパシタ、インダクタンス、マイクロストリップ線路などを含むＭＭＩＣ（Microwave Monolithic Integrated Circuit）であるものとする。ＭＭＩＣは、入力電極３０ａ、出力電極３０ｂ、バイアス印加用電極３０ｃ、３０ｄ、３０ｅ、３０ｆ、接地電極３０ｇなどを有することができる。   For example, it is assumed that the high-frequency semiconductor element 30 is an MMIC (Microwave Monolithic Integrated Circuit) including an active element such as a HEMT (High Electron Mobility Transistor), a capacitor, an inductance, a microstrip line, and the like. The MMIC can include an input electrode 30a, an output electrode 30b, bias application electrodes 30c, 30d, 30e, and 30f, a ground electrode 30g, and the like.

接地電極３０ｇは、接地リード部４０にボンディングワイヤＢＷ３などを介して接続される。なお、ＭＭＩＣ（または電界効果トランジスタなど）の裏面にバイアホール（図示せず）などを介して接地電極を設けると、ボンディングワイヤＢＷ３を設けなくともよい。なお、バイアスリード部の数は４つに限定されず、ＭＭＩＣの構成により選択すればよい。   The ground electrode 30g is connected to the ground lead part 40 via a bonding wire BW3 or the like. If a ground electrode is provided on the back surface of the MMIC (or field effect transistor or the like) via a via hole (not shown) or the like, the bonding wire BW3 may not be provided. The number of bias lead portions is not limited to four, and may be selected depending on the configuration of the MMIC.

図２（ａ）は第１の実施形態にかかる高周波半導体装置に用いるリードフレームの模式平面図、図２（ｂ）はＡ−Ａ線に沿った模式断面図、図２（ｃ）はＢ−Ｂ線に沿った模式断面図、である。
リードフレーム８０には、図２（ａ）に表される領域が、たとえば、数十個配列されている。１つの領域は、入力リード部１０、出力リード部２０、および接地リード部４０を少なくとも有する。本図において、接地リード部４０は、第１領域４２、４３と、第２領域４４、４５と、ダイパッド部４６と、を有する。 2A is a schematic plan view of a lead frame used in the high-frequency semiconductor device according to the first embodiment, FIG. 2B is a schematic cross-sectional view along the line AA, and FIG. It is a schematic cross section along the B line.
In the lead frame 80, for example, several tens of areas shown in FIG. One region has at least the input lead portion 10, the output lead portion 20, and the ground lead portion 40. In the drawing, the ground lead portion 40 includes first regions 42 and 43, second regions 44 and 45, and a die pad portion 46.

なお、リードフレームの素材となる金属薄板からリード部の不要部分が切り取られて、開口部８０ａが形成される。リードフレームの素材は、銅や銅合金などとすることができる。また、その厚さは、０．２〜０．５ｍｍなどとすることができる。   Note that an unnecessary portion of the lead portion is cut out from a thin metal plate that is a material of the lead frame, thereby forming an opening 80a. The material of the lead frame can be copper or copper alloy. Moreover, the thickness can be 0.2-0.5 mm.

図２（ｂ）に表すように、入力リード部１０および出力リード部２０は、ダイパッド部４６よりも後退した面とされる。また、図２（ｃ）に表すように、リードフレーム状態において、接地リード部４０の第１領域４３は、折り曲げ部４３ａおよび平坦部４３ｂを有し、接地リード部４０の第２領域４５は、折り曲げ部４５ａおよび平坦部４５ｂを有する。   As shown in FIG. 2B, the input lead portion 10 and the output lead portion 20 are surfaces that are recessed from the die pad portion 46. Further, as shown in FIG. 2C, in the lead frame state, the first region 43 of the ground lead portion 40 has a bent portion 43a and a flat portion 43b, and the second region 45 of the ground lead portion 40 is It has a bent part 45a and a flat part 45b.

入力リード部１０の表面、出力リード部２０の表面、接地リード部４０の第１領域４３の平坦部４３ｂの表面、および接地リード部４０の第２領域４５の平坦部４５ｂの表面は、第２の面７２を構成する。   The surface of the input lead portion 10, the surface of the output lead portion 20, the surface of the flat portion 43b of the first region 43 of the ground lead portion 40, and the surface of the flat portion 45b of the second region 45 of the ground lead portion 40 are second. The surface 72 is formed.

図３は第１の実施形態にかかる高周波半導体装置の製造工程を説明する模式図である。すなわち、図３（ａ）はリードフレームの模式断面図、図３（ｂ）は高周波半導体素子をダイパッド部に接合した後の模式断面図、図３（ｃ）は高周波半導体素子の電極とリードとをワイヤボンディングした後の模式断面図、図３（ｄ）は樹脂モールド後の模式断面図、図３（ｅ）はリード曲げ加工を行った後の模式断面図、である。   FIG. 3 is a schematic diagram for explaining a manufacturing process of the high-frequency semiconductor device according to the first embodiment. 3A is a schematic cross-sectional view of the lead frame, FIG. 3B is a schematic cross-sectional view after bonding the high-frequency semiconductor element to the die pad portion, and FIG. 3C is an electrode and leads of the high-frequency semiconductor element. 3D is a schematic cross-sectional view after wire bonding, FIG. 3D is a schematic cross-sectional view after resin molding, and FIG. 3E is a schematic cross-sectional view after lead bending.

図３（ａ）〜（ｃ）は、図２（ａ）のＡ−Ａ線に沿った断面を表す。リードフレーム８０の表面に金メッキや銀メッキを行うと、チップマウントやワイヤボンディングが容易となる（図３（ａ））。   3A to 3C show cross sections taken along the line AA in FIG. When the surface of the lead frame 80 is plated with gold or silver, chip mounting or wire bonding is facilitated (FIG. 3A).

次に、図３（ｂ）に表すように、ＨＥＭＴやＭＭＩＣなどの高周波半導体素子３０をダイパッド部４６のマウント面４６ａに、ＡｕＳｎ半田材（融点：約２８２℃）などを用いて接合する。高周波半導体素子３０には、たとえば、入力電極３０ａや出力電極３０ｂが設けられている。   Next, as shown in FIG. 3B, the high-frequency semiconductor element 30 such as HEMT or MMIC is bonded to the mount surface 46 a of the die pad portion 46 using AuSn solder material (melting point: about 282 ° C.) or the like. The high frequency semiconductor element 30 is provided with, for example, an input electrode 30a and an output electrode 30b.

次に、図３（ｃ）に表すように、高周波半導体素子３０の入力電極３０ａと、入力リード部１０と、をボンディングワイヤＢＷ１で接続する。さらに、高周波半導体素子３０の出力電極３０ｂと、出力リード部２０と、をボンディングワイヤＢＷ２で接続する。   Next, as shown in FIG. 3C, the input electrode 30a of the high-frequency semiconductor element 30 and the input lead portion 10 are connected by a bonding wire BW1. Further, the output electrode 30b of the high-frequency semiconductor element 30 and the output lead portion 20 are connected by a bonding wire BW2.

次に、図３（ｄ）に表すように、リードフレームを金型に挿入し熱硬化性のエポキシ樹脂などを用いて成型し熱硬化する。なお、図３（ｄ）、（ｅ）は、リードフレーム８０の上下を反転して表されている。ダイパッド部４６の露出面４６ｂが、封止樹脂層６０から露出するように樹脂が成型される。ダイパッド部４６の露出面４６ｂを、高周波半導体装置５の第１の面７０とする。露出面４６ｂを囲む封止樹脂層６０の表面を第１の面７０と共通にすると、放熱板の取り付けが容易となる。   Next, as shown in FIG. 3D, the lead frame is inserted into a mold, molded using a thermosetting epoxy resin, etc., and thermally cured. 3D and 3E are represented by inverting the top and bottom of the lead frame 80. FIG. Resin is molded so that the exposed surface 46 b of the die pad portion 46 is exposed from the sealing resin layer 60. The exposed surface 46 b of the die pad unit 46 is a first surface 70 of the high-frequency semiconductor device 5. When the surface of the sealing resin layer 60 surrounding the exposed surface 46b is made common with the first surface 70, the heat sink can be easily attached.

次に、図３（ｅ）に表すように、入力リード部１０と、出力リード部２０と、接地リード部４０のそれぞれのアウターリード部を折り曲げて第３の面７４を形成する。第３の面７４は、第２の面７２から第１の面７０とは反対の側に向かって折り曲げられた入力アウターリード部１２の平坦部１２ｂの表面と、第２の面７２から第１の面７０とは反対の側に向かって折り曲げられた出力アウターリード部２２の平坦部２２ｂの表面と、第１領域４２のアウターリード部の平坦部４２ｄの表面と、第２領域４４のアウターリード部の平坦部４４ｄの表面と、を含む。このようにすると、第３の面７４を実装基板へ表面実装可能な取り付け面とすることができる。   Next, as illustrated in FIG. 3E, the outer lead portions of the input lead portion 10, the output lead portion 20, and the ground lead portion 40 are bent to form the third surface 74. The third surface 74 includes a surface of the flat portion 12 b of the input outer lead portion 12 that is bent from the second surface 72 toward the side opposite to the first surface 70, and a first surface from the second surface 72. The surface of the flat portion 22b of the output outer lead portion 22 bent toward the side opposite to the surface 70, the surface of the flat portion 42d of the outer lead portion of the first region 42, and the outer lead of the second region 44 And the surface of the flat part 44d of the part. If it does in this way, the 3rd surface 74 can be made into the attachment surface which can be surface-mounted to a mounting substrate.

図４（ａ）は第１の実施形態にかかる高周波半導体装置が搭載された電子機器の模式断面図、図４（ｂ）はＣ−Ｃ線に沿った模式平面図、である。
図４（ａ）は、Ｂ−Ｂ線に沿った模式断面図である（但し、放熱板９９を除く）。本実施形態の電子機器は、第１の実施形態の高周波半導体装置５と、高周波半導体装置５が取り付けられた実装基板１００と、高周波半導体装置５のダイパッド部４６の露出面４６ｂと接合された放熱板９９と、を有する。 FIG. 4A is a schematic cross-sectional view of an electronic apparatus on which the high-frequency semiconductor device according to the first embodiment is mounted, and FIG. 4B is a schematic plan view taken along the line CC.
Fig.4 (a) is a schematic cross section along the BB line (however, except the heat sink 99). The electronic apparatus according to the present embodiment includes the high-frequency semiconductor device 5 according to the first embodiment, the mounting substrate 100 to which the high-frequency semiconductor device 5 is attached, and the heat radiation bonded to the exposed surface 46b of the die pad portion 46 of the high-frequency semiconductor device 5. And a plate 99.

図４（ｂ）に表すように、実装基板１００は、誘電体層１０２と、入力導電層１０４、出力導電層１０６と、上面接地導電層１０８、下面接地導電層１１０と、を有する。また、実装基板１００は、誘電体層１０２に設けられたスルーホール１０２ａ内に充填され、上面接地導電層１０８および下面接地導電層１１０にそれぞれ接続された金属層１０５（図４（ｂ）では４つの領域を含む）をさらに有してもよい。   As shown in FIG. 4B, the mounting substrate 100 includes a dielectric layer 102, an input conductive layer 104, an output conductive layer 106, an upper surface ground conductive layer 108, and a lower surface ground conductive layer 110. In addition, the mounting substrate 100 is filled in a through hole 102a provided in the dielectric layer 102, and is connected to the upper surface ground conductive layer 108 and the lower surface ground conductive layer 110, respectively (4 in FIG. 4B). One region).

ダイパッド部４６に接続された第１領域４２のアウターリード部の平坦部４２ｄ、４３ｄは、実装基板１００の上面接地導電層１０８に半田材１０９などで接合され、さらに金属層１０５を介して下面接地導電層１１０に接続される。また、ダイパッド部４６に接続された第２領域４４のアウターリード部の平坦部４４ｄ、４５ｄは、実装基板１００の上面接地導電層１０８に半田材１０９などで接合され、さらに金属層１０５を介して下面接地導電層１１０に接続される。このため、ダイパッド部４６は、電子機器の接地電位となる。   The flat portions 42 d and 43 d of the outer lead portion of the first region 42 connected to the die pad portion 46 are joined to the upper surface ground conductive layer 108 of the mounting substrate 100 by the solder material 109 or the like, and further, the lower surface ground via the metal layer 105. Connected to the conductive layer 110. Further, the flat portions 44 d and 45 d of the outer lead portion of the second region 44 connected to the die pad portion 46 are joined to the upper surface ground conductive layer 108 of the mounting substrate 100 by a solder material 109 or the like, and further through the metal layer 105. Connected to the bottom ground conductive layer 110. For this reason, the die pad unit 46 becomes the ground potential of the electronic device.

すなわち、高周波半導体装置５の接地リード部４０と、電子機器の接地面となる実装基板１００の下面接地導電層１１０と、の間の距離を短縮できる。また、実装基板１００にはマイクロストリップ線路を含む整合回路などを設けることができる。このため、高周波半導体装置５の接地インダクタンスが十分に低減され、マイクロ波特性の低下が抑制可能である。入力アウターリード部１２の平坦部１２ｂは、実装基板１００の入力導電層１０４に接続され、出力アウターリード部２２の平坦部２２ｂは、実装基板１００の出力導電層１０６に接続される。   That is, the distance between the ground lead portion 40 of the high-frequency semiconductor device 5 and the lower surface ground conductive layer 110 of the mounting substrate 100 that becomes the ground surface of the electronic device can be shortened. The mounting substrate 100 can be provided with a matching circuit including a microstrip line. For this reason, the ground inductance of the high-frequency semiconductor device 5 is sufficiently reduced, and the deterioration of the microwave characteristics can be suppressed. The flat portion 12 b of the input outer lead portion 12 is connected to the input conductive layer 104 of the mounting substrate 100, and the flat portion 22 b of the output outer lead portion 22 is connected to the output conductive layer 106 of the mounting substrate 100.

他方、第１の面７０を構成するダイパッド部４６の露出面４６ｂには放熱板９９が接続可能であるので発生熱ＨＦが効率よく外部に排出される。   On the other hand, since the heat sink 99 can be connected to the exposed surface 46b of the die pad portion 46 constituting the first surface 70, the generated heat HF is efficiently discharged to the outside.

図５（ａ）は比較例にかかる高周波半導体装置が搭載された電子機器の模式断面図、図５（ｂ）はＤ−Ｄ線に沿った模式断面図、である。
比較例の電子機器は、高周波半導体装置２０５と、高周波半導体装置２０５が取り付けられた実装基板２００と、高周波半導体装置２０５のダイパッド部２４６の露出面２４６ｂと接合された放熱板２９９と、を有する。 FIG. 5A is a schematic cross-sectional view of an electronic apparatus on which the high-frequency semiconductor device according to the comparative example is mounted, and FIG. 5B is a schematic cross-sectional view taken along the line DD.
The electronic device of the comparative example includes a high-frequency semiconductor device 205, a mounting substrate 200 to which the high-frequency semiconductor device 205 is attached, and a heat dissipation plate 299 joined to the exposed surface 246b of the die pad portion 246 of the high-frequency semiconductor device 205.

高周波半導体装置２０５は、入力リード部２１９と、出力リード部２２１と、高周波半導体素子１３０と、ダイパッド部２４６と、封止樹脂層２６０と、を有する。ダイパッド部２４６の封止樹脂層２６０からの露出面２４６ｂは、実装基板２００の側とされる。ダイパッド部２４６の露出面２４６ｂ、入力リード部２１９、出力リード部２２１、およびバイアスリード部２５０、２５１、２５２、２５３が半田材２２０により実装基板２００に接合される。   The high frequency semiconductor device 205 includes an input lead portion 219, an output lead portion 221, a high frequency semiconductor element 130, a die pad portion 246, and a sealing resin layer 260. An exposed surface 246 b of the die pad portion 246 from the sealing resin layer 260 is the mounting substrate 200 side. The exposed surface 246 b of the die pad portion 246, the input lead portion 219, the output lead portion 221, and the bias lead portions 250, 251, 252, and 253 are joined to the mounting substrate 200 by the solder material 220.

実装基板２００は、誘電体層２０２と、入力導電層２０４と、出力導電層２０６と、ダイパッド接続導電層２０７、下面接地導電層２１０と、誘電体層２０２のスルーホール内に充填されダイパッド接続導電層２０７および下面接地導電層２１０にそれぞれ接続された金属層２１４と、を有する。   The mounting substrate 200 is filled in the through holes of the dielectric layer 202, the input conductive layer 204, the output conductive layer 206, the die pad connection conductive layer 207, the lower surface ground conductive layer 210, and the dielectric layer 202, and the die pad connection conductive. And a metal layer 214 connected to each of the layer 207 and the lower surface ground conductive layer 210.

ダイパッド部２４６は、金属層２１４を介して、実装基板２００の下面接地導電層（電子機器の接地面とされる）２１０に接続可能なので接地リード部が設けられない。   Since the die pad portion 246 can be connected to the lower surface ground conductive layer (used as a ground surface of the electronic device) 210 of the mounting substrate 200 through the metal layer 214, no ground lead portion is provided.

高周波半導体素子１３０における発生熱ＨＦは、実装基板２００の金属層２１４を通り、放熱板２９９から外部に排出される。しかし、誘電体層２０２に設けられるスルーホールのサイズには上限があり、金属層２１４をダイパッド部２４６のサイズよりも大きくすることは困難である。このため、放熱性は、第１の実施形態の高周波半導体装置が搭載された電子機器よりも劣る。   The generated heat HF in the high-frequency semiconductor element 130 passes through the metal layer 214 of the mounting substrate 200 and is discharged from the heat sink 299 to the outside. However, the size of the through hole provided in the dielectric layer 202 has an upper limit, and it is difficult to make the metal layer 214 larger than the size of the die pad portion 246. For this reason, heat dissipation is inferior to the electronic device in which the high-frequency semiconductor device of the first embodiment is mounted.

これに対して、本実施形態の電子機器では、封止樹脂層６０から露出するダイパッド部４６の露出面４６ｂは、実装基板１００への取り付け面とされる封止樹脂層６０の反対の側とされる。また、接地リード部４０は２つの段差を有する第１領域４２および第２領域４４を有するので、ダイパッド部４６と実装基板１００の下面接地導電層１１０との間の距離を短縮し接地インダクタンスを低減できる。   On the other hand, in the electronic device of the present embodiment, the exposed surface 46b of the die pad portion 46 exposed from the sealing resin layer 60 is opposite to the side opposite to the sealing resin layer 60 that is an attachment surface to the mounting substrate 100. Is done. In addition, since the ground lead part 40 includes the first region 42 and the second region 44 having two steps, the distance between the die pad part 46 and the lower surface ground conductive layer 110 of the mounting substrate 100 is shortened to reduce the ground inductance. it can.

本実施形態によれば、放熱性が良好で表面実装が容易な高周波半導体装置が提供される。高周波半導体装置は樹脂成型構造であり、量産性に富む。このため、電子機器の価格低減が可能である。これらの高周波半導体装置は、たとえば、携帯電子機器や携帯電話基地局などに広く用いることができる。   According to the present embodiment, a high-frequency semiconductor device with good heat dissipation and easy surface mounting is provided. The high-frequency semiconductor device has a resin molding structure and is rich in mass productivity. For this reason, the price of electronic equipment can be reduced. These high-frequency semiconductor devices can be widely used, for example, in portable electronic devices and mobile phone base stations.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

５ 高周波半導体装置、１０ 入力リード部、１１ 入力インナーリード部、１２ 入力アウターリード部、２０ 出力リード部、２１ 出力インナーリード部、２２ 出力アウターリード部、３０ 高周波半導体素子、３０ｇ 接地電極、４０ 接地リード部、４２、４３ 第１領域、４４、４５ 第２領域、４２ｂ、４３ｂ インナーリード部の平坦部、４２ｄ、４３ｄ ４４ｄ、４５ｄ アウターリード部の平坦部、４３ｂ、４５ｂ インナーリード部の平坦部、４６ ダイパッド部、４６ａ マウント面、４６ｂ 露出面、５０、５１、５２、５３ バイアスリード部、５０ａ、５１ａ、５２ａ、５３ａ バイアスインナーリードの平坦部、５０ｂ、５１ｂ、５２ｂ、５２ｄ バイアスアウターリード部の平坦部、６０ 封止樹脂層、７０ 第１の面、７２ 第２の面、７４ 第３の面、９０ 第１の直線、９１ 第２の直線、９９ 放熱板、１００ 実装基板   5 High-frequency semiconductor device, 10 Input lead portion, 11 Input inner lead portion, 12 Input outer lead portion, 20 Output lead portion, 21 Output inner lead portion, 22 Output outer lead portion, 30 High-frequency semiconductor element, 30 g Ground electrode, 40 Ground Lead part, 42, 43 First region, 44, 45 Second region, 42b, 43b Flat part of inner lead part, 42d, 43d 44d, 45d Flat part of outer lead part, 43b, 45b Flat part of inner lead part, 46 Die pad portion, 46a Mount surface, 46b Exposed surface, 50, 51, 52, 53 Bias lead portion, 50a, 51a, 52a, 53a Flat portion of bias inner lead, 50b, 51b, 52b, 52d Flat portion of bias outer lead portion Part, 60 sealing resin layer, 70 1st surface 72 second surface 74 third surface, 90 a first straight line, 91 second straight line 99 radiating plate, 100 mounting board

Claims (5)

入力インナーリード部と入力アウターリード部とを有し、第１の直線に沿って延在する入力リード部と、
出力インナーリード部と出力アウターリード部とを有し、前記第１の直線に沿って延在する出力リード部と、
前記入力インナーリード部および前記出力インナーリード部にそれぞれ接続された高周波半導体素子と、
前記入力リード部に平行な第１領域と、前記出力リード部に平行な第２領域と、前記高周波半導体素子が接合されるマウント面を有するダイパッド部と、を有し、前記高周波半導体素子の接地電極に電気的に接続される接地リード部であって、前記第１領域と前記第２領域とは、前記第１の直線に平行な第２の直線に沿って延在する、接地リード部と、
前記入力インナーリード部と、前記出力インナーリード部と、前記高周波半導体素子と、前記ダイパッド部のうちの前記マウント面の側と、を覆う封止樹脂層であって、前記入力アウターリード部と前記出力アウターリード部とは互いに反対の方向に突出し、前記接地リードの前記第１領域と前記第２領域とは互いに反対方向に突出した、封止樹脂層と、
を備え、
第１の面は、前記マウント面とは反対の側となる前記ダイパッド部の露出面と、前記露出面の周囲に設けられた前記封止樹脂層の表面と、を含み、
第２の面は、前記第１の面から後退した入力インナーリード部の表面と、前記第１の面から後退した出力インナーリード部の表面と、前記第１の面から後退した前記第１領域のインナーリード部の平坦部の表面と、前記第１の面から後退した前記第２領域のインナーリード部の平坦部の表面と、を含み、
第３の面は、前記封止樹脂層の外部において、前記第２の面から前記第１の面とは反対の側に向かって折り曲げられた前記入力アウターリード部の平坦部の表面と、前記第２の面から前記第１の面とは反対の側に向かって折り曲げられた出力アウターリード部の平坦部の表面と、前記第１領域のアウターリード部の平坦部の表面と、前記第２領域のアウターリード部の平坦部の表面と、を含み、実装基板への取り付け面とされる、高周波半導体装置。 An input lead portion having an input inner lead portion and an input outer lead portion and extending along the first straight line;
An output lead portion having an output inner lead portion and an output outer lead portion and extending along the first straight line;
A high-frequency semiconductor element connected to each of the input inner lead portion and the output inner lead portion;
A first region parallel to the input lead portion; a second region parallel to the output lead portion; and a die pad portion having a mount surface to which the high-frequency semiconductor element is bonded, and grounding the high-frequency semiconductor element A ground lead portion electrically connected to the electrode, wherein the first region and the second region extend along a second straight line parallel to the first straight line; ,
A sealing resin layer covering the input inner lead portion, the output inner lead portion, the high-frequency semiconductor element, and the mount surface side of the die pad portion, the input outer lead portion and the An encapsulating resin layer protruding in opposite directions to the output outer lead portion, and the first region and the second region of the ground lead protruding in opposite directions;
With
The first surface includes an exposed surface of the die pad portion on the side opposite to the mount surface, and a surface of the sealing resin layer provided around the exposed surface,
The second surface includes a surface of the input inner lead portion that is retracted from the first surface, a surface of the output inner lead portion that is retracted from the first surface, and the first region that is retracted from the first surface. A surface of the flat portion of the inner lead portion, and a surface of the flat portion of the inner lead portion of the second region recessed from the first surface,
The third surface is a surface of the flat portion of the input outer lead portion that is bent from the second surface toward the side opposite to the first surface outside the sealing resin layer, and A surface of the flat portion of the output outer lead portion bent from the second surface toward the side opposite to the first surface, a surface of the flat portion of the outer lead portion of the first region, and the second surface And a surface of the flat portion of the outer lead portion of the region, the high-frequency semiconductor device being a mounting surface to the mounting substrate. 前記接地リード部の前記第１領域および前記第２領域は、前記第１の直線に関して、対称に設けられた２つをそれぞれ含む請求項１記載の高周波半導体装置。   2. The high-frequency semiconductor device according to claim 1, wherein the first region and the second region of the ground lead part each include two symmetrically provided with respect to the first straight line. 前記高周波半導体素子は、電界効果トランジスタである請求項１または２に記載の高周波半導体装置。   The high-frequency semiconductor device according to claim 1, wherein the high-frequency semiconductor element is a field effect transistor. 前記封止樹脂層に覆われたバイアスインナーリード部と、前記封止樹脂層から突出したバイアスアウターリード部とを有し、前記第１の直線に平行に延在するバイアスリード部をさらに備え、
前記高周波半導体素子は、電界効果トランジスタを含むマイクロ波集積回路であり、
前記バイアスインナーリード部は前記電界効果トランジスタに接続され、
前記第２の面は、前記第１の面から後退した前記バイアスインナーリード部の平坦部の表面をさらに含み、
前記第３の面は、前記第２の面から前記第１の面とは反対の側に向かって折り曲げられた前記バイアスアウターリード部の平坦部の表面をさらに含む、請求項１または２に記載の高周波半導体装置。 A bias inner lead portion covered with the sealing resin layer and a bias outer lead portion protruding from the sealing resin layer, further comprising a bias lead portion extending in parallel with the first straight line;
The high-frequency semiconductor element is a microwave integrated circuit including a field effect transistor,
The bias inner lead is connected to the field effect transistor;
The second surface further includes a surface of a flat portion of the bias inner lead portion that is recessed from the first surface,
The said 3rd surface further contains the surface of the flat part of the said bias outer lead part bent toward the opposite side to the said 1st surface from the said 2nd surface. High frequency semiconductor device. 請求項１〜４のいずれか１つに記載の高周波半導体装置と、
前記高周波半導体装置が取り付けられた実装基板と、
前記高周波半導体装置の前記ダイパッド部の前記露出面に接合された放熱板と、
を備えた電子機器。 A high-frequency semiconductor device according to any one of claims 1 to 4,
A mounting substrate to which the high-frequency semiconductor device is attached;
A heat sink bonded to the exposed surface of the die pad portion of the high-frequency semiconductor device;
With electronic equipment.
JP2016097860A 2016-05-16 2016-05-16 High-frequency semiconductor device and electronic equipment Pending JP2017208377A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210078533A (en) 2018-12-05 2021-06-28 미쓰비시덴키 가부시키가이샤 semiconductor device and antenna device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210078533A (en) 2018-12-05 2021-06-28 미쓰비시덴키 가부시키가이샤 semiconductor device and antenna device
US11393778B2 (en) 2018-12-05 2022-07-19 Mitsubishi Electric Corporation Semiconductor device and antenna device
DE112018008188B4 (en) 2018-12-05 2024-03-21 Mitsubishi Electric Corporation Semiconductor device and antenna device

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