JP2017194769A - Device storing information on work ram in non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain, when supply of power to a work RAM is blocked, the details of the work RAM in a minimum preliminary power supply ensuring a chip operation of performing back-up processing and a circuit device related thereto.SOLUTION: There is provided a processor for a game machine, a chip, and a device related thereto, the processor provided with a non-volatile memory and transmitting the details of the work RAM to the non-volatile memory when supply of power to the work RAM is blocked.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an apparatus for storing work RAM information in a nonvolatile memory.

  Conventionally, in a processor for a gaming machine, a chip, a substrate, and a device related thereto used in a pachinko machine or a pachislot machine also called a swivel type gaming machine, as a work RAM (also called a main memory), a volatile RAM has been used.

  In a gaming machine, it has been desired that the contents of the work RAM be maintained without being lost when a power interruption occurs in which no power is instantaneously supplied from the power supply. Conventionally, a standby power supply has been used to maintain the contents of the work RAM when the power is cut off. The contents of the work RAM could be maintained by supplying power to the work RAM when the main power was cut off.

  However, if the amount of power consumed by the work RAM exceeds the power supply capacity of the standby power supply, the supply of power is delayed, and the contents of the work RAM are lost. For this reason, a power supply capacity of a standby power supply having a large capacity, such as a supercapacitor, has been used. In addition, in a processor for a gaming machine, a chip, a substrate, and a device related thereto, a configuration in which a standby power supply and a circuit device related thereto are essential is required.

  When the power supply to the work RAM is cut off, the contents of the work RAM are maintained by a minimum standby power supply that guarantees the chip operation for performing the backup process and a circuit device related thereto.

  A gaming machine apparatus according to an embodiment of the present invention includes a backup processing unit, a volatile RAM used as a main memory, a non-volatile memory that stores part or all of the contents of the volatile RAM as a backup, and a gaming machine At least a first program that operates in a security mode that is a mode that performs at least processing related to the security of the device, and a second program that operates in a user mode that is a mode that performs at least lottery and / or presentation of gaming machines are stored. And a power failure detection circuit that detects that power supply in the gaming machine device has been interrupted, and the backup processing unit detects that the power failure detection circuit has detected power supply interruption. Based on the first program instruction or the second program instruction, a part or all of the contents of the volatile RAM is nonvolatile. When the power is supplied to the gaming machine device, the backup processing unit operates based on the instruction of the first program, and after the mode shifts from the security mode to the user mode, the user program Can operate based on instructions.

  In a processor for a gaming machine, a chip, and a device related thereto, a nonvolatile memory is provided, and when the power supply to the work RAM is cut off, the contents of the work RAM are transferred to the nonvolatile memory.

The conventional board | substrate for game machines is shown. 1 shows a gaming machine substrate according to an embodiment of the present invention. It is a flowchart which shows execution of backup of the information of RAM based on the instruction | indication of a user program by a processor core, and execution of loading to RAM of backed up information. It is a flowchart which shows execution of backup of the information of RAM based on the instruction | indication of a user program by a processor core and a dedicated logic circuit, and execution of the load to RAM of backed up information. It is a flowchart which shows execution of backup of the information of RAM based on the instruction | indication of the program which operate | moves in security modes, such as a boot program, and loading of the backed-up information to RAM by a processor core. It is a flowchart which shows execution of backup of the information of RAM based on the instruction | indication of the program which operate | moves in security modes, such as a boot program, and loading of the backed-up information to RAM by a processor core and a dedicated logic circuit . It is a flowchart which shows execution of the backup of the information of RAM based on the command of the program which operate | moves in backup mode by a processor core. It is a flowchart which shows execution of backup of the information of RAM based on the command of the program which operate | moves in backup mode by a processor core and a dedicated logic circuit. It is a flowchart which shows execution of the backup of the information of RAM based on the processing sequence of the dedicated logic which operate | moves in backup mode by a dedicated logic circuit.

Prior Art FIG. 1 shows a conventional gaming machine substrate. The substrate 100 has a chip 105 and a main power supply 135. The chip 105 includes a processor core 110, a peripheral circuit 115, a ROM 120, a RAM 125, a mode control circuit 127, and a power supply switching circuit 130. The power supply switching circuit 130 includes a power interruption detection circuit 137. The processor core 110, the peripheral circuit 115, the ROM 120, the RAM 125, and the mode control circuit 127 are connected via a bus. The power supply switching circuit 130 is connected to the RAM 125.

  The main power supply 135 is connected to the power supply switching circuit 130. The main power supply 135 supplies power to the chip 105 and is further connected to the capacitor 145 through the diode 140. The power interruption detection circuit 137 obtains power supply from the main power supply line 160. When the main power supply 135 stops supplying power (power is cut off), the power cut detection circuit 137 can detect the power cut by monitoring the voltage level of the main power supply line 160.

  When the main power supply 135 supplies power, the capacitor 145 is charged and charges are stored. Thereby, the capacitor 145 operates as a standby power supply by using the stored charge. When the main power supply 135 stops supplying power (power is cut off) and the power interruption detection circuit 137 detects power supply cut-off, the power supply switching circuit 130 changes the power supply line from the main power supply line 160 to the backup power supply line 165. Switch to. As a result, even if the main power supply 135 is disconnected, power is supplied from the capacitor 145 to the RAM 125 and power is supplied to the RAM 125, so that the contents of the RAM 125 are maintained.

  On the other hand, there is a limit to the amount of charge stored in the capacitor 145 that is a standby power supply. When the amount of power consumed by the RAM 125 exceeds the amount of power based on the amount of charge stored in the capacitor 145, the supply of power is delayed and the contents of the RAM 125 are lost.

Examples according to the present invention (configuration and representative implementation examples)
FIG. 2 shows a gaming machine substrate according to an embodiment of the present invention. The substrate 200 of the present invention includes a chip 205 and a main power source 235. The chip 205 includes a processor core 210, a peripheral circuit 215, a ROM 220, a volatile memory RAM 225, a power interruption detection circuit 237, a diode 260, and a capacitor 262, similar to the chip 105 of the prior art. In one embodiment, the power interruption detection circuit 237, the diode 260, and the capacitor 262 may be disposed on a substrate outside the chip 205 or a power supply device outside the substrate. The chip 205 of the present invention further includes a nonvolatile memory 230, an interrupt reset circuit 240, a mode control circuit 245, and a dedicated logic circuit 250. The processor core 210, peripheral circuit 215, ROM 220, RAM 225, power interruption detection circuit 237, nonvolatile memory 230, interrupt reset circuit 240, mode control circuit 245, and dedicated logic circuit 250 are connected via a bus. The RAM 225 is used as a work RAM (also called main memory). The ROM 220 stores at least a boot program and a user program. The chip 205 starts to operate in the security mode after reset, performs an initial operation process of the processor core 210, and executes a boot program for confirming by the processor core 210 whether the security of the chip 205 is established. When the processor core 210 confirms that the security of the chip 205 is established, the mode of the chip is switched from the security mode to the user mode, and the program to be executed is switched from the boot program to the user program. The user program is a program for controlling a lottery or presentation in a gaming machine.

  The processor core 210 can transfer the content stored in the RAM 225 to the nonvolatile memory 230. The peripheral circuit 215 is a peripheral circuit related to the chip 205, and receives instructions from the processor core 210 and executes various processes. In one embodiment, the peripheral circuit 215 may be an interface that sends instructions or data to one or more peripheral circuits that are peripheral circuits of the chip 205 and / or the substrate 200, and Or, commands and data are received from one or more peripheral circuits.

  The power interruption detection circuit 237 detects the power supply from the main power supply 235 by monitoring the voltage level of the power supply line, and notifies the interrupt reset circuit 240 that the power supply has been cut off. To do. When receiving the notification, the interrupt reset circuit 240 transmits an interrupt signal to the processor core 210 so that the processor core 210 starts interrupt processing.

  The mode control circuit 245 is a circuit that controls a predetermined mode in which the chip 205 is operating, determines a chip mode such as a security mode, a user mode, and a backup mode, and determines the operation of the chip 205. The security mode is a mode for performing an initial setting of the chip 205 and performing a security check of the user program. The user mode is a mode for executing a user program. The backup mode is a mode in which information stored in the RAM 225 is backed up to the nonvolatile memory 230. Although details will be described later, in the backup mode, power is supplied only to circuits and devices necessary for backup. In one embodiment, the backup process may be performed without using the backup mode.

  The nonvolatile memory 230 stores part or all of the contents stored in the RAM 225 as a backup while the power supply from the main power supply 235 is cut off. The dedicated logic circuit 250 is activated in accordance with an instruction from the processor core 210 and can transfer the content stored in the RAM 225 to the nonvolatile memory 230 without going through the processor core 210. Therefore, the backup processing from the RAM 225 to the nonvolatile memory 230 can be performed by the processor core 210 or the dedicated logic circuit 250.

  Therefore, in the gaming machine according to the present embodiment, when the power interruption detection circuit 237 detects that the power supply from the main power supply has been cut off due to a voltage drop, the power interruption detection circuit 237 notifies the interruption reset circuit 240 of the detection. The interrupt reset circuit 240 transmits an interrupt signal to the processor core 210. In response to receiving the interrupt signal, the processor core 210 executes a backup processing instruction for backing up the contents of the RAM 225 to the nonvolatile memory 230. In one embodiment, the processor core 210 may transmit a backup process command to the dedicated logic circuit 250, and the dedicated logic circuit 250 may execute the backup process in response to receiving the command. Good. In these embodiments, as will be understood by those skilled in the art, the chip 205 may not have the dedicated logic circuit 250 when the processor core 210 performs backup processing by a program.

  In another embodiment, when the processor core 210 or the dedicated logic circuit 250 backs up the contents of the RAM 225, the processor core 210 or the dedicated logic circuit 250 stores a calculated value that is a value calculated from the data in the nonvolatile memory 230 together with the data to be backed up. May be. Thus, in a later step, the value obtained by calculating the data to be backed up stored in the nonvolatile memory 230 is compared with the calculated value stored in the nonvolatile memory 230. It can be ensured that the stored information is not destroyed. For the calculation, various conceivable calculation methods such as a sum value, a hash value, and a bit operation can be used.

  In one embodiment, chip 205 may itself be a processor. In one embodiment, the chip 205 may be implemented as a single chip. In this case, the chip 205 is also called a one-chip microcomputer.

  Hereinafter, backup processing in the security mode or the user mode will be described. Here, in the gaming machine, there are at least two modes in which the chip 205 operates. The first is a security mode, and the second is a user mode. Regarding the security mode, when a power interruption, power-on reset, system reset, or the like is performed in the gaming machine or the board 200, the chip 205 initializes the chip 205 and determines whether security has been established. The rationality of the user program in the user ROM 220 is checked and confirmed. The rationality check of a user program is a check that is performed using a security code (checksum, hash value, etc.) that has been calculated and stored in advance. It is calculated and checked by comparing the recalculated value with the security code. When the security is established, the gaming machine or the board 200 is in the user mode, and control of the gaming machine can be started by the user program. The user program controls the lottery and production of gaming machines.

  The security mode is a mode for executing a boot program for performing chip initialization and user ROM security check, and the user mode is a mode for executing a user program. In each mode, a circuit that operates with different mapping addresses for the ROM and RAM processors has different operating conditions in each mode. In the security mode, the user ROM is mapped to an address in the data area and handled as data. In the user mode, the user ROM is mapped to a processor address as a user program and executed.

Example 1 (User program control by processor)
FIG. 3 is a flowchart showing execution of backup of RAM information and loading of backed-up information into the RAM based on instructions of the user program by the processor core. First, the power interruption detection circuit 237 detects that the main power supply 235 has stopped supplying power (power interruption), and notifies the interrupt reset circuit 240 that the power supply has been detected. The signal is transmitted to the processor core 210, and the processor core 210 receives the interrupt signal (step 302). The processor core 210 determines whether or not to execute backup processing (step 304). In this determination, for example, it is determined whether the flag of the value set in the user definition area of the user program is on or off. For example, when the flag is on, the processor core 210 determines to execute the backup process. In another embodiment, whether or not to execute a backup process is defined in a user program instruction, and the processor 210 may determine this definition. The user definition area may be a program management area prepared for writing a user definition and a security code separately from the user program.

  If it is determined in step 304 that the backup process is to be executed, the processor core 210 executes the backup process based on the instruction of the user program stored in the ROM. First, the processor core 210 stores part or all of the information in the RAM 225 in the nonvolatile memory 230 (step 306).

  The processor core 210 performs a calculation based on part or all of the information in the RAM 225, obtains a calculated value, and stores it in the nonvolatile memory 230 (step 308). Thereby, the nonvolatile memory 230 stores the calculated value together with a part or all of the information in the RAM 225. The calculation value includes a checksum value obtained by adding a part or all of the information in the RAM 225, a value obtained by hash calculation for a part or all of the information in the RAM 225, and a part or all of the bits in the information in the RAM 225. It can be a value obtained by a logical operation of expression, and may be a value obtained by various other methods that can be understood by those skilled in the art. In step 308, the calculation is described as a checksum for the sake of easy understanding of the explanation. The processor core 210 ends the backup process and pauses the operation (step 310). In one embodiment, the suspension of operation may be realized by not supplying power.

  Here, the main power supply 235 does not supply power until the operation of the processor core 210 stops after the power interruption is detected (step 302). The backup process is performed using the charge stored in the capacitor 262. Therefore, the amount of charge to be stored in the capacitor 262 needs to be larger than the amount corresponding to the amount of power required to execute the backup process.

  When it is determined in step 304 that the backup process is not executed, the processor core 210 pauses the operation without executing the backup process (step 310).

  When the main power supply 235 returns from power-off or powers on after a certain time of power-off, the processor core 210 operates in the security mode (step 312). In the security mode, the processor core 210 performs a security check or the like based on a boot program instruction stored in the ROM 220. The chip 205 and / or the mode control circuit 245 shifts the mode from the security mode to the user mode (step 314). In the user mode, the processor core 210 reads a user program stored in the ROM 220 and executes a process related to loading backup data based on the user program.

  The processor core 210 determines whether or not to execute backup data load processing (step 316). In this determination, for example, it is determined whether the flag of the value set in the user definition area of the user program is on or off. For example, when the flag is on, the processor core 210 determines to execute the backup data loading process. In another embodiment, whether or not to execute a backup process is defined in a user program instruction, and the processor 210 may determine this definition.

  If it is determined in step 316 that the backup data load process is to be executed, the processor core 210 executes the backup data load process based on the instruction of the user program stored in the ROM. First, the processor core 210 transfers (loads) the backup information stored in the nonvolatile memory 230 in step 306 to the RAM 225 (step 318). The processor core 210 performs calculation based on the backup information (step 320), and compares this calculated value with the calculated value stored in the nonvolatile memory 230 (step 322).

  If the comparison results match (step 322), the processor 210 clears the information in the nonvolatile memory 230 (step 324). In one embodiment, the flash memory cannot be overwritten, so step 324 cannot be omitted for the next writing. However, in another embodiment, step 324 can be omitted in a non-volatile memory that can be overwritten. In other embodiments, step 324 may be performed before or after other steps other than step 322. In still another embodiment, when the contents of the backup memory once read are not reusable (for example, when backup of power failure fails and the previous value is not used), information in the nonvolatile memory 230 Instead of clearing, information that cannot be reused (flag, code, etc.) may be referred to after writing.

  Thereafter, loading of data to the RAM 225 is completed (step 326), and the normal operation of the gaming machine is performed. In this embodiment, since the information in the RAM 225 at the time of interrupt processing in step 302 is backed up, the continuation of the processing of the user program at the time of interrupt processing is executed by loading the backup data.

  If the comparison results do not match (step 322), the processor 210 manages the gaming machine that the set of information (the backup data and the calculated value) stored in the nonvolatile memory 230 that is the load data does not match. A management computer such as a server at a game machine or a server on the Internet may be notified, or the operation of the processor core 210 and the chip 205 may be stopped (step 328). As another example, the RAM 255 and the nonvolatile memory 230 may be initialized and the gaming machine may be restarted.

  If it is determined in step 316 that the backup data load process is not to be executed, the processor core 210 performs the normal operation of the gaming machine without executing the backup data load process. (Step 326).

  The processor core 210 executes steps 302 to 310 and 316 to 328 based on a user program stored in the ROM 220. The processor core 210 executes steps 312 and 314 based on a program operating in a security mode such as a boot program stored in the ROM 220.

  In the present embodiment, processing related to backup is controlled based on a command of the user program, and the user program is created by the user, so that the user can freely implement the backup program.

  In this embodiment, the chip 205 may not have the dedicated logic circuit 250.

Example 2 (User program control by processor and dedicated logic circuit)
FIG. 4 is a flowchart showing execution of backup of RAM information and loading of backed-up information into the RAM based on instructions of the user program by the processor core and the dedicated logic circuit. The operations of Step 402 and Step 404 are the same as Step 302 and Step 304 shown in FIG.

  The processor core 210 instructs the dedicated logic circuit 250 to execute backup processing (step 406). The dedicated logic circuit 250 stores part or all of the information in the RAM 225 in the nonvolatile memory 230 (step 406).

  The dedicated logic circuit 250 performs a calculation similar to the calculation shown in step 308 of FIG. 3 based on a part or all of the information in the RAM 225, obtains a calculated value, and stores it in the nonvolatile memory 230 (step 408). . Thereby, the nonvolatile memory 230 stores the calculated value together with a part or all of the information in the RAM 225. The dedicated logic circuit 250 notifies the processor core 210 that the backup process has been completed (step 410). In the notification, for example, the dedicated logic circuit 250 sets a flag indicating that the backup processing is completed in a predetermined register or the like, and the processor core 210 has a flag such as the predetermined register turned on (or off). By confirming this, and / or when the dedicated logic 250 generates an interrupt in the processor core 210, it can be known that the backup processing is completed. The processor core 210 ends the backup process and stops the operation in response to receiving the notification of the end of the backup process (step 412).

  Also in the second embodiment, as in the first embodiment, the backup process when the power is turned off is performed using the charges stored in the capacitor 262. If it is determined in step 404 that the backup process is not executed, the processor core 210 pauses the operation without executing the backup process (step 412).

  When the main power supply 235 returns from power-off or turns on after a certain time of power-off, the processor core 210 executes processing in the security mode in the same manner as in step 312 shown in FIG. 3 (step 414). The chip 205 and / or the mode control circuit 245 shifts the mode from the security mode to the user mode (step 416). In the user mode, the processor core 210 and the dedicated logic circuit 250 read the user program stored in the ROM 220, and execute processing related to loading backup data based on the user program.

  Similar to step 316 shown in FIG. 3, the processor core 210 determines whether or not to execute backup data load processing (step 418).

  If it is determined in step 418 that the backup data loading process is to be executed, the processor core 210 and the dedicated logic circuit 250 execute the backup data loading process based on the instruction of the user program stored in the ROM. First, the processor core 210 instructs the dedicated logic circuit 250 to execute a backup data load process (step 420).

  The dedicated logic circuit 250 transfers (loads) the backup information stored in the nonvolatile memory 220 in step 406 to the RAM 225 (step 420). The dedicated logic circuit 250 performs calculation based on the backup information (step 422), and compares the calculated value with the calculated value stored in the nonvolatile memory 23 (step 424).

  If the comparison results match (step 424), the dedicated logic circuit 250 clears the information in the nonvolatile memory 230 (step 426). Step 426 may be omitted or moved in the order of execution, as in step 324 in FIG. 3 of the first embodiment, and information clear processing or information non-reuse processing may be performed.

  The dedicated logic circuit 250 notifies the processor core 210 that the backup data load processing has been completed (step 428). In the notification, for example, the dedicated logic circuit 250 sets a flag indicating that the load processing of the backup data is completed in a predetermined register or the like, and the processor core 210 determines that the flag such as the predetermined register is on (or off). It is possible to know that the backup data loading process has been completed by confirming that the processing is completed and / or by causing the dedicated logic 250 to generate an interrupt to the processor core 210. In response to the notification of the end of the backup process, the processor core 210 completes loading of data into the RAM 225 (step 430) and executes the normal operation of the gaming machine. Thereafter, in this embodiment as well, as in the first embodiment, the information in the RAM 225 at the time of interrupt processing in step 402 is backed up, so that the continuation of the processing of the user program at the time of interrupt processing is continued by loading backup data. Executed.

  If the comparison results do not match (step 424), the dedicated logic circuit 250 uses a flag in the register or another method to set a set of information stored in the nonvolatile memory 230 as load data (calculation with backup data). The processor 210 is notified that the values are inconsistent (step 432). In response to receiving the notification, the processor 210 notifies a management computer such as a server at the gaming machine site that manages the gaming machine or a server on the Internet that the data does not match, or the processor core 210 or The operation of the chip 205 may be stopped (step 432). As another example, the RAM 255 and the nonvolatile memory 230 may be initialized and the gaming machine may be restarted.

  When it is determined in step 418 that the backup data loading process is not to be executed, the processor core 210 performs the normal operation of the gaming machine without executing the backup data loading process. (Step 430).

  The processor core 210 and / or the dedicated logic circuit 250 executes steps 402 to 412 and 418 to 432 based on a user program stored in the ROM 220. The processor core 210 executes steps 414 and 416 based on a program operating in a security mode such as a boot program stored in the ROM 220.

  In this embodiment, the main processing (eg, steps 406 to 410 and steps 420 to 428) related to backup and backup data loading is not the processor core 210 but the dedicated logic circuit 250. And different. Since the circuit 250 is dedicated hardware, the processing can be performed faster than when all the processing is realized by the processor core 210 as in the first embodiment. Further, by using dedicated hardware, program instructions can be reduced. In a gaming machine, the capacity for storing a user program in the ROM 220 is limited to a predetermined capacity. Therefore, the capacity of the ROM 220 can be increased for lottery and production of gaming machines by reducing the number of commands related to the backup. It can be used effectively. Therefore, Example 2 has such a technical effect.

Example 3 (Control in Security Mode by Processor)
FIG. 5 is a flowchart showing execution of backup of RAM information and loading of backed-up information into RAM based on instructions of a program operating in a security mode such as a boot program by the processor core. . First, as described in step 302 shown in FIG. 3 of the first embodiment, the processor core 210 responds to the fact that the power interruption detection circuit 237 detects that the main power supply 235 has stopped supplying power (power interruption). Accepts a reset signal due to power interruption from the interrupt reset circuit 240 (step 502). The chip 205 shifts the mode from the user mode to the security mode in response to detecting the power-off (step 504). In the security mode, the processor core 210 reads the boot program stored in the ROM 220, and executes processing related to backup based on the boot program.

  The operations of steps 506, 508, 510, and 512 are the same as steps 304, 306, 308, and 310 shown in FIG. However, in the first embodiment, the processor core 210 executes steps 304 to 310 based on instructions of the user program, whereas in the third embodiment, the processor core 210 executes steps 506 to 512 based on instructions of the boot program. Execute.

  Also in the third embodiment, as in the first embodiment, the backup process is performed using the electric charge stored in the capacitor 262.

  When the main power source 235 returns from power-off or powers on after a certain time of power-off, the processor core 210 operates in the security mode (step 514). In the security mode, the processor core 210 performs a security check or the like based on a boot program instruction stored in the ROM 220. In the security mode, the processor core 210 executes processing related to loading backup data based on the boot program.

  The operations of steps 516, 518, 520, 522, 524, 526, and 530 are the same as those of steps 316, 318, 320, 322, 324, 326, and 328 shown in FIG. However, in the first embodiment, the processor core 210 executes steps 316 to 328 based on the instructions of the user program, whereas in the third embodiment, the processor core 210 executes steps 516 to 526 based on the instructions of the boot program. And 530.

  When the loading of the RAM data is completed in step 526, the chip 205 and / or the mode control circuit 245 shifts the mode from the security mode to the user mode (step 528). When shifting to the user mode, the normal operation of the gaming machine is performed. In this embodiment, since the information in the RAM 225 at the time of reset processing in step 502 is backed up, the continuation of the processing of the user program at the time of interrupt processing is executed by loading the backup data.

  In this embodiment, main processing (for example, steps 506 to 512 and steps 514 to 526 and 530) related to backup and backup data loading is executed based on boot program instructions, not user program instructions. This is different from the first embodiment. Accordingly, the backup program and / or the backup data loading process is executed by the boot program in the security mode, so that the burden on the developer of the user program can be reduced. Further, the backup and backup data load processing is defined by one boot program related to the plurality of types of user programs without defining the backup and backup data load processing for each of the plurality of types of user programs. Therefore, by sharing the processing, it is possible to reduce the burden of user program development and the capacity of the user program. In this embodiment, the user program only needs to define whether or not to execute the backup and backup data load processing. In one embodiment, whether or not to execute backup and backup data load processing may be determined by a flag in a user-defined area of a user program that can be referred to by a boot program. Therefore, Example 3 has such a technical effect.

Example 4 (control in security mode by processor and dedicated logic circuit)
FIG. 6 shows execution of backup of RAM information based on instructions of a program operating in a security mode such as a boot program and loading of backed-up information into the RAM by the processor core and the dedicated logic circuit. FIG. The operations of steps 602, 604, and 606 are the same as those of steps 502, 504, and 306 shown in FIG.

  In the security mode, the processor core 210 instructs the dedicated logic circuit 250 to execute backup processing (step 608). The dedicated logic circuit 250 stores part or all of the information in the RAM 225 in the nonvolatile memory 230 (step 608).

  The dedicated logic circuit 250 performs a calculation similar to the calculation shown in step 308 of FIG. 3 based on a part or all of the information in the RAM 225, obtains a calculated value, and stores it in the nonvolatile memory 230 (step 610). . Thereby, the nonvolatile memory 230 stores the calculated value together with a part or all of the information in the RAM 225. The dedicated logic circuit 250 notifies the processor core 210 that the backup process has been completed (step 612). In the notification, for example, the dedicated logic circuit 250 sets a flag indicating that the backup processing is completed in a predetermined register or the like, and the processor core 210 has a flag such as the predetermined register turned on (or off). By confirming this, and / or when the dedicated logic 250 generates an interrupt in the processor core 210, it can be known that the backup processing is completed. The processor core 210 ends the backup process and stops the operation in response to receiving the notification of the end of the backup process (step 614).

  Also in the fourth embodiment, as in the first embodiment, the backup process is performed using the electric charge stored in the capacitor 262. If it is determined in step 606 that the backup process is not to be executed, the processor core 210 pauses the operation without executing the backup process (step 614).

  When the main power supply 235 returns from power-off or powers on after a certain time of power-off, the processor core 210 executes processing in the security mode in the same manner as in step 312 shown in FIG. 3 (step 616). In the security mode, the processor core 210 and the dedicated logic circuit 250 read the boot program stored in the ROM 220, and execute processing related to loading backup data based on the boot program.

  Similar to step 316 shown in FIG. 3, the processor core 210 determines whether or not to execute backup data load processing (step 618). In this determination, for example, it is determined whether the flag of the value set in the user definition area of the user program is on or off. For example, when the flag is on, the processor core 210 determines to execute the backup data loading process.

  If it is determined in step 618 that the backup data load process is to be executed, the processor core 210 and the dedicated logic circuit 250 execute the backup data load process based on the instruction of the user program stored in the ROM. First, the processor core 210 instructs the dedicated logic circuit 250 to execute a backup data load process (step 620).

  The dedicated logic circuit 250 transfers (loads) the backup information stored in the nonvolatile memory 220 in step 608 to the RAM 225 (step 620). The dedicated logic circuit 250 performs calculation based on the backup information (step 622), and compares this calculated value with the calculated value stored in the nonvolatile memory 23 (step 624).

  If the comparison results match (step 624), the dedicated logic circuit 250 clears the information in the nonvolatile memory 230 (step 626). Step 626 may be omitted or moved in the execution order as in step 324 in FIG. 3 of the first embodiment, and information clear processing and information non-reuse processing may be performed.

  The dedicated logic circuit 250 notifies the processor core 210 that the backup data load processing has been completed (step 628). In the notification, for example, the dedicated logic circuit 250 sets a flag indicating that the load processing of the backup data is completed in a predetermined register or the like, and the processor core 210 determines that the flag such as the predetermined register is on (or off). It is possible to know that the backup data loading process has been completed by confirming that the processing is completed and / or by causing the dedicated logic 250 to generate an interrupt to the processor core 210. In response to receiving the notification of the end of the backup process, the processor core 210 completes loading of data into the RAM 225 (step 630). In step 630, when the loading of the RAM data is completed, the chip 205 and / or the mode control circuit 245 shifts the mode from the security mode to the user mode (step 632). Thereafter, in this embodiment as well, as in the first embodiment, the information in the RAM 225 at the time of the interrupt processing at step 602 is backed up. Executed.

  If the comparison result does not match (step 624), the processor 210 manages the gaming machine that the set of information (the backup data and the calculated value) stored in the nonvolatile memory 230 as the load data does not match. A management computer such as a game machine server or a server on the Internet may be notified, or the operation of the processor core 210 and the chip 205 may be stopped (step 634). As another example, the RAM 255 and the nonvolatile memory 230 may be initialized and the gaming machine may be restarted.

  In this embodiment, main processing (for example, steps 606 to 612 and steps 616 to 630 and 634) related to backup and backup data loading is executed based on the instructions of the boot program in the security mode, not the instructions of the user program. This is different from the first embodiment. Therefore, the present embodiment provides the technical effect obtained in the third embodiment obtained when the main processing related to backup and loading of backup data is based on the boot program instruction in the security mode, not on the instruction of the user program. I play.

  In the present embodiment, a part of main processing (for example, steps 608 to 612 and steps 620 to 630 and 634) related to backup and backup data loading is not the processor core 210 but the dedicated logic circuit 250. This is different from the first embodiment. Therefore, the present embodiment also has the technical effect described in the second embodiment obtained when the main processing execution subject relating to backup and loading of backup data is not the processor core 210 but the dedicated logic circuit 250. .

Example 5 (Control in Backup Mode by Processor)
FIG. 7 is a flowchart showing execution of RAM information backup based on instructions of a program operating in the backup mode by the processor core. First, as described in step 302 shown in FIG. 3 of the first embodiment, the processor core 210 responds to the fact that the power interruption detection circuit 237 detects that the main power supply 235 has stopped supplying power (power interruption). Accepts a reset signal due to power interruption from the interrupt reset circuit 240 (step 702).

  The chip 205 and / or the mode control circuit 245 shifts the mode from the user mode to the backup mode (step 704). In the backup mode, the processor core 210 operates based on a backup program instruction stored in the ROM 220.

  The backup mode is a mode different from the security mode and the user mode, and only the circuits related to the backup are operated. The backup program executed in the backup mode may be included in the ROM 220 as a part of the boot program, but may be built in a ROM separate from the ROM 220.

  When the power interruption detection circuit 237 detects the power interruption, the mode control circuit 245 sets the chip 205 to the backup mode, and puts circuits and devices not used in the backup processing into a dormant state, while the circuit used in the backup processing. And the operation of the apparatus is maintained (step 706). As a result, unused circuits are suspended in the backup process, so that power consumption in the backup process can be reduced. As an example, the unused circuit in the backup process is at least one of the power interruption detection circuit 237, the peripheral circuit 215 interrupt reset circuit 240, the ROM 220, and the like. In other words, in the backup mode, at least the processor 210, the nonvolatile memory 230, and the RAM 225 are not paused. In one embodiment, the suspension of the circuit or device may be realized by stopping the supply of power.

  The processor core 210 executes steps 708, 710, 712 and 714 shown in FIG. The operations of steps 708, 710, 712 and 714 shown in FIG. 7 are the same as the operations of steps 304, 306, 308 and 310 shown in FIG. However, steps 304, 306, 308, and 310 shown in FIG. 3 operate based on the instructions of the user program, whereas steps 708, 710, 712, and 714 shown in FIG. 7 are based on the instructions of the backup program. Works.

  Also in the fifth embodiment, as in the first embodiment, the backup process is performed using the electric charge stored in the capacitor 262.

  The backup data loading process in the fifth embodiment can be the same as the process shown in the first or third embodiment.

  In this embodiment, the power consumption during the backup process is suppressed by reducing the circuits that operate during the backup process, so that the backup process can be executed more reliably. In addition, since the boot program is executed in the security mode for the backup and / or backup data loading process, the burden on the user program developer and the user program capacity can be reduced. In one embodiment, whether or not to perform backup and backup data loading processing may be determined by a user program instruction or a flag set in a user-defined area of the user program. In one embodiment, the backup program may be stored in a memory dedicated to backup (for example, a ROM other than the ROM 220). Thereby, the capacity of the ROM 220 can be used effectively. Therefore, Example 5 has such a technical effect.

  In this embodiment, when the dedicated logic circuit 250 is not used, the chip 205 may not have the dedicated logic circuit 250.

Example 6 (Control in backup mode by processor and dedicated logic circuit)
FIG. 8 is a flowchart showing the execution of RAM information backup based on the instructions of the program operating in the backup mode by the processor core and the dedicated logic circuit. First, as described in step 302 shown in FIG. 3 of the first embodiment, the processor core 210 responds to the fact that the power interruption detection circuit 237 detects that the main power supply 235 has stopped supplying power (power interruption). Accepts a reset signal due to power interruption from the interrupt reset circuit 240 (step 802).

  The chip 205 and / or the mode control circuit 245 shifts the mode to the backup mode (step 804) in the same manner as the operations shown in steps 704 and 706 of FIG. 7 shown in the fifth embodiment, and the mode control circuit 245 Circuits and devices that are not used in the backup process are put into a dormant state, while operations of circuits and devices that are used in the backup process are maintained (step 806). In the backup mode, the processor core 210 operates based on a backup program instruction stored in the ROM 220. In this embodiment, the mode control circuit 245 suspends some circuits and devices of the chip 205, but does not suspend at least the processor 210, the dedicated logic circuit 250, the nonvolatile memory 230, and the RAM 225.

  The processor core 210 executes steps 808 and 816 shown in FIG. 8, and the dedicated logic circuit 250 executes steps 810, 812 and 814 shown in FIG. The operations of steps 808 and 816 shown in FIG. 8 are the same as the operations of steps 404 and 412 shown in FIG. 4, and the operations of steps 810, 812 and 814 shown in FIG. 8 are the same as those shown in FIG. The operation is the same as that of 406, 408, and 410. However, steps 404, 406, 408, 410, and 412 shown in FIG. 4 operate based on a user program instruction, whereas steps 808, 810, 812, 814, and 816 shown in FIG. It operates based on the instruction.

  Also in the sixth embodiment, as in the first embodiment, the backup process is performed using the electric charge stored in the capacitor 262.

  The backup data loading process can be the same as the process shown in the second or fourth embodiment.

  In this embodiment, since the operation is performed in the backup mode, the same technical effects as those of the fifth embodiment are obtained. Further, since the main process of backup is executed by the dedicated logic circuit 250, the technical effect described in the second embodiment obtained when the process execution subject is not the processor core 210 but the dedicated logic circuit 250. I also play.

Example 7 (Control in backup mode by dedicated logic circuit)
FIG. 9 is a flowchart showing the execution of RAM information backup based on the processing sequence of the dedicated logic operating in the backup mode by the dedicated logic circuit. First, as described in step 302 shown in FIG. 3 of the first embodiment, the processor core 210 responds to the fact that the power interruption detection circuit 237 detects that the main power supply 235 has stopped supplying power (power interruption). Suspends the processor that accepts the reset signal from the interruption reset circuit 240 (step 902). In the present embodiment, the dedicated logic circuit 250 can execute a backup process based on a predefined processing sequence.

  In response to the chip 205 receiving the power-off detection signal, the mode control circuit 245 shifts the operation mode of the chip 205 from the user mode to the backup mode, and controls the dedicated logic circuit 250 to execute the backup processing instruction. (Step 904). The chip 205 puts a circuit or device that is not used in the backup processing into a dormant state, while maintaining the operation of the circuit or device used in the backup processing (step 906). In the backup mode, the dedicated logic circuit 250 operates to back up the data stored in the RAM 225 to the nonvolatile memory 230. In this embodiment, the mode control circuit 245 pauses some circuits and devices of the chip 205, but does not pause at least the dedicated logic circuit 250, the nonvolatile memory 230, and the RAM 225.

  The dedicated logic circuit 250 determines whether to execute the backup process (step 908). In this determination, for example, the dedicated logic circuit 250 determines whether a flag having a value set in a predetermined register or the like is on or off. For example, when the flag is on, the dedicated logic circuit 250 determines to execute the backup process. The flag set in the user-defined area of the user program in the boot process at power-on is read in a predetermined register or the like, or the flag set in the user-defined area of the user program is read from the user ROM each time. But it ’s okay.

  If it is determined in step 908 that the backup process is to be executed, the dedicated logic circuit 250 executes the backup process. First, the dedicated logic circuit 250 stores part or all of the information in the RAM 225 in the nonvolatile memory 230 (step 910).

  Next, the dedicated logic circuit 250 performs a calculation based on part or all of the information in the RAM 225 to obtain a calculated value and store it in the nonvolatile memory 230 (step 912). Thereby, the nonvolatile memory 230 stores the calculated value together with a part or all of the information in the RAM 225. The dedicated logic circuit 250 notifies the mode control circuit 245 that the backup process has been completed (step 914). In the notification, for example, the dedicated logic circuit 250 sets a flag indicating that the backup processing is completed in a predetermined register or the like, and the mode control circuit 245 turns on (or off) the flag such as the predetermined register or the like. By confirming that the backup processing is complete, it is possible to know that the backup processing has been completed. The mode control circuit 245 terminates the backup process and stops the operation of all the circuits and devices in the chip 205 (step 915).

  Any of the embodiments described above may be used for the backup data loading process.

  In this embodiment, since the operation is performed in the backup mode, the same technical effects as those of the fifth embodiment are obtained. Further, since the main process of backup is executed by the dedicated logic circuit 250, the technical effect described in the second embodiment obtained when the process execution subject is not the processor core 210 but the dedicated logic circuit 250. I play. Furthermore, in this embodiment, the processor core 210 is suspended in the backup process, so that the power consumption in the backup process can be further reduced as compared with the fifth and sixth embodiments.

  In the first to seventh embodiments described above, the step of determining to perform backup and the step of determining to load backup data are always performed (for example, steps 304, 316, 404, 418, 506, 516, 606, 618, 708, 808, 908). However, as will be appreciated by those skilled in the art, one or both of determining to perform backup and determining to load backup data may not be performed (may be omitted). ). In this case, the backup and / or backup data is loaded without determining whether to perform backup and / or determining whether to load backup data.

本表において、◎は、所定のモード及びプログラムを他のモード及びプログラムに入れ替えることが不可であることを示し、○は、所定のモード及びプログラムを他のモード及びプログラムに入れ替えることが可であることを示す。 Summary of Embodiments 1 to 7 As described above, in Embodiments 1 to 7, the mode, the program, and the execution subject when operating by backup and loading of backup data are different. The table below shows the mode, program, and execution subject for each embodiment.

In this table, ◎ indicates that the predetermined mode and program cannot be replaced with other modes and programs, and ○ indicates that the predetermined mode and program can be replaced with other modes and programs. It shows that.

  In the prior art, when the amount of power required for the RAM 125 to store information exceeds the amount of power stored in the capacitor 145, the content of the RAM 125 has been lost because there is no power to operate the RAM 125. . In each of the embodiments according to the present invention, when the main power source 235 is off, the contents of the RAM 225 are stored in the nonvolatile memory 230. Accordingly, the contents of the RAM 225 are not lost because the contents of the RAM 225 are semi-permanently stored in the nonvolatile memory 230.

  When the power is turned on, the processor 210 may clear the content stored in the nonvolatile memory 230 when the power is turned off for a certain period and when the power is turned off. The predetermined period can be specified by a time measuring circuit such as a built-in timer. Moreover, the fixed period can be set to 12 hours, 24 hours, 2 days, 5 days, or the like, for example. As another embodiment, when a time measuring circuit such as a built-in timer is not provided, the charge charged in the capacitor when the power is turned on again using the internal discharge of the chip 205 and the like. The content stored in the nonvolatile memory 230 may be cleared by confirming that the amount is not fixed by the power-off detection circuit 237 or the like.

  In the embodiment of the present invention, the non-volatile memory 230 may be a Flash ROM, an EEPROM, a non-volatile RAM, or the like.

  In the embodiment of the present invention, the ROM 220 is described as one piece of hardware, but may be realized by two or more ROMs. When the ROM 220 is two or more ROMs, each ROM stores one or more of a boot program, a user program, and a backup program.

  In one embodiment, the substrate 200 can be for gaming machines. In one embodiment, the chip 205 shown in FIG. 2 may be mounted on one chip. One such chip is referred to as a microcomputer, a microcomputer, a one-chip microcomputer, a processor chip, or the like. In other embodiments, the chip 205 may itself be provided as a processor. In the gaming machine, a gaming machine using the board 200 as a main board and / or a sub board may be configured. In the gaming machine, the main board mainly controls the lottery of the gaming machines, and the sub board controls the payout and / or effect of the gaming machine.

  In the above embodiment, some or all of some elements described to be realized by hardware can be realized by software, and some elements described to be realized by software It will be understood that some or all of can be implemented in hardware.

  The “device for gaming machine” recited in the claims corresponds to the “chip 205” described in the specification. The “backup processing unit” described in the claims corresponds to “processor core 210” and / or “dedicated logic circuit 250” in the specification. The “volatile RAM” described in the claims corresponds to the description “RAM 225” in the specification. The “first program”, “second program”, and “third program” described in the claims correspond to the “boot program”, “user program”, and “backup program” in the specification, respectively. To do.

  As long as there is no inconsistency in the processing or processing order in the processing or processing order described above, such as using data that should not be used in that processing, the processing or processing order. Can be changed freely.

  Regarding each embodiment described above, a part or all of each embodiment may be combined and realized as one embodiment.

  Each Example described above is an illustration for explaining the present invention, and the present invention is not limited to these Examples. The present invention can be implemented in various forms without departing from the gist thereof.

200 substrate 205 chip 210 processor core 215 peripheral circuit 220 ROM
225 RAM
230 Non-volatile memory 235 Main power supply 237 Power interruption detection circuit 240 Interrupt reset circuit 245 Mode control circuit 250 Dedicated logic circuit 260 Diode 262 Capacitor

Claims (8)

A device for a gaming machine,
A backup processing unit;
Volatile RAM used as main memory,
A non-volatile memory that stores a part or all of the contents of the volatile RAM as a backup;
A first program that operates in a security mode that is a mode for performing at least processing related to security of the gaming machine device; and a second program that operates in a user mode that is a mode for performing at least lottery and / or presentation of gaming machines. A ROM that stores at least
An interruption detection circuit for detecting that the supply of power in the gaming machine device is interrupted,
In response to the power interruption detection circuit detecting the interruption of power supply, the backup processing unit determines the content of the volatile RAM based on the instruction of the first program or the instruction of the second program. Part or all of the data is stored in the nonvolatile memory;
When power is supplied to the gaming machine device, the backup processing unit operates based on an instruction of the first program, and after the mode shifts from the security mode to the user mode, the user program A device for a gaming machine that operates based on a command.   In response to detecting the return of the power supply after detecting the disconnection of the power supply, the backup processing unit transfers a part or all of the content stored in the nonvolatile memory to the volatile RAM. The gaming machine device according to claim 1, wherein the gaming machine device is loaded or transferred. The ROM further stores a third program that operates in a backup mode, which is a mode for performing at least processing related to the backup,
The gaming machine device according to claim 1 or 2, further comprising a mode control circuit that pauses at least the operation of the power interruption detection circuit in the backup mode.   The gaming machine device according to any one of claims 1 to 3, wherein the backup processing unit is a processor core and / or a dedicated logic circuit.   The gaming machine device according to any one of claims 1 to 4 is a chip.   The chip according to claim 5 is a one-chip.   A substrate having the chip according to claim 5.   A gaming machine having the board according to claim 7.

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