JP6385322B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus that saves log information or transmits it to a network when restarting.

  Information processing apparatuses that display advertisements or guidance information are popular in public facilities such as stations and airports, commercial facilities such as shopping centers, and public transportation such as trains, airplanes, and buses.

  In such an information processing apparatus, a failure such as stopping the update of advertisements or guidance information may occur due to a program runaway due to some problem. In such a case, the information processing apparatus investigates the cause by storing the state at the time of failure occurrence. There is also an information processing apparatus that is designed to automatically restart after a certain period of time has elapsed after the occurrence of a failure and resumes services such as advertisements or guidance information.

In the restart, a software reset of the volatile memory is usually performed. Therefore, there is a problem that data such as failure information held in the volatile memory is broken by restart.
To deal with such a problem, Patent Document 1 discloses that a monitoring device program called a service processor (SVP: Service Processor) that monitors the computer main body has an area outside the kernel management in the volatile memory when an abnormality occurs in the monitoring device. A method is disclosed in which failure information is stored in the memory and software reset that does not reset the volatile memory is performed to ensure the storage of the failure information and the failure information is acquired after the restart.

  Further, Patent Document 2 discloses a method of switching a plurality of volatile memories by changing the allocation of memory addresses at the time of restart after occurrence of a failure, and not overwriting the memory state at the time of error occurrence to be dumped at the time of restart. Is disclosed.

International Publication No. 2011-016115 (paragraph 0011, page 7-10, FIGS. 3 to 7) Japanese Patent Laying-Open No. 2015-90512 (paragraphs 0007 to 0008, FIGS. 1 and 5)

  In the method described in Patent Document 1, it is necessary to secure an area for storing failure information in an area outside the kernel management in advance, separately from the kernel management space in which the dynamic embedded driver and the user process can dynamically secure the memory. There is a problem that the capacity of the volatile memory cannot be fully utilized.

  Further, the method described in Patent Document 2 has a problem that it is necessary to provide a plurality of volatile memories in order to switch memories when restarting after a failure occurs.

  Therefore, the present invention is a device specification for storing log information when a failure occurs, specifically, normal operation without enlarging the memory capacity or squeezing the usable memory area. The purpose is to enable log information to be stored within a limited memory specification.

  An information processing apparatus according to an aspect of the present invention includes a nonvolatile memory that stores a program, a volatile memory, a processor that reads the program stored in the nonvolatile memory into the volatile memory, and executes the program. A timer monitoring unit for transmitting a reset signal to the processor and storing information from the processor when there is no access from the processor for a predetermined period of time, the processor comprising: When a reset signal is received from the timer monitoring unit, a storage area is secured in an unused area of the volatile memory, and at least a part of log information including information indicating the state of the information processing apparatus is stored in the storage area. Storing the address of the storage area storing at least a part of the log information in the timer monitoring unit. Et al., And restarts, the processor, after the restart, based on the stored address to the timer monitoring unit, characterized in that reading out at least part of the log information from the storage area.

  According to one aspect of the present invention, by dynamically securing an area for storing log information in a volatile memory area when a failure occurs, a device specification is fixed for storing log information when a failure occurs, Specifically, log information can be stored in a limited memory specification prepared for normal operation without enlarging the memory capacity or squeezing the usable memory area.

It is a block diagram which shows roughly the structure of the information processing apparatus which concerns on Embodiment 1-3. FIG. 3 is a block diagram schematically showing a configuration of a timer monitoring unit in the first embodiment. FIG. 3 is a schematic diagram for explaining a memory map of a processor in the first embodiment. 4 is a flowchart illustrating an operation from starting to normal operation in the first embodiment. 3 is a flowchart illustrating processor operation monitoring processing according to the first embodiment. 4 is a flowchart illustrating processing when a WDT interrupt (WDT error) occurs in the first embodiment. (A) And (B) is the schematic which shows the example of the memory map at the time of log information preserve | saving at the time of WDT error occurrence in Embodiment 1. FIG. 4 is a flowchart showing processing when a WDT interrupt occurs in the first embodiment when the volatile memory has a self-refresh mode. 4 is a flowchart showing an operation until starting a normal operation after startup in the case where the volatile memory has a self-refresh mode in the first embodiment. FIG. 6 is a schematic diagram for explaining a memory map of a processor according to a second embodiment. 9 is a flowchart illustrating processing when a WDT interrupt occurs in the second embodiment. 10 is a schematic diagram for explaining a memory map of a processor in Embodiment 3. FIG. 14 is a flowchart illustrating processing when a WDT interrupt occurs in the third embodiment.

Embodiment 1 FIG.
FIG. 1 is a block diagram schematically showing the configuration of the information processing apparatus 100 according to the first embodiment.
The information processing apparatus 100 includes a processor 101, a nonvolatile memory 102, a volatile memory 103, a connection interface (hereinafter referred to as connection I / F) 104, a communication interface (hereinafter referred to as communication I / F) 106, Timer monitoring unit 110. An external storage medium 105 is connected to the connection I / F 104.

  The processor 101 controls the operation of the information processing apparatus 100. For example, the processor 101 controls the operation of the information processing apparatus 100 by reading various programs stored in the nonvolatile memory 102 into the volatile memory 103 and executing them.

  The nonvolatile memory 102 stores data and programs necessary for the operation of the information processing apparatus 100. For example, the nonvolatile memory 102 is configured by a NOR flash memory and stores data and programs used by the processor 101. The nonvolatile memory 102 is not limited to a NOR type flash memory, and may be a mask ROM (Read Only Memory), an SD card, or the like.

  The volatile memory 103 is constituted by, for example, a DDR3 (Double Data Rate 3) memory, and functions as a work area when the processor 101 develops or executes various programs read from the nonvolatile memory 102. Note that the volatile memory 103 is not limited to the DDR3 memory, but may be a DDR2 memory, a DDR memory, or an SDRAM (Synchronous Dynamic Random Access Memory).

The connection I / F 104 is an interface for connecting the external storage medium 105.
The external storage medium 105 is a portable storage medium. For example, the external storage medium 105 is a removable non-volatile card type storage medium such as an SD card, a CF (Compact Flash (registered trademark) ) card, or a CFast card.

The communication I / F 106 is an interface for communicating with an external server 130 that is an external device. For example, the communication I / F 106 is an interface such as Ethernet (registered trademark) communication or RS485 communication.

The timer monitoring unit 110 monitors the operation of the processor 101. For example, the timer monitoring unit 110 monitors the operation of the processor 101, and transmits an interrupt signal to the processor 101 when there is no access from the processor 101 for a predetermined period. Send to.
In addition, the timer monitoring unit 110 stores information from the processor 101.

  Here, when the processor 101 receives a reset signal from the timer monitoring unit 110, the processor 101 secures a storage area (first storage area) in an unused area of the volatile memory 103 and changes the state of the information processing apparatus 100. At least a part of the log information including the indicated information is stored in the storage area, and the address of the storage area storing at least a part of the log information is stored in the timer monitoring unit 110, and then restarted. Then, the processor 101 reads at least a part of the log information from the storage area based on the address stored in the timer monitoring unit 110 after the restart.

FIG. 2 is a block diagram schematically showing a configuration of timer monitoring unit 110 in the first embodiment.
The timer monitoring unit 110 includes a WDT circuit 111 formed of a WDT (Watchdog Timer), an interrupt generation circuit 112 that generates an interrupt, a reset generation circuit 113 that generates a reset, and a temporary storage that stores the state of the apparatus when a failure occurs. A circuit 114 and a control circuit 115 that controls each internal circuit of the timer monitoring unit 110 are provided.

  The WDT circuit 111 determines whether there is an access from the processor 101 during a predetermined period. For example, the WDT circuit 111 monitors the operation of the processor 101 by monitoring whether the WDT counter is cleared from the processor 101 at regular intervals. The WDT circuit 111 issues an interrupt (WDT interrupt signal) to the processor 101 via the interrupt generation circuit 112 when clearing is not performed by the time of WDT time-out (referred to as a WDT error), and is reset after a predetermined time. A reset (WDT reset signal) is issued from the generation circuit 113.

  The interrupt generation circuit 112 receives a WDT time-up signal from the WDT circuit 111 and issues a WDT interrupt signal to the processor 101.

  The reset generation circuit 113 receives the WDT time-up signal from the WDT circuit 111 and issues a WDT reset signal to the processor 101 after a predetermined time (after the standby period has elapsed).

  The temporary storage circuit 114 receives the WDT interrupt signal from the interrupt generation circuit 112 after the processor 101, and then writes the device information (log) until after restart from reset by the WDT reset signal output from the reset generation circuit 113. Information write address). Note that the device information is retained as it is unless it is explicitly deleted even after restarting.

  The control circuit 115 receives a command from the processor 101 and controls the WDT circuit 111, the interrupt generation circuit 112, the reset generation circuit 113, and the temporary storage circuit 114.

The timer monitoring unit 110 in the first embodiment is realized by a PLD (Programmable Logic Device). A partial region of the PLD, specifically, the temporary storage circuit 114 and the WDT error status register are configured by flip-flops (F / F). In these cases, the F / F is cleared by a power-on reset (hardware reset) at power-on, but is not cleared by a software reset issued by the processor 101 or a WDT reset after the occurrence of WDT. For example, only the hardware reset signal is connected to the reset terminal (or set terminal) of the F / F, and the software reset signal is not connected.
Generally, the software reset initializes the processor 101, and whether to initialize peripheral circuits of other processors 101 depends on software running on the processor 101. In the first embodiment, the volatile memory 103 and the timer monitoring unit 110 are not initialized when restarting after a WDT error occurs.

FIG. 3 is a schematic diagram for explaining a memory map of the processor 101. The memory map shown in FIG. 3 is an example, and the present invention is not limited to this.
The nonvolatile memory 102 stores a boot program and a kernel.
The timer monitoring unit 110 is realized by PLD as described above. Note that the timer monitoring unit 110 is not limited to a PLD, and may be a small-scale microcomputer or the like.

  The volatile memory 103 is divided into a kernel management area and a non-kernel management area. The kernel management area is divided into a logical address space and a virtual address space.

Although not shown, the logical address space includes a text area (text segment or text section), a data area (data segment or data section), and a BSS area (BSS segment or BSS section).
The text area stores a data area machine language program or read-only data used by the program.
The data area stores data having an initial value used in the program.
The BSS area stores data initialized with “0”.

Although not shown, the virtual address space includes a heap area, a mmap area, and a stack area.
The heap area is an area where the processor 101 allocates memory as necessary during execution of the program.
The mmap area is an area that allows a user process to read / write a file by reading / writing a memory with a part of the contents of the file corresponding to a part of the virtual address space.
The stack area is an area temporarily used by a return address or a called subroutine when a program being executed reads out a subroutine.

  The non-kernel management area is an area that appears to the kernel as an I / O (Input / Output) space.

FIG. 4 is a flowchart showing an operation after starting up until a normal operation starts.
The processor 101 reads and confirms the status of the WDT error from the WDT circuit 111 of the timer monitoring unit 110 (S10). The status of the WDT error is the number of occurrences of WDT time-up that has occurred after power-on. The status of the WDT error is cleared to 0 when the power is turned off.

  The processor 101 determines whether or not the number of occurrences of the WDT error is greater than “0” in the read WDT error status (S11). If the number of occurrences of the WDT error is “0” (No in S11), the process proceeds to step S12. If the number of occurrences of WDT errors is greater than “0” (Yes in S11), the process proceeds to step S13.

In step S12, the processor 101 initializes the volatile memory 103 because no WDT error has occurred (first operation) after the power is turned on. Then, the process proceeds to step S13.
In step S13, the processor 101 performs kernel activation. If the number of occurrences of the WDT error is 1 or more, the restart is caused by the occurrence of the WDT error. Therefore, the processor 101 starts the kernel in step S13 as it is without initializing the volatile memory 103.

Next, the processor 101 inquires about the current time with a time server (not shown) and performs time adjustment (S14).
Then, the processor 101 again reads the status of the WDT error from the WDT circuit 111, and confirms the number of occurrences of the WDT error (S15).
If the number of WDT error occurrences is 1 or more (Yes in S15), the process proceeds to step S16. On the other hand, when the number of occurrences of the WDT error is 0 (No in S15), in other words, when the WDT error has not yet occurred after the power is turned on, the processor 101 proceeds to the normal operation as it is.

In step S <b> 16, the processor 101 acquires log information from the volatile memory 103.
Then, the processor 101 stores log information (S17). For example, the processor 101 stores log information in the external storage medium 105 via the connection I / F 104 or transmits the log information to the external server 130 via the communication I / F 106. Both of these may be performed.
Then, the processor 101 shifts to a normal operation.

FIG. 5 is a flowchart showing the operation monitoring process of the processor 101.
The monitoring program of the processor 101 receives a timer (not shown) interrupt in the processor 101 and periodically clears the WDT counter of the WDT circuit 111 (S20). For example, the processor 101 transmits a command for clearing the WDT counter to the WDT circuit 111.
When the monitoring program cannot clear the WDT due to the occurrence of a failure, the WDT circuit 111 in the timer monitoring unit 110 transmits a WDT time-up signal (WDT error signal) to the control circuit 115.
The control circuit 115 receives the WDT time-up signal input from the WDT circuit 111 and outputs a WDT interrupt signal from the interrupt generation circuit 112 to the processor 101.

  The processor 101 receives a WDT interrupt signal from the timer monitoring unit 110. The processor 101 resets the waiting time until the generation of the WDT reset signal output from the reset generation circuit 113 of the timer monitoring unit 110 and saves log information as necessary. Specifically, the reset generation circuit 113 is configured to generate a WDT reset signal after a certain time, for example, 1 second, as an initial value after WDT time-up (after generation of a WDT interrupt signal). When the processor 101 receives the WDT interrupt signal, the processor 101 resets the waiting time until the WDT reset signal is generated or temporarily stops the generation of the WDT reset signal according to the size of the log information to be stored. A WDT reset signal is generated after the log information is saved. The fixed time is set as the initial value when the processor 101 receives a failure that prevents the log information from being saved. This is because it is possible to return to the original service provision such as information and guidance information.

FIG. 6 is a flowchart showing processing when a WDT interrupt (WDT error) occurs.
When a WDT interrupt occurs, the processor 101 secures a first log information storage area that is a storage area for storing log information in the volatile memory 103 (S30).
Next, the processor 101 acquires the time when the WDT error occurs (WDT error occurrence time) (S31).

  Next, the processor 101 acquires necessary information from each unit of the information processing apparatus 100, and generates log information when a WDT error occurs (S32). The log information includes the WDT error occurrence time, the number of WDT error occurrences, the state of the information processing apparatus 100 at the time of WDT error occurrence (immediate process information, operating system (OS) information, hardware information, task trace information). ) Etc. The number of occurrences of WDT errors is the number of WDT errors that have occurred after power-on, and is cleared to 0 when the power is turned off. Therefore, it is possible to determine whether the error has occurred first time after the power is turned on or the error has occurred after restarting based on the number of times the WDT error has occurred.

  Next, the processor 101 stores the log information generated in step S32 in the first log information storage area of the volatile memory 103 secured in step S30 (S33).

Next, the processor 101 stores the log information storage address in the temporary storage circuit 114 of the timer monitoring unit 110 (S34).
Finally, the processor 101 explicitly issues a software reset as necessary (S35).

  Note that the order of the processing shown in FIG. 6 is not limited to this. For example, the time acquisition in step S31 and the generation of log information in step S32 may be reversed. Further, instead of storing the log information again in the volatile memory 103 in step S34, the processor 101 may store the acquired time information in the volatile memory 103 in step S31, or in step S32. Thus, the generated log information may be stored in the volatile memory 103. Further, after the time acquisition in step S31 and the log information generation in step S32, the processor 101 may reserve a first log information storage area for storing the log information again and save it in step S34.

  Here, log information effective for failure analysis or the like among information held by the kernel and hardware is acquired from the volatile memory 103 or the hardware of the information processing apparatus 100. Note that the information collected as log information includes information that has already been output to the volatile memory 103 when a WDT error occurs while the program is operating sequentially. If a WDT error occurs, a new instruction is executed. There is also information to be output.

FIGS. 7A and 7B are schematic diagrams illustrating examples of a memory map when log information is saved when a WDT error occurs.
In the example shown in FIG. 7A, the first log information storage area is “0x6800_0000 to 0x6FFF_FFFF”, the first address of the first log information storage area is “0x6800_0000”, and the storage size is “0x0800_0000”. Is.
In the example shown in FIG. 7B, the first log information storage area is divided into two locations of “0x4400_0000 to 0x4BFF_FFFF” and “0x6C00_0000 to 0x6FFF_FFFF”, and the top of the first log information storage area The addresses are “0x4400_0000” and “0x6C00_0000”, respectively, and the storage sizes are “0x0800_0000” and “0x0400_0000”, respectively.

  The processor 101 may reserve a plurality of areas as the first log information storage area when the large area where the log information is stored cannot be secured in step S30 of FIG. In that case, the processor 101 stores a plurality of log information storage addresses in the temporary storage circuit 114. Further, the processor 101 may store, for example, the first address and the storage size of the first log information storage area in the temporary storage circuit 114, or store only the first address and store the volatile memory 103. The storage size may be stored at the top of the destination.

  Unlike an apparatus in which a resource used after restart is changed according to a user operation history with a user operation, in the case of an information processing apparatus for installation, it returns to an initial state by restart unless it is a software update. Of the virtual address space of the volatile memory 103, for example, the areas secured immediately after startup are the first system initial secured area and the second secured area, as shown in FIGS. The mapping area is not limited to this, although it is limited by the device as in the system initial secured area. Therefore, the processor 101 does not initialize the volatile memory 103 after restarting, and can retrieve log information stored before restarting as long as it is read before entering normal operation using many resources. .

  A DRAM (Dynamic Random Access Memory), which is the volatile memory 103, maintains a state of “0” or “1” by storing electric charge in a capacitor. However, since the electric charge decreases with time, the DRAM decreases with time. A refresh operation for injecting charges is required. The data in the first log information storage area secured at the time of failure is retained without being lost if the refresh operation is performed even during the restart period or if the refresh operation can be resumed before the electric charge is discharged. be able to.

  DDR3 has a self-refresh mode, and if it is in a power supply state, it can hold data even when the external clock is stopped. Therefore, when the volatile memory 103 has the self-refresh mode, the processor 101 receives the interrupt signal from the timer monitoring unit 110 and stores the log information, and then sets the volatile memory 103 to the power saving state. Can do.

FIG. 8 is a flowchart showing a process when a WDT interrupt occurs when the volatile memory 103 has a self-refresh mode.
In the processing shown in FIG. 8, the same reference numerals as those in FIG. 6 are given to the same processing as in FIG.
The processing in steps S30 to S34 in FIG. 8 is the same as the processing in steps S30 to S34 in FIG. However, after the process of step S34 in FIG. 8, the process proceeds to step S40.
In step S40, the processor 101 sets a timer until a reset is generated from the reset generation circuit 113.
Then, the processor 101 shifts the volatile memory 103 to the self-refresh mode (S41).

  In FIG. 8, by shifting to the self-refresh mode in step S41, the volatile memory 103 used as a work area cannot be used, and the processor 101 does not operate. However, after the time set in the reset generation circuit 113 in step S40, a reset is automatically issued by the timer function and can be restarted.

FIG. 9 is a flowchart showing an operation from the start to the normal operation when the volatile memory 103 has the self-refresh mode.
In the processing shown in FIG. 9, the same processing as in FIG. 4 is denoted by the same reference numerals as in FIG.
The processing in steps S10 to S17 in FIG. 9 is the same as the processing in steps S10 to S17 in FIG. However, if the number of occurrences of WDT errors is 1 or more in step S11 of FIG. 9 (No in S11), the process proceeds to step S50.
In step S50, the processor 101 returns the volatile memory 103 from the self-refresh mode. Then, the process proceeds to step S13.

  As described above, the processor 101 can reliably hold the log information stored in the volatile memory 103 during the restart.

  When the information processing apparatus 100 provides a service such as an advertisement or guidance information, it is necessary to restart immediately when a WDT error occurs to restore the apparatus and restart the service.

  On the other hand, since the occurrence of a WDT error indicates the occurrence of a failure, depending on the content or size of the failure, a large amount of resources such as sending the acquired log information to the server via the network is required. It is not possible to perform complicated operations as required. Log information when a failure occurs is often stored in a non-volatile memory 102 (flash memory) that retains its contents even after the power is turned off. However, the nonvolatile memory 102 has a limit on the number of times of writing, and since writing requires erasing, high-speed writing cannot be performed. Further, since the capacity of the volatile memory such as DDR is small, it is sufficient. Disadvantageous in that it is impossible to write log information.

  According to the first embodiment, on the premise that the information processing apparatus 100 is restarted when a failure occurs, log information is stored in the volatile memory 103 that can easily secure a necessary memory capacity due to the large capacity and can perform high-speed writing. Is temporarily stored. Then, after restarting, the information processing apparatus 100 can read out the log information and store it in the external storage medium 105 having a larger capacity or transmit it to the external server 130 on the network while the resources are recovered.

  In the storage in the volatile memory 103, the information processing apparatus 100 dynamically secures the first log information storage area for the first time when a failure occurs. The information processing apparatus 100 stores the log information storage address of the first log information storage area that is dynamically secured in the temporary storage circuit 114. Then, the information processing apparatus 100 can hold the data of the volatile memory 103 by starting without initializing the volatile memory 103 at the time of restart. Further, the information processing apparatus 100 can read the log information from the log information storage address in the volatile memory 103 by referring to the log information storage address stored in the temporary storage circuit 114 after the restart. For this reason, since the information processing apparatus 100 can dynamically secure the first log information storage area, it can cope with log storage with a minimum memory configuration necessary for actual operation.

  The reset generation circuit 113 of the timer monitoring unit 110 can variably set a waiting period from generation of a WDT interrupt to reset issuance including an indefinite period according to the size of log information to be stored. For this reason, the information processing apparatus 100 does not generate a reset while saving log information or unnecessarily prolongs the time until the reset. Further, even when the standby period cannot be set due to a failure, the information processing apparatus 100 can be automatically restarted after a certain time and restarted by the initial setting.

  In the information processing apparatus 100, since the DDR 3 has a self-refresh mode, if the power supply can be maintained, the stored log information can be reliably retained.

  In the information processing apparatus 100, when a WDT error occurs, by storing the WDT error occurrence time as log information, it is possible to know when the WDT error has occurred and is effective for failure analysis.

  In the information processing apparatus 100, when a WDT error occurs, the WDT error occurrence count is stored as log information to distinguish between the first WDT error after power-on and the WDT error that occurred after restart due to the occurrence of the WDT error. This is useful for failure analysis.

  Since the information processing apparatus 100 recovers resources by restarting, the log information stored in the first log information storage area can be read and stored in the external storage medium 105 such as a USB memory, CF, or CFast. . Thereby, failure analysis is facilitated by extracting log information from the information processing apparatus 100.

  The information processing apparatus 100 can read the log information stored in the first log information storage area and transmit it to the external server 130 via a communication interface such as an Ethernet network because the resources are recovered by restarting. is there. Thereby, failure analysis is facilitated by extracting log information from the information processing apparatus 100.

Embodiment 2. FIG.
Next, a second embodiment will be described.
As shown in FIG. 1, the information processing apparatus 200 according to the second embodiment includes a processor 201, a nonvolatile memory 102, a volatile memory 203, a connection I / F 104, a communication I / F 106, Timer monitoring unit 110. An external storage medium 105 is connected to the connection I / F 104.
The information processing apparatus 200 according to the second embodiment is configured in the same manner as the information processing apparatus 100 according to the first embodiment, except that the memory map of the processor 201 is different.

FIG. 10 is a schematic diagram illustrating a memory map of the processor 201 according to the second embodiment. The memory map shown in FIG. 10 is an example, and the present invention is not limited to this.
The difference from the first embodiment is that a second log information storage area, which is a second storage area for storing log information, is provided in the non-kernel management area of the volatile memory 203. Since the non-kernel management area cannot dynamically secure the memory, the second log information storage area has a fixed address and a fixed size. Assume that the address of the second log information storage area is preset in the processor 201.

FIG. 11 is a flowchart showing processing when a WDT interrupt occurs in the second embodiment.
In the processing shown in FIG. 11, processing similar to that in FIG. 6 is denoted by the same reference numerals as in FIG. 6.
The processing of steps S30 to S32, step S34, and step S35 in FIG. 11 is the same as the processing of steps S30 to S32, step S34, and step S35 of FIG. However, after the process of step S32 in FIG. 11, the process proceeds to step S60.

In step S60, the processor 201 saves at least a part of the log information generated in step S32 in a non-kernel management area (second log information storage area).
Next, the processor 201 stores the remainder of the log information generated in step S32 in the first log information storage area of the volatile memory 203 secured in step S30 (S61). Then, after step S61, the process proceeds to step S34.
Note that the order is not limited to this, and the processing in step S60 may be performed after storage in the volatile memory 203 in step S61.

  The non-kernel management area stores the WDT error occurrence time and the number of WDT error occurrences. In addition, in the non-kernel management area, basic information such as process information, OS information or hardware information, information whose size is fixed, and information after the size of the WDT error are generated. Information that does not need to be stored, or information that remains for a while after the transition to normal operation is stored. The volatile memory 203 stores a large amount of information such as trace information. Note that which information is stored in which area is not limited to this.

  In the second embodiment, the information processing apparatus 200 can refer to the saved log information even after the normal operation by using the non-kernel management area together.

Embodiment 3 FIG.
Next, a third embodiment according to the present invention will be described.
As shown in FIG. 1, the information processing apparatus 300 according to the third embodiment includes a processor 301, a nonvolatile memory 302, a volatile memory 103, a connection I / F 104, a communication I / F 106, Timer monitoring unit 110. An external storage medium 105 is connected to the connection I / F 104.
The information processing apparatus 300 according to the third embodiment is configured similarly to the information processing apparatus 100 according to the first embodiment except that the memory map of the processor 301 is different.

FIG. 12 is a schematic diagram illustrating a memory map of the processor 301 in the third embodiment. The memory map shown in FIG. 12 is an example, and the present invention is not limited to this.
The nonvolatile memory 302 stores log information in a third log information storage area that is a third storage area for storing log information, in addition to the boot program and the kernel. Each of these is managed and stored by being divided into partitions, and is configured so that even if some partitions are depleted, the entire system is not affected.

FIG. 13 is a flowchart showing processing when a WDT interrupt occurs in the third embodiment.
In the processing shown in FIG. 13, the same reference numerals as those in FIG. 6 are assigned to the same processing as in FIG.
The processes in steps S30 to S32, step S34, and step S35 in FIG. 13 are the same as the processes in steps S30 to S32, step S34, and step S35 in FIG. However, after the process of step S32 in FIG. 13, the process proceeds to step S70.

In step S70, the processor 301 saves at least a part of the log information generated in step S32 in the nonvolatile memory 302 (third log information storage area).
Next, the processor 301 stores the rest of the log information generated in step S32 in the first log information storage area of the volatile memory 103 secured in step S30 (S71). Then, after the process of step S71, the process proceeds to step S34.
Note that the order is not limited to this, and the processing in step S70 may be performed after the storage in the volatile memory 103 in step S71.

  The nonvolatile memory 302 stores the WDT error occurrence time and the number of WDT error occurrences. The non-volatile memory 302 stores basic information such as process information, OS information, or hardware information, and information with relatively small capacity and important and high storage value in the state at the time of occurrence of the WDT error. At least one is saved. The volatile memory 103 stores a large amount of information such as trace information. Note that which information is stored in which area is not limited to this.

  In the third embodiment, the information processing apparatus 300 uses the non-volatile memory 302 in combination, so that the time until the restart increases, but the minimum log information is left even when the next restart is not possible due to a failure. Can do.

  The embodiment may be a combination of a kernel management area and a non-kernel management area of the volatile memory 203 as shown in the second embodiment, or a volatile memory as shown in the third embodiment. The combination of the kernel management area 103 and the nonvolatile memory 302 is not limited. For example, by combining the kernel management area and non-kernel management area of the volatile memory 103 and the non-volatile memory 102, it is possible to store log information that is more suitable for the purpose.

  100, 200, 300 Information processing apparatus, 101, 201, 301 Processor, 102, 302 Non-volatile memory, 103, 203 Volatile memory, 104 Connection I / F, 105 External storage medium, 106 Communication I / F, 110 Timer monitoring 111 WDT circuit, 112 interrupt generation circuit, 113 reset generation circuit, 114 temporary storage circuit, 115 control circuit, 130 external server.

Claims (14)

A non-volatile memory for storing the program;
Volatile memory,
A processor that reads a program stored in the nonvolatile memory into the volatile memory and executes the program;
A timer monitoring unit for transmitting a reset signal to the processor and storing information from the processor when there is no access from the processor for a predetermined period,
When the processor receives a reset signal from the timer monitoring unit, the processor secures a storage area in an unused area of the volatile memory and includes at least a part of log information including information indicating a state of the information processing apparatus Is stored in the storage area, the address of the storage area storing at least a part of the log information is stored in the timer monitoring unit, and then restarted.
The processor reads out at least a part of the log information from the storage area based on an address stored in the timer monitoring unit after the restart. The processor stores all of the log information in the storage area, and reads out all of the log information from the storage area based on an address stored in the timer monitoring unit after the restart. The information processing apparatus according to claim 1. The processor stores a part of the log information in a non-kernel management area of the volatile memory and stores the rest of the log information in the storage area. The information processing apparatus according to claim 1, wherein a part of the log information is read out from the storage area, and the rest of the log information is read out from the storage area based on an address stored in the timer monitoring unit. The processor stores a part of the log information in the nonvolatile memory, stores the rest of the log information in the storage area, and stores the log information from the nonvolatile memory after the restart. The information processing apparatus according to claim 1, wherein the information processing apparatus reads out the remaining portion of the log information from the storage area based on an address stored in the timer monitoring section. The timer monitoring unit
A WDT circuit for determining whether or not there is an access from the processor during the predetermined period;
A reset generation circuit that transmits the reset signal to the processor after a lapse of a waiting period after the WDT circuit determines that there is no access from the processor during the predetermined period;
The information processing apparatus according to any one of claims 1 to 4, further comprising a temporary storage circuit that stores the address. The timer monitoring unit further includes an interrupt generation circuit that transmits an interrupt signal to the processor when the WDT circuit determines that there is no access from the processor during the predetermined period;
The processor, when receiving the interrupt signal, reserves the storage area in an unused area of the volatile memory, and stores at least a part of the log information in the storage area. Item 6. The information processing device according to Item 5. In the reset generation circuit, an initial value of the standby period is preset,
The information processing apparatus according to claim 6, wherein the processor changes an initial value of the waiting period after receiving the interrupt signal and before receiving the reset signal. The volatile memory has a self-refresh mode,
The information processing apparatus according to claim 6, wherein the processor sets the volatile memory in a self-refresh mode after receiving the interrupt signal and before receiving the reset signal. The information processing apparatus according to claim 8, wherein the processor sets the volatile memory in a power saving state after receiving the interrupt signal. The information processing apparatus according to claim 8, wherein the volatile memory is a DDR3 memory. 11. The log information includes an error occurrence time that is a time when the WDT circuit determines that there is no access from the processor during the predetermined period. Information processing device. The log information includes an error occurrence number that is the number of times that the WDT circuit determines that there is no access from the processor during the predetermined period since the information processing apparatus is turned on. The information processing apparatus according to any one of claims 5 to 11. A connection interface for connecting an external storage medium;
The said processor memorize | stores the log information which read at least one part from the said storage area in the said external storage medium connected to the said connection interface. Information processing device. A communication interface for communicating;
The information processing according to any one of claims 1 to 13, wherein the processor transmits log information, at least a part of which is read from the storage area, to an external server via the communication interface. apparatus.

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