JP2017194326A - Peak hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a peak hold circuit which can increase the capability of holding the peak of an input voltage.SOLUTION: A peak hold circuit 100 includes a capacitor 8 for holding a voltage, a differential circuit 101, and a buffer circuit 20. The differential circuit 101 has a transistor 1 (first transistor) in which an input voltage Vi is input to a base, and a transistor 2 (second transistor) in which a voltage between both ends of a capacitor 8 is input to a base. A buffer circuit 20 has a series circuit of a power source and a diode, and generates a voltage according to the size of the input voltage Vi. In the buffer circuit 20, the connect point 203 of the power source and the diode is electrically connected to the collector of the transistor 2, and a current is supplied to the collector of the transistor 2 from the power source so that the active region of the transistor 2 will not be a saturated region.SELECTED DRAWING: Figure 1

Description

  The present invention relates generally to a peak hold circuit, and more particularly to a peak hold circuit that holds a peak value of an input voltage.

  Conventionally, a peak hold circuit that holds a peak value of an input voltage is known (see, for example, Patent Document 1). The peak hold circuit described in Patent Document 1 is a differential input type peak hold circuit including a peak value holding capacitor and a differential amplifier.

  In the peak hold circuit described in Patent Document 1, the input terminal is connected to the base of the npn-type first transistor. The emitter of the first transistor is connected to the emitter of the npn-type second transistor, and is grounded through a resistor. The collector of the first transistor is connected to the collector and base of the pnp-type third transistor and the base of the pnp-type fourth transistor. The base of the pnp-type fifth transistor is connected to the collector of the third transistor and the collector of the second transistor. The third to fifth transistors are both connected to the power supply terminal. The collector of the fifth transistor is connected to the output terminal and the base of the second transistor, and is grounded through a peak value holding capacitor. The input voltage is input to the base of the first transistor, and the voltage across the peak value holding capacitor is input to the base of the second transistor.

  In the peak hold circuit described in Patent Document 1, the base potential of the first transistor is compared with the base potential of the second transistor. When the base potential of the first transistor is larger, the peak value holding capacitor is charged. When the base potential of the first transistor is smaller, the charging current to the peak value holding capacitor is reduced, and the peak value is reduced. Is retained.

JP 58-220506 A

  In the peak hold circuit described in Patent Document 1, a parasitic transistor may be formed in the second transistor depending on the configuration of the peak hold circuit. The parasitic transistor has a base connected to the collector of the second transistor, an emitter connected to the gate of the second transistor, and a collector grounded. Therefore, in the peak hold circuit described in Patent Document 1, when the input voltage is reduced, the second transistor has a possibility that the collector current is reduced, the operation region becomes the saturation region, and the parasitic transistor is turned on. As a result, the peak value holding capacitor is discharged via the parasitic transistor, and the peak value of the input voltage may not be held.

  The present invention has been made in view of the above reasons, and an object thereof is to provide a peak hold circuit capable of improving the peak holding capability of an input voltage.

  The peak hold circuit according to the first aspect of the present invention includes a capacitor, a differential circuit, and a buffer circuit. The capacitor is a voltage holding capacitor. The differential circuit includes a first transistor in which the input voltage is input to a base, and a second transistor in which the voltage across the capacitor is input to the base. The buffer circuit has a series circuit of a current source and a diode. The buffer circuit receives the input voltage and generates a voltage corresponding to the magnitude of the input voltage at the output terminal by supplying a current from the current source to the output terminal via the diode. It is. In the buffer circuit, a connection point between the current source and the diode is electrically connected to a collector of the second transistor, and the current region is set so that an operation region of the second transistor does not become a saturation region. A function of supplying a current from a source to a collector of the second transistor;

  In the peak hold circuit according to a second aspect of the present invention, in the first aspect, the buffer circuit preferably includes a plurality of bipolar transistors and a MOSFET. The diode is a pn junction diode of one of the plurality of bipolar transistors. The current source is the MOSFET.

  The peak hold circuit according to a third aspect of the present invention is the peak hold circuit according to the second aspect, wherein the buffer circuit is a third transistor, a fourth transistor and a fifth transistor which are the plurality of bipolar transistors, and a sixth MOSFET. It is preferable to have a transistor, a first constant current source, and a second constant current source. Each of the third transistor, the fourth transistor, and the fifth transistor is an npn-type bipolar transistor. The sixth transistor is a p-channel MOSFET. In the third transistor, the input voltage is input to a base, and an emitter is electrically connected to an emitter of the fourth transistor. The base of the fourth transistor is electrically connected to the emitter of the fifth transistor. The base of the fifth transistor is electrically connected to the drain of the sixth transistor. The sixth transistor has a source electrically connected to a power source. A connection point between the drain of the sixth transistor and the base of the fifth transistor is electrically connected to the collector of the fourth transistor and the collector of the second transistor. The first constant current source is electrically connected between a connection point between the emitter of the third transistor and the emitter of the fourth transistor and circuit ground. The second constant current source is electrically connected between a connection point between a base of the fourth transistor and an emitter of the fifth transistor and the circuit ground. The diode is a pn junction diode between a base and an emitter of the fifth transistor.

  The peak hold circuit according to a fourth aspect of the present invention preferably includes a second buffer circuit different from the first buffer circuit including the buffer circuit according to any one of the first to third aspects. The second buffer circuit is electrically connected between both ends of the capacitor, and generates a voltage corresponding to the magnitude of the voltage across the capacitor.

  In the peak hold circuit of the present invention, since the current is supplied from the buffer circuit to the collector of the second transistor so that the operation region of the second transistor does not become the saturation region, the peak holding capability of the input voltage can be improved. There is an effect that it becomes possible.

FIG. 1 is a circuit diagram of a peak hold circuit according to an embodiment of the present invention. FIG. 2 is an operation waveform diagram in the above-described peak hold circuit. FIG. 3 is a circuit diagram of a peak hold circuit according to a first modification of the embodiment of the present invention. FIG. 4 is a circuit diagram of a peak hold circuit according to a second modification of the embodiment of the present invention. FIG. 5 is a circuit diagram of a peak hold circuit according to a third modification of the embodiment of the present invention. FIG. 6 is a circuit diagram of a peak hold circuit according to a fourth modification of the embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment)
(1 Overview)
FIG. 1 shows a circuit configuration diagram of the peak hold circuit 100 of the present embodiment. The peak hold circuit 100 of this embodiment is a peak hold circuit that generates an output voltage Vo that has a voltage value that holds the peak value of the input voltage Vi. The peak hold circuit 100 is connected to the power supply 30 and operates by the control voltage Vcc from the power supply 30. Note that the term “connection” used in the description of the present embodiment means electrical connection.

  The peak hold circuit 100 includes a pair of input terminals 41 and 42 and a pair of output terminals 51 and 52. The input terminal 42 is connected to circuit ground. An input voltage Vi is input between the pair of input terminals 41 and 42. The output terminal 52 is connected to circuit ground. The peak hold circuit 100 generates an output voltage Vo between the pair of output terminals 51 and 52. Note that the pair of input terminals 41 and 42 and the pair of output terminals 51 and 52 do not have to be actual components (terminals), and are included in, for example, electronic component leads and circuit boards (for example, printed circuit boards). It may be a part of the conductor.

(2 details)
Details of the peak hold circuit 100 of this embodiment will be described below. The peak hold circuit 100 according to this embodiment includes a main circuit 10 and a buffer circuit 20.

(2.1 Main circuit)
The main circuit 10 includes transistors 1 to 5, constant current sources 6 and 7, and a capacitor 8. The transistors 1 to 3 are npn bipolar transistors. The transistors 4 and 5 are enhancement type p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The constant current sources 6 and 7 are current sources for flowing a direct current.

  The transistor 1 (first transistor) has a base connected to the input terminal 41, a collector connected to the power supply 30, and an emitter connected to the emitter of the transistor 2. The transistor 2 (second transistor) has a base connected to the output terminal 51 and a collector connected to the power supply 30 via the transistor 5. A connection point between the emitter of the transistor 1 and the emitter of the transistor 2 is connected to a constant current source 6. The constant current source 6 allows a direct current having a current value “I” to flow from the connection point between the emitter of the transistor 1 and the emitter of the transistor 2 toward the circuit ground. That is, the differential circuit 101 is configured by the transistor 1, the transistor 2, and the constant current source 6.

  The transistor 3 has a base connected to a connection point between the drain of the transistor 5 and the collector of the transistor 2, a collector connected to the power supply 30, and an emitter connected to the output terminal 51. The capacitor 8 is a voltage holding capacitor that is charged according to the magnitude of the input voltage Vi, and is connected between the pair of output terminals 51 and 52. That is, a series circuit of the transistor 3 and the capacitor 8 is connected between the output terminals of the power supply 30, and the capacitor 8 is charged by the current flowing through the transistor 3.

  The transistor 4 has a source connected to the power supply 30 and a drain connected to the constant current source 7 and the gate. The constant current source 7 passes a DC current having a current value “I / 2” from the transistor 4 toward the circuit ground. The transistor 5 has a source connected to the power supply 30, a drain connected to the collector of the transistor 2 and the base of the transistor 3, and a gate connected to the gate of the transistor 4. That is, the transistor 4 and the transistor 5 constitute a current mirror circuit, and a direct current having a current value of “I / 2” flows through the transistors 4 and 5.

  Further, the peak hold circuit 100 of this embodiment includes a semiconductor chip (integrated circuit) in which at least the transistors 1 and 2 are integrally formed. The transistor 2 is formed in an element formation region in an n-type epitaxial layer (eg, Si epitaxial layer) on the surface of a p-type semiconductor substrate (eg, Si substrate). A collector region, which is an n-type conductive region, and a base region, which is a p-type conductive region, are provided in the element formation region on the surface side of the element formation region of the epitaxial layer, and a p-type conductive region (base ) Is provided with an emitter region which is an n-type conductive region. In the epitaxial layer, adjacent element formation regions are separated by pn junction by p-type element isolation formation. A parasitic transistor 12 is formed on the semiconductor chip including the transistor 2 having such a configuration. The parasitic transistor 12 includes a p-type conductive region that is a base region of the transistor 4 as an emitter region, an n-type conductive region that is a collector region of the transistor 4 as a base region, and a p-type isolation region (circuit ground) as a collector region. This is a pnp type bipolar transistor. In FIG. 1, the parasitic transistor 12 is indicated by a dotted line.

(2.2 Buffer circuit)
The buffer circuit 20 includes transistors 21 to 23 and 25 and constant current sources 26 and 29. The transistors 21 to 23 are npn-type bipolar transistors. The transistor 25 is an enhancement type p-channel MOSFET. The constant current sources 26 and 29 are current sources for flowing a direct current.

  The transistor 21 (third transistor) has a base connected to the input terminal 41, a collector connected to the power supply 30, and an emitter connected to the emitter of the transistor 22. The transistor 22 (fourth transistor) has a base connected to the constant current source 29 and a collector connected to the power supply 30 via the transistor 25. A connection point 202 between the emitter of the transistor 21 and the emitter of the transistor 22 is connected to the constant current source 26. The constant current source 26 (first constant current source) passes a direct current having a current value “I” from the connection point 202 between the emitter of the transistor 21 and the emitter of the transistor 22 toward the circuit ground. That is, the transistor 21, the transistor 22, and the constant current source 26 constitute a differential circuit.

  The base of the transistor 23 (fifth transistor) is connected to the drain of the transistor 25 and the collector of the transistor 22, the collector is connected to the power supply 30, and the emitter is connected to the constant current source 29. Since the transistor 23 is an npn-type bipolar transistor, the pn junction between the base and the emitter functions as a diode. The constant current source 29 (second constant current source) passes a DC current having a current value “I” from the transistor 23 toward the circuit ground.

  The transistor 25 (sixth transistor) has a source connected to the power supply 30, a drain connected to the collector of the transistor 22 and the base of the transistor 23, and a gate connected to the gate of the transistor 4. In other words, the transistor 4 and the transistor 25 constitute a current mirror circuit, and the transistor 25 functions as a current source for flowing a direct current having a current value of “I / 2”. Further, the drain of the transistor 25 is connected to the collector of the transistor 2.

  The buffer circuit 20 is a circuit that generates a voltage according to the input voltage Vi, and a connection point between the base of the transistor 22, the emitter of the transistor 23, and the constant current source 29 functions as the output terminal 201 of the buffer circuit 20.

  The buffer circuit 20 also functions as a current supply circuit that supplies current to the collector of the transistor 2. The drain of the transistor 25 is connected to the collector of the transistor 2. In other words, a connection point 203 between the transistor 25 functioning as a current source and the base-emitter pn junction diode of the transistor 23 functioning as a diode is connected to the collector of the transistor 2. The buffer circuit 20 is configured to supply current from the transistor 25 as a current source to the collector of the transistor 2 so that the operation region of the transistor 2 does not become a saturation region.

(3 operation)
Next, the operation of the peak hold circuit 100 of this embodiment will be described with reference to the operation waveform diagram of FIG. As shown in FIG. 2, the waveform of the input voltage Vi in this embodiment is a rectangular wave whose voltage level alternately changes between an H level (High level) and an L level (Low level). Note that the waveform of the input voltage Vi is not limited to a rectangular wave, and may be a waveform (for example, a sine wave) in which the voltage level continuously increases or decreases.

(3.1 Input voltage, L level → H level)
First, the operation of the peak hold circuit 100 when the voltage level of the input voltage Vi changes from the L level to the H level will be described.

  In the main circuit 10, when the voltage level of the input voltage Vi changes from the L level to the H level, the transistor 1 is turned on and the transistor 2 is turned off. When the transistor 2 is turned off, a current flowing through the transistor 5 flows to the base of the transistor 3 and the transistor 3 is turned on. When the transistor 3 is turned on, a current is supplied from the power supply 30 to the capacitor 8 via the transistor 3 and the capacitor 8 is charged. Thereby, the output voltage Vo rises so as to follow the change of the input voltage Vi. As the output voltage Vo increases, the difference between the input voltage Vi and the output voltage Vo decreases, so that a current starts to flow through the transistor 1. In the first equilibrium state in which the input voltage Vi and the output voltage Vo coincide with each other, a current flows through each of the transistors 1, 2, and 3 so as to maintain the state in which the output voltage Vo coincides with the input voltage Vi.

  In the buffer circuit 20, when the voltage level of the input voltage Vi changes from the L level to the H level, the transistor 21 is turned on and the transistor 22 is turned off. When the transistor 22 is turned off, a current flowing through the transistor 25 flows to the base of the transistor 23, and the transistor 23 is turned on. When the transistor 23 is turned on, the potential of the output terminal 201 (the base potential of the transistor 22) rises so as to follow the change in the input voltage Vi. As the base potential of the transistor 22 increases, the difference between the base potential (input voltage Vi) of the transistor 21 and the base potential of the transistor 22 decreases, so that current starts to flow through the transistor 21. In the second equilibrium state in which the base potential (input voltage Vi) of the transistor 21 and the base potential of the transistor 22 match, the transistors 21, A current flows through 22 and 23. As described above, the voltage generated at the output terminal 201 of the buffer circuit 20 changes following the change of the input voltage Vi.

(3.2 Input voltage, H level → L level)
Next, the operation of the peak hold circuit 100 when the voltage level of the input voltage Vi changes from the H level to the L level will be described.

  In the main circuit 10, when the voltage level of the input voltage Vi changes from the H level to the L level, the transistor 1 is turned off and the transistor 2 is turned on. When the transistor 2 is turned on, the current flowing through the transistor 5 flows to the transistor 2, the base current of the transistor 3 is reduced, and the transistor 3 is turned off. The capacitor 8 is in a state in which the current supplied from the transistor 3 is reduced, but the peak value (H level) of the input voltage Vi is held.

  In the buffer circuit 20, when the voltage level of the input voltage Vi changes from the H level to the L level, the transistor 21 is turned off and the transistor 22 is turned on. When the transistor 22 is turned on, the transistor 23 is turned off, and the potential of the output terminal 201 (the base potential of the transistor 22) decreases so as to follow the change in the input voltage Vi.

  Here, in the main circuit 10, the capacitor 8 is connected to the base of the transistor 2, while the constant current source 29 is connected to the base of the transistor 22. Therefore, when the voltage level of the input voltage Vi changes from the H level to the L level, the base potential of the transistor 2 is held by the capacitor 8, whereas the base potential of the transistor 22 decreases following the input voltage Vi. To do. That is, the buffer circuit 20 enters the second equilibrium state earlier than the main circuit 10 enters the first equilibrium state.

  When the main circuit 10 is not in the first balanced state and the buffer circuit 20 is in the second balanced state, a part of the current flowing through the transistor 25 is supplied to the collector of the transistor 2. As a result, the operation region of the transistor 2 is suppressed from becoming a saturation region. In other words, current supply from the buffer circuit 20 suppresses a decrease in the collector potential of the transistor 2 (base potential of the parasitic transistor 12), and suppresses the parasitic transistor 12 from being turned on. Therefore, discharging of the capacitor 8 through the parasitic transistor 12 is suppressed, and the voltage across the capacitor 8 (output voltage Vo) is held at the peak value for a longer time.

(4 Summary)
As described above, the peak hold circuit 100 according to the present embodiment includes the capacitor 8, the differential circuit 101, and the buffer circuit 20. The capacitor 8 is a voltage holding capacitor. The differential circuit 101 includes a transistor 1 (first transistor) in which an input voltage Vi is input to the base and a transistor 2 (second transistor) in which the voltage across the capacitor 8 is input to the base. The buffer circuit 20 has a series circuit of a current source (transistor 25) and a diode (pn junction diode between the base and emitter of the transistor 23). The buffer circuit 20 is a buffer circuit that generates a voltage corresponding to the magnitude of the input voltage Vi at the output terminal 201 when an input voltage Vi is input and current is supplied from the current source to the output terminal 201 via a diode. is there. In the buffer circuit 20, the connection point 203 between the current source and the diode is electrically connected to the collector of the transistor 2, so that the operation region of the transistor 2 does not become a saturation region. Has a function of supplying a current.

  With the above configuration, when the input voltage Vi decreases and the current flowing through the transistor 2 increases, the current is supplied from the buffer circuit 20 to the collector of the transistor 2. Thereby, a decrease in the collector potential of the transistor 2 is suppressed, and the operation region of the transistor 2 is suppressed from becoming a saturation region. That is, the capacitor 8 is prevented from discharging through the parasitic transistor 12, and the voltage across the capacitor 8 (output voltage Vo) is held at the peak value for a longer time. That is, the peak hold circuit 100 in this embodiment can improve the peak holding capability of the input voltage Vi.

  In the peak hold circuit 100, the buffer circuit 20 preferably includes a plurality of bipolar transistors (transistors 21 to 23) and a MOSFET (transistor 25). The diode is a pn junction diode of one bipolar transistor (transistor 23) among the plurality of bipolar transistors. The current source is a MOSFET (transistor 25). With the above configuration, since one bipolar transistor (transistor 23) also functions as a diode and MOSFET (transistor 25) also functions as a current source, the configuration of the buffer circuit 20 can be simplified. .

  The buffer circuit 20 includes a plurality of bipolar transistors 21 to 23 (third to fifth transistors), a MOSFET 25 (sixth transistor), and constant current sources 26 and 29 (first and second constants). Current source). Each of the transistors 21 to 23 is an npn-type bipolar transistor. The transistor 25 is a p-channel type MOSFET. In the transistor 21, the input voltage Vi is input to the base, and the emitter is electrically connected to the emitter of the transistor 22. The base of the transistor 22 is electrically connected to the emitter of the transistor 23. The base of the transistor 23 is electrically connected to the drain of the transistor 25. The source of the transistor 25 is electrically connected to the power supply 30. A connection point 202 between the drain of the transistor 25 and the base of the transistor 23 is electrically connected to the collector of the transistor 22 and the collector of the transistor 2. The constant current source 26 is electrically connected between a connection point 202 between the emitter of the transistor 21 and the emitter of the transistor 22 and the circuit ground. The constant current source 29 is electrically connected between a connection point (output terminal 201) between the base of the transistor 22 and the emitter of the transistor 23 and the circuit ground. The diode is a pn junction diode between the base and emitter of the transistor 23.

  With the above configuration, the buffer circuit 20 can cause the generated voltage to follow the change of the input voltage Vi more quickly. Therefore, when the input voltage Vi decreases, the buffer circuit 20 shifts faster to the second equilibrium state in which the base potential of the transistor 21 and the base potential of the transistor 22 coincide with each other, and supplies current to the collector of the transistor 2. Can do. This further suppresses the operation region of the transistor 2 from becoming a saturation region, and the peak hold circuit 100 can further improve the peak holding capability of the input voltage Vi.

  Further, the peak hold circuit 100 according to the present embodiment causes the transistor 25 formed of a p-channel MOSFET to function as a current source that supplies current to the collector of the transistor 2. Therefore, no diode is included in the path of the current supplied from the power supply 30 to the collector of the transistor 2. Thus, the peak hold circuit 100 can be driven if the control voltage Vcc is equal to or higher than a voltage value capable of driving only two bipolar transistors (transistors 2 and 3). In other words, when the base-emitter of each of the transistors 2 and 3 is regarded as a pn junction diode, the peak hold circuit 100 can be operated if the control voltage Vcc is equal to or higher than the voltage value for conducting the two pn junction diodes. Become. As a result, the control voltage Vcc, which is the operation power supply of the peak hold circuit 100, can be lowered.

(5 Modifications)
Next, a modified example of the peak hold circuit 100 of this embodiment will be described. In the modified example described below, the same components as those of the peak hold circuit 100 described above are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

(5.1 First Modification)
A circuit diagram of the peak hold circuit 100A of the first modification is shown in FIG. In addition to the main circuit 10 and the buffer circuit 20 (first buffer circuit 20), the peak hold circuit 100A further includes a second buffer circuit 60 that generates a voltage corresponding to the magnitude of the voltage across the capacitor 8.

  The second buffer circuit 60 includes transistors 61 to 63 and 65 and constant current sources 66 and 69, and is connected between the main circuit 10 and the pair of output terminals 51 and 52.

  The transistor 61 has a base connected to the high potential side of the capacitor 8, a collector connected to the power supply 30, and an emitter connected to the emitter of the transistor 62. The transistor 62 has a base connected to the output terminal 51 and a collector connected to the power supply 30 via the transistor 65. A connection point between the emitter of the transistor 61 and the emitter of the transistor 62 is connected to a constant current source 66. The constant current source 66 causes a direct current having a current value “I” to flow from the connection point between the emitter of the transistor 61 and the emitter of the transistor 62 toward the circuit ground. That is, the transistor 61, the transistor 62, and the constant current source 66 constitute a differential circuit.

  The base of the transistor 63 is connected to the drain of the transistor 65 and the collector of the transistor 62, the collector is connected to the power supply 30, and the emitter is connected to the constant current source 69. The constant current source 69 allows a DC current having a current value “I” to flow from the transistor 63 toward the circuit ground.

  The transistor 65 has a source connected to the power supply 30, a drain connected to the collector of the transistor 62 and the base of the transistor 63, and a gate connected to the gate of the transistor 4 of the main circuit 10. That is, the transistor 4 and the transistor 65 constitute a current mirror circuit, and a direct current having a current value of “I / 2” flows through the transistor 65.

  The second buffer circuit 60 uses the base of the transistor 61 as an input terminal and the base of the transistor 62 as an output terminal, and outputs an output voltage Vo that follows the change in the voltage across the capacitor 8 as an input voltage between the pair of output terminals 51 and 52. To generate.

  Thus, it is preferable that the peak hold circuit 100A of this modification includes the second buffer circuit 60 different from the buffer circuit 20 (first buffer circuit 20). The second buffer circuit 60 is electrically connected between both ends of the capacitor 8 and generates a voltage corresponding to the magnitude of the voltage across the capacitor 8. The second buffer circuit 60 performs impedance matching with a circuit connected to the subsequent stage of the peak hold circuit 100A. For example, even when a circuit having a low input impedance is connected between the pair of output terminals 51 and 52, the capacitor 8 is suppressed from discharging. Thereby, the peak hold circuit 100A can further improve the peak holding capability of the input voltage Vi.

(Second modification)
A circuit diagram of a peak hold circuit 100B of the second modification is shown in FIG. The peak hold circuit 100B includes a main circuit 10B and a buffer circuit 20.

  The main circuit 10B further includes a transistor 14 as a difference from the main circuit 10 (see FIG. 1) in the peak hold circuit 100 of the embodiment. The transistor 14 is an enhancement type p-channel MOSFET. The transistor 14 has a source connected to the power supply 30, a drain connected to the collector of the transistor 1, and a gate connected to the drain. The gate of the transistor 5 in the main circuit 10 </ b> B is connected to the gate of the transistor 14. That is, the transistor 14 and the transistor 5 constitute a current mirror circuit, and a current having the same current value as the collector current of the transistor 1 flows through the transistor 5.

  Also in the peak hold circuit 100B of this modification, a current is supplied from the buffer circuit 20 to the collector of the transistor 2 so that the operation region of the transistor 2 does not become a saturation region, similarly to the peak hold circuit 100 of the embodiment. Thereby, the peak hold circuit 100B can improve the peak holding capability of the input voltage Vi.

  The peak hold circuit 100B may further include the second buffer circuit 60 in the peak hold circuit 100A of the first modification.

(Third Modification)
A circuit diagram of the peak hold circuit 100C of the third modification is shown in FIG. The peak hold circuit 100C includes a main circuit 10 and a buffer circuit 20C.

  The buffer circuit 20C further includes a transistor 24 as a difference from the buffer circuit 20 (see FIG. 1) in the peak hold circuit 100 of the embodiment. The transistor 24 is an enhancement type p-channel MOSFET. The transistor 24 has a source connected to the power supply 30, a drain connected to the collector of the transistor 21, and a gate connected to the drain. The gate of the transistor 25 in the buffer circuit 20C is connected to the gate of the transistor 24. That is, the transistor 24 and the transistor 25 constitute a current mirror circuit, and a current having the same current value as the collector current of the transistor 21 flows through the transistor 25.

  Also in the peak hold circuit 100C of this modification, a current is supplied from the buffer circuit 20C to the collector of the transistor 2 so that the operation region of the transistor 2 does not become a saturation region, similarly to the peak hold circuit 100 of the embodiment. Thereby, the peak hold circuit 100C can improve the peak holding capability of the input voltage Vi.

  The peak hold circuit 100C may further include a second buffer circuit 60 in the peak hold circuit 100A of the first modification.

(Fourth modification)
A circuit diagram of a peak hold circuit 100D of the fourth modification is shown in FIG. The peak hold circuit 100D includes a main circuit 10D and a buffer circuit 20D.

  The main circuit 10D has a configuration in which the transistor 4 and the constant current source 7 are omitted from the main circuit 10B (see FIG. 4) in the second modified example, and the transistor 14 and the transistor 5 form a current mirror circuit. The buffer circuit 20D has the same configuration as the buffer circuit 20C (see FIG. 5) in the third modification example, and the transistor 24 and the transistor 25 form a current mirror circuit.

  Also in the peak hold circuit 100D of the present modification, a current is supplied from the buffer circuit 20D to the collector of the transistor 2 so that the operation region of the transistor 2 does not become a saturation region, similarly to the peak hold circuit 100 of the embodiment. Thereby, the peak hold circuit 100D can improve the peak holding capability of the input voltage Vi.

  The peak hold circuit 100D may be configured to further include the second buffer circuit 60 in the peak hold circuit 100A of the first modification.

  In addition, embodiment mentioned above and each modification are examples of this invention. For this reason, the present invention is not limited to the above-described embodiment and each modification, and even if other than this embodiment and modification, as long as they do not depart from the technical idea of the present invention, Of course, various changes are possible depending on the design and the like.

1 transistor (first transistor)
2 transistors (second transistors)
8 capacitors 20, 20C, 20D buffer circuit (first buffer circuit)
21 transistor (bipolar transistor, third transistor)
22 transistors (bipolar transistors, fourth transistors)
23 transistor (bipolar transistor, fifth transistor)
25 transistors (MOSFET, current source, sixth transistor)
26 Constant current source (first constant current source)
29 Constant current source (second constant current source)
60 Buffer circuit (second buffer circuit)
100, 100A, 100B, 100C, 100D Peak hold circuit 101 Differential circuit 201 Output terminal 202, 203 Connection point

Claims (4)

A voltage holding capacitor that is charged according to the magnitude of the input voltage;
A differential circuit having a first transistor to which the input voltage is input to a base, and a second transistor to which a voltage across the capacitor is input to a base;
A series circuit of a current source and a diode; the input voltage is input; and a current corresponding to the magnitude of the input voltage is supplied from the current source to the output terminal via the diode. A buffer circuit to be generated at the output end,
In the buffer circuit, a connection point between the current source and the diode is electrically connected to a collector of the second transistor, so that the operation region of the second transistor does not become a saturation region. A peak hold circuit having a function of supplying a current to a collector of the second transistor. The buffer circuit includes a plurality of bipolar transistors and a MOSFET,
The diode is a pn junction diode of one of the plurality of bipolar transistors;
The peak hold circuit according to claim 1, wherein the current source is the MOSFET. The buffer circuit includes a third transistor, a fourth transistor, and a fifth transistor that are the plurality of bipolar transistors, a sixth transistor that is the MOSFET, a first constant current source, and a second constant current source. And
Each of the third transistor, the fourth transistor, and the fifth transistor is an npn bipolar transistor,
The sixth transistor is a p-channel MOSFET;
In the third transistor, the input voltage is input to a base, an emitter is electrically connected to an emitter of the fourth transistor,
The base of the fourth transistor is electrically connected to the emitter of the fifth transistor;
The fifth transistor has a base electrically connected to a drain of the sixth transistor,
The sixth transistor has a source electrically connected to a power source,
A connection point between a drain of the sixth transistor and a base of the fifth transistor is electrically connected to a collector of the fourth transistor and a collector of the second transistor;
The first constant current source is electrically connected between a connection point between the emitter of the third transistor and the emitter of the fourth transistor and a circuit ground,
The second constant current source is electrically connected between a connection point between a base of the fourth transistor and an emitter of the fifth transistor, and the circuit ground.
The peak hold circuit according to claim 2, wherein the diode is a pn junction diode between a base and an emitter of the fifth transistor. A second buffer circuit different from the first buffer circuit comprising the buffer circuit;
The said 2nd buffer circuit is electrically connected between the both ends of the said capacitor | condenser, and produces | generates the voltage according to the magnitude | size of the both-ends voltage of the said capacitor | condenser. The peak hold circuit described.

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