JP2017194280A - IMAGING CIRCUIT, SIGNAL READING CIRCUIT, INfrared Imaging Device, Infrared Detecting Circuit, And Imaging Circuit Operation Method - Google Patents

Abstract

An imaging circuit of an infrared imaging device in which the influence of random, telegraph, and noise is reduced is provided.
An imaging circuit of an infrared imaging device including a plurality of infrared detection units, comprising a plurality of signal readout circuits connected to the plurality of infrared detection units, each signal readout circuit having one terminal The detection capacitor unit C1 connected to the first power supply GND, the operation switch unit _Trig A- _Trig C connected between the infrared detection unit and the other terminal of the detection capacitor unit, and the other of the detection capacitor unit A reset switch Tr _R connected between the terminal and the second power source, a transfer capacitor unit C2, and a transfer switch 34, and the operation switch unit is connected in parallel and can be operated independently. MOS transistors.
[Selection] Figure 7

Description

  The present invention relates to an imaging circuit, a signal readout circuit, an infrared imaging device, an infrared detection circuit, and an operation method of the imaging circuit.

  An infrared detector is an element that converts the intensity of infrared light incident on the infrared detector into an electrical signal with respect to infrared light emitted by thermal radiation of an object. For example, an infrared image can be obtained by configuring a so-called focal plane array (FPA) type infrared imaging device in which such infrared detectors are two-dimensionally arranged. In contrast to imaging devices in the visible light region, infrared images can be used to capture the target object even in the dark, and are used in application fields such as the so-called security field. In addition, since the intensity of the infrared rays emitted from the target object is a function of the temperature of the target object, an image reflecting the temperature distribution in the object can be obtained from the infrared radiation intensity distribution in the imaging object. . Utilizing this fact, application in the medical field is also expected.

  In an FPA-type infrared imaging device in which infrared detectors are arranged in a two-dimensional array on a plane, the infrared intensity projected on the infrared detector is converted into an electrical signal distribution to detect infrared rays and obtain an infrared image. In this case, for example, the current flowing through the infrared detector is often accumulated (integrated) in a storage capacitor for a certain period of time using a signal readout circuit including a current-voltage conversion circuit such as a direct-injection circuit and used as a voltage signal. For such a signal readout circuit, a Si-MOS integrated circuit using Si (silicon) that can be manufactured in a technically stable and inexpensive manner and at the same time has favorable characteristics in terms of thermal conductivity, etc. Many.

  By the way, in such an Si-MOS integrated circuit, a general-purpose circuit using a normal transistor design or manufacturing process is often used unless it is customized for a special purpose. In such a case, as is well known, the element size, particularly the gate (channel) length, is decreasing year by year by so-called scaling. As the gate length (channel) becomes longer in this way, the effective volume of the channel region naturally decreases, and the number of so-called traps caused by lattice defects contained therein decreases.

  Such a trap fluctuates the device current of the transistor with time by capturing and releasing electrons or holes constituting the device current of the transistor. Naturally, the cycle of the fluctuation of the transistor element current is determined by the trap / release probability (frequency) of the corresponding trap. In the case of long gate (channel) devices, the number of such traps is relatively large, so fluctuations in device current due to their capture and emission are the result of overlapping effects of various trap capture and emission processes. Averaged to be relatively calm. As a result, the noise of the infrared imaging element is relatively smaller than that of a short gate (channel) transistor.

  On the other hand, as already mentioned, in the case of a short gate (channel) transistor, which has been used in recent years, the number of traps contained in the channel is reduced, and the respective capture and emission processes are performed in the transistor. The effect on the device current is increased. As a result, the variation in the device current of the transistor is close to 0-1. The so-called digital transistor current fluctuation observed as a result is called random telegraph noise (RTN).

  As is well known, the trapping / releasing process of carriers by such a trap is determined by a process including a thermal motion process of carriers, and is assumed to be in an equilibrium state with an element temperature (here, an electron temperature or a hole temperature). ) Is lower, the probability of capture / release is lower, and therefore the cycle or time constant of capture / release is longer.

  Therefore, in an infrared imaging device using a cooling type infrared detector that is cooled and used, such as a quantum well type infrared detector, a quantum dot type, or a type-II type infrared detector whose characteristics have been remarkably improved in recent years.・ Effects of telegraph and noise become more prominent. In an infrared imaging device using such a cooled infrared detector, random telegraph noise having a period corresponding to several frames may be generated in an image.

  Incidentally, Non-Patent Document 1 describes random telegraph noise in such a MOS transistor. According to Non-Patent Document 1, the operation of the MOS transistor is suppressed by appropriately switching the gate-source voltage between an accumulation mode that is at or below a threshold value and an inversion mode that is greater than the threshold value. Can do. By changing the gate-source voltage as described above, the potential distribution of the channel, and hence the electric field, is changed, and as a result, trapped carriers are forcibly released or traps that have not trapped carriers. Force the carrier to capture. In this way, by artificially manipulating the charge state, the initial state of the trap capture / emission process is made constant (hereinafter referred to as reset), and at the timing when device operation is required, carrier trapping in the trap is performed.・ To prevent release as much as possible.

JP 62-14028 A JP 2009-74898 A JP 2003-149047 A JP 2007-295264 A JP2015-14509A

B. Dierickx and E. Simoen "The decrease of" random telegraph signal "noise in metal-oxide-semiconductor field-effect transistors when cycled from inversion to accumulation", J. Applied Phys., Vol. 71, No. 4, 14 , February 1992

  Therefore, even in the pixel signal readout / integration system MOS transistor in the signal readout circuit of the infrared image sensor, the gate-source voltage is kept below the threshold during the integration operation of the pixel signal. Telegraph noise can be suppressed.

  However, as described above, in the case of a cooling-type infrared imaging device, the entire imaging device, and thus the signal readout circuit, is also used by cooling, so the period of random telegraph noise in the signal readout circuit is long. Therefore, in order to sufficiently suppress random, telegraph, and noise to a necessary level, it is necessary to keep the gate-source voltage below the threshold value for a time corresponding to several frames in at least an image.

  However, this means that one pixel signal readout / integration system MOS transistor cannot be brought into a bias state that requires a time corresponding to several frames, and an infrared image cannot be obtained at a predetermined frame rate. Invite the situation. Therefore, in the signal readout circuit of the infrared imaging device, it is difficult to reduce random telegraph noise by simply using the method as described above.

  An object of the present invention is to reduce random telegraph noise in an infrared detector signal readout circuit operating at a predetermined detection speed and an imaging circuit of an infrared imaging element that generates an infrared image at a predetermined frame rate. .

  In one aspect, the imaging circuit is an imaging circuit of an infrared imaging device including a plurality of infrared detection units arranged so as to form pixels, and a plurality of imaging circuits connected to the plurality of infrared detection units of the infrared imaging device. A signal readout circuit; Each of the plurality of signal readout circuits includes a detection capacitor unit, an operation switch unit, a reset switch, a transfer capacitor unit, and a transfer switch. One terminal of the detection capacitor unit is connected to the first power source. The operation switch unit is connected between the infrared detection unit and the other terminal of the detection capacitor unit. The reset switch is connected between the other terminal of the detection capacitor unit and the second power source. The transfer switch is connected between the detection capacitor unit and the transfer capacitor unit. The operation switch section has a plurality of independently operated MOS transistors connected in parallel.

  In another aspect, the signal readout circuit is a signal readout circuit connected to the infrared detection unit, wherein one terminal is connected to the first power source, the infrared detection unit, and the other terminal of the capacitance unit. And a reset switch connected between the other terminal of the capacitor unit and the second power source, and the operation switch unit operates independently and connected in parallel. A plurality of MOS transistors.

  In yet another aspect, an infrared imaging device includes an infrared imaging device including a plurality of infrared detection units arranged to form pixels, and a plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging device. And an imaging circuit. Each signal readout circuit includes a detection capacitor unit, an operation switch unit, a reset switch, a transfer capacitor unit, and a transfer switch. One terminal of the detection capacitor unit is connected to the first power source. The operation switch unit is connected between the infrared detection unit and the other terminal of the detection capacitor unit. The reset switch is connected between the other terminal of the detection capacitor unit and the second power source. The transfer switch is connected between the detection capacitor unit and the transfer capacitor unit. The operation switch section has a plurality of independently operated MOS transistors connected in parallel.

  In yet another aspect, the infrared detection circuit includes an infrared detection unit and a signal readout circuit connected to the infrared detection unit. The signal readout circuit includes a capacitor unit, an operation switch unit, and a reset switch. One terminal of the capacitor is connected to the first power source. The operation switch unit is connected between the infrared detection unit and the other terminal of the capacitor unit. The reset switch is connected between the other terminal of the capacitor unit and the second power source. The operation switch section has a plurality of independently operated MOS transistors connected in parallel.

  In yet another aspect, the operating method of the imaging circuit is an operating method of the imaging circuit of the infrared imaging device including a plurality of infrared detection units arranged to form pixels. The imaging circuit has a plurality of signal readout circuits connected to a plurality of infrared detection units of the infrared imaging element. Each of the plurality of signal readout circuits includes a detection capacitor unit, an operation switch unit, a reset switch, a transfer capacitor unit, and a transfer switch. One terminal of the detection capacitor unit is connected to the first power source. The operation switch unit is connected between the infrared detection unit and the other terminal of the detection capacitor unit. The reset switch is connected between the other terminal of the detection capacitor unit and the second power source. The transfer switch is connected between the detection capacitor unit and the transfer capacitor unit. The operation switch section has a plurality of independently operated MOS transistors connected in parallel. According to this operation method of the imaging circuit, the detection capacitor unit is charged to the voltage difference between the second power supply and the first power supply by turning on the reset switch while the plurality of MOS transistors and the transfer switch are turned off. . With the reset switch and the transfer switch turned off, one of the plurality of operation switches is turned on for a predetermined time, thereby discharging the detection capacitor unit with a current corresponding to the amount of infrared detected by the infrared detection unit. With the plurality of MOS transistors and the reset switch turned off, the transfer switch is turned on to transfer the charge in the detection capacitor unit to the transfer capacitor unit. The above operation sequence is repeated, and the voltages of the transfer capacitor portions of the plurality of signal read circuits are sequentially read during each operation sequence. For each operation sequence, the MOS transistors that are turned on for a predetermined time among the plurality of MOS transistors are sequentially changed.

  According to the present invention, a signal readout circuit of an infrared detector and an imaging circuit of an infrared imaging device with reduced influence of random, telegraph, and noise can be obtained.

It is a figure which shows schematic structure of the video system using an infrared imaging device. It is a figure which shows the structural example of the imaging chip containing the infrared imaging element 2 and an imaging circuit. It is a figure which shows schematic structure and operation | movement of an infrared rays detection circuit, (A) is a block diagram, (B) is a time chart which shows operation | movement. It is a figure which shows schematic structure of the infrared rays detection circuit of 1st Embodiment. It is a time chart which shows operation | movement of the infrared rays detection apparatus of 1st Embodiment. It is a figure which shows the structure of the imaging circuit of the infrared imaging device of 2nd Embodiment. 3 is a diagram illustrating a detailed circuit configuration of a portion including four signal input circuits 21 in an imaging circuit. FIG. 8 is an operation signal time chart in an imaging circuit having the signal input circuit shown in FIG. 7. It is a figure which shows the example of an electric current change by the random telegraph noise (RTN) of an infrared detector.

Before describing the embodiment, a general infrared imaging device will be described.
FIG. 1 is a diagram illustrating a schematic configuration of a video system using an infrared imaging device. As shown in FIG. 1, the lens 3 projects an infrared image emitted from the observation object 4 onto the infrared imaging element 2 in the infrared imaging device 1. The projected infrared image is converted into an electrical signal by the photosensitive portion of the infrared imaging device 2. The electrical signals are multiplexed (multiplexed) by an imaging circuit provided adjacent to the infrared imaging device 2 in the infrared imaging device 1 and then sent to a signal processing circuit 10 provided outside the infrared imaging device 1. . The imaging circuit has a plurality of signal readout circuits corresponding to the plurality of photosensitive portions of the infrared imaging element 2. The signal processing circuit 10 includes, for example, an A / D conversion circuit, an arithmetic circuit, and a memory, and converts an analog signal output from the signal readout circuit of the imaging circuit into a digital signal. The signal processing circuit 10 may be provided in the infrared imaging device 1 in some cases.

  FIG. 2 is a diagram illustrating a structure example of an imaging chip including the infrared imaging device 2 and the imaging circuit. The imaging chip 5 includes an infrared imaging device (infrared sensor) (photosensitive portion) 2 made of a compound semiconductor material, and an imaging circuit 6 made of silicon (Si), and the infrared imaging device 2 and the imaging circuit 6. Are connected by bumps 7 made of indium (In). The infrared imaging element 2 has a plurality of pixels (photoelectric conversion units) arranged in a matrix, and each pixel outputs an electrical signal corresponding to incident light. The imaging circuit has a plurality of signal readout circuits corresponding to the plurality of pixels of the infrared imaging element 2.

FIG. 3 is a diagram showing a schematic configuration and operation of the infrared detection circuit, (A) is a configuration diagram, and (B) is a time chart showing the operation.
The infrared detection circuit shown in FIG. 3A is used in a form that is included in each pixel of the infrared imaging device that forms an infrared image, but realizes an infrared detection device such as an infrared thermometer alone. Can also be used.

Infrared detection circuit includes an infrared detector 8, the detection capacitor 11, and the MOS transistor Tr _R to form the reset switch, a MOS transistor Tr _ig forming the operation switch, the. A portion excluding the infrared detector 8 forms a signal readout circuit of the imaging circuit. When the infrared detector of FIG. 3 is used to form each pixel of the imaging circuit 6 of the imaging chip 5 of FIG. 2, the infrared detector 8 and the signal readout circuit are connected by the bump 7.

As shown in FIG. 3A, the MOS transistor Tr _R and the detection capacitor 11 are connected in series between the second power supply (VDR) and the first power supply (V _com (GND)). Reference symbol A indicates a connection node between the MOS transistor Tr _R and the detection capacitor 11, and the voltage at the node _A is represented by V _A. The MOS transistor _Trig and the infrared detector 8 are connected in series between the node A and the first power supply (V _com (GND)). Here, although the infrared detector 8 was connected to the first power source (V _com (GND)), may be connected to a power source of low negative voltage than the first power source (V _com (GND)) is there. A reset signal φR is applied to the gate of the MOS transistor Tr _R , and a signal φI _g is applied to the gate of the MOS transistor _Trig .

  The infrared detector 8 is used for a cooled infrared detector that is cooled and used, such as a quantum well infrared detector, a quantum dot infrared detector, or a Type-II infrared detector whose characteristics have been greatly improved in recent years. Element. As described above, in the signal readout circuit (imaging circuit) using the MOS transistor cooled together with such a cooled infrared detector, the influence of random, telegraph, and noise becomes significant. Quantum well type infrared detectors, quantum dot type infrared detectors, and Type-II type infrared detectors are widely known and will not be described in detail.

Here, the operation switch is shown to be formed by one MOS transistor _Trig, but is formed by connecting two transistors in series, one for determining the bias and the other for determining the integration timing and integration time. There is also a case. It is assumed that the operation switch includes the functions of these two transistors.

As shown in FIG. 3B, when the MOS transistor Tr _R is turned on while the MOS transistor _Trig is turned off, the detection capacitor 11 is charged and the voltage V _A at the node A is charged. Becomes the voltage V _R of the second power supply. Next, when the MOS transistor Tr _R is turned off and the MOS transistor _Trig is turned on for a predetermined time, the charge of the detection capacitor 11 is discharged through the MOS transistor _Trig and the infrared detector 8, and V _A is set to a predetermined discharge current. Decreases by the amount multiplied by time. Since the infrared detector 8 generates a current according to the amount of incident infrared rays, the discharge current changes in the infrared detector 8 according to the amount of infrared rays, and _VA changes according to the amount of infrared rays. Therefore, after a predetermined time has elapsed, the infrared detector 8 can detect the amount of incident infrared rays by reading V _A with the MOS transistor Tr _R and the MOS transistor _Trig turned off. Thereafter, the above operation is repeated every time the amount of infrared rays is detected.

As described above, when the MOS transistor is used in a cooled state, the influence of random telegraph and noise becomes remarkable. It is conceivable to reduce the influence of random telegraph noise by setting the period during which the gate-source voltage of the MOS transistor is below the threshold to be longer than the generation period of random telegraph noise. Here, in the infrared detecting device shown in FIG. 3A, it is considered that a constant bias voltage is applied to the first power supply (V _com ) with respect to the gate electrode of the transistor _Trig . At this time, the constant bias voltage applied to the first power supply (V _com ) may be 0 V (GND) or an arbitrary negative potential. In the following description, V _com = GND. In other words, this means applying a reverse bias voltage to the gate electrode of the transistor _Trig with respect to the voltage of the first power supply (V _com ).

When the voltage between the gate and source electrodes of the transistor _Trig in FIG. 3A is equal to or lower than the threshold value of the transistor, no current flows through the infrared detector 8. Therefore, according to Ohm's law, the potential of the source electrode of the transistor _Trig matches V _com . From this, at the timing (Tr _R is OFF in FIG. 3B) other than the integration time of the signal of the infrared detector 8 (Tr _R is ON in FIG. 3B), the transistor Tr It becomes possible to perform reset operation against random, telegraph and noise of _ig . The following two methods can be considered for the reset operation.

(1) The bias voltage applied to the gate electrode of the transistor _Trig is controlled so that the gate-source voltage is less than the threshold value.
(2) The bias voltage V _com applied to the first power source to which the infrared detector 8 and the detection capacitor 11 are connected is set to an appropriate value, and the gate-source voltage of the transistor _Trig is set to a threshold value or less.
First, the transistor by controlling the bias voltage applied to the gate electrode of Tr _ig, the gate of the Tr _ig of (1) - explaining an example of the source voltage below the threshold.

  As described above, in a signal readout circuit (imaging circuit) in an infrared imaging device that is used by cooling in particular, the generated random telegraph noise often has a period corresponding to several frames in an image. In such a case, the influence of random telegraph noise can be reduced by turning off the signal readout circuit for a period longer than this period and then performing readout. However, in this case, in the configuration shown in FIG. 3A, a period during which detection cannot be performed occurs, and continuity of detection is impaired. In particular, when the configuration shown in FIG. 3A is applied to an infrared imaging device that generates an infrared image, the signal readout circuit is stopped for a period corresponding to several frames, and the generated frames are non- There is a problem of continuous images.

In any case, when the configuration shown in FIG. 3A is applied to a normal infrared imaging apparatus, there is a problem that random telegraph noise cannot be sufficiently suppressed.
In the embodiment described below, in order to solve this problem, an operation switch is formed by a plurality of transistors connected in parallel that can operate independently, and these transistor systems are sequentially arranged according to the integration timing corresponding to each image frame. Switch between and use. As a result, while one transistor of the plurality of transistors is operating (ON), the other remaining transistors are turned OFF, and the gate-source voltages of the remaining transistors are set to the threshold value or less. Since the period during which the transistors can be turned off is determined by the number of transistors provided in parallel, the number of transistors is set according to the period in which random telegraph noise occurs.

FIG. 4 is a diagram illustrating a schematic configuration of the infrared detection circuit according to the first embodiment.
The infrared detection circuit of the first embodiment is different from the general infrared detection device of FIG. 3 in that the operation switch is formed by three MOS transistors _Trig A to _Trig C connected in parallel. Are the same. Here, an example is shown in which three MOS transistors _Trig A to _Trig C are provided in parallel, but the number of MOS transistors provided in parallel is set as appropriate according to the period in which random, telegraph, and noise are generated.

FIG. 5 is a time chart showing the operation of the infrared detecting device of the first embodiment.
First, in the first cycle, when the MOS transistor Tr _R is turned on while the MOS transistors _Trig A to _Trig C are turned off, the detection capacitor 11 is charged, and the voltage V _A at the node A is equal to that of the second power supply. The voltage becomes V _R. When the MOS transistors _Trig A- _Trig C are turned off, the gate-source voltage is equal to or lower than the threshold value Vth. Next, when the MOS transistor Tr _R and the MOS transistor _Trig A to _Trig C are turned off and the MOS transistor _Trig A is turned on for a predetermined time, the electric charge of the detection capacitor 11 causes the MOS transistor _Trig A and the infrared detector 8 to be turned on. V _A decreases by an amount obtained by multiplying the discharge current by a predetermined time. Then, by turning on the read signal R _P read gate (not shown), it reads the V _A.

In the second cycle, when the MOS transistor Tr _R is turned on while the MOS transistors _Trig A to _Trig C are turned off, the detection capacitor 11 is charged, and the voltage V _A at the node A is the voltage V _A of the second power supply. Become _R. Next, when the MOS transistor Tr _R and the MOS transistors _Trig A and _Trig C are turned off and the MOS transistor _Trig B is turned on for a predetermined time, the charge of the detection capacitor 11 causes the MOS transistor _Trig B and the infrared detector 8 to be turned on. V _A decreases by an amount obtained by multiplying the discharge current by a predetermined time. Then, by turning on the read signal R _P to read gate, reads the V _A.

In the third cycle, when the MOS transistor Tr _R is turned on while the MOS transistors _Trig A to _Trig C are turned off, the detection capacitor 11 is charged, and the voltage V _A at the node A is equal to the voltage V of the second power supply. Become _R. Next, when the MOS transistor Tr _R and the MOS transistors _Trig A and _Trig B are turned off and the MOS transistor _Trig C is turned on for a predetermined time, the electric charge of the detection capacitor 11 causes the MOS transistor _Trig C and the infrared detector 8 to be turned on. V _A decreases by an amount obtained by multiplying the discharge current by a predetermined time. Then, by turning on the read signal R _P to read gate, reads the V _A.

  By repeating the above first to third cycles, the amount of infrared rays incident on the infrared detector 8 can be continuously detected.

As described above, in the first embodiment, the MOS transistor Tr _R repeats the same operation as (B) in FIG. 3, between the three on-off operation of the MOS transistor Tr _R, 3 pieces of MOS Transistors _Trig A- _Trig C are turned on one by one in order. The timing at which the MOS transistors _Trig A to _Trig C are turned on with respect to the operation timing of the MOS transistor Tr _R is the same as (B) in FIG. Accordingly, each of the MOS transistors _Trig A to _Trig C is turned off for a period of at least two cycles or more, and actually a little shorter than the period of three cycles, and the gate-source voltage during this period is smaller than the threshold value. . If the period in which random, telegraph, and noise are generated is sufficiently shorter than the period of 3 cycles, random telegraph and noise will not be generated during the period when each of the MOS transistors _Trig A to _Trig C is turned on. Noise can be reduced. If the period in which random, telegraph, and noise are generated is longer, increase the number of MOS transistors connected in parallel and set the period for turning off each MOS transistor to be longer than the period in which random, telegraph, and noise are generated. Lengthen.

In FIG. 5, the bias voltage V _com applied to the first power source to which the infrared detector 8 and the detection capacitor 11 are connected is fixed to GND, and the bias voltage applied to the gate electrodes of the transistors _Trig A to _Trig C is controlled. The gate voltage of the MOS transistors _Trig A to _Trig C to be turned off was set to a threshold value or less. However, as described above, the bias voltage V _com applied to the first power source to which the infrared detector 8 and the detection capacitor 11 are connected is set to an appropriate value, and the gate-source voltage of the MOS transistors _Trig A to _Trig C is set. Can be set to be equal to or less than a threshold value.

  The second embodiment to be described next relates to an infrared imaging device having a focal plane array (FPA) type infrared imaging device, in which the configuration of the infrared detection circuit of the first embodiment is applied to the pixels of the infrared imaging device. . The following description of the infrared imaging device of the second embodiment relates to an imaging chip including the infrared imaging device 2 and the imaging circuit shown in FIGS. 1 and 2.

FIG. 6 is a diagram illustrating a configuration of an imaging circuit of the infrared imaging device according to the second embodiment.
The imaging circuit is a circuit that reads an electrical signal from each of a plurality of pixels arranged in a matrix of an infrared imaging device by a signal readout circuit.

  As shown in FIG. 6, the imaging circuit includes a plurality of scan lines SL0 to SLn-1, a plurality of vertical bus lines BL0 to BLm-1, a plurality of signal input circuits 21, a vertical shift register 22, and a horizontal shift. And a register 23. The imaging circuit further includes a plurality of bus selection switches 24, a plurality of bus selection lines CL0 to CLm-1, a common line 25, an amplifier 26, and a control circuit 27.

  The plurality of scan lines SL0 to SLn-1 and the plurality of vertical bus lines BL0 to BLm-1 are arranged corresponding to the matrix arrangement of the plurality of pixels of the infrared imaging element 2. The plurality of signal input circuits 21 are arranged corresponding to the intersections of the plurality of scan lines SL0 to SLn-1 and the plurality of vertical bus lines BL0 to BLm-1.

  The vertical shift register 22 sequentially applies vertical position selection signals (scan signals) to the plurality of scan lines SL according to the vertical scan start signal φVDT and the vertical shift clock φVCK. When a vertical position selection signal is applied to the corresponding scan line SL, the signal input circuit 21 of each row outputs a signal corresponding to the amount of charge held in the transfer capacitor to the corresponding vertical bus line BL.

  The horizontal shift register 23 sequentially applies a horizontal position selection signal to the plurality of bus selection lines CL in response to the horizontal selection start signal φHDT and the horizontal shift clock φHCK. In response to this, the plurality of bus selection switches 24 are sequentially turned on, and the signals output from the signal input circuits 21 of each row to the plurality of vertical bus lines BL are output to the common line 25 and output from the amplifier 26.

In addition to the vertical shift register 22 and the horizontal shift register 23, the control circuit 27 generates a signal for controlling a switch of the signal input circuit 21 shown in FIG.
Since the entire configuration of the imaging circuit in FIG. 6 is widely known, further description thereof is omitted.

  FIG. 7 is a diagram showing a detailed circuit configuration of a part including four signal input circuits 21 in the imaging circuit.

The signal input circuit 21 includes a detection capacitor C1, a transfer capacitor C2, three operation transistors _Trig A- _Trig C, two N-type MOS transistors (NMOS) 35 and 36, and a P-type MOS transistor ( PMOS) Tr _R and a transfer gate (TG) 34. The operating transistors _Trig A- _Trig C are also NOS transistors. Operating transistor Tr _ig A-Tr _ig C corresponds to the operating transistor Tr _ig A-Tr _ig C in FIG. Although the transistor Tr _R has a different polarity, it corresponds to the reset transistor Tr _R in FIG. C1 corresponds to the detection capacitor 11.

Tr _R and C1 are connected in series between the reset power supply VDR and the ground GND. When the reset signal φR applied to the gate of Tr _R is “Low (L)”, Tr _R becomes conductive, and C1 is reset. Charged to voltage. Tr _ig A to _Trig C are connected in parallel between the connection terminal to the bump 7 connected to the sensor element 8 of the corresponding pixel of the image sensor 2 and the connection node (node A) of Tr _R and C1. The Tr _ig A-Tr _ig applied signal φIga-φIgc to the gate of C is "high (High: H)" when the, conductive and tr _ig A-tr _ig C, node A is connected to the bump 7. The TG 34 is conductive when one terminal is connected to the node A, the other terminal is connected to the gate of the transistor 35, and the sample hold signal φSH is H. Sample hold signal φSH corresponds to read signal R _P. C2 is connected between the other terminal of TG34 and GND. Transistors 35 and 36 are connected in series between analog power supply VDA and corresponding vertical bus line BLj. The gate of the transistor 35 is connected to the connection node (the other terminal of the TG 34) of C2 and TG 34, and the gate of the transistor 36 is connected to the corresponding scan line SLi. Other signal input circuits have the same configuration.

In the signal input circuit 21, when the reset signal φR becomes L, Tr _R becomes conductive and a reset operation is performed in which the detection capacitor C 1 is charged to the reset voltage VDR. When the reset signal φR is reset operation changes to H is completed, any of the signals φIga-φIgc becomes H, either the corresponding Tr _ig A-Tr _ig C are turned on, turned-on transistors, the bumps 7 Thus, a current corresponding to the light receiving state of the sensor element 8 flows from C1 to GND. In other words, the current corresponding to the light receiving state of the sensor element 8 is discharged from C1 charged to the reset voltage VDR, and an accumulation operation is performed in which the voltage of C1 becomes a voltage corresponding to the light receiving state. Signal φIga-φIgc all become L, was blocked Tr _ig A-Tr _ig C, the sample hold signal φSH becomes H, TG 34 becomes conductive, C1 and C2 are the same voltage, that is, the voltage of C1 is C2 The transfer operation is performed after being transferred to and held. After the transfer operation, φSH becomes L again. Such an operation is performed in each of the other signal input circuits, and a voltage corresponding to the light intensity of each sensor is held in the S / H capacitor C2. Thereafter, the signal input circuit sequentially changes the transistors to be turned on among _Trig A to _Trig C to perform the above-described operation on C1, and also performs the read operation of reading the voltage held in C2. . Here, in the transfer operation, the charge accumulated in the storage capacitor C1 is distributed to the storage capacitor C1 and the S / H capacitor C2 according to the capacity ratio. Therefore, it is desirable that the capacity of the S / H capacity C2 is sufficiently smaller than the storage capacity C1.

  In the reading operation, as described above, the vertical scanning shift register 22 sequentially outputs scan signals (vertical position selection signals) for selecting the plurality of scan lines SL one by one. In response to this, the voltage held in the S / H capacitor C2 of the signal input circuit 21 of each line is output to the plurality of vertical bus lines BL via the transistors 35 and 36. The horizontal shift register 23 sequentially selects the plurality of bus selection switches 24, and the detection signals output to the plurality of vertical bus lines BL are sequentially output via the common line 25 and the amplifier 26.

Since the operation as described above, may be referred to the Tr _R reset switch, exposing the Tr _ig A-Tr _ig C switch, the sample-hold switch TG 34, the signal conversion unit transistors 35, select transistors 36 switches, and.

FIG. 8 is an operation signal time chart in the imaging circuit having the signal input circuit 21 shown in FIG.
The vertical scan start signal φVDT is a positive pulse that is normally L and has a short time H. The signal φR is a negative pulse that is normally H and has a short time L, and the period of L is the same as that of φVDT. Each of the signals φIga-φIgc is a pulse that becomes a time H, which is normally L, and the period that becomes H is a period that is three times as large as φR. After φR changes from L to H, it changes to H, φVDT changes to L before it changes from L to H. φIga changes to H after the negative pulse of φR changes from L to H, and changes to L before the positive pulse of φVDT changes from L to H, but then changes with two negative pulses of φR. L is maintained, and then changes to H after the change of the negative pulse of φR from L to H as described above. The same applies to φIgb and φIgc. In φIga−φIgc, the period of H shifts by one period of φR.

  As described in the first embodiment, the reset operation is performed when φR becomes L, then φR becomes H, and the accumulation operation is performed during the period of φIga = H. When φIga becomes L, φS / H becomes H for a short period of time, and a transfer operation is performed. Thereafter, this operation is repeated while sequentially changing the signal which becomes H among φIga-φIgc. On the other hand, in parallel with the above operation, after φS / H changes from H to L and the transfer operation is completed, a read operation is performed in a period of φS / H = L.

  Vertical shift register 22 receives vertical synchronizing signal φVDT and vertical clock φVCK. The vertical synchronization signal φVDT is output for each reading operation for reading all the pixels of the infrared imaging element 2, and the vertical clock φVCK corresponds to a cycle for reading the pixels of one scan line SL. The horizontal shift register 23 receives a horizontal synchronization signal φHDT and a horizontal clock φHCK. The horizontal synchronization signal φHDT has the same cycle as the vertical clock φVCK. The vertical synchronization signal φVDT becomes H in response to φS / H becoming H, becomes L in response to φS / H becoming L, and when it is H, the register of the vertical shift register 22 is reset. To do. When φHDT changes from H to L, the vertical shift register 22 sequentially outputs scan signals from the first scan line SL to the last scan line SL in the cycle of the vertical clock φVCK. The horizontal synchronizing signal φHDT returns to L after it becomes H for a short time in synchronization with the rising edge of the vertical clock φVCK. When the horizontal synchronization signal φHDT changes from H to L, the horizontal shift register 23 outputs a selection signal for sequentially selecting the last selection switch from the first selection switch. Here, it is assumed that the cycle of the selection signal is equal to the cycle of the horizontal clock φHCK.

The horizontal shift register 23 and the vertical shift register 22 apply the above signals to the plurality of scan lines SL0 to SLn-1 and the plurality of vertical bus lines BL0 to BLm-1, thereby transferring the charges transferred to the transfer capacitors of all the pixels. A voltage corresponding to the quantity is read. As a result, in one read operation, the charge amount (voltage) due to the accumulation operation performed when _Trig A is turned on is read, and in the next read operation, the charge amount due to the accumulation operation performed when _Trig B is turned on is read. In the next read operation, the charge amount (voltage) by the accumulation operation performed when _Trig C is turned on is read.

Thus, each of the MOS transistors Tr _ig A-Tr _ig C of each pixel, and a little shorter period off than three periods of FaiVDT, during this period of the gate - source voltage is smaller than the threshold. If the period of random, telegraph, and noise generation is sufficiently shorter than the period of 3 cycles, random telegraph and noise will not occur during the period when each of _Trig A- _Trig C is turned on. Can be reduced.

Here, the random / telegraph / noise suppression effect is considered more quantitatively.
FIG. 9 is a diagram showing an example of current change due to random telegraph noise (RTN) of the infrared detector.

  In FIG. 9, assuming that the intensity of the infrared ray incident on the infrared detector is constant, the change in the current flowing through the infrared detector and the MOS transistor when the accumulation operation for setting the gate-source voltage of the MOS transistor below the threshold is not performed. An example is shown. Since the accumulation operation is not performed, it is considered that RTN occurs and the current fluctuation changes as shown. In this case, the same apparent signal output is obtained in the first and second frames, but the apparent signal output varies in the third frame. Therefore, in this case, an accumulation operation necessary for suppressing the current fluctuation of the MOS transistor due to RTN for a time corresponding to at least three frames is required.

  Here, in the trap related to RTN, if it is considered that the capture probability and the release probability are the same, it is estimated that the accumulation operation needs to be performed for at least three frames.

  Similarly, in a general imaging circuit, when the number of MOS transistors provided in parallel in the operation switch is N and the frame frequency of the image is ff, the accumulation operation time Ta for one transistor is Ta = (N− 1) / ff Therefore, when the RTN generation cycle is Tn, it can be seen that the effect of suppressing the influence by RTN is obtained when (N−1) / ff> Tn is satisfied.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
An imaging circuit of an infrared imaging device including a plurality of infrared detection units arranged to form a pixel,
A plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging device;
Each of the plurality of signal readout circuits includes:
A detection capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the detection capacitor;
A reset switch connected between the other terminal of the detection capacitor unit and a second power source;
A transfer capacity section;
A transfer switch connected between the detection capacitor unit and the transfer capacitor unit;
The image pickup circuit, wherein the operation switch section includes a plurality of independently operated MOS transistors connected in parallel.
(Appendix 2)
The imaging circuit according to appendix 1, wherein the imaging circuit is cooled together with the infrared imaging device.
(Appendix 3)
The imaging circuit according to appendix 1 or 2, wherein the plurality of MOS transistors are operated by being sequentially switched.
(Appendix 4)
When the average period of random telegraph noise caused by the MOS transistor is Tn,
Each of the plurality of MOS transistors is sequentially turned on with an interval of Tn or more,
The imaging circuit according to any one of supplementary notes 1 to 3, wherein a gate-source voltage of the plurality of MOS transistors other than the turned-on MOS transistor is not more than a threshold value.
(Appendix 5)
When the number of the plurality of MOS transistors is N and the frame frequency is ff,
The imaging circuit according to appendix 4, wherein (N-1) / ff> Tn.
(Appendix 6)
The imaging circuit according to any one of appendices 1 to 5, wherein the infrared detection unit includes a quantum well infrared detector.
(Appendix 7)
The imaging circuit according to any one of appendices 1 to 5, wherein the infrared detection unit includes a quantum dot infrared detector.
(Appendix 8)
The imaging circuit according to any one of appendices 1 to 5, wherein the infrared detection unit includes a Type-II superlattice infrared detector.
(Appendix 9)
A signal readout circuit connected to the infrared detector;
A capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the capacitor;
A reset switch connected between the other terminal of the capacitor and a second power source,
The operation switch section includes a plurality of independently operated MOS transistors connected in parallel.
(Appendix 10)
An infrared imaging device including a plurality of infrared detectors arranged to form pixels;
An imaging circuit having a plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging element;
Each signal readout circuit
A detection capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the detection capacitor;
A reset switch connected between the other terminal of the detection capacitor unit and a second power source;
A transfer capacity section;
A transfer switch connected between the detection capacitor unit and the transfer capacitor unit;
The operation switch section includes a plurality of independently operated MOS transistors connected in parallel.
(Appendix 11)
An infrared detector;
A signal readout circuit connected to the infrared detector,
The signal readout circuit includes:
A capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the capacitor;
A reset switch connected between the other terminal of the capacitor and a second power source,
The infrared ray detection circuit, wherein the operation switch section includes a plurality of independently operated MOS transistors connected in parallel.
(Appendix 12)
An imaging circuit of an infrared imaging element including a plurality of infrared detection units arranged so as to form a pixel, and having a plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging element; Each of the plurality of signal readout circuits includes a detection capacitor unit having one terminal connected to a first power supply, and an operation switch unit connected between the infrared detection unit and the other terminal of the detection capacitor unit. A reset switch connected between the other terminal of the detection capacitor unit and the second power source, a transfer capacitor unit, and a transfer switch connected between the detection capacitor unit and the transfer capacitor unit. The operation switch unit is an operation method of an imaging circuit having a plurality of independently operated MOS transistors connected in parallel,
With the plurality of MOS transistors and the transfer switch turned off, by turning on the reset switch, the detection capacitor unit is charged to the voltage difference between the second power supply and the first power supply,
With the reset switch and the transfer switch turned off, one of the plurality of MOS transistors is turned on for a predetermined time, thereby discharging the detection capacitor unit with a current corresponding to the amount of infrared detected by the infrared detection unit. ,
With the plurality of MOS transistors and the reset switch turned off, by turning on the transfer switch, the charge of the detection capacitor unit is transferred to the transfer capacitor unit, and an operation sequence is repeated.
During each operation sequence, sequentially read the voltages of the transfer capacitor portions of the plurality of signal readout circuits,
A method for operating an imaging circuit, wherein MOS transistors that are turned on for a predetermined time among the plurality of MOS transistors are sequentially changed for each operation sequence.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 1 Infrared imaging device 2 Infrared imaging device 3 Lens 5 Imaging chip 6 Imaging circuit 7 Bump 8 Infrared detector 11 Detection capacity 21 Signal input circuit 22 Vertical shift register 23 Horizontal shift register 24 Bus selection switch 25 Common line 26 Amplifier 27 Control circuit C1 Detection capacity C2 Transfer capacity
Tr _R Reset transistor
Tr _ig A-Tr _ig C operation switching transistor SL0~SLn-1 scan line BL0 to BLm-1 vertical bus line CL0~CLm-1 bus select line

Claims (9)

An imaging circuit of an infrared imaging device including a plurality of infrared detection units arranged to form a pixel,
A plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging device;
Each of the plurality of signal readout circuits includes:
A detection capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the detection capacitor;
A reset switch connected between the other terminal of the detection capacitor unit and a second power source;
A transfer capacity section;
A transfer switch connected between the detection capacitor unit and the transfer capacitor unit;
The image pickup circuit, wherein the operation switch section includes a plurality of independently operated MOS transistors connected in parallel.   The imaging circuit according to claim 1, wherein the imaging circuit is cooled together with the infrared imaging device.   The imaging circuit according to claim 1, wherein the plurality of MOS transistors are operated by being sequentially switched. When the average period of random telegraph noise caused by the MOS transistor is Tn,
Each of the plurality of MOS transistors is sequentially turned on with an interval of Tn or more,
4. The imaging circuit according to claim 1, wherein the MOS transistors other than the plurality of MOS transistors that are not turned on have a gate-source voltage equal to or lower than a threshold value. 5. When the number of the plurality of MOS transistors is N and the frame frequency is ff,
The imaging circuit according to claim 4, wherein (N−1) / ff> Tn. A signal readout circuit connected to the infrared detector;
A capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the capacitor;
A reset switch connected between the other terminal of the capacitor and a second power source,
The operation switch section includes a plurality of independently operated MOS transistors connected in parallel. An infrared imaging device including a plurality of infrared detectors arranged to form pixels;
An imaging circuit having a plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging element;
Each signal readout circuit
A detection capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the detection capacitor;
A reset switch connected between the other terminal of the detection capacitor unit and a second power source;
A transfer capacity section;
A transfer switch connected between the detection capacitor unit and the transfer capacitor unit;
The operation switch section includes a plurality of independently operated MOS transistors connected in parallel. An infrared detector;
A signal readout circuit connected to the infrared detector,
The signal readout circuit includes:
A capacitor having one terminal connected to the first power source;
An operation switch connected between the infrared detector and the other terminal of the capacitor;
A reset switch connected between the other terminal of the capacitor and a second power source,
The infrared ray detection circuit, wherein the operation switch section includes a plurality of independently operated MOS transistors connected in parallel. An imaging circuit of an infrared imaging element including a plurality of infrared detection units arranged so as to form a pixel, and having a plurality of signal readout circuits connected to the plurality of infrared detection units of the infrared imaging element; Each of the plurality of signal readout circuits includes a detection capacitor unit having one terminal connected to a first power supply, and an operation switch unit connected between the infrared detection unit and the other terminal of the detection capacitor unit. A reset switch connected between the other terminal of the detection capacitor unit and the second power source, a transfer capacitor unit, and a transfer switch connected between the detection capacitor unit and the transfer capacitor unit. The operation switch unit is an operation method of an imaging circuit having a plurality of independently operated MOS transistors connected in parallel,
With the plurality of MOS transistors and the transfer switch turned off, by turning on the reset switch, the detection capacitor unit is charged to the voltage difference between the second power supply and the first power supply,
With the reset switch and the transfer switch turned off, one of the plurality of MOS transistors is turned on for a predetermined time, thereby discharging the detection capacitor unit with a current corresponding to the amount of infrared detected by the infrared detection unit. ,
With the plurality of MOS transistors and the reset switch turned off, by turning on the transfer switch, the charge of the detection capacitor unit is transferred to the transfer capacitor unit, and an operation sequence is repeated.
During each operation sequence, sequentially read the voltages of the transfer capacitor portions of the plurality of signal readout circuits,
A method of operating an imaging circuit, wherein MOS transistors that are turned on for a predetermined time among the plurality of MOS transistors are sequentially changed for each operation sequence.

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