JP2017191464A - Information processing system, transmitter, and control method of information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an erroneous packet transmitted by a transmitter from being processed by a receiver.SOLUTION: Software to be executed by a transmitter stores data in a first holding unit which holds first key information. A management unit of the transmitter stores second key information in a second holding unit configured to prohibit the software from writing data. A packet generation unit of the transmitter generates a packet including the data held by the first and second holding units and first and second key information. A first comparison unit of the receiver compares the first key information included in the packet with first key information held by a third holding unit. A second comparison unit of the receiver compares the second key information included in the packet with second key information held in the third holding unit. A write control unit of the receiver writes the data included in the packet on a storage unit when both first and second comparison units show coincidence.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing system, a transmission apparatus, and a control method for the information processing system.

  In an information processing system including a plurality of nodes that transmit and receive data to and from each other, a method is proposed in which a plurality of pointer sets that store a write pointer and a read pointer that indicate a storage position of reception data in a queue that stores reception data are provided at the reception node Has been. In this type of information processing system, a program executed by a transmission node that transmits data stores transmission data and information indicating a pointer set used by the reception node in a register for transmission. The transmission node generates a packet including transmission data stored in the transmission register and information indicating the pointer set, and transmits the generated packet to the reception node. The receiving node selects the pointer set indicated by the information included in the received packet, and stores the received data in the area indicated by the write pointer of the selected pointer set (see, for example, Patent Document 1).

  Further, in an information processing system including a transmitting terminal device that transmits a packet and a receiving terminal device that receives a packet, the receiving terminal device is held in a slot identified by a slot identification value included in the received packet. There is known a technique for processing a packet by using the received information. If the protection terminal included in the received packet matches the protection key held in the slot identified by the slot identification value, the receiving terminal device determines that the received packet is normal and accepts the packet. The process is executed (see, for example, Patent Document 2).

JP2013-214168A JP-A-6-309252

  In the information processing system described above, for example, even when another transmitting terminal device transmits a packet including a protection key and an incorrect slot identification value to the receiving terminal device, the receiving terminal device matches even the protection key. If so, the packet is accepted. In this case, the receiving terminal device may malfunction due to processing of a packet received in error.

  In some cases, each of a plurality of programs executed by the transmitting terminal device transmits a packet to each of the plurality of programs executed by the receiving terminal device using the slot identification value and the protection key. In this case, when the program executed by the transmitting terminal device transmits a packet including a slot identification value and a protection key used in another program, the program of the receiving terminal device corresponding to the other program is incorrect. A packet is received.

  In one aspect, the information processing system, the transmission device, and the control method for the information processing system disclosed herein may cause the system to malfunction by preventing an erroneous packet transmitted by the transmission device from being processed by the reception device. The purpose is to prevent.

  According to one aspect, in an information processing system including a transmission device that transmits data and a reception device that receives data from the transmission device, the transmission device includes a data processing unit that executes software for generating data, A first holding unit for holding the key information and the data generated by the software, a management unit for managing the operation of the data processing unit and generating the second key information, and a second key generated by the management unit A second holding unit that holds information and is prohibited from being written by software; data and first key information held by the first holding unit; and second key information held by the second holding unit A packet generation unit that generates a packet including a packet transmission unit that transmits a packet generated by the packet generation unit, and the reception device includes a packet reception unit that receives a packet from the transmission device, A third holding unit that holds the first key information and the second key information, the first key information included in the packet received by the packet receiving unit, and the first key held in the third holding unit A first comparison unit that compares the second key information held in the third holding unit with the first comparison unit that compares the second key information held in the packet received by the packet receiving unit. When the comparison results of the second comparison unit and the first comparison unit indicate coincidence and the comparison result of the second comparison unit indicates coincidence, the data included in the packet received by the packet reception unit is stored in the storage unit. A write controller for writing;

  According to another aspect, a transmitting device that is mounted on an information processing system together with a receiving device and transmits data to the receiving device is generated by a data processing unit that executes software for generating data, first key information and software A first holding unit for holding data, a management unit for managing the operation of the data processing unit and generating second key information, a second key information generated by the management unit, and writing by software Packet generation for generating a packet including a second holding unit in which data is prohibited, data and first key information held by the first holding unit, and second key information held by the second holding unit And a packet transmission unit that transmits the packet generated by the packet generation unit.

  According to still another aspect, in a control method of an information processing system including a transmission device that transmits data and a reception device that receives data from the transmission device, a data processing unit included in the transmission device generates data, The software that stores the generated data in the first holding unit that holds the first key information is executed, and the management unit of the transmission device manages the operation of the data processing unit and generates the second key information Then, the generated second key information is stored in a second holding unit that is prohibited from being written by software, and the packet generation unit included in the transmission apparatus stores data and first key information held by the first holding unit. And the second key information held by the second holding unit, the packet transmission unit included in the transmission device transmits the packet generated by the packet generation unit, and the packet included in the reception device. The packet reception unit receives the packet from the transmission device, and the first comparison unit included in the reception device holds the first key information included in the packet received by the packet reception unit and the third holding unit. The second comparison unit included in the reception device compares the second key information contained in the packet received by the packet reception unit with the first key information held in the third holding unit. 2, the write control unit of the receiving device has a packet reception unit when the comparison result by the first comparison unit shows a match and the comparison result by the second comparison unit shows a match. The data included in the received packet is written in the storage unit.

  The information processing system, the transmission device, and the control method for the information processing system disclosed in the present disclosure may prevent the system from malfunctioning by suppressing an erroneous packet transmitted by the transmission device from being processed by the reception device. it can.

It is a figure which shows one Embodiment of the information processing system, the transmitter, and the control method of an information processing system. It is a figure which shows an example of operation | movement of the information processing system shown in FIG. It is a figure which shows another embodiment of the information processing system, the transmission apparatus, and the control method of an information processing system. It is a figure which shows an example of CPU shown in FIG. FIG. 5 is a diagram illustrating an example of a register unit 20 illustrated in FIG. 4 and elements that operate when a packet control unit transmits a packet. It is a figure which shows an example of the packet which the packet generation part shown in FIG. 5 produces | generates. It is a figure which shows an example of the state of the information processing system shown in FIG. It is a figure which shows an example of the access authority of the register | resistor provided in each entry of the register part shown in FIG. FIG. 5 is a diagram illustrating an example of a register unit 60 illustrated in FIG. 4 and elements that operate when a packet control unit receives a packet. It is a figure which shows an example of the packet determination part shown in FIG. It is a figure which shows an example of operation | movement of the information processing system shown in FIG. It is a figure which shows another example of operation | movement of the information processing system shown in FIG. It is a figure which shows an example of operation | movement of another information processing system. It is a figure which shows an example of the process which transmits the packet which the packet control part shown in FIG. 4 performs. It is a figure which shows an example of the process which receives the packet which the packet control part shown in FIG. 4 performs. FIG. 16 is a diagram showing a continuation of the processing shown in FIG. 15. It is a figure which shows an example of a process in the case of transmitting a packet with the application program which the core shown in FIG. 4 performs. It is a figure which shows an example of a process in case a packet is received by the application program which the core shown in FIG. 4 performs.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of an information processing system, a transmission device, and a control method for the information processing system. The information processing system SYS1 illustrated in FIG. 1 includes a transmission device 100 that transmits data and a reception device 200 that receives data from the transmission device 100. The transmission apparatus 100 includes a data processing unit 110, a management unit 120, holding units 130 and 140, a packet generation unit 150, and a packet transmission unit 160. The receiving apparatus 200 includes a packet receiving unit 210, a holding unit 220, comparison units 230 and 240, a write control unit 250, and a storage unit 260. The holding unit 130 is an example of a first holding unit, the holding unit 140 is an example of a second holding unit, and the holding unit 220 is an example of a third holding unit.

  The data processing unit 110 generates data DATA by executing the application program APRG, and stores the generated data DATA in the holding unit 130 that holds the key information KEY1. The application program APRG is an example of software executed by the data processing unit 110. The data processing unit 110 is a processor such as a CPU (Central Processing Unit) mounted on the transmission device 100 or a processor core included in the processor.

  The management unit 120 manages the operation of the data processing unit 110, generates key information KEY2, and stores the generated key information KEY2 in the holding unit 140. The management unit 120 is realized by a management program such as an OS (Operating System) that manages the operation of the data processing unit 110 or a control program such as a hypervisor that controls a virtual machine that executes the OS. Alternatively, the management unit 120 is realized by a state management program executed by a management device such as a service processor that manages the state of the data processing unit 110. Note that the management unit 120 may be provided outside the transmission apparatus 100.

  For example, the storage areas of the holding units 130 and 140 are allocated to the I / O space. The holding unit 130 can be accessed by the application program APRG, and the holding unit 140 is prohibited from being written by the application program APRG. That is, the holding unit 130 and the holding unit 140 have different access authorities. For this reason, it is possible to prevent the wrong key information KEY2 from being stored in the holding unit 140 due to a malfunction of the application program APRG or the like. In other words, the key information KEY2 held in the holding unit 140 is not erroneously rewritten by the application program APRG. The key information KEY1 is an example of first key information, and the key information KEY2 is an example of second key information.

  The packet generation unit 150 generates a packet including the data DATA and key information KEY1 held in the holding unit 130 and the key information KEY2 held in the holding unit 140. That is, the packet generation unit 150 generates a packet including the key information KEY1 and KEY2 held in the plurality of holding units 130 and 140 having different access authorities. The packet transmission unit 160 transmits the packet generated by the packet generation unit 150 to the reception device 200.

  The packet receiving unit 210 receives a packet from the transmission device 100. Further, the packet receiving unit 210 receives key information KEY1 and KEY2 generated before the transmitting apparatus 100 transmits data DATA, and stores the received key information KEY1 and KEY2 in the holding unit 220. That is, the holding unit 220 holds the key information KEY1 and KEY2 generated by the transmission device 100 in advance before the data DATA is transferred from the transmission device 100.

  The comparison unit 230 compares the key information KEY1 included in the packet received by the packet reception unit 210 with the key information KEY1 held in the holding unit 220, and outputs the comparison result to the write control unit 250. The comparison unit 240 compares the key information KEY2 included in the packet received by the packet reception unit 210 with the key information KEY2 held in the holding unit 220, and outputs the comparison result to the write control unit 250. The comparison unit 230 is an example of a first comparison unit, and the comparison unit 240 is an example of a second comparison unit.

  When the comparison result by the comparison unit 230 indicates a match and the comparison result by the comparison unit 240 indicates a match, the write control unit 250 determines that the packet received by the packet reception unit 210 is normal and is included in the packet Data to be written into the storage unit 260. On the other hand, when at least one of the comparison result by the comparison unit 230 and the comparison result by the comparison unit 240 indicates a mismatch, the write control unit 250 determines that the packet received by the packet reception unit 210 is not normal. In this case, the write control unit 250 discards the data included in the packet without writing it in the storage unit 260. For example, the storage unit 260 is allocated to a storage device such as an SDRAM (Synchronous Dynamic Random Access Memory), an HDD (Hard Disk Drive), or an SSD (Solid State Drive). The storage unit 260 may be provided outside the receiving device 200.

  As described above, the receiving apparatus 200 determines whether or not the received packet is normal using the key information KEY1 and KEY2 held in the plurality of holding units 130 and 140 having different access authorities. Therefore, compared with the case where it is determined whether or not the received packet is normal using one key information or a plurality of key information held in a plurality of holding units having the same access authority. Reliability can be improved. As a result, it is possible to prevent the receiving apparatus 200 from executing data processing or the like using erroneous data included in an abnormal packet, and the reliability of the information processing system SYS1 can be improved.

  FIG. 2 shows an example of the operation of the information processing system SYS1 shown in FIG. That is, FIG. 2 shows an example of a control method of the information processing system.

  The management unit 120 stores the key information KEY2 in the holding unit 140 and transfers it to the reception device 200 before transmission of data DATA to the reception device 200 is started (FIG. 2A). That is, storage of the key information KEY2 in the holding unit 140 by a program such as an OS higher than the application program APRG is executed in advance before the data DATA is transferred. For this reason, at the time of transferring data DATA to the receiving apparatus 200, the process switching for accessing the holding unit 140 does not occur, and the context switch for saving the process state does not occur at the process switching. Therefore, it is possible to prevent the execution efficiency of the application program APRG from decreasing due to a context switch or the like.

  The application program APRG transfers the key information KEY1 to the receiving device 200 before starting transmission of the data DATA to the receiving device 200 (FIG. 2 (b)). The receiving apparatus 200 stores the key information KEY1 and KEY2 transferred from the transmitting apparatus 100 in the holding unit 220 (FIG. 2 (c)).

  When transmitting the data DATA to the receiving device 200, the application program APRG stores the data DATA and the key information KEY1 in the holding unit 130 (FIG. 2 (d)). Thereafter, as indicated by the dashed arrow in FIG. 2, the application program APRG instructs the packet generation unit 150 to generate a packet (FIG. 2 (e)).

  Based on the instruction from the application program APRG, the packet generation unit 150 reads the data DATA and the key information KEY1 from the holding unit 130, and reads the key information KEY2 from the holding unit 140 (FIG. 2 (f)). Then, the packet generation unit 150 generates a packet including the data DATA and the key information KEY1 and KEY2, and transmits the generated packet to the reception device 200 (FIG. 2 (g)).

  The packet receiving unit 210 of the receiving apparatus 200 outputs the key information KEY1 included in the received packet to the comparison unit 230, and outputs the key information KEY2 included in the received packet to the comparison unit 240 (FIG. 2 (h)). .

  The comparison unit 230 compares the key information KEY1 from the packet reception unit 210 with the key information KEY1 held in the holding unit 220, and outputs the comparison result to the write control unit 250 (FIG. 2 (i)). The comparison unit 240 compares the key information KEY2 from the packet reception unit 210 with the key information KEY2 held in the holding unit 220, and outputs the comparison result to the write control unit 250 (FIG. 2 (j)).

  In the example illustrated in FIG. 2, the comparison result by the comparison unit 230 indicates a match, and the comparison result by the comparison unit 240 indicates a match, so that the write control unit 250 has a normal packet received by the packet reception unit 210. Is determined. Then, the write control unit 250 writes the data DATA included in the packet into the storage unit 260 (FIG. 2 (k)).

  As described above, in the embodiment shown in FIGS. 1 and 2, a program such as an OS higher than the application program APRG stores the key information KEY2 in the holding unit 140 that is not permitted to be accessed by the application program APRG. As a result, it is possible to prevent erroneous key information KEY2 from being stored in the holding unit 140 due to a malfunction of the application program APRG or the like. Further, by using the key information KEY1 and KEY2 held in the plurality of holding units 130 and 140 having different access authorities, it is possible to improve the reliability of the determination by determining whether or not the received packet is normal. Can do.

  Therefore, it is possible to prevent an erroneous packet transmitted by the transmission device 100 from being processed by the reception device 200, and the reception device 200 executes data processing or the like using data included in the erroneous packet. Can be suppressed. As a result, the reliability of the information processing system SYS1 can be improved.

  Storage of the key information KEY2 in the holding unit 140 by a program such as an OS higher than the application program APRG is executed in advance before the data DATA is transferred. For this reason, a context switch or the like does not occur when the data DATA is transferred to the receiving apparatus 200, and the execution efficiency of the application program APRG can be prevented from being lowered by the context switch or the like.

  FIG. 3 shows another embodiment of the information processing system, the transmission apparatus, and the control method of the information processing system. The information processing system SYS2 illustrated in FIG. 3 includes a plurality of nodes ND (ND0, ND1, ND2, ND3) connected to each other by a crossbar switch GXB. Each node ND is constructed by an information processing apparatus such as a server. Note that the number of nodes ND mounted in the information processing system SYS2 is not limited to four. Since the nodes ND0 to ND3 have the same or similar configuration, the configuration of the node ND0 will be described below.

  The node ND0 includes a plurality of CPUs (CPU0, CPU1), a plurality of storage devices MEM (MEM0, MEM1), a crossbar switch LXB, a switch SW, an HDD, and a network interface NWIF. Each CPU is connected to different storage devices MEM via a memory bus MBUS (MBUS0, MBUS1). For example, the storage device MEM is a DIMM (Dual Inline Memory Module) equipped with a plurality of SDRAMs. Each node ND may have an SSD instead of the HDD, or may have both an HDD and an SSD.

  In each node ND, the CPU can access the storage device MEM connected to another CPU. Further, the CPU of each node ND can access the storage device MEM connected to the CPUs of other nodes ND via the crossbar switches LXB and GXB. That is, the information processing system SYS2 functions as a multiprocessor system adopting a cc-NUMA (cache-coherent NonUniform Memory Access) architecture.

  The crossbar switch LXB connects each CPU to the crossbar switch GXB. The CPU in each node ND can directly transmit and receive information such as data without going through the crossbar switch LXB. The switch SW is, for example, a PCIe (Peripheral Component Interconnect express) switch or the like, and connects each CPU to the HDD or the network interface NWIF. The network interface NWIF is connected to a network such as a LAN (Local Area Network).

  The crossbar switch GXB outputs a packet including data received from each node ND to the node ND indicated by the destination information included in the packet. The crossbar switch GXB has a service processor SP that manages resources such as hardware of each node ND.

  For example, the service processor SP executes a state management program to control the power supply voltage and the clock frequency supplied to the CPU, and according to the temperature in the casing in which the CPU and the like in the node ND are stored. The number of rotations of a fan (not shown) attached to is controlled. The service processor SP is an example of a management device that manages the state of the CPU and the CPU core 10 shown in FIG. The service processor SP may be mounted on each node ND.

  FIG. 4 shows an example of the CPU shown in FIG. FIG. 4 shows elements related to processing of packets transferred between the CPU cores 10, and description of elements related to connection between the CPU and the switch SW shown in FIG. Omitted. A CPU that transmits a packet functions as a transmitting device, and a CPU that receives a packet functions as a receiving device.

  The CPU is connected to the CPU cores 10 (10a, 10b, 10c, 10d), the register unit 20, the packet control unit 30, the register unit 60, the memory control unit 70, and the memory control unit 70 connected to each other via the system bus SBUS. It has a connected cache memory 80. The CPU core 10 may be connected to the system bus SBUS via the memory control unit 70. The number of CPU cores 10 mounted on the CPU is not limited to four. In the following description, the CPU core 10 is also referred to as the core 10.

  Each core 10 executes an application program stored in the storage device MEM (FIG. 3) connected via the memory bus MBUS. The application program is an example of software executed by the core 10. Then, each core 10 transmits information such as data used for processing of the application program to the other core 10 or receives information such as data from the other core 10. That is, information such as data is transferred between application programs executed by the plurality of cores 10. The core 10 that transfers information such as data to each other may be included in one node ND or may be included in different nodes ND. The application program (instruction code) stored in the storage device MEM is held in the cache memory 80 based on being fetched by the core 10. The core 10 is an example of a data processing unit that executes an application program.

  The register unit 20 has a plurality of entries that hold data to be transmitted from each core 10 to other cores 10, information used for data transmission processing, and information included in responses from other cores 10 to the transmitted data Have ENTS. The entries ENTS are provided corresponding to the cores 10, respectively. The register unit 20 is accessed by each core 10 in the CPU and the packet control unit 30. An example of entry ENTS is shown in FIG.

  The packet control unit 30 includes a packet transmission control unit 40 and a packet reception control unit 50. When transmitting data, the packet transmission control unit 40 generates a packet using information including data held in the entry ENTS of the register unit 20, and transmits the generated packet via the crossbar switch LXB. Transmit to the previous core 10. Further, when the corresponding packet reception control unit 50 receives data, the packet transmission control unit 40 generates a response packet, and sends the generated response packet to the core 10 that is the data transmission source via the crossbar switch LXB. Send.

  The packet reception control unit 50 receives the packet via the crossbar switch LXB, and stores the data included in the received packet in the message queue MQUE (FIG. 9) assigned to the storage device MEM (FIG. 3). At this time, the packet reception control unit 50 refers to any of the entries ENTR in the register unit 60 based on information included in the packet, and determines a message queue MQUE for storing data. Further, when receiving a response packet corresponding to the packet transmitted by the packet transmission control unit 40, the packet reception control unit 50 executes the following operation. That is, the packet reception control unit 50 extracts information indicating the state of the message queue MQUE assigned to the core 10 that has transmitted the response packet from the response packet. Then, the packet reception control unit 50 stores the extracted information in the entry ENTS used for generating the transmission of the original packet among the entries ENTS of the register unit 20.

  When the core 10 that transmits a packet and the core 10 that receives a packet are included in one node ND, the packet is directly transferred between the cores 10 without going through the crossbar switch LXB. Examples of the packet transmission control unit 40 and the packet reception control unit 50 are shown in FIGS.

  The register unit 60 includes a plurality of entries ENTR that hold information accessed by the packet reception control unit 50 during packet reception processing. The entry ENTR is allocated for each application program that receives data. An example of the entry ENTR is shown in FIG.

  The memory control unit 70 operates based on a memory access request received from the core 10 via the system bus SBUS. Here, when the core 10 issuing the memory access request is included in another CPU, the memory access request is transferred from the core 10 of the other CPU to the memory control unit 70 via the packet reception control unit 50. The memory control unit 70 accesses the cache memory 80 when the target data of the memory access request is held in the cache memory 80 (cache hit). When the target data for the memory access request is not held in the cache memory 80 (cache miss), the memory control unit 70 accesses the storage device MEM connected to the memory bus MBUS, or requests a memory access to another CPU. Forward.

  The other CPU to which the memory access request has been transferred accesses the storage device MEM connected to the memory bus MBUS and issues an access result as a response. Note that the memory control unit 70 performs consistency processing (cache coherency) between the data held by the storage device MEM and the data held by the cache memory 80 by executing a eviction process or the like that drives data from the cache memory 80. Execute control. For example, the cache memory 80 is a secondary cache, and holds instructions executed by the application program and data processed by the application program.

  FIG. 5 shows an example of the register unit 20 shown in FIG. 4 and elements that operate when the packet control unit 30 transmits a packet. The element illustrated in FIG. 5 functions as a transmission device that transmits a packet. The packet transmission control unit 40 illustrated in FIG. 4 includes a packet generation unit 42 and a packet transmission unit 44, and the packet reception control unit 50 illustrated in FIG. 4 includes a packet reception unit 52 and a response storage unit 54.

  Each entry ENTS of the register unit 20 includes registers MSG-DT, MSGQ-ID (Identification), SEND-MSG, PK-SP, PK-HV, PK-OS, and ST. The register unit 20 is provided in an area (for example, an I / O space) different from the address space to which the storage device MEM is allocated. The application program (process) executed by the core 10 generates information to be held in the registers MSG-DT and MSGQ-ID, and stores the generated information in the registers MSG-DT and MSGQ-ID.

  The register PK-SP stores key information generated by the management program executed by the service processor SP. The register PK-HV stores key information generated by the hypervisor HV that is a control program for controlling the virtual machine that is activated in the node ND. The register PK-OS stores key information generated by the OS executed by the core 10 or the virtual machine. The application program (process) operates under the management of the OS, and the OS operates under the management of the hypervisor HV. The access authority of the registers PK-SP, PK-HV, and PK-OS will be described with reference to FIG. In the following description, the key information stored in the register PK-SP is referred to as key information PK-SP, the key information stored in the register PK-HV is referred to as key information PK-HV, and the register PK- The key information stored in the OS is referred to as key information PK-OS. Key information PK-SP, PK-HV, and PK-OS are examples of second key information. The register unit 20 is an example of a first holding unit and a second holding unit.

  For example, different entry key information PK-SP, different key information PK-HV, and different key information PK-OS are stored in the entry ENTS used by each of the plurality of cores 10 that execute the application program (process). . When the plurality of cores 10 execute application programs (processes), the processes can be switched without rewriting the key information PK-SP, PK-HV, and PK-OS held in the entry ENTS. That is, no context switch occurs when switching processes executed by different cores 10. On the other hand, when one core 10 executes a plurality of application programs (processes), since the plurality of processes use a common entry ENTS, a context switch occurs at the time of process switching.

  Each entry ENTS may include at least one of registers PK-SP, PK-HV, and PK-OS. For example, each entry ENTS may have only the register PK-OS, may have only the register PK-HV, or may have only the register PK-SP. Alternatively, each entry ENTS may have two registers PK-OS and PK-HV, two registers PK-OS and PK-SP, and two registers PK-HF and PK- You may have SP. For example, in an information processing system in which a virtual machine is not activated, each entry ENTS has two registers PK-OS and PK-HV.

  Information stored in the registers MSG-DT, MSGQ-ID, PK-SP, PK-HV, and PK-OS is read by the packet generation unit 42. Further, the application program sets the register SEND-MSG when the packet generation unit 42 generates a packet. Information held in the register ST is written by the response storage unit 54 and read by the application program.

  The register MSG-DT stores data (transmission data) transferred from the packet transmission source application program to the packet transmission destination application program. In the following description, the data stored in the register MSG-DT is also referred to as message data MSG-DT. Although not particularly limited, the message data MSG-DT is 32 bytes or 64 bytes.

  The register MSGQ-ID stores management information for transmitting the message data MSG-DT to the destination process. In the following description, data stored in the register MSGQ-ID is also referred to as management information MSGQ-ID. An example of the management information MSGQ-ID stored in the register MSGQ-ID is shown in FIG.

  The register SEND-MSG stores transmission request information when the packet generation unit 42 generates a packet and transmits the packet from the packet transmission unit 44. For example, the register SEND-MSG is 1 bit, and the transmission request information is logic 1. When the application program writes logic 1 to the register SEND-MSG, the register unit 20 outputs a one-shot pulse signal indicating a transmission request to the packet generation unit 42. In the following description, the logic 1 stored in the register SEND-MSG and the one-shot pulse signal output to the packet generator 42 are also referred to as a transmission request SEND-MSG.

  The register ST stores state information included in the response corresponding to the packet transmitted to the destination process. In the following description, the state information stored in the register ST is also referred to as state information ST. An example of the state information ST will be described with reference to FIG.

  The packet generation unit 42 generates a packet based on the reception of the transmission request SEND-MSG from the process via the register SEND-MSG, and outputs the generated packet to the packet transmission unit 44. That is, the packet generation unit 42 includes the transmission source CPU-ID and the entry ID, the management information MSGQ-ID, the message data MSG-DT, and the key information PK-SP, PK-HV, and PK-OS held in the entry ENTS. Is used to generate a packet. The transmission source CPU-ID indicates a number for identifying a CPU including the packet generation unit 42. The entry ID is a sequence number or the like added to the packet, and is used to take a correspondence between the packet and the response packet. An example of a packet generated by the packet generator 42 is shown in FIG.

  The packet generation unit 42 arbitrates the message data MSG-DT, management information MSGQ-ID, and key information PK-SP, PK-HV, and PK-OS held in the entry ENTS that has output the transmission request SEND-MSG. An arbitration unit (not shown) is selected.

  The packet transmission unit 44 transmits the packet received from the packet generation unit 42 toward the transmission destination core 10 via the crossbar switch LXB.

  The packet receiving unit 52 receives a packet (response packet) including the state information ST from the core 10 that is the destination of the packet via the crossbar switch LXB, and receives the state information ST included in the received packet as a response storage unit To 54. The response storage unit 54 stores the state information ST received from the packet reception unit 52 in the register ST of the entry ENTS that holds information that generated the original packet corresponding to the response packet.

  When transmitting the message data MSG-DT, the application program executes a process of transmitting a packet using the corresponding entry ENTS. After transmitting the packet, the application program reads the state information ST from the register ST based on the state information ST being written to the register ST.

  FIG. 6 shows an example of a packet generated by the packet generator 42 shown in FIG. The packet includes a destination CPU-ID, a source CPU-ID, an entry ID, management information MSGQ-ID, key information PK-SP, PK-HV, PK-OS, and message data MSG-DT. In the packet, destination CPU-ID, source CPU-ID, entry ID, management information MSGQ-ID and key information PK-SP, PK-HV, PK-OS are header parts, and message data MSG-DT is The data part. As the destination CPU-ID, the CPU information CPU-ID included in the management information MSGQ-ID is used.

  The management information MSGQ-ID includes CPU information CPU-ID, register set information REG-ID, key information AKEY, and message size M-SIZE. The CPU information CPU-ID includes a number that identifies the destination CPU of the packet. The register set information REG-ID is a number for identifying the entry ENTR (FIG. 9) of the register unit 60 used by the CPU that receives the packet. The key information AKEY is an example of first key information used for identification between the core 10 that transmits a packet and the core 10 that receives the packet, and is used to determine whether or not the packet is normal. . The register set information REG-ID and key information KEY are notified in advance from the packet receiving process to the packet transmitting process.

  The packet transmission / reception is managed not only by the key information AKEY but also by the key information PK-SP, PK-HV, and PK-OS that cannot be rewritten by the application program, so that the packet transmission / reception between predetermined application programs can be performed. Can be guaranteed. In other words, even when an application program malfunctions, packets can be prevented from being transmitted and received between erroneous application programs, so that the reliability of the information processing system SYS2 can be improved. The key information PK-SP, PK-HV, and PK-OS may be stored together with the key information KEY in the management information MSGQ-ID.

  Message size M-SIZE indicates the size (32 bytes or 64 bytes) of message data MSG-DT. When there is only one type of message data MSG-DT, the management information MSGQ-ID does not include the message size M-SIZE. Note that the packets shown in FIG. 6 are sent to the crossbar switch LXB in order from the destination CPU-ID.

  FIG. 7 shows an example of the state of the information processing system SYS2 shown in FIG. In the example illustrated in FIG. 7, the hypervisor HV is activated in the node ND0, and the hypervisor HV activates three virtual machines and causes the virtual machines to execute the OS (OS0, OS1, OS2). OS2 is executed by CPU0. Then, three processes PROC (PROC0, PROC1, PROC2; that is, an application program) operate on the OS2. A broken line frame illustrated in FIG. 7 indicates an operation state of the software. The OS is an example of a management program that manages the operation of the core 10, and the hypervisor HV is an example of a control program that controls a virtual machine.

  For example, before the process PROC2 starts transmitting data, the state management program executed by the service processor SP stores the key information PK-SP in the entry ENTS used in the process PROC2. Similarly, the hypervisor HV stores the key information PK-HV in the entry ENTS used in the process PROC2, and the OS2 stores the key information PK-OS in the entry ENTS used in the process PROC2. Then, the process PROC2 operating on the OS2 stores the key information KEY in the entry ENTS to be used.

  As described above, the management unit that stores the key information PK-SP, PK-HV, and PK-OS in the registers PK-SP, PK-HV, and PK-OS includes the state management program, the hypervisor HV, and the OS. Each is realized. That is, the state management program, the hypervisor HV, and the OS are examples of a management unit that manages the operation of the core 10 and generates the key information PK-SP, PK-HV, and PK-OS. As described with reference to FIG. 5, each entry ENTS may include at least one of registers PK-SP, PK-HV, and PK-OS.

  FIG. 8 shows an example of the access authority of the registers AKEY, PK-OS, PK-HV, and PK-SP provided in each entry ENTS of the register unit 20 shown in FIG. The register AKEY can be accessed by the processes PROC, OS, the hypervisor HV, and the service processor SP, and the register PK-OS can be accessed by the OS, the hypervisor HV, and the service processor SP. The register PK-HV can be accessed by the hypervisor HV and the service processor SP, and the register PK-SP can be accessed only by the service processor SP. That is, the registers PK-OS, PK-HV, and PK-SP are prohibited from being accessed by the process PROC.

  FIG. 9 shows an example of the register unit 60 shown in FIG. 4 and elements that operate when the packet control unit 30 receives a packet. The element shown in FIG. 9 functions as a receiving device that receives a packet. The packet reception control unit 50 of the packet control unit 30 illustrated in FIG. 4 includes a packet determination unit 56 and a write control unit 58 in addition to the packet reception unit 52 and the response storage unit 54 illustrated in FIG. The packet transmission control unit 40 illustrated in FIG. 4 includes a response packet generation unit 46 in addition to the packet generation unit 42 and the packet transmission unit 44 illustrated in FIG.

  Each entry ENTR of the register unit 60 has a plurality of registers for storing a base address BADRS, key information AKEY, PK-OS, PK-HV, PK-SP, a write pointer WP, and a read pointer RP, respectively. The register unit 60 is provided in an area (for example, an I / O space) different from the address space to which the storage device MEM is allocated. The entry ENTR is an example of a third holding unit.

  Each entry ENTS validates permission information OSEN indicating whether key information PK-OS is valid, permission information HVEN indicating whether key information PK-HV is valid, and key information PK-SP. Has an area for storing permission information SPEN indicating the above. For example, each of the permission information OSEN, HVEN, and SPEN is 1 bit, and indicates invalidity when the logic is 0 and indicates validity when the logic is 1. The permission information OSEN, HVEN, SPEN is an example of a validity flag that sets whether or not the comparison of the key information PK-OS, PK-HV, PK-SP by the packet determination unit 56 is validated. The packet determination unit 56 selects and uses the entry ENTR identified by the register set information REG-ID included in the received packet management information MSGQ-ID.

  The key information AKEY is determined in advance between application programs that transmit and receive packets, and before the application program starts transmitting the message data MSG-DT, the key information AKEY is notified from the receiving process to the transmitting process. . For example, the key information PK-OS is a unique value determined for each process by the OS on the transmission side of the message data MSG-DT. The key information PK-HV is a unique value determined for each process by the hypervisor HV on the transmission side of the message data MSG-DT. The key information PK-SP is a unique value determined for each process by the service processor SP on the transmission side of the message data MSG-DT.

  When all of the key information PK-SP, PK-HV, and PK-OS are validated by the permission information SPEN, HVEN, and OSEN, the key information PK-SP, PK-HV, and PK-OS are as follows: It may be set as shown. That is, the key information PK-SP is set to the number of the node ND where the process is executed, the key information PK-HV is set to the number of the OS where the process is executed, and the key information PK-OS is the process number. May be set.

  The write pointer WP indicates the head address (relative value) for storing the message data MSG-DT included in the received packet in the message queue MQUE assigned to the storage device MEM. The read pointer RP indicates the head address (relative value) of the storage area that holds the message data MSG-DT that has not been read out of the message data MSG-DT stored in the message queue MQUE.

  A plurality of message queues MQUE corresponding to the entries ENTR of the register unit 60 are allocated to the storage device MEM. The message queue MQUE is an example of a storage unit. Each message queue MQUE functions as a ring buffer, and valid message data MSG-DT is held in a storage area sandwiched between the write pointer WP and the read pointer RP.

  The base address BADRS indicates, for example, the head address (physical address) of the message queue MQUE assigned to the storage device MEM corresponding to each entry ENTR of the register unit 60. Then, by adding the value of the write pointer WP to the base address BADRS, the head address for storing the message data MSG-DT is calculated. Further, by adding the value of the read pointer RP to the base address BADRS, the head address for reading the message data MSG-DT is calculated.

  The base address BADRS may be indicated by a predetermined number of upper bits in the head address of each message queue MQUE. In this case, the head address for storing the message data MSG-DT is calculated by combining the bit value of the base address BADRS and the bit value of the write pointer WP. Further, the head address for reading the message data MSG-DT is calculated by combining the bit value of the base address BADRS and the bit value of the read pointer RP.

  When the packet reception unit 52 receives a packet, the packet determination unit 56 reads information stored in the entry ENTR indicated by the register set information REG-ID included in the packet, and determines whether the packet is valid. That is, the packet determination unit 56 compares the key information AKEY included in the packet with the key information AKEY read from the entry ENTR. When the permission information SPEN read from the entry ENTR indicates validity, the packet determination unit 56 compares the key information PK-SP included in the packet with the key information PK-SP read from the entry ENTR. When the permission information HVEN read from the entry ENTR indicates validity, the packet determination unit 56 compares the key information PK-HV included in the packet with the key information PK-HV read from the entry ENTR. When the permission information OSEN read from the entry ENTR indicates validity, the packet determining unit 56 compares the key information PK-OS included in the packet with the key information PK-OS read from the entry ENTR. The packet determination unit 56 determines that the received packet is valid (normal) when all of the comparison results indicate a match, and the received packet is invalid when at least one of the comparison results indicates a mismatch. Judge that there is.

  When the received packet is valid, the packet determination unit 56 reads the base address BADRS and the write pointer WP from the entry ENTR indicated by the register set information REG-ID included in the packet. Then, the packet determination unit 56 outputs the message data MSG-DT included in the packet, the base address BADRS and the write pointer WP read from the entry ENTR to the write control unit 58. Further, the packet determination unit 56 notifies the response packet generation unit 46 that the received packet is normal, and updates the write pointer WP based on the message size M-SIZE included in the packet.

  When the received packet is invalid, the packet determination unit 56 discards the message data MSG-DT included in the packet, and notifies the response packet generation unit 46 of information indicating that the received packet is invalid. . In this case, the write pointer WP is not updated.

  When the write control unit 58 receives the base address BADRS and the write pointer WP from the packet determination unit 56, the write control unit 58 calculates the address of the storage area of the message queue MQUE indicated by the base address BADRS and the write pointer WP. Then, the write control unit 58 writes the message data MSG-DT received from the packet determination unit 56 in the storage area indicated by the calculated address. The message data MSG-DT written in the message queue MQUE is read by an application program that processes the received message data MSG-DT.

  After writing the message data MSG-DT into the message queue MQUE, the write control unit 58 notifies the response packet generator 46 of information indicating the state of the message queue MQUE. For example, when the message queue MQUE has room to store the message data MSG-DT to be received next, the write control unit 58 sends information indicating that further reception of the message data MSG-DT is possible to the response packet generation unit 46. Notify When the message queue MQUE is full, the write control unit 58 notifies the response packet generation unit 46 of information indicating that the message queue MQUE is full. Further, when the message queue MQUE has stopped operating and the message data MSG-DT cannot be written to the message queue MQUE, the write control unit 58 notifies the response packet generation unit 46 of information indicating the non-operation of the message queue MQUE. To do.

  The response packet generator 46 generates a response packet based on the information received from the packet determination unit 56 and the information received from the write controller 58, and outputs the generated response packet to the packet transmitter 44. The response packet includes transmission destination CPU-ID, transmission source CPU-ID, entry ID, and state information ST indicating the state of the message queue MQUE. Response packets are sent to the crossbar switch LXB in order from the destination CPU-ID.

  The transmission destination CPU-ID is the transmission source CPU-ID included in the original packet corresponding to the response packet, and the transmission source CPU-ID is the transmission destination CPU-ID included in the original packet corresponding to the response packet. is there. The entry ID is an entry ID included in the original packet corresponding to the response packet.

  The status information ST is 2 bits, for example, and indicates one of “INVALID”, “INACTIVE”, “FULL”, and “COMPLETE” according to the bit value. “INVALID” indicates that a mismatch of the key information AKEY has occurred (error response). “INACTIVE” indicates that the message queue MQUE has stopped operating, and the message data MSG-DT cannot be written (error response). “FULL” indicates that the message queue MQUE is full (error response). “COMPLETE” indicates that the message data MSG-DT is normally stored in the message queue MQUE and the message data MSG-DT can be further received (normal response).

  The packet transmission unit 44 transmits the response packet received from the response packet generation unit 46 to the CPU that is the transmission source of the packet.

  FIG. 10 shows an example of the packet determination unit 56 shown in FIG. The packet determination unit 56 includes a selector SEL, a key information extraction unit KEYOUT, a key checker KEYCHK, OSCHK, HVCHK, SPCHK, and an AND circuit AND. The key checker KEYCHK is an example of a first comparison unit, and the key checkers OSCHK, HVCHK, and SPCHK are examples of a second comparison unit.

  The selector SEL selects the entry ENTR indicated by the register set information REG-ID included in the received packet, and outputs the information held in the selected entry ENTR. The key information extraction unit KEYOUT extracts key information AKEY, PK-OS, PK-HV, and PK-SP from the received packet.

  The key checker KEYCHK compares the key information AKEY read from the entry ENTR with the key information AKEY extracted from the packet by the key information extraction unit KEYOUT. The key checker AKEYCHK outputs a logic 1 indicating a match when the key information AKEY from the entry ENTR matches the key information AKEY from the key information extraction unit KEYOUT. If the key information AKEY from the entry ENTR does not match the key information AKEY from the key information extraction unit KEYOUT, the key checker KEYCHK outputs a logical 0 indicating a mismatch.

  In the key checker OSCHK, when the permission information OSEN read from the entry ENTR indicates a valid state (logic 1), the key information PK-OS read from the entry ENTR and the key information PK-OS extracted from the packet by the key information extraction unit KEYOUT And compare. When the key information PK-OS from the entry ENTR matches the key information PK-OS from the key information extraction unit KEYOUT, the key checker OSCHK outputs a logic 1 indicating a match. When the key information PK-OS from the entry ENTR and the key information PK-OS from the key information extraction unit KEYOUT do not match, the key checker OSCHK outputs a logical 0 indicating a mismatch. When the permission information OSEN from the entry ENTR indicates an invalid state (logic 0), the key checker OSCHK shows a comparison result between the key information PK-OS from the entry ENTR and the key information PK-OS from the key information extraction unit KEYOUT. Regardless, it outputs a logic 1 indicating a match.

  In the key checker HVCHK, when the permission information HVEN read from the entry ENTR indicates a valid state (logic 1), the key information PK-HV read from the packet by the key information extraction unit KEYOUT and the key information PK- read from the entry ENTR Compare with HV. When the key information PK-HV from the entry ENTR matches the key information PK-HV from the key information extraction unit KEYOUT, the key checker HVCHK outputs a logic 1 indicating the match. If the key information PK-HV from the entry ENTR does not match the key information PK-HV from the key information extraction unit KEYOUT, the key checker HVCHK outputs a logic 0 indicating a mismatch. When the permission information HVEN from the entry ENTR indicates an invalid state (logic 0), the key checker HVCHK shows the comparison result between the key information PK-HV from the entry ENTR and the key information PK-HV from the key information extraction unit KEYOUT. Regardless, it outputs a logic 1 indicating a match.

  In the key checker SPCHK, when the permission information SPEN read from the entry ENTR indicates a valid state (logic 1), the key information PK-SP extracted from the packet by the key information extraction unit KEYOUT and the key information PK- read from the entry ENTR Compare with SP. When the key information PK-SP from the entry ENTR matches the key information PK-SP from the key information extraction unit KEYOUT, the key checker SPCHK outputs a logic 1 indicating the match. If the key information PK-SP from the entry ENTR and the key information PK-SP from the key information extraction unit KEYOUT do not match, the key checker SPCHK outputs a logical 0 indicating a mismatch. When the permission information SPEN from the entry ENTR indicates an invalid state (logic 0), the key checker SPCHK indicates the comparison result between the key information PK-SP from the entry ENTR and the key information PK-SP from the key information extraction unit KEYOUT. Regardless, it outputs a logic 1 indicating a match.

  As described above, the packet determination unit 56 sets the comparison operation by each of the key checkers OSCHK, HVCHK, and SPCHK to be valid or invalid according to the logic of the permission information OSEN, HVEN, and SPEN. Thereby, the number of key information PK-OS, PK-HV, and PK-SP to be compared can be changed in accordance with the reliability required for the information processing system SYS2. For example, the logic “PK-OS, PK-HV, PK-SP” of the permission information PK-OS, PK-HV, PK-SP is “000” as the reliability required for the information processing system SYS2 increases. , “100”, “110”, and “111”.

  The key information PK-OS, PK-HV, and PK-SP used by the packet determination unit 56 for determination is determined according to the logic of the permission information OSEN, HVEN, and SPEN set by the packet receiving device. In other words, the key information used by the packet determination unit 56 for the determination without rewriting the key information PK-OS, PK-HV, and PK-SP held in the entry ENTS shown in FIG. PK-OS, PK-HV, and PK-SP can be changed.

  The AND circuit AND outputs a determination result RSLT (logic 1) indicating that the packet is valid when it receives logic 1 from all of the key checkers KEYCHK, OSCHK, HVCHK, and SPCHK. On the other hand, the AND circuit AND outputs a determination result RSLT (logic 0) indicating that the packet is invalid when it receives logic 0 from at least one of the key checkers KEYCHK, OSCHK, HVCHK, and SPCHK.

  FIG. 11 shows an example of the operation of the information processing system SYS2 shown in FIG. FIG. 11 shows an example in which message data MSG-DT is transferred from a packet transmitting device to a packet receiving device. In other words, any one of the cores 10 corresponding to the transmitting device executes the application program 1, and any one of the cores 10 corresponding to the receiving device executes the application program 2. Then, message data MSG-DT is transferred between the application program 1 and the application program 2.

  The transmitting device uses one of the entries ENTS, and the receiving device uses one of the entries ENTR indicated by the register set information REG-ID included in the packet transmitted from the transmitting device. For example, the entry ENTS is assigned to each core 10 corresponding to the transmission device. In other words, the registers MSG-DT, MSGQ-ID, SEND-MSG, PK-SP, PK-HV, PK-OS, and ST are provided for each core 10 that executes an application program in the transmission apparatus. The entry ENTR is allocated for each application program executed by the core 10 corresponding to the receiving device.

  The transmitting apparatus determines key information PK-SP, PK-HV, and PK-OS to be used before message data MSG-DT is transmitted / received to / from the receiving apparatus. That is, the state management program executed by the service processor SP shown in FIG. 7 determines the key information PK-SP used in the application program 1, and stores the determined key information PK-SP in the register PK-SP of the entry ENTS. . The hypervisor HV shown in FIG. 7 determines key information PK-HV used in the application program 1, and stores the determined key information PK-HV in the register PK-HV of the entry ENTS. The OS that manages the application program 1 determines the key information PK-OS used in the application program 1, and stores the determined key information PK-OS in the register PK-OS of the entry ENTS (FIG. 11A). Each of the key information PK-SP, PK-HV, and PK-OS is different for each application program executed by the core 10 corresponding to the transmission device.

  Then, the packet control unit 30 of the transmitting apparatus notifies the receiving apparatus of the key information PK-SP, PK-HV, and PK-OS stored in the entry ENTS used in the application program 1 (FIG. 11 (b)). For example, key information PK-SP, PK-HV, and PK-OS are notified to the receiving device for each application program. The packet control unit 30 of the receiving apparatus notified of the key information PK-SP, PK-HV, and PK-OS stores the key information PK-SP, PK-HV, and PK-OS in the entry ENTR used in the application program 2. (FIG. 11C).

  In the example illustrated in FIG. 11, the packet control unit 30 of the receiving apparatus stores permission information SPEN, HVEN, and OSEN indicating the valid state in the entry ENTR together with the key information PK-SP, PK-HV, and PK-OS. . Therefore, when receiving a packet from the transmitting device, the receiving device uses key information PK-SP, PK-HV, PK-OS corresponding to permission information SPEN, HVEN, OSEN indicating validity together with key information AKEY. The validity of the packet can be checked.

  The application program 2 reads the value of the write pointer WP and the value of the read pointer RP of the entry ENTR to be used at a predetermined frequency. If there is no difference between the value of the write pointer WP and the value of the read pointer RP, the application program 2 determines that the message data MSG-DT has not been received (FIG. 11 (d)).

  When transferring the message data MSG-DT1 to the application program 2, the application program 1 stores the management information MSGQ-ID together with the message data MSG-DT2 in the entry ENTS (FIG. 11 (e)). For example, the value CD1 set in the key information AKEY of the management information MSGQ-ID is notified in advance from the receiving apparatus to the transmitting apparatus. After storing the information in the entry ENTS, the application program 1 stores the transmission request SEND-MSG of logic 1 in the entry ENTS (FIG. 11 (f)).

  Based on the logic 1 of the transmission request SEND-MSG, the packet control unit 30 of the transmission device reads the message data MSG-DT1 and the management information MSGQ-ID stored in the entry ENTS from the entry ENTS based on the logic 1 of the transmission request SEND-MSG (FIG. 11). (G)). Further, the packet control unit 30 reads the key information PK-SP, PK-HV, and PK-OS stored in the entry ENTS. Then, the packet control unit 30 generates a packet including the message data MSG-DT1, the management information MSGQ-ID, and the key information PK-SP, PK-HV, and PK-OS read from the entry ENTS, and sends the packet to the receiving device. Transmit (FIG. 11 (h)).

  The packet control unit 30 of the receiving device receives the packet, and reads out the key information AKEY stored in the entry ENTR indicated by the register set information REG-ID of the management information MSGQ-ID included in the received packet. The packet control unit 30 compares the key information AKEY included in the received packet with the key information AKEY read from the entry ENTR.

  Further, the packet control unit 30 compares the key information PK-SP, PK-HV, and PK-OS included in the received packet with the key information PK-SP, PK-HV, and PK-OS read from the entry ENTR, respectively. . Here, the entry ENTR for reading the key information PK-SP, PK-HV, and PK-OS is the entry ENTR indicated by the register set information REG-ID included in the received packet.

  In the example shown in FIG. 11, since the key information AKEY matches, the key information PK-SP matches, the key information PK-HV matches, and the key information PK-OS matches, the packet control unit 30 receives It is determined that the packet is valid (FIG. 11 (i)). Then, the packet control unit 30 stores the message data MSG-DT1 included in the received packet in the storage area of the message queue MQUE indicated by the write pointer WP of the entry ENTR (FIG. 11 (j)). Here, the packet control unit 30 detects the size of the message data MSG-DT based on the message size M-SIZE included in the received packet.

  The packet control unit 30 of the receiving apparatus updates the write pointer WP according to the message size M-SIZE. Then, the packet control unit 30 generates a response packet including the status information ST indicating that the message data MSG-DT has been normally received, and transmits the generated response packet to the transmission device (FIG. 11 (k)). ).

  The packet control unit 30 of the transmitting apparatus receives the response packet, and stores the status information ST included in the response packet in the register ST of the entry ENTS used for generating the transmitted packet ((l) in FIG. 11). The packet control unit 30 notifies the application program 1 that the response packet has been received. The reception of the response packet may be notified to the application program 1 by setting a reception flag assigned to the I / O space or the like, or may be notified to the application program 1 by an interrupt.

  The application program 1 reads the status information ST stored in the entry ENTS based on the response packet reception notification, and detects that the message data MSG-DT1 has been normally transferred to the receiving device (FIG. 11 (m )). Then, the application program 1 releases the entry ENTS from which the state information ST has been read.

  On the other hand, the application program 2 executed by the core 10 corresponding to the receiving device reads the value of the write pointer WP and the value of the read pointer RP of the entry ENTR. Since there is a difference between the value of the write pointer WP and the value of the read pointer RP, the application program 2 determines that new message data MSG-DT has been received (FIG. 11 (n)).

  The application program 2 issues a read access request to the storage device MEM, and reads the received message data MSG-DT1 from the message queue MQUE (FIG. 11 (o)). After reading the message data MSG-DT, the application program 2 updates the read pointer RP of the entry ENTR according to the size of the read message data MSG-DT1. Note that the update of the read pointer RP may be executed by the packet control unit 30 of the receiving device based on a read completion notification from the application program 2. The application program 2 executes data processing and the like using the message data MSG-DT1 read from the message queue MQUE.

  FIG. 12 shows another example of the operation of the information processing system SYS2 shown in FIG. Detailed description of the same or similar operations as in FIG. 11 is omitted. Operation until the application program 1 reads the status information ST stored in the entry ENTS and detects that the message data MSG-DT has been normally transferred to the receiving device (FIG. 12 (a) to FIG. 12 (m)). Is the same as or similar to FIG.

  That is, the packet control unit 30 of the receiving apparatus stores the permission information SPEN, HVEN, and OSEN indicating the valid state in the entry ENTS together with the key information PK-SP, PK-HV, and PK-OS. Therefore, when receiving a packet from the transmitting apparatus, the receiving apparatus checks the validity of the packet by using the key information PK-SP, PK-HV, and PK-OS together with the key information AKEY.

  In the example shown in FIG. 12, first, the application program 1 executed by the core 10 corresponding to the transmission device transmits the message data MSG-DT1 to the application program 2 executed by the core 10 corresponding to the reception device. Next, the application program 3 executed by the core 10 corresponding to the transmission device transmits the message data MSG-DT2 using the wrong management information MSGQ-ID. For example, the application program 3 transmits the message data MSG-DT2 to the receiving device using the management information MSGQ-ID used by the application program 1.

  The application program 3 executes processing for transferring the message data MSG-DT2 to the receiving device. However, the application program 3 stores the wrong management information MSGQ-ID together with the message data MSG-DT2 in the entry ENTS (FIG. 12 (p)). For example, the register set information REG-ID of the management information MSGQ-ID indicates the entry ENTR used in the application program 2, and the key information KEY of the management information MSGQ-ID is the value CD1 determined between the application programs 1 and 2. The same. For example, incorrect management information MSGQ-ID is stored in the entry ENTS due to a bug in the application program 3.

  After storing the information in the entry ENTS, the application program 3 stores the transmission request SEND-MSG of logic 1 in the entry ENTS (FIG. 12 (q)). Based on the logic 1 of the transmission request SEND-MSG, the packet control unit 30 of the transmission device reads the message data MSG-DT2 and the management information MSGQ-ID stored in the entry ENTS from the entry ENTS based on the logic 1 of the transmission request SEND-MSG (FIG. 12 (R)). Further, the packet control unit 30 reads the key information PK-SP, PK-HV, and PK-OS stored in the entry ENTS. The key information PK-SP, PK-HV, and PK-OS stored in the entry ENTS are different from the key information PK-SP, PK-HV, and PK-OS stored in the entry ENTS used by the application program 2, respectively. .

  Then, the packet control unit 30 generates a packet including the message data MSG-DT1, the management information MSGQ-ID, and the key information PK-SP, PK-HV, and PK-OS read from the entry ENTS, and sends the packet to the receiving device. Transmit (FIG. 12 (s)).

  The packet control unit 30 of the receiving device receives the packet, and reads the key information AKEY stored in the entry ENTR indicated by the incorrect register set information REG-ID included in the received packet. The packet control unit 30 compares the key information AKEY included in the received packet with the key information AKEY read from the entry ENTR, and detects a match.

  Further, the packet control unit 30 compares the key information PK-SP, PK-HV, and PK-OS included in the received packet with the key information PK-SP, PK-HV, and PK-OS read from the entry ENTR. Here, the entry ENTR for reading the key information PK-SP, PK-HV, and PK-OS is an entry ENTR used in the application program 2 indicated by the register set information REG-ID included in the received packet. For this reason, the key information PK-SP, PK-HV, and PK-OS read from the entry ENTR do not correspond to the application program 3, and are incorrect key information PK-SP, PK-HV, and PK-OS. .

  In the example illustrated in FIG. 12, the key information AKEY matches, but the key information PK-SP, PK-HV, and PK-OS do not match, so the packet control unit 30 invalidates the received packet. (FIG. 12 (t)). Therefore, the packet control unit 30 discards the message data MSG-DT2 included in the received packet without storing it in the message queue MQUE. Then, the packet control unit 30 generates a response packet (error response) including the state information ST indicating that the message data MSG-DT has not been normally received, and transmits the generated response packet to the transmission device. (FIG. 12 (u)).

  The packet control unit 30 of the transmitting device receives the response packet, and stores the status information ST included in the response packet in the register ST of the entry ENTS used for generating the transmitted packet (FIG. 12 (v)). The packet control unit 30 notifies the application program 3 that the response packet has been received.

  The application program 3 reads the status information ST stored in the entry ENTS based on the notification of reception of the response packet, and detects that the message data MSG-DT has not been normally transferred to the receiving device (FIG. 12 ( w)). Then, the application program 3 releases the entry ENTS from which the status information ST has been read, and executes error processing and the like.

  On the other hand, the application program 2 executed by the core 10 corresponding to the receiving device reads the value of the write pointer WP and the value of the read pointer RP of the entry ENTR, as in FIG. Since there is a difference between the value of the write pointer WP and the value of the read pointer RP, the application program 2 determines that new message data MSG-DT has been received (FIG. 12 (n)).

  The application program 2 issues a read access request to the storage device MEM, and reads the received message data MSG-DT1 from the message queue MQUE (FIG. 12 (o)). After reading the message data MSG-DT, the application program 2 updates the read pointer RP of the entry ENTR according to the size of the read message data MSG-DT1. Then, the application program 2 executes data processing and the like using the message data MSG-DT1 read from the message queue MQUE.

  FIG. 13 shows an example of the operation of another information processing system. The configuration of the information processing system that realizes the operation shown in FIG. 13 is the same as that of the information processing system SYS2 shown in FIG. 3, and the configuration of the CPU mounted in the information processing system is the same as the CPU shown in FIG. However, the entry ENTS of the register unit 20 does not have the registers PK-SP, PK-HV, and PK-OS shown in FIG. That is, the packet control unit 30 of the receiving apparatus determines whether the packet is valid based only on the key information AKEY included in the received packet. The operation until the application program 1 reads the status information ST stored in the entry ENTS is that the packet transferred from the transmitting device to the receiving device does not include the key information PK-SP, PK-HV, and PK-OS. This is the same as FIG.

  Also in FIG. 13, as in FIG. 12, first, the application program 1 executed by the core 10 corresponding to the transmission device transmits the message data MSG-DT1. Next, the application program 3 executed by the core 10 corresponding to the transmission device transmits the message data MSG-DT2 using the wrong management information MSGQ-ID.

  For example, the application program 3 uses the management information MSGQ-ID used by the application program 1 to transfer the message data MSG-DT2 to the receiving device. The register set information REG-ID of the management information MSGQ-ID indicates the entry ENTR used in the application program 1, and the key information KEY of the management information MSGQ-ID is the same as the value CD1 used in the application program 1. Based on the logic 1 of the transmission request SEND-MSG, the packet control unit 30 of the transmission device transmits a packet including the message data MSG-DT2 and the management information MSGQ-ID to the reception device (FIG. 13A). ).

  The packet control unit 30 of the receiving device receives the packet, and reads the key information AKEY stored in the entry ENTR indicated by the incorrect register set information REG-ID included in the received packet. The packet control unit 30 compares the key information AKEY included in the received packet with the key information AKEY read from the entry ENTR, and determines that the received packet is valid because the key information AKEY matches (FIG. 13 ( b)).

  Then, the packet control unit 30 stores the message data MSG-DT2 included in the received packet in the storage area of the message queue MQUE indicated by the write pointer WP of the entry ENTR used in the application program 2 (FIG. 13 (c)). ). The packet control unit 30 of the receiving apparatus updates the write pointer WP according to the message size M-SIZE. Then, the packet control unit 30 generates a response packet including the status information ST indicating that the message data MSG-DT has been normally received, and transmits the generated response packet to the transmission device (FIG. 13D). ).

  The packet control unit 30 of the transmission apparatus receives the response packet, and stores the status information ST included in the response packet in the register ST of the entry ENTS used in the application program 3 (FIG. 13 (e)). The packet control unit 30 notifies the application program 3 that the response packet has been received. Based on the notification of reception of the response packet, the application program 3 reads the status information ST stored in the entry ENTS and detects that the message data MSG-DT2 has been normally transferred to the receiving device (FIG. 13 (f )).

  On the other hand, the application program 2 executed by the core 10 corresponding to the receiving device reads the value of the write pointer WP and the value of the read pointer RP of the entry ENTR. Since there is a difference between the value of the write pointer WP and the value of the read pointer RP, the application program 2 determines that new message data MSG-DT has been received (FIG. 13 (g)).

  The application program 2 issues a read access request to the storage device MEM, and reads the received message data MSG-DT1 and MSG-DT2 from the message queue MQUE (FIG. 13 (h)). However, the message data MSG-DT2 is not data processed by the application program 2.

  The application program 2 reads the message data MSG-DT1, MSG-DT2, and then updates the read pointer RP of the entry ENTR according to the size of the read message data MSG-DT1, MSG-DT2. Thereafter, the application program 2 executes data processing and the like using the message data MSG-DT1 and MSG-DT2 read from the message queue MQUE. However, since the message data MSG-DT2 is not data to be processed by the application program 2, the application program 2 executes erroneous data processing. As a result, the application program 2 may malfunction.

  FIG. 14 shows an example of a process of transmitting a packet executed by the packet control unit 30 shown in FIG. The process shown in FIG. 14 is repeatedly executed at a predetermined frequency.

  First, in step S10, the packet generation unit 42 shown in FIG. 5 determines whether any of the registers SEND-MSG of the entry ENTS of the register unit 20 is set to logic 1. If the register SEND-MSG is set to logic 1, the process proceeds to step S12. If the register SEND-MSG is not set to logic 1, the process proceeds to step S16.

  In step S12, the packet generator 42 generates a packet using the message data MSG-DT stored in the entry ENTS in which the register SEND-MSG is set to logic 1, and the process proceeds to step S14. In step S14, the packet transmission unit 44 illustrated in FIG. 5 transmits the packet generated by the packet generation unit 42 to the reception device.

  Next, in step S16, the packet receiver 52 shown in FIG. 5 determines whether a response packet has been received. If a response packet is received, the process proceeds to step S18. If no response packet is received, the process ends. In step S18, the response storage unit 54 shown in FIG. 5 stores the status information ST included in the response packet in the register ST of the entry ENTS, and ends the process.

  FIG. 15 shows an example of a process of receiving a packet executed by the packet control unit 30 shown in FIG. The process shown in FIG. 15 is repeatedly executed at a predetermined frequency.

  First, in step S20, the packet receiver 52 shown in FIG. 9 determines whether or not a packet has been received. If a packet is received, the process proceeds to step S22. If no packet is received, the process ends.

  In step S22, the packet determination unit 56 shown in FIG. 9 matches the key information AKEY included in the received packet with the key information AKEY stored in the entry ENTR indicated by the register set information REG-ID included in the packet. It is determined whether or not. If the key information AKEY matches, the process proceeds to step S24. If the key information AKEY does not match, the process proceeds to step S44 shown in FIG.

  In step S24, the packet determination unit 56 determines whether or not the permission information SPEN stored in the entry ENTR indicated by the register set information REG-ID included in the packet is valid. If the permission information SPEN is valid (logic 1), the process proceeds to step S26, and if the permission information SPEN is invalid (logic 0), the process proceeds to step S28.

  In step S26, the packet determination unit 56 matches the key information PK-SP included in the received packet with the key information PK-SP stored in the entry ENTR indicated by the register set information REG-ID included in the packet. It is determined whether or not. If the key information PK-SP matches, the process proceeds to step S28. If the key information PK-SP does not match, the process proceeds to step S44 shown in FIG.

  In step S28, the packet determination unit 56 determines whether or not the permission information HVEN stored in the entry ENTR indicated by the register set information REG-ID included in the packet is valid. If the permission information HVEN is valid (logic 1), the process proceeds to step S30. If the permission information HVEN is invalid (logic 0), the process proceeds to step S32 shown in FIG.

  In step S30, the packet determination unit 56 matches the key information PK-HV included in the received packet with the key information PK-HV stored in the entry ENTR indicated by the register set information REG-ID included in the packet. It is determined whether or not. If the key information PK-HV matches, the process proceeds to step S32 shown in FIG. 16, and if the key information PK-HV does not match, the process moves to step S44 shown in FIG.

  In step S32 shown in FIG. 16, the packet determination unit 56 determines whether or not the permission information OSEN stored in the entry ENTR indicated by the register set information REG-ID included in the packet is valid. If the permission information OSEN is valid (logic 1), the process proceeds to step S34. If the permission information OSEN is invalid (logic 0), the process proceeds to step S36.

  In step S34, the packet determination unit 56 matches the key information PK-OS included in the received packet with the key information PK-OS stored in the entry ENTR indicated by the register set information REG-ID included in the packet. It is determined whether or not. If the key information PK-OS matches, the process proceeds to step S36. If the key information PK-OS does not match, the process proceeds to step S44.

  In step S36, the packet determination unit 56 determines whether or not the message queue MQUE is normal. For example, when the message queue MQUE has stopped operating, or when the message queue MQUE is full, it is determined that the message queue MQUE is not normal. If the message queue MQUE is normal, the process proceeds to step S38. If the message queue MQUE is not normal, the process proceeds to step S44.

  In step S38, the write control unit 58 shown in FIG. 9 stores the received message data MSG-DT in the message queue MQUE. Next, in step S40, the packet determination unit 56 updates the write pointer WP, and the process proceeds to step S42.

  In step S42, the response packet generator 46 shown in FIG. 9 generates a normal response packet indicating that the received packet has been processed normally, and the process proceeds to step S46. The status information ST included in the normal response packet indicates “COMPLETE” shown in FIG.

  In step S44, the response packet generator 46 generates an error response packet indicating that the message data MSG-DT has not been received normally, and the process proceeds to step S46. The status information ST included in the error response packet indicates one of “INVALID”, “INACTIVE”, and “FULL” shown in FIG.

  Next, in step S46, the packet transmission unit 44 illustrated in FIG. 9 transmits the response packet generated by the response packet generation unit 46 to the packet transmission device, and ends the process.

  FIG. 17 shows an example of processing when a packet is transmitted by an application program executed by the core 10 shown in FIG. For example, the application program is the application program 1 shown in FIGS. The process shown in FIG. 17 is repeatedly executed at a predetermined frequency.

  First, in step S50, when transmitting the message data MSG-DT, the application program stores the message data MSG-DT in one of the entries ENTS of the register unit 20. Next, in step S52, the application program stores the management information MSGQ-ID in the entry ENTS. Next, in step S54, the application program stores the transmission request SEND-MSG of logic 1 in the entry ENTS, causes the packet control unit 30 to transmit the packet, and shifts the processing to step S56.

  In step S56, the application program determines whether or not the state information ST is stored in the entry ENTS. That is, the application program determines whether or not a response packet corresponding to the transmitted packet has been received. If the state information ST is stored in the entry ENTS, the process proceeds to step S58. If the state information ST is not stored in the entry ENTS, the process ends. In step S58, the application program reads the status information ST stored in the entry ENTS, confirms whether the message data MSG-DT has been normally transferred, and ends the process.

  FIG. 18 shows an example of processing when a packet is received by an application program executed by the core 10 shown in FIG. For example, the application program is the application program 2 shown in FIGS. The process shown in FIG. 18 is repeatedly executed at a predetermined frequency.

  First, in step S60, the application program reads the value of the write pointer WP and the value of the read pointer RP from the entry ENTR of the register unit 60 corresponding to the message queue MQUE to be used. An entry ENTR for reading the value of the write pointer WP and the value of the read pointer RP is indicated by register set information REG-ID included in the received packet.

  Next, in step S62, the application program determines whether message data MSG-DT is stored in the message queue MQUE based on the difference between the value of the write pointer WP and the value of the read pointer RP. If it is determined that message data MSG-DT is stored in message queue MQUE, the process proceeds to step S64. If it is determined that message data MSG-DT is not stored in message queue MQUE, the process ends. .

  In step S64, the application program reads message data MSG-DT from the message queue MQUE. Next, in step S66, the application program updates the read pointer RP and ends the process.

  As described above, also in the embodiment shown in FIGS. 3 to 18, the same effect as that of the embodiment shown in FIG. 1 can be obtained. That is, key information PK-SP, PK-HV, and PK-OS are stored in registers PK-SP, PK-HV, and PK-OS that are not permitted to be accessed by application programs. As a result, it is possible to prevent erroneous key information PK-SP, PK-HV, and PK-OS from being stored in the register due to an application program malfunction or the like. Further, it is determined whether or not the received packet is normal by using the key information held in the register MSGQ-ID (AKEY) having different access authority and the registers PK-SP, PK-HV, and PK-OS. Thus, the reliability of determination can be improved.

  Therefore, it is possible to prevent an erroneous packet transmitted by the transmission device from being processed by an application program executed by the core 10 corresponding to the reception device. As a result, the application program executed by the core 10 corresponding to the receiving device can be prevented from executing data processing using data included in the wrong packet, and the reliability of the information processing system SYS2 is improved. can do.

  Storage of key information PK-SP, PK-HV, and PK-OS in registers PK-SP, PK-HV, and PK-OS by a program such as an OS higher than the application program is executed in advance before transfer of transmission data. The For this reason, a context switch or the like does not occur when transmission data is transferred to the receiving device, and the execution efficiency of the application program can be prevented from being lowered by the context switch or the like.

  Further, in the embodiment shown in FIGS. 3 to 18, the key information PK-OS, PK-HV, and PK-SP used by the packet determination unit 56 for the determination are the permission information OSEN, HVEN, It is determined according to the logic of SPEN. Therefore, the key information PK-OS, PK- used by the packet determination unit 56 without rewriting the key information PK-OS, PK-HV, PK-SP held in the entry ENTS of the packet transmitting apparatus. HV and PK-SP can be changed. As a result, the key information PK-OS, PK-HV, and PK-SP used by the packet determination unit 56 for determination can be changed without causing a context switch or the like in the packet transmission apparatus. That is, the key information PK-OS, PK-HV, and PK-SP that the packet determination unit 56 uses for determination can be changed without lowering the process execution efficiency.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... CPU core; 20 ... Register part; 30 ... Packet control part; 40 ... Packet transmission control part; 42 ... Packet generation part; 44 ... Packet transmission part; 46 ... Response packet generation part; ... Packet receiver; 54 ... Response storage; 56 ... Packet determination; 58 ... Write controller; 60 ... Register controller; 70 ... Memory controller; 80 ... Cache memory; 120: management unit; 130, 140 ... holding unit; 150 ... packet generating unit; 160 ... packet transmitting unit; 200 ... receiving device; 210 ... packet receiving unit; 220 ... holding unit; 230, 240 ... comparing unit; Control part; 260 ... Storage part; KEY ... Key information; KEYCHK ... Key checker; APRG ... Application program; BAD S ... Base address; CPU-ID ... CPU information; DATA ... Data; ENTR, ENTS ... Entry; GXB ... Crossbar switch; HV ... Hypervisor; HVCHK ... Key checker; HVEN ... Permission information; KEY1, KEY2 ... Key information; KEYOUT: Key information extraction unit; LXB: Crossbar switch; MBUS ... Memory bus; MEM ... Storage device; MQUE ... Message queue; MSG-DT ... Message data; MSGQ-ID ... Management information; M-SIZE ... Message size; ... Node; NWIF ... Network interface; OSCHK ... Key checker; OSEN ... Authorization information; PK-HV, PK-OS, PK-SP ... Key information; REG-ID ... Register set information; RP ... Read pointer; SEND-MSG Transmission request; SP ... service processor; SPCHK ... key checker; SPEN ... permission information; ST ... status information; SW ... switch; SYS1, SYS2 ... information processing system; WP ... write pointer

Claims (8)

In an information processing system having a transmission device that transmits data and a reception device that receives data from the transmission device,
The transmitter is
A data processing unit that executes software for generating data;
A first holding unit for holding first key information and data generated by the software;
A management unit for managing the operation of the data processing unit and generating second key information;
A second holding unit that holds the second key information generated by the management unit and is prohibited from being written by the software;
A packet generation unit that generates a packet including data and first key information held by the first holding unit, and second key information held by the second holding unit;
A packet transmitter for transmitting the packet generated by the packet generator;
The receiving device is:
A packet receiver for receiving a packet from the transmitter;
A third holding unit for holding the first key information and the second key information;
A first comparison unit that compares the first key information included in the packet received by the packet reception unit with the first key information held in the third holding unit;
A second comparing unit that compares the second key information included in the packet received by the packet receiving unit with the second key information held in the third holding unit;
Write control for writing data included in the packet received by the packet receiving unit to the storage unit when the comparison result by the first comparing unit shows a match and the comparison result by the second comparing unit shows a match An information processing system having a section.   The information processing system according to claim 1, wherein the management unit is realized by a management program that manages an operation of the data processing unit.   The information processing system according to claim 1, wherein the management unit is realized by a control program that controls a virtual machine that executes a management program that manages an operation of the data processing unit.   The information processing system according to any one of claims 1 to 3, wherein the management unit is realized by a state management program executed by a management device that manages a state of the data processing unit. The third holding unit has an effective flag for setting whether to enable the comparison of the second key information by the second comparing unit,
When the valid flag held in the third holding unit indicates invalidity, the second comparison unit outputs information indicating the comparison result to the write control unit regardless of the comparison result. The information processing system according to any one of claims 1 to 4. When the transmission device has a plurality of the data processing units that execute a plurality of the software,
The first holding unit and the second holding unit are provided for each of the plurality of data processing units,
The information processing system according to any one of claims 1 to 5, wherein the third holding unit is provided for each of the plurality of pieces of software. In a transmission device that is mounted in an information processing system together with a reception device and transmits data to the reception device,
A data processing unit that executes software for generating data;
A first holding unit for holding first key information and data generated by the software;
A management unit for managing the operation of the data processing unit and generating second key information;
A second holding unit that holds the second key information generated by the management unit and is prohibited from being written by the software;
A packet generation unit that generates a packet including data and first key information held by the first holding unit, and second key information held by the second holding unit;
A transmission apparatus comprising: a packet transmission unit that transmits a packet generated by the packet generation unit. In a control method of an information processing system having a transmission device that transmits data and a reception device that receives data from the transmission device,
A data processing unit included in the transmission device generates data, and executes software that stores the generated data in a first holding unit that holds first key information;
The management unit included in the transmission device manages the operation of the data processing unit and generates second key information, and the generated second key information is stored in the second holding unit that is prohibited from writing by the software. Store and
A packet generation unit included in the transmission device generates a packet including data and first key information held by the first holding unit, and second key information held by the second holding unit;
The packet transmission unit of the transmission device transmits the packet generated by the packet generation unit,
A packet receiving unit included in the receiving device receives a packet from the transmitting device;
A first comparison unit included in the reception device compares the first key information included in the packet received by the packet reception unit and the first key information held in the third holding unit;
A second comparison unit included in the reception device compares the second key information included in the packet received by the packet reception unit and the second key information held in the third holding unit;
When the write control unit included in the receiving device indicates that the comparison result by the first comparison unit indicates a match and the comparison result by the second comparison unit indicates a match, the packet reception unit A control method for an information processing system, wherein the data included is written in a storage unit.

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