JP2017184302A - Power supply circuit and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress power consumption when a DC/DC converter is in a low load state.SOLUTION: A DC/DC converter 11 converts first DC voltage to second DC voltage smaller than or larger than the first DC voltage. A capacitor C1 holds output voltage Vout based on the second DC voltage. A switch 12 is connected between an output terminal of the DC/DC converter 11 and one end of the capacitor C1. A comparison circuit 13 compares the output voltage Vout with a first value (voltage Vref), and outputs comparison results cmp. A control circuit 14 stops operation of the DC/DC converter 11 and turns off the switch 12 when it receives a state signal st indicating an operating state of a load circuit 21 in which the output voltage Vout operates as power supply voltage and the comparison results cmp, the operating state is a second state in which the load is lower than the first state, and the comparison results cmp indicate that the output voltage Vout is larger than the first value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply circuit and an electronic device.

  A sensing terminal that combines a wireless module and a sensor has attracted attention as a technology for realizing IoT (Internet of Things). In order to eliminate the need for battery replacement in sensing terminals, it has been proposed to use energy harvesting that converts energy present in the environment around us into electric power.

  A power storage element such as a secondary battery is charged by a current generated by energy harvesting. And the charging voltage of an electrical storage element is converted into the voltage suitable for load circuits, such as a sensing terminal, with the power supply circuit containing DC (Direct Current) / DC circuit. The amount of power generated by energy harvesting fluctuates from moment to moment, and fluctuations in charging voltage are also large.

JP 2008-61433 A JP2015-89260A JP-A-10-243642

In order to cope with such fluctuations in the charging voltage, it is conceivable to use a step-up / step-down DC / DC converter that can operate in a relatively wide input voltage range.
However, the step-up / step-down DC / DC converter has a problem in that it consumes a large amount of electric power when the load is low, as compared with a step-down or step-up DC / DC converter. For example, when a load circuit having a long standby time such as a sensing terminal that operates with power generated by energy harvesting is used, the time during which the load is low is increased, and the power consumption is further increased.

  An object of the present invention is to suppress power consumption at a low load in a power supply circuit using a step-up / step-down DC / DC converter.

  In one aspect, the power supply circuit converts the first DC voltage into a second DC voltage that is smaller than the first DC voltage or larger than the first DC voltage. A capacitor that holds an output voltage based on the second DC voltage, a first switch connected between an output terminal of the first DC / DC converter, and one end of the capacitor, and the output A first comparison circuit that compares a voltage with a first value and outputs a first comparison result; a status signal that indicates an operating state of a load circuit that operates using the output voltage as a power supply voltage; and In response to the comparison result, the operating state is a second state in which the load is lower than that in the first state, and the first comparison result indicates that the output voltage is greater than the first value. The first DC / DC converter It stops operating, and a control circuit for turning off said first switch.

  In one aspect, the electronic device controls a load circuit, a control unit that controls the load circuit and outputs a state signal indicating an operation state of the load circuit, a first DC voltage, and the first DC voltage. A first DC / DC converter that converts a second DC voltage that is smaller than the first DC voltage or greater than the first DC voltage; and an output voltage that is connected to the load circuit and that is based on the second DC voltage. A first switch connected between a capacitor to be held, an output terminal of the first DC / DC converter, and one end of the capacitor, and the output voltage and the first value are compared; The first comparison circuit that outputs the comparison result of the first, the state signal, and the first comparison result, the operation state is a second state that is a lower load than the first state, The first comparison result shows that the output voltage is the first When the indicating greater than a value, having a power supply circuit and a control circuit which stops the operation of the first DC / DC converter, turning off the first switch.

  According to the disclosed power supply circuit and electronic device, power consumption at low load can be suppressed.

It is a figure which shows an example of the power supply circuit of 1st Embodiment. It is a timing chart which shows an example of operation of a power circuit. It is a figure which shows an example of an electronic device. It is a figure which shows an example of the time change of a battery voltage. It is a figure which shows an example of the time change of the consumption current of a load circuit. It is a figure which shows the comparative example with the power supply circuit of 1st Embodiment, a pressure | voltage fall type DC / DC converter, and a buck-boost type DC / DC converter. It is a figure which shows an example of the power supply circuit of 2nd Embodiment. It is a figure explaining operation | movement of a power supply circuit when a battery voltage is larger than voltage Vrefa. It is a figure explaining operation | movement of the power supply circuit at the time of a high load when battery voltage is smaller than voltage Vrefa. It is a figure explaining operation | movement of a power supply circuit when a battery voltage is smaller than the voltage Vref, the time of low load, and the output voltage Vout is larger than the voltage Vref. It is a figure which shows the comparative example with the power supply circuit of 2nd Embodiment, a pressure | voltage fall type DC / DC converter, and a buck-boost type DC / DC converter. It is a figure which shows an example of the power supply circuit of 3rd Embodiment. It is a figure explaining operation | movement of a power supply circuit when using the electrical storage element with a battery voltage larger than output voltage Vout + (alpha). It is a figure explaining operation | movement of the power supply circuit at the time of high load using the electrical storage element in which battery voltage is smaller than output voltage Vout + (alpha). It is a figure explaining the operation | movement of a power supply circuit when the battery voltage uses the electrical storage element smaller than output voltage Vout + (alpha), and the output voltage Vout is larger than the voltage Vref at the time of low load. It is a figure which shows an example of the relationship between the battery to be used, the power supply efficiency at the time of high load, and the consumption current at the time of low load.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a power supply circuit according to the first embodiment.

The power supply circuit 10 includes a step-up / step-down DC / DC converter 11, a capacitor C 1, a switch 12, a comparison circuit 13, and a control circuit 14.
The DC / DC converter 11 converts the direct current voltage held in the storage element 20 into a direct current voltage that is smaller or larger than the direct current voltage. That is, the DC / DC converter 11 boosts or steps down the input voltage so that the voltage is suitable for the load circuit 21.

  The DC / DC converter 11 is, for example, an LSI (Large Scale Integrated circuit) having an enable terminal in addition to an input / output terminal. Based on the logic level of the enable signal en input to the enable terminal, the DC / DC converter 11 enters an active state (operation state) or a standby state (operation stop state). In the standby state, the DC / DC converter 11 outputs 0 V, for example, regardless of the magnitude of the input voltage.

  Capacitor C <b> 1 holds output voltage Vout of power supply circuit 10 based on the DC voltage output from DC / DC converter 11. Capacitor C1 is charged by the output current of DC / DC converter 11 when switch 12 is on. One end of the capacitor C1 is connected to the switch 12, the comparison circuit 13, and the load circuit 21. The other end of the capacitor C1 is grounded.

  The switch 12 is connected between the output terminal of the DC / DC converter 11 and one end of the capacitor C1. The switch 12 is turned on or off based on a control signal cnt output from the control circuit 14.

  For example, as shown in FIG. 1, the switch 12 is realized by using a p-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) (hereinafter abbreviated as pMOS) 12a. One of the source and the drain of the pMOS 12a is connected to the output terminal of the DC / DC converter 11, and the other is connected to one end of the capacitor C1. A control signal cnt is supplied to the gate of the pMOS 12a.

  The comparison circuit 13 compares the output voltage Vout and the voltage Vref, and outputs a comparison result cmp. The voltage Vref is, for example, a lower limit value of the operating voltage range of the load circuit 21. The lower limit is, for example, the lower limit of the voltage required to hold information in the memory in the load circuit 21. For example, when the output voltage Vout is smaller than Vref, the comparison circuit 13 outputs a comparison result cmp whose logic level is H (High) level, and when the output voltage Vout is larger than Vref, the logic level is L (Low). The level comparison result cmp is output.

  Note that the voltage Vref may be, for example, a voltage obtained by dividing a voltage supplied from a battery (not shown), or may be a voltage obtained by dividing the DC voltage held in the power storage element 20 by resistance. .

  The control circuit 14 receives the state signal st indicating the operation state of the load circuit 21 from the control unit 22 and receives the comparison result cmp output from the comparison circuit 13. The control circuit 14 is in the second state where the operation state is a lower load than the first state, and when the comparison result cmp indicates that the output voltage Vout is greater than the voltage Vref, the DC / DC converter 11 is stopped, and the switch 12 is turned off. The control circuit 14 operates the DC / DC converter 11 and turns on the switch 12 when the operation state is the second state and the comparison result cmp indicates that the output voltage Vout is smaller than the voltage Vref. . Even when the operating state is the first state, the control circuit 14 operates the DC / DC converter 11 and turns on the switch 12.

  Note that the first state is, for example, a state in which the load circuit 21 is active (for example, a state in which a sensor operation is performed). The second state is, for example, a state where the load circuit 21 is in a standby state (for example, a state where no sensor operation is performed). In the second state, the output current of the power supply circuit 10 is smaller than that in the first state.

Hereinafter, the time when the load circuit 21 is in the first state is referred to as a high load, and the time when the load circuit 21 is in the second state is referred to as a low load.
For example, the state signal st has a logic level of H level when the load is high, and a logic level of L when the load is low.

The control circuit 14 includes, for example, an enable control circuit 14a and a switch control circuit 14b as shown in FIG.
The enable control circuit 14a is an enable that controls whether the DC / DC converter 11 is in an active state or a standby state based on the state signal st indicating the operation state of the load circuit 21 and the comparison result cmp in the comparison circuit 13. A signal en is generated and output.

  The switch control circuit 14b generates and outputs a control signal cnt for controlling the switch 12 based on the enable signal en. When the switch control circuit 14b receives the enable signal en that activates the DC / DC converter 11, the switch control circuit 14b outputs a control signal cnt for turning on the switch 12 after a predetermined delay time.

Thereby, it can suppress that output noise (overshoot etc.) at the time of the operation | movement start of the DC / DC converter 11 is propagated to the load circuit 21 side.
The enable control circuit 14a and the switch control circuit 14b can be realized by a circuit as shown in FIG. 1, for example.

  In the following description, it is assumed that when Vout <Vref, the logical level of the comparison result cmp is H level, and when Vout> Vref, the logical level of the comparison result cmp is L level. Further, it is assumed that the logic level of the state signal st is H level when the load is high, and the logic level of the state signal st is L level when the load is low. When the logic level of the enable signal en is H level, the DC / DC converter 11 is in an active state, and when it is L level, the DC / DC converter 11 is in a standby state. Further, the switch 12 is turned off when the logic level of the control signal cnt is H level, and the switch 12 is turned on when the control signal cnt is L level.

  The enable control circuit 14a includes an OR circuit 14a1 that outputs an OR logic of the state signal st and the comparison result cmp as an enable signal en. The OR circuit 14a1 outputs an enable signal en of H level and operates the DC / DC converter 11 when at least one logic level of the state signal st and the comparison result cmp is H level. The OR circuit 14a1 outputs an L level enable signal en when both the state signal st and the comparison result cmp are at the L level, and stops the operation of the DC / DC converter 11 (sets the standby state). .

The switch control circuit 14b includes an inverter circuit 14b1, a pMOS 14b2, a resistor R1, and a capacitor C2.
The input terminal of the inverter circuit 14b1 is connected to the output terminal of the OR circuit 14a1, and the output terminal of the inverter circuit 14b1 is connected to one end of the resistor R1.

  The gate of the pMOS 14b2 is connected to the output terminal of the OR circuit 14a1, and the drain of the pMOS 14b2 is connected to the other end of the resistor R1, one end of the capacitor C2, and the switch 12 (the gate of the pMOS 12a). The power supply voltage VDD is supplied to the source of the pMOS 14b2. The other end of the capacitor C2 is grounded.

The power supply voltage VDD may be supplied from a battery (not shown), or may be a DC voltage held in the storage element 20.
The values of the resistor R1 and the capacitor C2 are appropriately set based on, for example, the time until the output of the DC / DC converter 11 is stabilized when the operation of the DC / DC converter 11 is started.

  In such a switch control circuit 14b, when the logic level of the enable signal en is H level, the pMOS 14b2 is turned off. Further, the logic level of the output signal of the inverter circuit 14b1 becomes L level. After a delay time in the delay circuit by the resistor R1 and the capacitor C2, the logic level of the control signal cnt becomes L level, and the switch 12 is turned on. When the logic level of the enable signal en becomes L level, the pMOS 14b2 is turned on, so that the logic level of the control signal cnt becomes H level and the switch 12 is turned off.

The above is an example of the configuration of the power supply circuit 10.
The power supply circuit 10 described above is merely an example. For example, an inverter circuit may be added and the circuit may be changed as appropriate, such as using an n-channel MOSFET instead of the pMOS 12a and 14b2.

1 is, for example, a capacitor, a secondary battery, or a primary battery.
The load circuit 21 is, for example, a sensor or a wireless module. Various electronic circuits and electronic devices can be applied as the load circuit 21.

  The control unit 22 is an MCU (Micro Control Unit), for example, and controls the operation of the load circuit 21. Further, the control unit 22 supplies a state signal st corresponding to the operation state of the load circuit 21 to the power circuit 10.

Hereinafter, an example of the operation of the power supply circuit 10 according to the first embodiment will be described.
FIG. 2 is a timing chart showing an example of the operation of the power supply circuit. FIG. 2 shows an example of current consumption of the load circuit 21, the status signal st, the output of the DC / DC converter 11, the output voltage Vout, the comparison result cmp, and the control signal cnt. In FIG. 2, the enable signal en shown in FIG. 1 is not shown.

  When the load is high, the logic level of the state signal st rises from the L level to the H level (timing t1). As a result, the logic level of the enable signal en becomes H level, and the DC / DC converter 11 starts operating.

  Further, after the predetermined delay time described above from the timing t1, the logic level of the control signal cnt falls from the H level to the L level (timing t2). As a result, the switch 12 is turned on and the current consumption of the load circuit 21 increases.

  When the load circuit 21 enters a standby state (when the load is low), the current consumption of the load circuit 21 decreases, and the logic level of the state signal st falls from the H level to the L level (timing t3). At this time, since the output voltage Vout is larger than the voltage Vref, the logical level of the comparison result cmp remains at the L level. Therefore, the logic level of the enable signal en becomes L level, and the DC / DC converter 11 stops its operation (becomes a standby state). Further, since the pMOS 14b2 is turned on when the logic level of the enable signal en becomes L level, the logic level of the control signal cnt becomes H level and the switch 12 is turned off.

  As a result, the output voltage Vout is supplied from the capacitor C1 to the load circuit 21 as a power supply voltage. When the switch 12 is off, the output voltage Vout gradually decreases. When the logic level of the state signal st becomes H level again before the output voltage Vout falls below the voltage Vref, operations similar to those at timings t1 to t3 are performed (timing t4, t5, t6).

  When the output voltage Vout becomes smaller than the voltage Vref (timing t7), the logic level of the comparison result cmp rises from the L level to the H level. As a result, the logic level of the enable signal en becomes H level, and the DC / DC converter 11 starts operating (becomes active).

  Further, after the predetermined delay time described above has elapsed from timing t7, the logic level of the control signal cnt falls from the H level to the L level (timing t8). As a result, the switch 12 is turned on, the capacitor C1 is charged, and the output voltage Vout increases.

  When the output voltage Vout becomes higher than the voltage Vref (timing t9), the logical level of the comparison result cmp falls from the H level to the L level. As a result, the logic level of the enable signal en becomes L level, and the DC / DC converter 11 stops operating.

  Further, since the pMOS 14b2 is turned on when the logic level of the enable signal en becomes L level, the logic level of the control signal cnt becomes H level and the switch 12 is turned off.

  As a result, the output voltage Vout is again supplied from the capacitor C1 to the load circuit 21 as the power supply voltage. Further, since the switch 12 is off, the output voltage Vout gradually decreases.

  When the output voltage Vout becomes smaller than the voltage Vref again, operations similar to those at timings t7 to t9 are performed (timing t10, t11, t12). Thus, at the time of low load, the DC / DC converter 11 is intermittently operated based on the comparison result cmp between the output voltage Vout and the voltage Vref.

  As described above, in the power supply circuit 10 according to the present embodiment, when the output voltage Vout is higher than the voltage Vref at low load, the operation of the DC / DC converter 11 is stopped (becomes a standby state), and the switch 12 is turned off. The Thereby, the time of the operation (voltage conversion operation) of the DC / DC converter 11 at the time of low load is reduced, and the current consumption in the DC / DC converter 11 is reduced. Therefore, the power consumption of the power supply circuit 10 can be suppressed.

  Further, when the output voltage Vout is lower than the voltage Vref at low load, the operation of the DC / DC converter 11 is started, the switch 12 is turned on, and the capacitor C1 is charged, so that the output voltage Vout can be maintained. . Thereby, for example, it is possible to maintain the supply of electric power for holding the stored contents of a memory (not shown) in the load circuit 21.

Further, when the load is high, the DC / DC converter 11 is in an active state and the switch 12 is turned on, so that sufficient power is supplied to the load circuit 21.
Further, by using a commercially available buck-boost type DC / DC converter 11 with an enable terminal, the power supply circuit 10 having the above functions can be realized with a relatively simple circuit.

Hereinafter, an example of an electronic device using the power supply circuit 10 as described above will be described.
(Example of electronic device)
FIG. 3 is a diagram illustrating an example of an electronic device. The same elements as those shown in FIG. 1 are denoted by the same reference numerals.

The electronic device 30 includes an energy generation unit 31 and a charging circuit 32 in addition to the power supply circuit 10, the storage element 20, the load circuit 21, and the control unit 22 illustrated in FIG. 1.
The environmental power generation unit 31 is, for example, a solar battery and performs environmental power generation.

  The charging circuit 32 stores the electric power generated by the energy harvesting unit 31 in the storage element (secondary battery or capacitor) 20. Note that the charging circuit 32 may have a function of preventing a backflow of current from the power storage element 20 to the energy harvesting unit 31.

The voltage of the power storage element 20 (hereinafter referred to as the battery voltage) fluctuates due to environmental changes (for example, changes in the illuminance of sunlight).
FIG. 4 is a diagram illustrating an example of time variation of the battery voltage. The vertical axis represents the battery voltage, and the horizontal axis represents time.

  As shown in FIG. 4, the battery voltage varies greatly. Therefore, it is desirable that the power supply circuit 10 operate in a wide input voltage range. Since the power supply circuit 10 of the present embodiment uses the step-up / step-down DC / DC converter 11, it can cope with a wide input voltage range.

FIG. 5 is a diagram illustrating an example of a change over time in current consumption of the load circuit. The vertical axis indicates the current consumption of the load circuit 21, and the horizontal axis indicates time.
The load circuit 21 is in an active state from timing t20 to timing t21, from timing t22 to timing t23, and from timing t24 to timing t25, and current consumption increases. Other than this, the standby state is established, and the standby state is longer than the active state. When such a load circuit 21 (for example, a sensor or a wireless module) is used, it is desirable for the power supply circuit 10 to suppress power consumption at a low load.

  The step-up / step-down DC / DC converter 11 has a larger current consumption when the load circuit 21 is a low load and consumes more power than the step-down and step-up types because of the structure of the internal switching regulator. However, in the power supply circuit 10 of the present embodiment, when the output voltage Vout is higher than the voltage Vref, the operation of the DC / DC converter 11 is stopped, and thus an increase in power consumption can be suppressed as described above.

FIG. 6 is a diagram illustrating a comparative example of the power supply circuit, the step-down DC / DC converter, and the step-up / step-down DC / DC converter according to the first embodiment.
In FIG. 6, the high load of the power supply circuit 10, the step-down DC / DC converter, and the step-up / step-down DC / DC converter when the battery voltage is between the maximum value and the converter output voltage + α and the converter output voltage + α to the minimum value. An example of power efficiency at the time and current consumption at low load is shown.

  Although the maximum value and the minimum value of the battery voltage are determined by the storage element 20, for example, the maximum value is 5V and the minimum value is 0V. The converter output voltage is an output voltage in the active state of the step-down DC / DC converter or the step-up / step-down DC / DC converter. In the power supply circuit 10, the output voltage in the active state of the DC / DC converter 11 corresponds to the output voltage Vout of the power supply circuit 10. The converter output voltage becomes the power supply voltage of the load circuit 21 and is a value (for example, 3.3 V) between the maximum value and the minimum value in the example of FIG. α is a value based on an input voltage range in which the step-down DC / DC converter performing the step-down operation can operate. In FIG. 6, the power supply circuit 10 and the step-up / step-down DC / DC converter according to the first embodiment are assumed to be operable in the range of the battery voltage from the minimum value to the maximum value.

  In the power supply circuit 10 and the step-up / step-down DC / DC converter, the power supply efficiency under a high load is about 85% at the maximum. Further, in the buck-boost type DC / DC converter, the current consumption at the time of low load is about 50 μA at the maximum, whereas in the power supply circuit 10 of the first embodiment, it is suppressed to about 1 μA at the maximum.

  The step-down DC / DC converter operates in the range of the battery voltage from the maximum value to the converter output voltage + α. The power efficiency of the step-down DC / DC converter at high load is as high as about 95%, and the current consumption at low load is also as small as 0.5 μA at maximum. However, the step-down DC / DC converter does not operate when the battery voltage is in the range from the converter output voltage + α to the minimum value.

As described above, the step-down DC / DC converter has higher power efficiency at the time of high load than that of the power circuit 10. A power supply circuit that takes advantage of this advantage will be described below.
(Second Embodiment)
FIG. 7 is a diagram illustrating an example of a power supply circuit according to the second embodiment. The same elements as those shown in FIG. 1 are denoted by the same reference numerals.

  The power supply circuit 40 according to the second embodiment includes a step-down DC / DC converter 41 in addition to the step-up DC / DC converter 11. Furthermore, the power supply circuit 40 includes a switch 42 connected between the output terminal of the DC / DC converter 41 and one end of the capacitor C1.

  The step-down DC / DC converter 41 converts the DC voltage held in the storage element 20 into a DC voltage smaller than the DC voltage. That is, the DC / DC converter 41 steps down the input voltage so that the voltage is suitable for the load circuit 21.

  The DC / DC converter 41 is, for example, an LSI having an enable terminal in addition to an input / output terminal. Based on the logic level of the enable signal ena input to the enable terminal, the DC / DC converter 41 enters an active state (operation state) or a standby state (operation stop state).

  For example, as shown in FIG. 7, the switch 42 is realized by using a pMOS 42a. One of the source and the drain of the pMOS 42a is connected to the output terminal of the DC / DC converter 41, and the other is connected to one end of the capacitor C1. The control signal cnta is supplied to the gate of the pMOS 42a.

  In the power supply circuit 40, the control circuit 43 stops the operation of the DC / DC converter 11 when the DC voltage held in the storage element 20 is within the input voltage range in which the DC / DC converter 41 can operate. Then, the DC / DC converter 41 is operated. Further, the control circuit 43 turns off the switch 12 and turns on the switch 42.

The operable input voltage range of the DC / DC converter 41 is, for example, a voltage equal to or higher than the converter output voltage + α as shown in FIG.
The control circuit 43 stops the operation of the DC / DC converter 41 when the DC voltage held in the storage element 20 is not within the input voltage range in which the DC / DC converter 41 can operate. Turn off. Further, the control circuit 43 controls the DC / DC converter 11 and the switch 12 in the same manner as the control circuit 14 of the power supply circuit 10 according to the first embodiment.

For example, as shown in FIG. 7, the control circuit 43 includes an enable control circuit 43a, a switch control circuit 43b, and a comparison circuit 43c.
The enable control circuit 43a receives the state signal st indicating the operation state of the load circuit 21, the comparison result cmp in the comparison circuit 13, and the enable signal ena for the DC / DC converter 41 output from the comparison circuit 43c. . Then, the enable control circuit 43a outputs an enable signal en that controls whether the DC / DC converter 11 is in an active state or a standby state based on the state signal st, the comparison result cmp, and the enable signal ena.

  The switch control circuit 43b outputs a control signal cnt for controlling the switch 12 and a control signal cnta for controlling the switch 42 based on the enable signals en and ena. When the switch control circuit 43b receives the enable signal ena for activating the DC / DC converter 41, the switch control circuit 43b outputs a control signal cnta for turning on the switch 42 after a predetermined delay time. When the switch control circuit 43b receives an enable signal ena for setting the DC / DC converter 41 in a standby state, the switch control circuit 43b outputs a control signal cnta for turning off the switch 42. Further, when receiving the enable signal en for activating the DC / DC converter 11, the switch control circuit 43b outputs a control signal cnt for turning on the switch 12 after a predetermined delay time. When the switch control circuit 43b receives an enable signal en for setting the DC / DC converter 11 in the standby state, the switch control circuit 43b outputs a control signal cnt for turning off the switch 12.

Thereby, it can suppress that output noise (overshoot etc.) at the time of the operation | movement start of DC / DC converters 11 and 41 is propagated to the load circuit 21 side.
The comparison circuit 43c compares the DC voltage held in the storage element 20 with the voltage Vrefa, and outputs an enable signal ena as a comparison result. The voltage Vrefa is a value based on the lower limit value of the operable input of the DC / DC converter 41 (or the lower limit value itself), and is, for example, the converter output voltage + α described above.

The enable control circuit 43a and the switch control circuit 43b can be realized by a circuit as shown in FIG. 7, for example.
In the following description, it is assumed that when Vout <Vref, the logical level of the comparison result cmp is H level, and when Vout> Vref, the logical level of the comparison result cmp is L level. Further, it is assumed that the logic level of the state signal st is H level when the load is high, and the logic level of the state signal st is L level when the load is low. When the logic level of the enable signal en is H level, the DC / DC converter 11 is in an active state, and when it is L level, the DC / DC converter 11 is in a standby state. Further, when the logic level of the enable signal ena is H level, the DC / DC converter 41 is in an active state, and when the logic level is L level, the DC / DC converter 41 is in a standby state. Further, the switch 12 is turned off when the logic level of the control signal cnt is H level, and the switch 12 is turned on when the control signal cnt is L level. Further, it is assumed that the switch 42 is turned off when the logic level of the control signal cnta is H level, and the switch 42 is turned on when it is L level.

  The enable control circuit 43a outputs an AND logic of a signal obtained by inverting the logic level of the enable signal ena and the output signal of the OR circuit 14a1, in addition to the OR circuit 14a1 that outputs the OR logic of the state signal st and the comparison result cmp. An AND circuit 43a1 is provided. The output signal of the AND circuit 43a1 becomes the enable signal en.

  In such an enable control circuit 43a, if the logic level of the enable signal ena is H level, the logic level of the enable signal en becomes L level regardless of the logic level of the state signal st and the comparison result cmp. As a result, the operation of the DC / DC converter 11 stops (becomes a standby state).

  If the logic level of the enable signal ena is L level, the logic level of the enable signal en is determined based on the logic level of the state signal st and the comparison result cmp. When the logic level of at least one of the state signal st and the comparison result cmp is H level, the enable control circuit 43a outputs an H level enable signal en and operates the DC / DC converter 11. Further, the enable control circuit 43a outputs an L level enable signal en and stops the operation of the DC / DC converter 11 when the logic levels of both the state signal st and the comparison result cmp are L level.

  The switch control circuit 43b includes a pMOS 43b1, an inverter circuit 43b2, a resistor R2, and a capacitor C3 for controlling the switch 42 in addition to the inverter circuit 14b1, the pMOS 14b2, the resistor R1, and the capacitor C2 for controlling the switch 12. .

The input terminal of the inverter circuit 14b1 is connected to the output terminal of the AND circuit 43a1, and the output terminal of the inverter circuit 14b1 is connected to one end of the resistor R1.
The gate of the pMOS 14b2 is connected to the output terminal of the AND circuit 43a1, and the drain of the pMOS 14b2 is connected to the other end of the resistor R1, one end of the capacitor C2, and the switch 12 (the gate of the pMOS 12a). The power supply voltage VDD is supplied to the source of the pMOS 14b2. The other end of the capacitor C2 is grounded.

The enable signal ena is input to the input terminal of the inverter circuit 43b2, and the output terminal of the inverter circuit 43b2 is connected to one end of the resistor R2.
The other end of the resistor R2 is connected to the drain of the pMOS 43b1, one end of the capacitor C3, and the switch 42 (the gate of the pMOS 42a). An enable signal ena is input to the gate of the pMOS 43b1. The power supply voltage VDD is supplied to the source of the pMOS 43b1. The other end of the capacitor C3 is grounded.

  The values of the resistor R2 and the capacitor C3 are appropriately set based on, for example, the time until the output of the DC / DC converter 41 is stabilized when the operation of the DC / DC converter 41 starts.

  In such a switch control circuit 43b, when the logic level of the enable signal en is H level, the pMOS 14b2 is turned off. Further, when the logic level of the enable signal ena is L level, the pMOS 43b1 is turned on. Therefore, the logic level of the control signal cnta becomes H level, the switch 42 is turned off, and after the delay time in the delay circuit by the resistor R1 and the capacitor C2, the logic level of the control signal cnt becomes L level and the switch 12 is turned on. .

  When the logic level of the enable signal en becomes L level, the pMOS 14b2 is turned on, so that the logic level of the control signal cnt becomes H level and the switch 12 is turned off. Further, when the logic level of the enable signal ena is H level, the pMOS 43b1 is turned off, and after the delay time in the delay circuit by the resistor R2 and the capacitor C3, the logic level of the control signal cnta becomes L level and the switch 42 is turned on.

The above is an example of the configuration of the power supply circuit 40.
The power supply circuit 40 described above is merely an example. For example, an inverter circuit may be added and the circuit may be changed as appropriate, such as using an n-channel MOSFET instead of the pMOS 12a, 14b2, 42a, 43b1.

Hereinafter, an operation example of the power supply circuit 40 will be described.
FIG. 8 is a diagram for explaining the operation of the power supply circuit when the battery voltage is higher than the voltage Vrefa.

  In the example of FIG. 8, the maximum value of the battery voltage of the power storage element 20 is 5V, and the minimum value is 0V. In the example of FIG. 8, the minimum value of the input voltage range in which the step-up / step-down DC / DC converter 11 can operate is β.

  When the battery voltage is higher than the voltage Vrefa, the logic level of the enable signal ena becomes H level, and the step-down DC / DC converter 41 enters an active state. When the logic level of the enable signal ena is H level, the logic level of the enable signal en becomes L level regardless of the logic level of the state signal st and the comparison result cmp. Therefore, the step-up / step-down DC / DC converter 11 is in a standby state.

Further, the logic level of the control signal cnt becomes H level, the logic level of the control signal cnta becomes L level, the switch 12 is turned off, and the switch 42 is turned on.
As a result, current flows in the direction of arrow 45, and the battery voltage of power storage element 20 is stepped down by DC / DC converter 41 to obtain output voltage Vout, which is supplied to load circuit 21.

FIG. 9 is a diagram for explaining the operation of the power supply circuit when the battery voltage is lower than the voltage Vrefa and the load is high.
When the range of the battery voltage is smaller than the voltage Vrefa, the logic level of the enable signal ena becomes L level, and the step-down DC / DC converter 41 enters a standby state. When the logic level of the enable signal ena is L level, the logic level of the enable signal en is determined by the logic level of the state signal st and the comparison result cmp.

  When the load is high, the logic level of the state signal st is H level. As a result, the logic level of the enable signal en becomes H level, so that the step-up / step-down DC / DC converter 11 becomes active. Further, since the logic level of the enable signal en becomes H level, the logic level of the control signal cnt becomes L level and the logic level of the enable signal ena is L level, so that the logic level of the control signal cnta becomes H level. The switch 12 is turned on and the switch 42 is turned off.

  Thereby, a current flows in the direction of arrow 46, and the battery voltage of power storage element 20 is boosted or stepped down by DC / DC converter 11 to obtain output voltage Vout, which is supplied to load circuit 21.

FIG. 10 is a diagram for explaining the operation of the power supply circuit when the battery voltage is smaller than the voltage Vref, the load is low, and the output voltage Vout is larger than the voltage Vref.
When the range of the battery voltage is smaller than the voltage Vrefa, the step-down DC / DC converter 41 is in a standby state as in the case shown in FIG.

  Further, when the load is low, the logic level of the state signal st is L level. When the output voltage Vout is higher than the voltage Vref, the logical level of the comparison result cmp is L level. As a result, the logic level of the enable signal en becomes L level, and the step-up / step-down DC / DC converter 11 is also in a standby state.

  Further, when the logic level of the enable signal en becomes L level, the logic level of the control signal cnt becomes H level. Since the logic level of the enable signal ena is also L level, the logic level of the control signal cnta becomes H level and both the switches 12 and 42 are turned off.

As a result, a current flows from the capacitor C1 to the load circuit 21 in the direction of the arrow 47, and the output voltage Vout is supplied to the load circuit 21.
Note that when the battery voltage is smaller than the voltage Vref, the load is low, and the output voltage Vout is smaller than the voltage Vref, the logical level of the comparison result cmp becomes the H level. Then, as shown in FIG. 9, the DC / DC converter 11 becomes active, the switch 12 is turned on, the capacitor C1 is charged, and the output voltage Vout increases.

FIG. 11 is a diagram illustrating a comparative example of the power supply circuit according to the second embodiment, a step-down DC / DC converter, and a step-up / step-down DC / DC converter.
In FIG. 11, the high load of the power supply circuit 40, the step-down DC / DC converter, and the step-up / step-down DC / DC converter when the battery voltage is the maximum value to the converter output voltage + α and the converter output voltage + α to the minimum value. An example of power efficiency at the time and current consumption at low load is shown.

In FIG. 11, the power supply circuit 40 and the step-up / step-down DC / DC converter according to the second embodiment are assumed to be operable in the range of the battery voltage from the minimum value to the maximum value.
As shown in FIG. 11, in the power supply circuit 40, the power supply efficiency at the time of high load is improved as compared with the power supply circuit 10 shown in FIG. 6 when the battery voltage is in the range from the maximum value to the converter output voltage + α. I understand. Further, the current consumption at the time of low load can be suppressed to about 1 μA at the maximum similarly to the power supply circuit 10 of the first embodiment.

For this reason, in the power supply circuit 40, the battery capacity can be used more effectively in a wide input voltage range.
The power supply circuit 40 can be used instead of the power supply circuit 10 of the electronic device 30 shown in FIG.

(Third embodiment)
FIG. 12 is a diagram illustrating an example of a power supply circuit according to the third embodiment. The same elements as those shown in FIG. 7 are denoted by the same reference numerals.

  In the power supply circuit 50 of the third embodiment, the DC / DC converter 11 receives the battery voltage from the power storage element 20a, and the DC / DC converter 41 receives the battery voltage from the power storage element 20b. The battery voltage of power storage element 20a is smaller than output voltage Vout + α, and the battery voltage of power storage element 20b is larger than output voltage Vout + α. That is, the battery voltage of the storage element 20a is outside the input voltage range in which the step-down DC / DC converter 41 can operate, and the battery voltage of the storage element 20b is an input in which the step-down DC / DC converter 41 can operate. Within the voltage range.

  Further, unlike the power supply circuit 40 of the second embodiment, the power supply circuit 50 receives the enable signal ena from the control unit 22a. For this reason, the control circuit 51 is not provided with the comparison circuit 43c shown in FIG.

  When the control unit 22a causes the power supply circuit 50 to perform DC / DC conversion using the battery voltage of the power storage element 20b, the control unit 22a outputs an enable signal ena whose logic level is H level. In addition, when the control unit 22a causes the power supply circuit 50 to perform DC / DC conversion using the battery voltage of the storage element 20a, the control unit 22a outputs an enable signal ena whose logic level is L level. Therefore, the enable signal ena functions as a selection signal for selecting the power storage elements 20a and 20b used by the power supply circuit 50.

Hereinafter, an operation example of the power supply circuit 50 will be described.
FIG. 13 is a diagram for explaining the operation of the power supply circuit when a battery element having a battery voltage larger than the output voltage Vout + α is used.

  When the enable signal ena whose logic level is H level is supplied from the control unit 22a to the power supply circuit 50, the power supply circuit 50 uses the storage element 20b having a battery voltage higher than the output voltage Vout + α.

  The step-down DC / DC converter 41 is activated by an enable signal ena having a logic level of H level. When the logic level of the enable signal ena is H level, the logic level of the enable signal en is L level regardless of the logic level of the state signal st and the comparison result cmp. Therefore, the step-up / step-down DC / DC converter 11 is in a standby state.

Further, the logic level of the control signal cnt becomes H level, the logic level of the control signal cnta becomes L level, the switch 12 is turned off, and the switch 42 is turned on.
As a result, current flows in the direction of arrow 55, and the battery voltage of power storage element 20 b is stepped down by DC / DC converter 41 to obtain output voltage Vout, which is supplied to load circuit 21.

FIG. 14 is a diagram for explaining the operation of the power supply circuit at the time of high load, using a storage element whose battery voltage is smaller than the output voltage Vout + α.
When the enable signal ena whose logic level is L level is supplied from the control unit 22a to the power supply circuit 50, the power supply circuit 50 uses the power storage element 20a whose battery voltage is smaller than the output voltage Vout + α.

  The step-down DC / DC converter 41 enters a standby state by an enable signal ena having a logic level of L level. When the logic level of the enable signal ena is L level, the logic level of the enable signal en is determined by the logic level of the state signal st and the comparison result cmp.

  When the load is high, the logic level of the state signal st is H level. As a result, the logic level of the enable signal en becomes H level, so that the step-up / step-down DC / DC converter 11 becomes active. Further, since the logic level of the enable signal en becomes H level, the logic level of the control signal cnt becomes L level, the logic level of the control signal cnta becomes H level, the switch 12 is turned on, and the switch 42 is turned off.

  As a result, current flows in the direction of arrow 56, and the battery voltage of power storage element 20 a is boosted or stepped down by DC / DC converter 11 to obtain output voltage Vout, which is supplied to load circuit 21.

  FIG. 15 is a diagram for explaining the operation of the power supply circuit when the battery voltage is lower than the output voltage Vout + α and the load voltage is low and the output voltage Vout is higher than the voltage Vref.

  Similarly to the case of FIG. 14, when the enable signal ena having a logic level of L level is supplied from the control unit 22 a to the power supply circuit 50, the step-down DC / DC converter 41 enters a standby state.

  On the other hand, when the load is low, the logic level of the state signal st is L level. When the output voltage Vout is higher than the voltage Vref, the logical level of the comparison result cmp is L level. As a result, the logic level of the enable signal en becomes L level, and the step-up / step-down DC / DC converter 11 is also in a standby state.

  Further, when the logic level of the enable signal en becomes L level, the logic level of the control signal cnt becomes H level. Further, when the logic level of the enable signal ena becomes L level, the logic level of the control signal cnta becomes H level, and both the switches 12 and 42 are turned off.

Thereby, a current flows from the capacitor C1 to the load circuit 21 in the direction of the arrow 57, and the output voltage Vout is supplied to the load circuit 21.
Note that an enable signal ena having a logic level of L level is supplied from the control unit 22a to the power supply circuit 50. When the load voltage is low and the output voltage Vout is smaller than the voltage Vref, the logic level of the comparison result cmp is H. Become a level. Then, as shown in FIG. 14, the DC / DC converter 11 becomes active, the switch 12 is turned on, the capacitor C1 is charged, and the output voltage Vout increases.

FIG. 16 is a diagram illustrating an example of a relationship between a battery to be used, power supply efficiency at high load, and current consumption at low load.
When the power supply circuit 50 uses the power storage element 20b, since the step-down DC / DC converter 41 is used, the power supply efficiency at high load is as high as about 95%. In addition, the current consumption at the time of low load can be suppressed to about 1 μA at the maximum.

  When the power supply circuit 50 uses the storage element 20a, the step-up / step-down DC / DC converter 11 is used, and the power supply efficiency at the time of high load is about 85% at the maximum. In addition, the current consumption at the time of low load can be suppressed to a maximum of about 1 μA by the intermittent operation described above.

For this reason, in the power supply circuit 50, the battery capacity can be effectively used in accordance with the selected power storage elements 20a and 20b.
The power supply circuit 50 can also be used instead of the power supply circuit 10 of the electronic device 30 shown in FIG.

  As mentioned above, although one viewpoint of the power supply circuit and electronic device of this invention has been demonstrated based on embodiment, these are only examples and are not limited to said description.

10 Power supply circuit 11 DC / DC converter (Buck-boost type)
12 switch 12a, 14b2 pMOS
13 comparison circuit 14 control circuit 14a enable control circuit 14a1 OR circuit 14b switch control circuit 14b1 inverter circuit 20 storage element 21 load circuit 22 control unit C1, C2 capacitor cmp comparison result cnt control signal en enable signal R1 resistance st state signal VDD power supply voltage Vout output voltage Vref voltage

Claims (8)

A first DC / DC converter that converts a first DC voltage into a second DC voltage that is smaller than or greater than the first DC voltage;
A capacitor for holding an output voltage based on the second DC voltage;
A first switch connected between an output terminal of the first DC / DC converter and one end of the capacitor;
A first comparison circuit that compares the output voltage with a first value and outputs a first comparison result;
A second state in which the operation state receives a state signal indicating an operation state of a load circuit that operates using the output voltage as a power supply voltage and the first comparison result, and the operation state has a lower load than the first state. A control circuit that stops the operation of the first DC / DC converter and turns off the first switch when the first comparison result indicates that the output voltage is greater than the first value; When,
A power supply circuit comprising:   The control circuit includes the first DC / DC converter when the operation state is the second state and the first comparison result indicates that the output voltage is smaller than the first value. The power supply circuit according to claim 1, wherein the first switch is turned on.   The power supply circuit according to claim 2, wherein the control circuit turns on the first switch with a delay of a first time from an operation start timing of the first DC / DC converter. A second DC / DC converter that steps down the first DC voltage and converts it to the second DC voltage;
A second switch connected between the output terminal of the second DC / DC converter and the one end of the capacitor;
The control circuit stops the operation of the first DC / DC converter when the first DC voltage is within an input voltage range in which the second DC / DC converter can operate. The first DC / DC converter is operated, the first switch is turned off, and the second switch is turned on.
The power supply circuit according to any one of claims 1 to 3, wherein   5. The power supply circuit according to claim 4, wherein the control circuit turns on the second switch with a second time delay from an operation start timing of the second DC / DC converter. The control circuit compares the first DC voltage supplied from the power storage element with a second value based on a lower limit value of an input voltage at which the second DC / DC converter can operate, A second comparison circuit for outputting a comparison result;
When the second comparison result indicates that the first DC voltage is larger than the second value, the control circuit stops the operation of the first DC / DC converter, and the second DC voltage is 6. The power supply circuit according to claim 4, wherein the DC / DC converter is operated to turn off the first switch and turn on the second switch. 7. The control circuit includes: a first storage element whose held voltage range is outside an operable input voltage range of the second DC / DC converter; and a held voltage range within the input voltage range. Receiving a selection signal indicating which of the second power storage elements to select;
When the selection signal indicates that the second power storage element is selected, the control circuit stops the operation of the first DC / DC converter and the first power supplied from the second power storage element. 6. The power supply circuit according to claim 4, wherein the second DC / DC converter is operated based on a direct current voltage to turn off the first switch and turn on the second switch. 7. A load circuit;
A control unit that controls the load circuit and outputs a state signal indicating an operation state of the load circuit;
A first DC / DC converter that converts a first DC voltage into a second DC voltage that is smaller than or greater than the first DC voltage; and is connected to the load circuit; A capacitor that holds an output voltage based on the second DC voltage, an output terminal of the first DC / DC converter, a first switch connected between one end of the capacitor, and the output voltage. The first comparison circuit that compares the first value and outputs the first comparison result, the state signal, and the first comparison result are received, and the operation state is lower than the first state. A second state of a load, and when the first comparison result indicates that the output voltage is greater than the first value, the operation of the first DC / DC converter is stopped; A control circuit for turning off the first switch; And a power supply circuit,
An electronic device comprising:

Images