JP2017175497A - AD converter and audio signal amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AD converter which can perform AD conversion in a short time.SOLUTION: An AD converter 10 includes: a triangular wave generation unit 11 which generates a triangular wave signal which, by a clock obtained by dividing a reference clock, rises to a voltage according to a first digital value, and falls to a voltage according to a second digital value smaller than the first digital value; a comparator 12 which compares the triangular wave signal generated by the triangular wave generation unit 11 with an input voltage being input; and a first calculation unit 13 which, according to the comparison result of the comparator 12 at the timing of at least one rise or fall time of the reference clock, performs processing to update at least one of the first digital value and the second digital value in a manner to reduce a difference between the first digital and second digital values. The first calculation unit 13 performs conversion into a digital value between the first and second digital values obtained after performing input voltage update processing.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to an AD converter and an audio signal amplifier using the AD converter.

  An AD (Analog to Digital) converter is a circuit that converts an input analog voltage into a digital signal, and is used in various fields. For example, the AD converter sequentially compares an input analog voltage with a plurality of reference voltages and converts the analog voltage into a digital signal. Patent Document 1 discloses a technique related to such an AD converter.

JP 2014-207518 A

  By the way, a digital amplifier that amplifies a digital audio signal demodulates to an analog signal by passing the output of the digital amplifier through a low-pass filter. At that time, the analog signal includes distortion due to non-linearity of the coil, etc., which occurs in demodulation by the low-pass filter. Therefore, an AD converter is used to correct the distortion. Specifically, an analog signal including distortion is converted into a digital signal by the AD converter, and the digital signal is fed back to the input of the digital amplifier to correct the distortion. At this time, in order to cope with recent high resolution audio, AD conversion is preferably performed quickly.

  Therefore, the present disclosure provides an AD converter and an audio signal amplifier that can perform AD conversion in a short time.

  The AD converter according to the present disclosure generates a triangular wave signal that rises to a voltage corresponding to the first digital value and falls to a voltage corresponding to a second digital value that is smaller than the first digital value by a clock obtained by dividing the reference clock. Comparison result of the triangular wave generation unit to be generated, a comparator that compares the triangular wave signal generated by the triangular wave generation unit and the input voltage to be input, and the comparator at the timing of rising or falling of the reference clock at least once And a first arithmetic unit that performs a process of updating at least one of the first digital value and the second digital value so that a difference between the first digital value and the second digital value is reduced. The first arithmetic unit performs the process of updating the input voltage and the second digital value and the second digital value. Into a digital value between Le values.

  An audio signal amplifier according to the present disclosure includes a delta-sigma modulation unit that resamples a digital audio signal with a quantization number smaller than the quantization number of the digital audio signal, and a signal output from the delta-sigma modulation unit. A pulse width modulation unit that converts a gradation of amplitude level into a pulse width modulation signal having a gradation of pulse width, a power amplification unit that amplifies a signal output from the pulse width modulation unit, and the power amplification unit outputs A low-pass filter that reduces and outputs a component higher than a predetermined cutoff frequency in the signal, a sample-hold circuit that holds the voltage of the signal output from the low-pass filter, and a voltage held by the sample-hold circuit as the input voltage The AD converter for converting to the digital value, and the digital output from the AD converter A second computing unit that computes a difference between a digital value and the digital audio signal, and the second computing unit calculates the digital audio signal from the digital audio signal when the digital audio signal is larger than the digital value. A value obtained by subtracting a digital value is added to the digital audio signal and output to the delta-sigma modulation unit. When the digital audio signal is smaller than the digital value, the digital audio signal is subtracted from the digital value. The value is subtracted from the digital audio signal and output to the delta-sigma modulator.

  The AD converter and the audio signal amplifier in the present disclosure can perform AD conversion in a short time.

2 is a configuration diagram illustrating an example of an AD converter according to Embodiment 1. FIG. 3 is a configuration diagram illustrating an example of a triangular wave generation unit according to Embodiment 1. FIG. It is a figure which shows an example of the waveform of a reference | standard clock. It is a figure which shows an example of the waveform of the frequency-divided clock. It is a figure which shows an example of the waveform of the output of a multibit DA converter. It is a figure which shows an example of the waveform of the output of a triangular wave production | generation part (integrator). 3 is a flowchart illustrating an example of an operation of the AD converter according to the first embodiment. 6 is an explanatory diagram illustrating an example of an operation of the AD converter according to Embodiment 1. FIG. FIG. 6 is an explanatory diagram illustrating another example of the operation of the AD converter according to the first embodiment. FIG. 5 is a configuration diagram illustrating an example of an audio signal amplifier according to a second embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

  The inventor provides the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and is not intended to limit the subject matter described in the claims. Absent.

(Embodiment 1)
The first embodiment will be described below with reference to FIGS.

[Constitution]
FIG. 1 is a configuration diagram illustrating an example of an AD converter 10 according to the first embodiment.

  The AD converter 10 is a circuit that converts an analog voltage into a digital electric signal. In this embodiment, as shown in FIG. 1, an input voltage input to a comparator 12 described later is converted into a digital value. That is, the input voltage is a voltage converted into a digital value. A reference clock (master clock) is input to the AD converter 10. The reference clock is a clock of 100 MHz, for example. The AD converter 10 includes a triangular wave generation unit 11, a comparator 12, a first calculation unit 13, a control unit 14, and a frequency divider circuit 15.

  The triangular wave generation unit 11 is a circuit that generates a triangular wave signal, and generates a triangular wave signal according to the frequency of the input clock and two input digital values. Specifically, the triangular wave generator 11 has a frequency corresponding to the clock obtained by dividing the reference clock by the frequency divider circuit 15 described later, and rises to a voltage corresponding to the first digital value. Is a circuit that generates a triangular wave signal that drops to a voltage corresponding to a small second digital value. Here, the triangular wave generation unit 11 will be described with reference to FIG.

  FIG. 2 is a configuration diagram illustrating an example of the triangular wave generation unit 11 according to the first embodiment.

  As shown in FIG. 2, the triangular wave generator 11 includes a multi-bit DA (Digital to Analog) converter 11a and an integrator 11b.

  The multi-bit DA converter 11a receives the divided clock and two digital values, and outputs a pulse corresponding to these signals. Specifically, the multi-bit DA converter 11a has the frequency of the input divided clock, the high level is the first voltage corresponding to the first digital value, and the low level is the first voltage corresponding to the second digital value. An analog pulse signal having two voltages is output. The first digital value and the second digital value are, for example, digital values stored in a storage unit (not shown) included in the AD converter 10. When the first digital value or the second digital value is updated, the multi-bit DA converter 11a has a first voltage corresponding to the first digital value whose high level is updated and a second digital whose low level is updated. An analog pulse signal having a second voltage corresponding to the value is output.

  The integrator 11b integrates the analog pulse signal output from the multi-bit DA converter 11a to output a triangular wave signal.

  The comparator 12 is a circuit that compares two input signals (for example, analog voltage) and outputs a high level or low level signal according to the magnitude relationship. The comparator 12 compares the triangular wave signal generated by the triangular wave generator 11 and the input voltage as two input signals.

  The first arithmetic unit 13 receives the reference clock, and the difference between the first digital value and the second digital value is small according to the comparison result of the comparator 12 at the timing of rising or falling of the reference clock at least once. The process which updates at least one of a 1st digital value and a 2nd digital value is performed. Here, the rising or falling timing of the reference clock is at least one of rising and falling timings of the reference clock. Further, updating at least one of the first digital value and the second digital value means updating at least one of the first digital value and the second digital value stored in the storage unit to a different value, for example. Then, the first calculation unit 13 converts the input voltage to a digital value between the first digital value and the second digital value after performing a process of updating at least one of the first digital value and the second digital value. Convert. The first calculation unit 13 will be described in detail with reference to FIG.

  The control unit 14 determines whether or not the first calculation unit 13 has performed the process of updating at least one of the first digital value and the second digital value a predetermined number of times. That is, the control unit 14 counts, as one cycle, that the triangular wave generation unit 11 generates a triangular wave signal and the first calculation unit 13 performs a process of updating at least one of the first digital value and the second digital value. Then, it is determined whether or not the cycle has been performed a predetermined number of times.

  The frequency dividing circuit 15 is a circuit that divides the reference clock by a desired frequency dividing ratio. For example, the frequency dividing circuit 15 outputs a clock in which the frequency of the reference clock is halved by dividing the reference clock by one. It is assumed that the divided clock output from the frequency dividing circuit 15 is synchronized with the reference clock. Further, the frequency dividing circuit 15 is not limited to dividing the reference clock by 1 and may divide by 2 or more.

  Note that the AD converter 10 may not include the frequency dividing circuit 15, and the AD converter 10 may receive a frequency-divided clock from the frequency dividing circuit 15 outside the AD converter 10. However, even in this case, it is assumed that the clock for generating the triangular wave signal by the triangular wave generation unit 11 and the reference clock input to the first calculation unit 13 are synchronized.

  Here, the reference clock, the divided clock, the output of the multi-bit DA converter 11a, and the triangular wave signal (output of the integrator 11b) will be described with reference to FIGS. 3A to 3D.

  FIG. 3A is a diagram illustrating an example of a waveform of a reference clock. FIG. 3B is a diagram illustrating an example of a divided clock waveform. FIG. 3C is a diagram illustrating an example of an output waveform of the multi-bit DA converter 11a. FIG. 3D is a diagram illustrating an example of an output waveform of the triangular wave generator 11 (integrator 11b).

  As shown in FIG. 3B, the frequency dividing circuit 15 outputs a clock that is half the frequency of the reference clock by dividing the reference clock by 1, for example. Next, as shown in FIG. 3C, the multi-bit DA converter 11a outputs an analog pulse signal having a frequency corresponding to the input divided clock. At this time, the multi-bit DA converter 11a outputs an analog pulse signal whose high level is a first voltage corresponding to the first digital value and whose low level is a second voltage corresponding to the second digital value. Then, as shown in FIG. 3D, the integrator 11b integrates the input analog pulse signal and outputs a triangular wave signal. In the triangular wave signal, the high level period of the input analog pulse signal corresponds to the rising period in which the voltage rises from the second voltage to the first voltage, and the falling period in which the low level period falls from the first voltage to the second voltage. Corresponding to In this way, the lowest voltage (second voltage) is a voltage corresponding to the second digital value, the highest voltage (first voltage) is a voltage corresponding to the first digital value, and the triangular wave signal is synchronized with the reference clock. Is generated.

[Operation]
Next, the operation of the AD converter 10 will be described with reference to FIGS.

  FIG. 4 is a flowchart showing an example of the operation of the AD converter 10 according to the first embodiment. FIG. 5 is an explanatory diagram for explaining an example of the operation of the AD converter 10 according to the first embodiment. In FIG. 5, for example, the operation of the AD converter 10 when the clock obtained by dividing the reference clock is a clock obtained by dividing the reference clock is described.

  First, the triangular wave generator 11 has a frequency corresponding to a clock obtained by dividing the reference clock (divided by 1), and rises to a voltage (first voltage) corresponding to the first digital value. A triangular wave signal that falls to a voltage (second voltage) corresponding to the second digital value that is also smaller is generated (step S11). As a result, as shown in the upper part of FIG. 5, a triangular wave signal synchronized with the reference clock is input to the input terminal of the comparator 12. Specifically, a triangular wave signal whose timing of rising of the reference clock is an intermediate timing in the rising period is input to the input terminal of the comparator 12. For example, an input voltage is input to the positive input terminal of the comparator 12 and a triangular wave signal is input to the negative input terminal. At the beginning of the operation of the AD converter 10, the first digital value is a value corresponding to the maximum value that the input voltage can take, and the second digital value is a value corresponding to the minimum value that the input voltage can take.

  Next, the comparator 12 compares the input triangular wave signal with the input voltage (step S12). Thus, it can be seen that the input voltage is larger than the triangular wave signal when the output of the comparator 12 is high level, and the input voltage is smaller than the triangular wave signal when the output of the comparator 12 is low level. I understand.

  Next, the first arithmetic unit 13 determines the first digital value as the timing of rising or falling of the reference clock at least once, for example, according to the comparison result of the comparator 12 at the timing of rising of the reference clock once. A process of updating at least one of the first digital value and the second digital value so as to reduce the difference from the second digital value is performed (step S13). Specifically, the first calculation unit 13 determines at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the timing of one rising of the reference clock in the rising period of the triangular wave signal. Process to update. For example, it can be seen that the input voltage is larger than the triangular wave signal at the rising timing of the reference clock as indicated by a point 201 shown in FIG. That is, it can be seen that the input voltage is larger than the voltage of the triangular wave signal at this timing (point 201) and smaller than the first voltage. Therefore, the first calculation unit 13 updates the second digital value to a value corresponding to the voltage of the triangular wave signal at the point 201 so that the difference between the first digital value and the second digital value becomes small. Note that, since the reference clock and the triangular wave signal are synchronized, the first arithmetic unit 13 can recognize the voltage of the triangular wave signal at the rising timing of the reference clock. For example, when the triangular wave signal is a signal obtained by dividing the reference clock by 1, the voltage of the triangular wave signal at the rising timing of the reference clock is an intermediate voltage between the first voltage and the second voltage. That is, the value corresponding to the voltage of the triangular wave signal at the rising timing of the reference clock is an intermediate value between the first digital value and the second digital value.

  Next, the control unit 14 determines whether or not the first calculation unit 13 has performed processing for updating at least one of the first digital value and the second digital value a predetermined number of times (step S14).

  When the control unit 14 determines that the first calculation unit 13 has not performed the process of updating at least one of the first digital value and the second digital value a predetermined number of times (No in step S14), the process from step S11 is performed. Processing is performed again. Specifically, the triangular wave generator 11 generates a triangular wave signal that rises to a voltage corresponding to the first digital value and falls to a voltage corresponding to the updated second digital value by a clock obtained by dividing the reference clock by one. Regenerate. Thereby, a triangular wave signal as shown in the center of FIG. 5 is input to the input terminal of the comparator 12. It can be seen that the width of the amplitude of the triangular wave signal is narrowed by updating the second digital value. Therefore, the input voltage is specified as a voltage within a narrower range. Then, the first calculation unit 13 performs again the process of updating at least one of the first digital value and the second digital value in accordance with the comparison result of the comparator 12 at the timing of one rising of the reference clock. For example, it can be seen that the input voltage is smaller than the triangular wave signal at the rising timing of the reference clock as indicated by a point 202 shown in the center of FIG. That is, it can be seen that the input voltage is smaller than the voltage of the triangular wave signal at this timing (point 202) and larger than the second voltage. Therefore, the first calculation unit 13 updates the first digital value to a value corresponding to the voltage of the triangular wave signal at the point 202 so that the difference between the first digital value and the second digital value becomes smaller. Then, the control unit 14 determines whether or not the first calculation unit 13 has performed processing for updating at least one of the first digital value and the second digital value a predetermined number of times.

  By repeating this, the AD converter 10 specifies the input voltage in a narrower range.

  When the control unit 14 determines that the first calculation unit 13 has performed a predetermined number of times to update at least one of the first digital value and the second digital value (Yes in step S14), the first calculation unit 13 converts the input voltage into a digital value between the first digital value and the second digital value after the update process has been performed a predetermined number of times. In order to perform AD conversion on the next input voltage, the first digital value is updated to a value corresponding to the maximum value that the input voltage can take, and the second digital value corresponds to the minimum value that the input voltage can take. To be updated.

  Thus, when the first calculation unit 13 performs a process of updating at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at one timing, the first calculation unit 13 When the voltage of the triangular wave signal at one timing is larger than the input voltage, the first digital value is updated to a value corresponding to the voltage of the triangular wave signal at one timing, and the voltage of the triangular wave signal at one timing is input. When the voltage is smaller than the voltage, the second digital value is updated to a value corresponding to the voltage of the triangular wave signal at one timing.

  As a result, the input voltage can be AD-converted more accurately as the number of times of repeating step S11 to step S13 (a predetermined number of times) is increased. The predetermined number of times is predetermined by the user, for example. For example, when the user desires AD conversion with a precision of 24 bits, the predetermined number of times is predetermined as 24 times. That is, the predetermined number of times is determined according to the accuracy of AD conversion desired by the user.

  In FIG. 5, for example, the operation of the AD converter 10 in the case where the clock obtained by dividing the reference clock is the clock divided by 1 has been described. However, the divided clock is not limited to 1 divided by 2 It may be a clock having more than one round. Here, the operation of the AD converter 10 when the reference clock is generated by, for example, a ternary up counter will be described with reference to FIG.

  FIG. 6 is an explanatory diagram for explaining another example of the operation of the AD converter 10 according to the first embodiment.

  First, the triangular wave generator 11 rises to a voltage corresponding to the first digital value (first voltage) by the clock generated by the ternary up counter as the reference clock, and sets the second digital value smaller than the first digital value. A triangular wave signal that falls to a corresponding voltage (second voltage) is generated. Thereby, as shown in the upper part of FIG. 6, a triangular wave signal synchronized with the reference clock is input to the input terminal of the comparator 12. Specifically, the six rising and falling timings of the reference clock are respectively 1/6, 2/6, 3/6, 4/6, 5/6, and 6 minutes in the rising period. A triangular wave signal having a timing of 6 is input to the input terminal of the comparator 12.

  Next, the first calculation unit 13 updates at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the rising and falling timings of the six reference clocks, for example. I do. Specifically, the first calculation unit 13 determines the first digital value and the second digital value according to the comparison result of the comparator 12 at the rising and falling timings of the six reference clocks during the rising period of the triangular wave signal. A process of updating at least one of the values is performed. For example, the input voltage is larger than the triangular wave signal at the rising timings of the reference clocks such as points 301 and 303 shown in FIG. 6 and at the falling timing of the reference clock such as point 302. I understand that. Further, the input voltage is smaller than the triangular wave signal at the rising timing of the reference clock as shown at point 305 and the falling timing of the reference clock as shown at points 304 and 306 shown in FIG. I understand. That is, the input voltage is larger than the voltage of the triangular wave signal at the largest point 303 among the points 301, 302, and 303, and the voltage of the triangular wave signal at the smallest point 304 among the points 304, 305, and 306. You can see that it is smaller. Therefore, the first calculation unit 13 updates the first digital value to a value corresponding to the voltage of the triangular wave signal at the point 304 so that the difference between the first digital value and the second digital value becomes small, and the second digital value. Is updated to a value corresponding to the voltage of the triangular wave signal at point 303. Then, the control unit 14 determines whether or not the first calculation unit 13 has performed processing for updating at least one of the first digital value and the second digital value a predetermined number of times.

  When the control unit 14 determines that the first calculation unit 13 has not performed the process of updating at least one of the first digital value and the second digital value a predetermined number of times, the triangular wave generation unit 11 sets the reference clock to 3 By the clock generated by the decimal up counter, the voltage rises to a voltage corresponding to the updated first digital value (the voltage of the triangular wave signal at the point 304), and the voltage corresponding to the updated second digital value (the triangular wave signal at the point 304) Reproduce the triangular wave signal that falls to the voltage. Thereby, a triangular wave signal as shown in the lower part of FIG. 6 is input to the input terminal of the comparator 12. It can be seen that the amplitude of the triangular wave signal is narrowed by updating the first digital value and the second digital value. Therefore, the input voltage is specified as a voltage within a narrower range. Then, the first arithmetic unit 13 performs a process of updating at least one of the first digital value and the second digital value in accordance with the comparison result of the comparator 12 at the rising and falling timings of the six reference clocks, for example. Try again. For example, at the rising timing of the reference clock such as point 307 and point 309 shown at the bottom of FIG. 6 and at the falling timing of the reference clock such as point 308 and point 310, the input voltage is higher than the triangular wave signal. It can be seen that is large. Further, it can be seen that the input voltage is smaller than the triangular wave signal at the rising timing of the reference clock as indicated by a point 311 shown at the bottom of FIG. 6 and the falling timing of the reference clock as indicated by a point 312. That is, the input voltage is larger than the voltage of the triangular wave signal at the largest point 310 among the points 307 to 310 and smaller than the voltage of the triangular wave signal at the smallest point 311 among the points 311 and 312. . Therefore, the first calculation unit 13 updates the first digital value to a value corresponding to the voltage of the triangular wave signal at the point 311 so that the difference between the first digital value and the second digital value becomes smaller, and the second digital value The value is updated to a value corresponding to the voltage of the triangular wave signal at point 310. Then, the control unit 14 determines whether or not the first calculation unit 13 has performed processing for updating at least one of the first digital value and the second digital value a predetermined number of times.

  By repeating this, the AD converter 10 specifies the input voltage in a narrower range.

  When the control unit 14 determines that the first calculation unit 13 has performed a predetermined number of times to update at least one of the first digital value and the second digital value, the first calculation unit 13 sets the input voltage to Then, the digital value is converted into a digital value between the first digital value and the second digital value after the updating process is performed a predetermined number of times.

  Thus, when the first calculation unit 13 performs a process of updating at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at a plurality of times, the first calculation unit 13 When there are a plurality of times when the voltage of the triangular wave signal becomes larger than the input voltage, the first digital value is updated to the smallest value among the values corresponding to the voltage of the triangular wave signal at the plurality of times. In addition, when there are a plurality of times when the voltage of the triangular wave signal becomes smaller than the input voltage, the first calculation unit 13 sets the second digital value to the largest value among the values corresponding to the voltage of the triangular wave signal at the plurality of times. Update to value. When the timing at which the voltage of the triangular wave signal becomes larger than the input voltage is one time, the first arithmetic unit 13 updates the first digital value to a value corresponding to the voltage of the triangular wave signal at the one timing. In addition, when the timing at which the voltage of the triangular wave signal becomes smaller than the input voltage is one time, the first arithmetic unit 13 updates the second digital value to a value corresponding to the voltage of the triangular wave signal at the single timing.

  Accordingly, the process according to the comparison result of the comparator 12 at a plurality of timings is performed rather than the process of updating at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at one timing. By performing the process, the input voltage can be specified in a narrower range by the process once. For multiple timings, by using both the rising and falling edges of the reference clock, the input voltage is specified in a time shorter than the time for comparing the input voltage with the triangular wave generated from the clock divided by 1 can do.

[Effects]
As described above, in the present embodiment, the AD converter 10 rises to a voltage corresponding to the first digital value by the clock obtained by dividing the reference clock, and responds to the second digital value smaller than the first digital value. A triangular wave generation unit 11 for generating a triangular wave signal that falls to a predetermined voltage. The AD converter 10 also includes a comparator 12 that compares the triangular wave signal generated by the triangular wave generation unit 11 with the input voltage that is input. In addition, the AD converter 10 includes the first digital value so that the difference between the first digital value and the second digital value becomes small according to the comparison result of the comparator 12 at the timing of rising or falling of the reference clock at least once. The 1st calculating part 13 which performs the process which updates at least one of a value and a 2nd digital value is provided. And the 1st calculating part 13 is converted into the digital value between the 1st digital value after performing the process which updates an input voltage, and a 2nd digital value.

  As a result, by performing a process of updating at least one of the first digital value and the second digital value, the input voltage can be specified as a value within a narrower range, that is, the input voltage can be AD converted. . Specifically, by performing the process once according to the comparison result of the comparator 12 at the rising or falling timing of one reference clock as the rising or falling timing of the reference clock, for example. The input voltage can be specified as a value within a range of ½ before the processing is performed. Therefore, by increasing the number of times that the processing is performed, the accuracy of AD conversion increases by a power of 2. Further, when comparing the comparator 12 at the timing of rising and falling of the reference clock at least once as the timing of rising or falling of the reference clock, for example, a clock generated by a ternary up counter, for example, In the comparison between the triangular wave signal generated from the input voltage and the input voltage, the accuracy of AD conversion increases by a power of 6. For example, in the comparison between the triangular wave signal generated from the clock generated by dividing the reference clock by 2 and the input voltage, 8 The precision of AD conversion increases with a power. In addition, since the processing can be performed in a short time such as 10 ns according to a reference clock such as 100 MHz, AD conversion can be performed in a short time even if the number of times of the processing is increased. Thus, the AD converter 10 can perform AD conversion in a short time. Further, the AD converter 10 can perform AD conversion with high accuracy by increasing the number of times of performing the processing.

  Further, in the present embodiment, the AD converter 10 further determines whether or not the first calculation unit 13 has performed the process of updating at least one of the first digital value and the second digital value a predetermined number of times. A control unit 14 is provided. When the control unit 14 determines that the process of updating by the first calculation unit 13 has not been performed a predetermined number of times, the triangular wave generation unit 11 responds to the first digital value and the second digital value after the process of updating. The first arithmetic unit 13 regenerates the triangular wave signal, and updates the at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the rising or falling timing of the reference clock. Try again. In addition, when the control unit 14 determines that the process of updating the first calculation unit 13 has been performed a predetermined number of times, the first calculation unit 13 performs the process of updating the input voltage a predetermined number of times. To a digital value between the first digital value and the second digital value.

  The predetermined number of times is predetermined by the user, for example. Therefore, it is possible to perform AD conversion with accuracy according to the user's request. For example, when the user desires AD conversion with a precision of 24 bits, the predetermined number of times is predetermined to 24. Even when the predetermined number of times is large, since the process of updating at least one of the first digital value and the second digital value is performed in a short time per time, AD conversion can be performed in a short time.

  In the present embodiment, the first arithmetic unit 13 updates at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the timing of rising or falling of the reference clock once. When performing the processing, the first arithmetic unit 13 updates the first digital value to a value corresponding to the voltage of the triangular wave signal at the timing when the voltage of the triangular wave signal at the timing is larger than the input voltage. In addition, when the voltage of the triangular wave signal at the timing is smaller than the input voltage, the first calculation unit 13 updates the second digital value to a value corresponding to the voltage of the triangular wave signal at the timing.

  As a result, the process of updating at least one of the first digital value and the second digital value is performed in accordance with the comparison result of the comparator 12 at the timing of rising or falling of the reference clock once, so that AD can be performed in a shorter time. Conversion can be performed.

  Further, in the present embodiment, the first calculation unit 13 updates at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the timing of rising or falling of the reference clock a plurality of times. In the case of performing the processing, when the timing at which the voltage of the triangular wave signal becomes larger than the input voltage is one time, the first arithmetic unit 13 corresponds the first digital value to the voltage of the triangular wave signal at the one timing. Update to value. In addition, when the timing at which the voltage of the triangular wave signal becomes larger than the input voltage is a plurality of times, the first arithmetic unit 13 determines the first digital value among the values corresponding to the voltage of the triangular wave signal at the plurality of times of the timing. Update to the smallest value. In addition, when the timing at which the voltage of the triangular wave signal becomes smaller than the input voltage is once, the first arithmetic unit 13 updates the second digital value to a value corresponding to the voltage of the triangular wave signal at the one timing. To do. In addition, when the timing at which the voltage of the triangular wave signal becomes smaller than the input voltage is a plurality of times, the first calculation unit 13 sets the second digital value among the values corresponding to the voltage of the triangular wave signal at the plurality of times of the timing. Update to the highest value.

  As a result, a process of updating at least one of the first digital value and the second digital value is performed according to the comparison result of the comparator 12 at a plurality of times, so that the input voltage is kept within a narrower range by one process. Can be specified.

(Embodiment 2)
Next, the audio signal amplifier 100 according to Embodiment 2 will be described with reference to FIG.

  FIG. 7 is a configuration diagram illustrating an example of the audio signal amplifier 100 according to the second embodiment.

  The audio signal amplifier 100 is a digital amplifier that amplifies the digital audio signal, and demodulates it into an analog signal by passing the output of the digital amplifier through the low-pass filter 50. At that time, the analog signal includes distortion due to non-linearity of the coil and the like generated in demodulation by the low-pass filter 50. The analog signal also includes distortion due to the on-resistance of the power amplifier 40, for example. Therefore, the AD converter 10 according to Embodiment 1 is used to correct the distortion. Specifically, an analog signal including distortion is converted into a digital signal by the AD converter 10, and the distortion is corrected by feeding back the digital signal to the input of the digital amplifier. Since the AD converter 10 can perform AD conversion in a short time, it can feed back the AD converted digital signal corresponding to the recent high resolution audio (sampling frequency 768 kHz audio). FIG. 7 also shows a speaker 110 that is not a component of the audio signal amplifier 100. The speaker 110 converts the power of the analog audio signal output from the audio signal amplifier 100 into acoustic energy.

  The audio signal amplifier 100 includes an AD converter 10, a delta sigma modulation unit 20, a pulse width modulation unit 30, a power amplification unit 40, a low-pass filter 50, a sample hold circuit 60, and a second calculation unit 70.

  The delta sigma modulation unit 20 resamples the digital audio signal with a quantization number smaller than the quantization number of the digital audio signal. Specifically, the delta sigma modulation unit 20 includes an oversampling filter and a noise shaper. First, the oversampling filter converts the sampling frequency of the input audio signal to a power of 2 and removes the aliasing component from the signal. Next, the noise shaper requantizes the oversampled audio signal with a smaller quantization number than the input audio signal. The noise shaper reduces the requantization noise generated when requantization is performed at, for example, an audio band of 20 kHz or less.

  The pulse width modulation unit 30 converts the signal output from the delta sigma modulation unit 20 into a pulse width modulation signal (PWM signal) having the gradation of the amplitude level of the signal as the gradation of the pulse width.

  The power amplifier 40 is a circuit that amplifies the signal output from the pulse width modulator 30. The power amplifier 40 includes a push-pull circuit, for example. The push-pull circuit is an amplifier circuit having two switching transistors, for example, and is a half-bridge circuit. Each switching transistor is, for example, an n-type MOSFET. The switching transistor may be a combination of an n-type MOSFET and a p-type MOSFET.

  The low-pass filter 50 is a filter that demodulates the signal amplified by the power amplifier 40 into an analog audio signal, and reduces and outputs a component higher than a predetermined cutoff frequency in the signal output from the power amplifier 40. The low pass filter 50 includes an inductor and a capacitor in order to reduce power loss.

  The sample hold circuit 60 is a circuit that holds the voltage of the analog audio signal output from the low pass filter 50. Thereby, the analog audio signal input to the AD converter 10 is held, and the AD converter 10 can perform AD conversion.

  The AD converter 10 converts the voltage held by the sample hold circuit 60 as an input voltage into a digital value in a short time.

  When the digital audio signal is larger than the digital value obtained by AD-converting the voltage held by the AD converter 10 in the sample hold circuit 60, the second arithmetic unit 70 calculates a value obtained by subtracting the digital value from the digital audio signal. The signal is added to the signal and output to the delta-sigma modulation unit 20. That is, when the analog audio signal is reduced due to distortion generated in the analog audio signal output from the low-pass filter 50, the distortion can be corrected by feeding back the reduced analog audio signal. Specifically, if an amount that the analog audio signal becomes smaller due to distortion (difference between the digital audio signal and the AD converted digital value) is added to the digital audio signal input to the delta-sigma modulation unit 20, Distortion can be corrected.

  When the digital audio signal is smaller than the digital value obtained by AD converting the voltage held by the sample hold circuit 60 by the AD converter 10, the second arithmetic unit 70 obtains a value obtained by subtracting the digital audio signal from the digital value. Subtract from the signal and output to the delta-sigma modulator 20. That is, when the analog audio signal is increased due to distortion generated in the analog audio signal output from the low-pass filter 50, the distortion can be corrected by feeding back the increased analog audio signal. Specifically, by subtracting from the digital audio signal input to the delta-sigma modulation unit 20 an amount by which the analog audio signal increases due to distortion (the difference between the digital value obtained by AD conversion and the digital audio signal), Distortion can be corrected.

  Thus, in this embodiment, the audio signal amplifier 100 includes the delta sigma modulation unit 20 that resamples the digital audio signal with a quantization number smaller than the quantization number of the digital audio signal, and the delta sigma modulation unit 20. And a pulse width modulation unit 30 that converts the signal output from the signal into a pulse width modulation signal having the gradation of the amplitude level of the signal as the gradation of the pulse width. The audio signal amplifier 100 also includes a power amplifying unit 40 that amplifies the signal output from the pulse width modulation unit 30 and a low-pass that reduces and outputs a component higher than a predetermined cutoff frequency in the signal output from the power amplifying unit 40. And a filter 50. The audio signal amplifier 100 includes a sample hold circuit 60 that holds the voltage of the signal output from the low-pass filter 50, an AD converter 10 that converts the voltage held by the sample hold circuit 60 as an input voltage into a digital value, and an AD converter. 10 includes a second calculation unit 70 that calculates the difference between the digital value output from the digital audio signal 10 and the digital audio signal. When the digital audio signal is larger than the digital value converted by the AD converter 10, the second arithmetic unit 70 adds a value obtained by subtracting the digital value from the digital audio signal to the digital audio signal to add the delta sigma modulation unit 20. Output to. Further, when the digital audio signal is smaller than the digital value converted by the AD converter 10, the second arithmetic unit 70 subtracts a value obtained by subtracting the digital audio signal from the digital value from the digital audio signal to perform delta-sigma modulation. To the unit 20.

  As a result, the analog audio signal output from the low-pass filter 50 is converted into a digital signal by the AD converter 10 in a short time, and the increase or decrease in the signal due to distortion is added to or subtracted from the digital audio signal input to the audio signal amplifier 100. Therefore, distortion generated by the power amplifying unit 40 and the low-pass filter 50 can be corrected.

(Other embodiments)
As described above, the embodiments have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can be applied to embodiments in which changes, replacements, additions, omissions, and the like are appropriately performed. Moreover, it is also possible to combine each component demonstrated in the said embodiment and it can also be set as a new embodiment.

  Then, the following other embodiment is illustrated.

  In the above embodiment, the first arithmetic unit 13 determines at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the rising or falling timing of the reference clock in the rising period of the triangular wave signal. Although the process of updating one is described, the present invention is not limited to this. For example, the first calculation unit 13 updates at least one of the first digital value and the second digital value according to the comparison result of the comparator 12 at the rising or falling timing of the reference clock in the falling period of the triangular wave signal. Processing may be performed.

  In the above embodiment, an example is described in which an input voltage is input to the plus input terminal of the comparator 12 and a triangular wave signal is input to the minus input terminal. However, the present invention is not limited to this. For example, a triangular wave signal may be input to the positive input terminal of the comparator 12 and an input voltage may be input to the negative input terminal.

  Moreover, in the said embodiment, when the control part 14 determines that the 1st calculating part 13 performed the process of updating at least one of a 1st digital value and a 2nd digital value for the predetermined number of times, a 1st calculating part 13 describes that the input voltage is converted into a digital value between the first digital value and the second digital value after the update process has been performed a predetermined number of times. However, the present invention is not limited to this. For example, when the difference between the first digital value and the second digital value becomes a predetermined difference, the first calculation unit 13 changes the input voltage to a digital value between the first digital value and the second digital value. It may be converted to a value.

  Further, in the second embodiment, the second arithmetic unit 70 has a function of correcting the amplitude and phase characteristics of the analog signal output from the low-pass filter 50, and a data that is input to the digital audio signal and output to the delta-sigma modulation unit 20 And a function of correcting a delay with respect to data input from the AD converter 10, and may have different phase characteristics and amplitude characteristics depending on the frequency when calculating an error.

  In addition, the present disclosure can be realized not only as the AD converter 10 but also as a method including steps (processing) performed by the control unit 14 configuring the AD converter 10.

  For example, these steps may be performed by a computer (computer system). The present disclosure can be realized as a program for causing a computer to execute the steps included in these methods. Furthermore, the present disclosure can be realized as a non-transitory computer-readable recording medium such as a CD-ROM or the like on which the program is recorded.

  For example, when the present disclosure is realized by a program (software), each step is executed by executing the program using hardware resources such as a computer CPU, a memory, and an input / output circuit. . That is, each step is executed by the CPU obtaining data from a memory or an input / output circuit or the like, and outputting the calculation result to the memory or the input / output circuit.

  Further, the control unit 14 included in the AD converter 10 according to the above embodiment may be realized as an LSI (Large Scale Integration) which is an integrated circuit (IC: Integrated Circuit).

  The integrated circuit is not limited to an LSI, and may be realized by a dedicated circuit or a general-purpose processor. A programmable programmable gate array (FPGA) or a reconfigurable processor in which connection and setting of circuit cells inside the LSI can be reconfigured may be used.

  Further, if an integrated circuit technology that replaces LSI appears due to the advancement of semiconductor technology or another derivative technology, naturally, the integrated circuit of the control unit 14 included in the AD converter 10 is performed using that technology. Also good.

  As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

  Accordingly, the constituent elements described in the accompanying drawings and the detailed description may include not only constituent elements essential for solving the problem but also constituent elements not essential for solving the problem. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

  Moreover, since the above-mentioned embodiment is for demonstrating the technique in this indication, a various change, substitution, addition, abbreviation, etc. can be performed in a claim or its equivalent range.

  The present disclosure is applicable to an AD converter that is required to perform AD conversion in a short time. Specifically, the present disclosure is applicable to a device that reproduces sound such as an audio device, a television, and a portable device.

DESCRIPTION OF SYMBOLS 10 AD converter 11 Triangular wave production | generation part 11a Multibit DA converter 11b Integrator 12 Comparator 13 1st calculating part 14 Control part 15 Frequency dividing circuit 20 Delta-sigma modulation part 30 Pulse width modulation part 40 Power amplification part 50 Low pass filter 60 Sample hold circuit 70 Second operation unit 100 Audio signal amplifier 110 Speaker 201 to 203, 301 to 312 points

Claims (5)

A triangular wave generating unit that generates a triangular wave signal that rises to a voltage corresponding to the first digital value and falls to a voltage corresponding to a second digital value that is smaller than the first digital value by a clock obtained by dividing the reference clock;
A comparator that compares the triangular wave signal generated by the triangular wave generation unit with an input voltage that is input;
The first digital value and the first digital value and the second digital value are reduced so that a difference between the first digital value and the second digital value is reduced according to a comparison result of the comparator at a timing of rising or falling of the reference clock at least once. A first arithmetic unit that performs a process of updating at least one of the second digital values,
The first operation unit converts the input voltage into a digital value between the first digital value and the second digital value after performing the process of updating the input voltage. AD converter. And a controller that determines whether or not the first calculation unit has performed the updating process a predetermined number of times.
When the control unit determines that the first calculation unit has not performed the update process a predetermined number of times, the triangular wave generation unit is configured to output the first digital value and the second digital value after the update process. The triangular wave signal is regenerated according to a value, and the first calculation unit updates at least one of the first digital value and the second digital value according to a comparison result of the comparator at the timing. Do it again,
When the control unit determines that the first calculation unit has performed the update process a predetermined number of times, the first calculation unit has performed the update process for the input voltage a predetermined number of times. The AD converter according to claim 1, wherein the AD converter converts the digital value between the first digital value and the second digital value later. When the first calculation unit performs the update process according to the comparison result of the comparator at one timing,
The first calculation unit includes:
If the voltage of the triangular wave signal at the timing is greater than the input voltage, the first digital value is updated to a value corresponding to the voltage of the triangular wave signal at the timing,
The AD converter according to claim 1 or 2, wherein when the voltage of the triangular wave signal at the timing is smaller than the input voltage, the second digital value is updated to a value corresponding to the voltage of the triangular wave signal at the timing. When the first arithmetic unit performs the update process according to the comparison result of the comparator at the timing multiple times,
The first calculation unit includes:
When the timing at which the voltage of the triangular wave signal is greater than the input voltage is once, the first digital value is updated to a value corresponding to the voltage of the triangular wave signal at the one timing.
When the timing at which the voltage of the triangular wave signal becomes larger than the input voltage is multiple times, the first digital value is updated to the smallest value among the values corresponding to the voltage of the triangular wave signal at the multiple times of the timing. And
When the timing at which the voltage of the triangular wave signal becomes smaller than the input voltage is once, the second digital value is updated to a value corresponding to the voltage of the triangular wave signal at the one timing.
When the timing at which the voltage of the triangular wave signal becomes smaller than the input voltage is multiple times, the second digital value is updated to the largest value among the values corresponding to the voltage of the triangular wave signal at the multiple times of the timing. The AD converter according to claim 1 or 2. A delta-sigma modulator that resamples the digital audio signal with a quantization number smaller than the quantization number of the digital audio signal;
A pulse width modulation unit that converts a signal output from the delta-sigma modulation unit into a pulse width modulation signal having a gradation of an amplitude level of the signal as a gradation of a pulse width;
A power amplifying unit for amplifying a signal output from the pulse width modulation unit;
A low-pass filter that reduces and outputs a component higher than a predetermined cutoff frequency among the signals output by the power amplification unit;
A sample-and-hold circuit that holds the voltage of the signal output by the low-pass filter;
The AD converter according to any one of claims 1 to 4, which converts the voltage held by the sample hold circuit as the input voltage into the digital value;
A second calculator that calculates a difference between the digital value output from the AD converter and the digital audio signal;
The second calculation unit includes:
When the digital audio signal is larger than the digital value, a value obtained by subtracting the digital value from the digital audio signal is added to the digital audio signal and output to the delta-sigma modulation unit,
An audio signal amplifier that, when the digital audio signal is smaller than the digital value, subtracts a value obtained by subtracting the digital audio signal from the digital value from the digital audio signal and outputs the result to the delta-sigma modulation unit.

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