JP2016063388A - Digital/analog converter, and correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the error correction accuracy of a D/A converter.SOLUTION: A D/A converter 1 comprises: a D/A conversion part 20; an acquisition part 101 operable to acquire a digital signal; and a signal conversion part 102 operable to convert the digital signal acquired by the acquisition part 101 into a correction digital signal of a value based on a conversion error in the D/A conversion part 20, which has a cycle equal to or smaller than a cycle of the digital signal. The D/A conversion part 20 converts the correction digital signal into an analog signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a digital / analog conversion device that converts a digital signal into an analog signal, and a correction circuit that corrects a conversion error in the digital / analog conversion device.

  In a digital / analog converter (hereinafter referred to as a D / A converter), it is known that an error occurs when a digital signal is converted into an analog signal. Patent Document 1 outputs an analog signal as designed for an input digital signal due to the influence of variations in the characteristics of the resistors constituting the ladder circuit (R-2R ladder resistor network) of the D / A converter. The problem of not being pointed out is pointed out. In Patent Document 1, a correction signal for correcting an error is generated, and the correction signal is input to the D / A converter as a part of a plurality of bits constituting the digital signal input to the D / A converter. A circuit for correcting the value of an analog signal output from a D / A converter is disclosed.

JP 2000-151403 A

  In a conventional circuit, in order to reduce an error in converting an n-bit (n is an integer of 2 or more) digital signal into an analog signal, an (n + m) -bit D / A converter is configured, and an m-bit ( It is necessary to input a correction signal (m is a positive integer) to the D / A converter. Since the m-bit correction signal is also converted into an analog signal by the D / A converter, there is a problem that the error cannot be corrected if there is an error in the circuit that converts the correction signal into the analog signal.

  Further, when the correction signal is arranged in the lower bits of the D / A converter, a large error in the upper bits cannot be corrected. When the correction signal is arranged in the upper bits of the D / A converter, a small error in the lower bits There was also a problem that it could not be corrected.

  Accordingly, the present invention has been made in view of these points, and an object thereof is to improve the correction accuracy of conversion errors in a D / A converter.

  In the first aspect of the present invention, the digital / analog conversion means, the acquisition means for acquiring a digital signal, and the digital signal acquired by the acquisition means has a period equal to or less than the period of the digital signal. Conversion means for converting into a correction digital signal having a value based on a conversion error in the analog conversion means, wherein the digital / analog conversion means converts the correction digital signal into an analog signal. Providing equipment. The period of the digital signal is, for example, an integral multiple of the period of the corrected digital signal.

  The digital / analog conversion device described above is a smoothing that passes a frequency equal to or lower than a half of the frequency corresponding to the reciprocal of the period of the correction digital signal among the analog signals output by the digital / analog conversion means. You may further have a means.

  The conversion unit may include a storage unit that stores the value of the digital signal and the value of the correction digital signal corresponding to the conversion error in association with each other.

  In addition, the conversion unit includes a storage unit that stores the digital signal value and the conversion error value in association with each other, and the storage unit outputs the value according to the value of the signal input to the storage unit. And adding means for adding a signal based on the value of the conversion error to the digital signal and inputting the addition result to the digital / analog conversion means and the storage means.

  The digital / analog conversion device may further include error detection means for detecting the conversion error of the digital / analog conversion means.

  According to a second aspect of the present invention, there is provided a correction circuit for correcting a conversion error in the digital / analog conversion means, wherein an acquisition means for acquiring a digital signal and the digital signal acquired by the acquisition means are converted into the digital signal. There is provided a correction circuit comprising: a conversion unit having a period equal to or less than the period of the signal, and converting the signal into a correction digital signal having a value based on a conversion error in the digital / analog conversion unit.

  According to the present invention, it is possible to improve the correction accuracy of the conversion error in the D / A converter.

1 shows a configuration of a D / A converter 1 according to a first embodiment. 3 is an example of a table stored in a storage unit 103. The relationship between the digital signal value, the corrected digital signal value, and the analog signal voltage is shown. The voltage waveform of the analog signal when not corrected and the voltage waveform of the analog signal when corrected are shown. An output waveform from the D / A conversion unit 20 and an output waveform (example) from the filter unit 30 are shown. An output waveform from the D / A conversion unit 20 and an output waveform from the filter unit 30 (comparative example) are shown. The structure of the D / A converter 2 which concerns on 2nd Embodiment is shown. 4 is an example of a table stored in a storage unit 113. It is a figure which shows the structure of the calculating part. The structure of the D / A converter 3 which concerns on 3rd Embodiment is shown.

<First Embodiment>
FIG. 1 is a diagram illustrating a configuration of a D / A converter 1 according to the first embodiment. The D / A converter 1 includes a correction unit 10, a D / A conversion unit 20, and a filter unit 30. The correction unit 10 includes a circuit that corrects a conversion error in the D / A conversion unit 20.

  The correction unit 10 is configured by, for example, a digital signal processing processor (DSP). The correction unit 10 corrects the digital signal by converting the digital signal input to the D / A converter 1 into a correction digital signal having a period equal to or less than the period of the digital signal. The corrected digital signal changes to a plurality of values at a period equal to or less than the period of the digital signal. The value of the correction digital signal is a value determined based on the conversion error in the D / A conversion unit 20. Details of the configuration and operation of the correction unit 10 will be described later.

  The D / A converter 20 is a ladder type D / A converter circuit configured by, for example, an R-2R ladder resistor network. The D / A converter 20 converts a digital signal that is a discrete voltage corresponding to a logical value into an analog signal that is a voltage having a value larger than a voltage that the digital signal can take. For example, the D / A converter 20 converts an 8-bit width digital signal that changes to either 0V or 5V at a predetermined timing to any one of 256 different voltages between 0V and 5V. Convert to analog signal that changes to voltage.

  The filter unit 30 is a low-pass filter that removes high-frequency components contained in the analog signal output from the D / A conversion unit 20. The filter unit 30 passes a frequency equal to or lower than the frequency determined based on the frequency corresponding to the reciprocal of the period of the correction digital signal, among the analog signals output from the D / A conversion unit 20. Specifically, the filter unit 30 multiplies the frequency corresponding to the reciprocal of the period of the corrected digital signal by a ratio of the period of the corrected digital signal to the period of the digital signal, which is half or less of the frequency obtained. Let the frequency pass. For example, when the period of the digital signal is equal to or greater than twice the period of the corrected digital signal, the filter unit 30 passes a frequency equal to or lower than a quarter of the frequency corresponding to the reciprocal of the period of the corrected digital signal. When the period of the digital signal is equal to the period of the correction digital signal, the filter unit 30 passes a frequency equal to or lower than a half of the frequency corresponding to the reciprocal of the period of the correction digital signal.

  Since the filter unit 30 has such characteristics, the filter unit 30 removes the high-frequency component included in the corrected digital signal included in the analog signal output from the D / A conversion unit 20, and the D / A low frequency band analog signal which is a generation source of the digital signal input to the A converter 1 can be passed. Since the D / A converter 1 includes such a filter unit 30, the analog signal output from the D / A converter 20 is a high-frequency component associated with the digital signal converted into the corrected digital signal by the correction unit 10. Is removed and smoothed, and the filter unit 30 outputs an analog signal from which the conversion error in the D / A conversion unit 20 is removed.

Hereinafter, the configuration and operation of the correction unit 10 will be described in detail.
The correction unit 10 includes an acquisition unit 101, a signal conversion unit 102, and a storage unit 103. The acquisition unit 101 acquires a digital signal input from the outside. The digital signal is a signal composed of n bits (n is an integer of 1 or more), and has 2 ⁿ gradations. When n = 8, the value of the digital signal is an integer value of 0 or more and 255 or less.

  The digital signal is a signal generated by, for example, sampling an audio signal at a predetermined sampling frequency f. In this case, the period T of the digital signal is T = 1 / f. The digital signal is a signal whose value can change every period T. The acquisition unit 101 may acquire a digital signal obtained by oversampling a digital signal having a period T generated by sampling the audio signal at the sampling frequency f at a frequency higher than the sampling frequency f. Good. In this specification, a plurality of digital signals generated by oversampling a digital signal obtained by sampling an audio signal are treated as digital signals having a period T in this specification.

  The signal conversion unit 102 converts the digital signal acquired by the acquisition unit 101 into a corrected digital signal having a period equal to or less than the period T of the digital signal. Specifically, the signal conversion unit 102 generates a plurality of corrected digital signals having a predetermined value corresponding to the value of the digital signal based on the conversion error of the D / A conversion unit 20. For example, the signal conversion unit 102 refers to a table that is stored in the storage unit 103 and associates digital signal values with a plurality of corrected digital signal values corresponding to conversion errors in the D / A conversion unit 20. Thus, a plurality of corrected digital signals are generated for one digital signal.

  The signal conversion unit 102 converts, for example, an n-bit digital signal having a period T into m corrected digital signals having an n-bit period T / m (m is an integer). The period T of the digital signal is m times the corrected digital signal. The frequency of the main lobe in the frequency spectrum obtained by Fourier transforming the corrected digital signal is m times the frequency of the main lobe in the frequency spectrum obtained by Fourier transforming the digital signal.

  FIG. 2 is an example of a table stored in the storage unit 103 configured by a nonvolatile memory such as a flash memory. In the table shown in FIG. 2, four corrected digital signal values are associated with one digital signal value. For example, the storage unit 103 sequentially outputs four correction digital signals having values corresponding to the values of the input digital signals each time a read signal is input. The signal conversion unit 102 writes the value of the digital signal in the storage unit 103 and inputs a read signal to the storage unit 103 at every cycle T / m, so that the value of the digital signal in one digital signal cycle. Four correction digital signals having the same or different values are generated. The correction digital signal stored in the storage unit 103 measures, for example, the conversion error of the D / A conversion unit 20 in advance, and the average value of a plurality of correction digital signals subtracts the conversion error from the value of the digital signal. It was obtained by adjusting the value so as to be the value obtained.

  FIG. 3 is a diagram illustrating the relationship between the digital signal value, the corrected digital signal value, and the analog signal voltage. The horizontal axis in FIG. 3 indicates time, and t1, t2, t3,..., T8 correspond to the timing at which the acquisition unit 101 acquires a digital signal. For example, the time t2-t1 corresponds to the period T of the digital signal. The vertical axis in FIG. 3 indicates the value of the digital signal, the value of the correction digital signal, and the voltage of the analog signal. 3 (a) and 3 (b) do not show the waveforms of the digital signal and the corrected digital signal, but how the values of the digital signal composed of n bits and the corrected digital signal change. Show.

  FIG. 3A shows how the value of the digital signal acquired by the acquisition unit 101 changes, and it can be seen that the value changes every period T. FIG. 3B shows how the value of the corrected digital signal generated by the signal conversion unit 102 changes. The value of the correction digital signal can take up to four values during the period T. That is, the period of the correction digital signal shown in FIG. 3B is T / 4. The signal conversion unit 102 refers to the storage unit 103, and converts the digital signal shown in FIG. 3A to the corrected digital signal shown in FIG. 3B at a time interval corresponding to the period T of the digital signal. Convert to

  The broken line in FIG. 3C is the waveform of the analog signal output from the D / A converter 20, and corresponds to the corrected digital signal shown in FIG. The solid line in FIG. 3C shows the waveform of the analog signal generated based on the corrected digital signal indicated by the broken line. The analog signal is a signal obtained after the analog signal output from the D / A converter 20 to which the correction digital signal is input passes through the filter unit 30.

  The filter unit 30 passes a frequency component lower than the cutoff frequency determined based on the period of the digital signal among the frequency components included in the analog signal output by the D / A conversion unit 20, and has a frequency equal to or higher than the cutoff frequency. Block the passage of ingredients. The cut-off frequency of the filter unit 30 is equal to or less than half the frequency corresponding to the reciprocal of the period of the digital signal. For example, when the sampling frequency of the digital signal is set to a frequency that is twice or more the upper limit frequency of the frequency band of the audio signal that is the digital signal generation source, the cutoff frequency of the filter unit 30 is the digital signal generation frequency. The signal in the frequency band of the audio signal that is the source can be passed, and other signals are blocked from passing.

  By doing so, at the time when the D / A conversion unit 20 outputs, the value of the analog signal that has changed every cycle T / 4 as shown by the broken line in FIG. 3C is smoothed. The At this time, the value of the analog signal after smoothing is a value obtained by correcting the analog signal obtained by converting the digital signal as it is by the D / A conversion unit 20 by an amount corresponding to the conversion error. It has become.

  FIG. 4 is a diagram illustrating a voltage waveform of the analog signal when the conversion error of the D / A conversion unit 20 is not corrected and a voltage waveform of the analog signal when corrected. A broken line in FIG. 4A is a voltage waveform of an analog signal output from the D / A converter 20 when the digital signal is input to the D / A converter 20 without being corrected. The solid line in FIG. 4A is a voltage waveform of the signal after the analog signal output from the D / A conversion unit 20 is smoothed by the filter unit 30.

  A broken line in FIG. 4B is a voltage waveform of an analog signal output from the D / A converter 20 when the corrected digital signal is input to the D / A converter 20. The solid line in FIG. 4B is a voltage waveform of the signal after the analog signal output from the D / A conversion unit 20 is smoothed by the filter unit 30. FIG. 4C is a diagram in which the voltage waveform of the analog signal shown in FIG. 4A and the voltage waveform of the analog signal shown in FIG.

  The broken line in FIG. 4 (c) shows the voltage waveform of the analog signal before correction shown in FIG. 4 (a), and the solid line shows the voltage waveform of the analog signal after correction shown in FIG. 4 (b). Show. According to FIG. 4C, it can be seen that there is a difference between the voltage waveform when the conversion error of the D / A conversion unit 20 is corrected and the voltage waveform when the conversion error is corrected. For digital signal values that need to be corrected for conversion errors, the average value of a plurality of corrected digital signals included in one period of the digital signal is different from the digital signal value. Therefore, the D / A converter 1 can correct the analog signal by a magnitude corresponding to the conversion error by smoothing the analog signal output from the D / A converter 20 by the filter unit 30.

  In the above description, the example in which the signal conversion unit 102 converts the n-bit width digital signal into the n-bit width correction digital signal has been described. However, the signal conversion unit 102 converts the correction digital signal to a signal other than n bits. It can be any bit width. The signal conversion unit 102 preferably makes the bit width of the corrected digital signal larger than n bits. For example, the signal conversion unit 102 sets the bit width of the corrected digital signal to (n + 1) bits. By doing so, the signal conversion unit 102 sets the value of the analog signal output from the D / A conversion unit 20 when the digital signal has the maximum value (for example, “11111111”) to a value corresponding to “11111111”. It can correct | amend so that it may become a bigger value.

<Example>
FIG. 5 is a diagram illustrating a voltage waveform of an output signal from the D / A conversion unit 20 (hereinafter referred to as an output waveform) and an output waveform from the filter unit 30 when the present embodiment is implemented. The upper stage is an output waveform from the filter unit 30, and the lower stage is an output waveform from the D / A conversion unit 20. These output waveforms are observed with an oscilloscope. The output waveform from the D / A converter 20 has a high-frequency signal corresponding to the corrected digital signal superimposed on a sine wave having a peak-to-peak voltage of about 1.7 V and a frequency of 1.0 kHz. In this embodiment, the period of the digital signal is about 20.8 μsec (sampling frequency 48 KHz), and the period of the correction digital signal is about 2.6 μsec (frequency 384 KHz).

  Since the filter unit 30 in this embodiment has an amplifier circuit, the output waveform from the filter unit 30 has a peak-to-peak voltage of about 6V. It can be seen that the output waveform from the filter unit 30 does not have a waveform corresponding to the correction digital signal included in the output waveform from the D / A conversion unit 20, and is a smooth waveform.

<Comparative example>
FIG. 6 is a diagram illustrating an output waveform from the D / A conversion unit 20 and an output waveform from the filter unit 30 when the correction digital signal is not used. The voltage and frequency of the output waveform from the D / A converter 20 and the output waveform from the filter unit 30 are the same as those shown in FIG.

  The high-frequency signal corresponding to the corrected digital signal is not superimposed on the output waveform from the D / A converter 20 shown in FIG. When the output waveform from the filter unit 30 shown in FIG. 6 is compared with the output waveform from the filter unit 30 shown in FIG. 5, distortion that is not seen in FIG. 5 is observed in FIG. Thus, according to the present embodiment, it was confirmed that the conversion error in the D / A conversion unit 20 can be corrected by superimposing the correction digital signal and removing the high frequency component by the filter unit 30.

[Effect in the first embodiment]
As described above, the D / A converter 1 according to the first embodiment corrects an input digital signal with a value based on a conversion error in the D / A conversion unit 20 having a period equal to or less than the period of the digital signal. Convert to signal. Then, after the D / A conversion unit 20 converts the corrected digital signal into an analog signal, the filter unit 30 removes the high-frequency component added by the corrected digital signal. By doing so, the D / A converter 1 can improve the correction accuracy of the conversion error of the D / A converter 20.

<Second Embodiment>
FIG. 7 is a diagram illustrating a configuration of the D / A converter 2 according to the second embodiment. The D / A converter 2 includes a correction unit 11 instead of the correction unit 10 in the D / A converter 1 according to the first embodiment shown in FIG. The correction unit 11 includes an acquisition unit 111, a switch 112, a storage unit 113, a calculation unit 114, and an adder 115.

  The acquisition unit 111 has a function equivalent to that of the acquisition unit 101 and acquires a digital signal from the outside.

  Whether the switch 112 causes the digital signal output from the acquisition unit 111 to be input to the storage unit 113 or the correction digital signal output from the adder 115 to be input to the storage unit 113 based on a control signal input from the outside. Switch. Specifically, the switch 112 switches to the A side in FIG. 7 for the time of one period of the corrected digital signal after the new period of the digital signal, and the digital signal acquired by the acquisition unit 111 is stored in the storage unit 113. Let them enter. Thereafter, the connection is switched to the B side, and the corrected digital signal output from the adder 115 is input to the storage unit 113.

  The storage unit 113 stores the value of the digital signal and the value of the conversion error in the D / A conversion unit 20 in association with each other. FIG. 8 is an example of a table stored in the storage unit 113. The storage unit 113 outputs a conversion error value corresponding to the value of the signal input via the switch 112.

  The arithmetic unit 114 performs digital signal processing on the signal corresponding to the conversion error output from the storage unit 113, and outputs a signal generated by multiply-adding the input signal. The calculation unit 114 outputs the calculated signal to the adder 115 in synchronization with a clock having a cycle T / m (m is an integer) equal to or less than the cycle T of the digital signal.

  FIG. 9 is a diagram illustrating a configuration of the calculation unit 114. The arithmetic unit 114 includes a plurality of delay circuits 121 (121a, 121b), a plurality of coefficient multiplication circuits 122 (122a, 122b), and an adder circuit 123. The digital signal input to the arithmetic unit 114 is delayed by the period T / m by the delay circuit 121a, and then multiplied by the coefficient a0 in the coefficient multiplier circuit 122a. The signal delayed by the delay circuit 121a is input to the delay circuit 121b, further delayed by a period T / m in the delay circuit 121b, and then multiplied by the coefficient a1 in the coefficient multiplier circuit 122b. The adder circuit 123 adds the data after multiplication in the coefficient multiplication circuit 122a and the data after multiplication in the coefficient multiplication circuit 122b, and outputs the result. Note that although the calculation unit 114 in FIG. 9 has two delay circuits 121, the calculation unit 114 may have more delay circuits 121.

  The adder 115 is a signal based on the value of the conversion error output from the storage unit 113 according to the value of the signal input to the storage unit 113 (for example, the calculation unit 114 calculates the value based on the value of the conversion error. Signal) is added to the digital signal acquired by the acquisition unit 111 to generate a corrected digital signal. The adder 115 inputs the corrected digital signal as a result of the addition to the D / A conversion unit 20 and the storage unit 113. Since the calculation unit 114 outputs a different value for each cycle T / m, the adder 115 outputs a corrected digital signal having a cycle T / m, as in the first embodiment.

  In the above description, a case has been described in which the switch 112 is switched to the A side for the time corresponding to one cycle of the corrected digital signal after the new cycle of the digital signal. However, even if the switch 112 is fixed to the B side. Good. That is, although the example where the correction unit 11 includes the switch 112 has been described, the correction unit 11 may not include the switch 112. Even in such a configuration, the correction digital signal output from the adder 115 is input to the storage unit 113, whereby the conversion error of the D / A conversion unit 20 can be corrected.

[Effects of Second Embodiment]
The D / A converter 2 according to the second embodiment generates a corrected digital signal by adding a signal having a value corresponding to the conversion error to the digital signal in the adder 115. Then, the generated correction digital signal is fed back to change the value input to the adder 115 in the next cycle. By doing so, the D / A converter 2 does not need to store a plurality of correction digital signal values for one value of the digital signal, and thus the D / A converter according to the first embodiment. The capacity of the storage unit 113 can be made smaller than that of the storage unit 103 in the A converter 1.

<Third Embodiment>
In the first embodiment, the conversion error of the D / A conversion unit 20 is known, and the signal conversion unit 102 performs digital conversion based on the table stored in the storage unit 103 in order to correct the conversion error. The signal was converted to a corrected digital signal. On the other hand, in the third embodiment, the conversion error of the D / A converter 20 is not known, and the signal converter 102 converts the digital signal into an optimal corrected digital signal according to the conversion error. This is different from the first embodiment.

  FIG. 10 is a diagram illustrating a configuration of the D / A converter 3 according to the third embodiment. The D / A converter 3 differs from the D / A converter 1 according to the first embodiment shown in FIG. 1 in that it further includes an error detection unit 40, and is the same in other points. The error detection unit 40 detects a conversion error of the D / A conversion unit 20 in the calibration mode. Specifically, the error detection unit 40 calculates the value of the correction digital signal for each value of the digital signal based on the conversion error detected while the calibration signal is input to the D / A converter 3. Write to the storage unit 103. For example, the error detection unit 40 calculates values of a plurality of correction digital signals in which an average value of the plurality of correction digital signals is a value obtained by subtracting a conversion error from the value of the digital signal.

When an n-bit digital signal can be input to the D / A converter 3, a digital signal that sequentially changes to any one of ²ⁿ values can be used as the calibration signal. The error detection unit 40 includes, for example, a memory that holds a value of an analog signal output from an ideal D / A converter when a calibration signal having a predetermined value is input. The error detection unit 40 uses the analog signal value output from the D / A conversion unit 20 in a state where a predetermined calibration signal is input as the analog signal value output from the ideal D / A converter. By comparing, the conversion error of the D / A converter 20 is detected. In the calibration mode, the signal conversion unit 102 outputs the digital signal as it is to the D / A conversion unit 20 without converting the digital signal into a corrected digital signal.

[Effect in the third embodiment]
As described above, the D / A converter 3 according to the third embodiment can detect the conversion error of the D / A converter 20. Therefore, the D / A converter 3 also converts the D / A conversion unit 20 even when the resistance value of the resistor of the D / A conversion unit 20 changes due to aging. Since a correction digital signal corresponding to the error can be generated, the conversion error of the D / A converter 20 can be corrected with higher accuracy.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  For example, in the above embodiment, the D / A conversion unit 20 has been described as a ladder type D / A conversion circuit configured by an R-2R ladder resistor network, but the D / A conversion unit 20 An arbitrary circuit configuration may be provided. In the above embodiment, the case where the number of bits of the corrected digital signal is equal to the number of bits of the digital signal has been described. However, the number of bits of the corrected digital signal may be different from the number of bits of the digital signal.

  In the above-described embodiment, the correction unit 10 and the correction unit 11 convert one digital signal into a plurality of correction digital signals. However, the present invention is not limited to this. For example, the correction unit 10 and the correction unit 11 convert one digital signal into one correction digital signal having a value different from the value of the digital signal based on the conversion error of the D / A conversion unit 20. May be.

  In addition, when a digital signal having a sampling frequency higher than necessary with respect to the frequency band of the analog signal that the filter unit 30 passes is input to the D / A converters 1, 2, and 3, the digital signal is input to the acquisition unit 101. The sampling frequency of the digital signal is considered to be about twice the frequency band of the analog signal that the filter unit 30 passes. That is, the period of the digital signal input to the acquisition unit 101 is 1 / (2fc) when the cutoff frequency of the filter unit 30 is fc.

  For example, when the cutoff frequency of the filter unit 30 is 20 kHz, a digital signal having a sampling frequency of 200 kHz is input to the D / A converters 1, 2, and 3 even though the sampling frequency of the digital signal is 40 kHz. It is possible. In this case, since five digital signals are converted into one corrected digital signal, the sampling frequency of the digital signal acquired by the acquisition unit 101 is considered to be 40 kHz, and the period of the digital signal is 1 / (40 kHz ) = 0.025 ms. And the correction | amendment part 10 produces | generates the correction | amendment digital signal of a period of 0.025 ms or less based on the said digital signal.

  In the above embodiment, the case where the periods of the respective correction digital signals are the same has been described. However, the periods of the respective correction digital signals may be different. The signal converter 102 may convert the digital signal into a corrected digital signal having a value and a period corresponding to the conversion error.

  In the above embodiment, the correction unit 10 has been described as correcting the conversion error in the D / A conversion unit 20, but the present invention is not limited to this. The correction unit 10 may generate a correction digital signal based on the digital signal, with an error obtained by adding the error in the filter unit 30 to the conversion error in the D / A conversion unit 20 as a conversion error.

1 D / A converter 2 D / A converter 3 D / A converter 10 Correction unit 20 D / A conversion unit 30 Filter unit 40 Error detection unit 101 Acquisition unit 102 Signal conversion unit 103 Storage unit 111 Acquisition unit 112 Switch 113 Storage unit 114 Operation unit 115 Adder 121 Delay circuit 122 Coefficient multiplication circuit 123 Addition circuit

Claims (7)

Digital / analog conversion means;
An acquisition means for acquiring a digital signal;
Conversion means for converting the digital signal acquired by the acquisition means into a corrected digital signal of a value based on a conversion error in the digital / analog conversion means, having a period equal to or less than the period of the digital signal;
With
The digital / analog converting means converts the corrected digital signal into an analog signal. The period of the digital signal is an integral multiple of the period of the correction digital signal,
The digital / analog converter according to claim 1. The analog signal output from the digital / analog conversion means further includes a smoothing means for passing a frequency equal to or lower than a half of the frequency corresponding to the reciprocal of the period of the correction digital signal. ,
The digital / analog converter according to claim 2. The conversion means includes storage means for storing the value of the digital signal and the value of the correction digital signal corresponding to the conversion error in association with each other.
The digital / analog conversion device according to claim 1. The converting means includes
Storage means for storing the digital signal value and the conversion error value in association with each other;
A signal based on the value of the conversion error output according to the value of the signal input to the storage means is added from the storage means to the digital signal, and the addition result is the digital / analog conversion means and the storage. Adding means for inputting to the means;
It is characterized by having
The digital / analog conversion device according to claim 1. It further comprises error detection means for detecting the conversion error of the digital / analog conversion means,
The digital / analog conversion device according to claim 1. A correction circuit for correcting a conversion error in the digital / analog conversion means,
An acquisition means for acquiring a digital signal;
Conversion means for converting the digital signal acquired by the acquisition means into a corrected digital signal of a value based on a conversion error in the digital / analog conversion means, having a period equal to or less than the period of the digital signal;
A correction circuit comprising: