JP2017165646A5 - - Google Patents

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JP2017165646A5
JP2017165646A5 JP2017046201A JP2017046201A JP2017165646A5 JP 2017165646 A5 JP2017165646 A5 JP 2017165646A5 JP 2017046201 A JP2017046201 A JP 2017046201A JP 2017046201 A JP2017046201 A JP 2017046201A JP 2017165646 A5 JP2017165646 A5 JP 2017165646A5
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インジウム元素（Ｉｎ）、ガリウム元素（Ｇａ）及び錫元素（Ｓｎ）を、下記式（１）〜（３）の原子比で含む酸化物焼結体であって、亜鉛元素（Ｚｎ）の含有量が１００ｐｐｍ以下であり、内部において、粒径２μｍ以上のガリウム酸化物の凝集部分の数が１０個／８１００μｍ ２ 以下であり、酸化物半導体膜成膜用である酸化物焼結体。
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ （１）
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５ （２）
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ （３）
但し、前記酸化物焼結体が、下記式（Ｘ）、（Ｙ）及び（Ｚ）の原子比で含む場合を除く。
０．４０＜Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ （Ｘ）
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）＜０．３０ （Ｙ）
０．２０＜Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５０ （Ｚ） An oxide sintered body containing an indium element (In), a gallium element (Ga), and a tin element (Sn) at an atomic ratio of the following formulas (1) to (3), and the content of the zinc element (Zn) Is an oxide sintered body for forming an oxide semiconductor film, in which the number of aggregated portions of gallium oxide having a particle diameter of 2 μm or more is 10/8100 μm 2 or less .
0.10 ≦ In / (In + Ga + Sn) ≦ 0.60 (1)
0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55 (2)
0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.60 (3)
However, the case where the oxide sintered body includes an atomic ratio of the following formulas (X), (Y), and (Z) is excluded.
0.40 <In / (In + Ga + Sn) ≦ 0.60 (X)
0.10 ≦ Ga / (In + Ga + Sn) <0.30 (Y)
0.20 <Sn / (In + Ga + Sn) ≦ 0.50 (Z) 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項１に記載の酸化物焼結体。  The oxide sintered body according to claim 1, wherein the atomic ratio of In, Ga, and Sn satisfies the following formula.
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０  0.10 ≦ In / (In + Ga + Sn) ≦ 0.60
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５  0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．２０  0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.20 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項１に記載の酸化物焼結体。  The oxide sintered body according to claim 1, wherein the atomic ratio of In, Ga, and Sn satisfies the following formula.
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０  0.10 ≦ In / (In + Ga + Sn) ≦ 0.60
０．３０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５  0.30 ≦ Ga / (In + Ga + Sn) ≦ 0.55
０．２０＜Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．４０  0.20 <Sn / (In + Ga + Sn) ≦ 0.40 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項１に記載の酸化物焼結体。  The oxide sintered body according to claim 1, wherein the atomic ratio of In, Ga, and Sn satisfies the following formula.
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．４０  0.10 ≦ In / (In + Ga + Sn) ≦ 0.40
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）＜０．３０  0.10 ≦ Ga / (In + Ga + Sn) <0.30
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０  0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.60 インジウム元素（Ｉｎ）、ガリウム元素（Ｇａ）及び錫元素（Ｓｎ）を、下記式（１）〜（３）の原子比で含む酸化物焼結体であって、亜鉛元素（Ｚｎ）の含有量が１００ｐｐｍ以下であり、酸化物半導体膜成膜用である酸化物焼結体。  An oxide sintered body containing an indium element (In), a gallium element (Ga), and a tin element (Sn) at an atomic ratio of the following formulas (1) to (3), and the content of the zinc element (Zn) Is an oxide sintered body for forming an oxide semiconductor film.
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ （１）  0.10 ≦ In / (In + Ga + Sn) ≦ 0.60 (1)
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５ （２）  0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55 (2)
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．２０ （３）  0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.20 (3) 内部において、粒径２μｍ以上のガリウム酸化物の凝集部分の数が１０個／８１００μｍ  Inside, the number of aggregated portions of gallium oxide having a particle size of 2 μm or more is 10/8100 μm ２2 以下である請求項５に記載の酸化物焼結体。The oxide sintered body according to claim 5, wherein: 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式（５）を満たす請求項１，５及び６のいずれかに記載の酸化物焼結体。
０．３０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５ （５） The oxide sintered body according to any one of claims 1 , 5, and 6, wherein an atomic ratio of the In, Ga, and Sn satisfies the following formula (5) .
0.30 ≦ Ga / (In + Ga + Sn) ≦ 0.55 (5) 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式（７）を満たす請求項１，５及び６のいずれかに記載の酸化物焼結体。
０．３０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）＜０．６０ （７） The oxide sintered body according to any one of claims 1 , 5, and 6, wherein an atomic ratio of the In, Ga, and Sn satisfies the following formula (7) .
0.30 ≦ In / (In + Ga + Sn) <0.60 (7) 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式（８）及び（９）を満たす請求項１，５及び６のいずれかに記載の酸化物焼結体。
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．１５ （８）
０．３０＜Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５０ （９） The oxide sintered body according to any one of claims 1 , 5, and 6, wherein an atomic ratio of the In, Ga, and Sn satisfies the following formulas (8) and (9).
0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.15 (8)
0.30 <Ga / (In + Ga + Sn) ≦ 0.50 (9) 前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式（１０）及び（１１）を満たす請求項１，５及び６のいずれかに記載の酸化物焼結体。
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．１１ （１０）
０．３２≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．４８ （１１） The oxide sintered body according to any one of claims 1 , 5, and 6, wherein an atomic ratio of the In, Ga, and Sn satisfies the following formulas (10) and (11).
0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.11 (10)
0.32 ≦ Ga / (In + Ga + Sn) ≦ 0.48 (11) Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項８に記載の酸化物焼結体。
０．３０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．４０
０．２０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．４０ The oxide sintered body according to claim 8 , wherein an atomic ratio of In, Ga, and Sn satisfies the following formula.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.40
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.40 相対密度が８５％以上である請求項１〜１１のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 11, having a relative density of 85% or more. 相対密度が９２％以上である請求項１〜１２のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 12, having a relative density of 92% or more. 相対密度が９５％以上である請求項１〜１３のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 13, having a relative density of 95% or more. 相対密度が９７％以上である請求項１〜１４のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 14, having a relative density of 97% or more. 比抵抗が７００ｍΩｃｍ以下である請求項１〜１５のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 15, which has a specific resistance of 700 mΩcm or less. 比抵抗が１００ｍΩｃｍ以下である請求項１〜１６のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 16, which has a specific resistance of 100 mΩcm or less. 比抵抗が５０ｍΩｃｍ以下である請求項１〜１７のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 17, which has a specific resistance of 50 mΩcm or less. 比抵抗が２０ｍΩｃｍ以下である請求項１〜１８のいずれかに記載の酸化物焼結体。 The oxide sintered body according to any one of claims 1 to 18, which has a specific resistance of 20 mΩcm or less. 酸化物焼結体をＸ線回析で分析すると、（１）３０．０〜３２．０°、（２）３５．０〜３７．０°、（３）５１．０〜５３．０°、（４）６０．５〜６３．０°の範囲にピークが存在する請求項１〜１９のいずれかに記載の酸化物焼結体。 When the oxide sintered body is analyzed by X-ray diffraction, (1) 30.0 to 32.0 °, (2) 35.0 to 37.0 °, (3) 51.0 to 53.0 °, (4) The oxide sintered body according to any one of claims 1 to 19 , wherein a peak exists in a range of 60.5 to 63.0 °. 前記金属酸化物焼結体を構成する金属酸化物に対する、Ｉｎ酸化物、Ｇａ酸化物、及びＳｎ酸化物の含有率が、９５重量％以上１００重量％以下である、請求項１〜２０のいずれかに記載の酸化物焼結体。 The content rate of In oxide, Ga oxide, and Sn oxide with respect to the metal oxide which comprises the said metal oxide sintered compact is 95 weight% or more and 100 weight% or less, Any of Claims 1-20 An oxide sintered body according to any one of the above. Ｇａ３−ｘＩｎ５＋ｘＳｎ２Ｏ１６（式中、Ｘは０〜１である。）で表される結晶構造の化合物を含む請求項１〜２０のいずれかに記載の酸化物焼結体。 Ga 3-x In 5 + x Sn 2 O 16 ( wherein, X is 0-1.) The oxide sintered body according to any of claims 1 to 20 comprising a compound of the crystal structure represented by. 前記Ｇａ３−ｘＩｎ５＋ｘＳｎ２Ｏ１６で表される結晶構造の化合物が、Ｇａ２Ｉｎ６Ｓｎ２Ｏ１６又はＧａ２．４Ｉｎ５．６Ｓｎ２Ｏ１６である、請求項２２に記載の酸化物焼結体。 The compound having a crystal structure represented by Ga 3-x In 5 + x Sn 2 O 16 is Ga 2 In 6 Sn 2 O 16 or Ga 2.4 In 5.6 Sn 2 O 16. Oxide sintered body. 前記Ｇａ３−ｘＩｎ５＋ｘＳｎ２Ｏ１６（式中、Ｘは０〜１である。）で表される結晶構造の化合物を、主成分、又は第二成分とする、請求項２２に記載の酸化物焼結体。 The compound having a crystal structure represented by the Ga 3-x In 5 + x Sn 2 O 16 (wherein X is 0 to 1) as a main component or a second component. Oxide sintered body. 前記Ｇａ３−ｘＩｎ５＋ｘＳｎ２Ｏ１６（式中、Ｘは０〜１である。）で表される結晶構造の化合物を、主成分とする、請求項２２に記載の酸化物焼結体。 The oxide sintered body according to claim 22, comprising a compound having a crystal structure represented by Ga 3−x In 5 + x Sn 2 O 16 (wherein X is 0 to 1) as a main component. . Ｘ線回析によって得られたピークのうち、主成分とは最大ピーク強度が最も高いものであり、第二成分とは最大ピーク強度が主成分の次に高いものである請求項２４に記載の酸化物焼結体。   25. The peak obtained by X-ray diffraction has the highest peak intensity as the main component, and the second component has the second highest peak intensity after the main component. Oxide sintered body. 請求項１〜２６いずれかに記載の酸化物焼結体を用いたスパッタリングターゲット。   A sputtering target using the oxide sintered body according to claim 1. 下記（ａ）〜（ｅ）の工程を含む請求項２７のスパッタリングターゲットの製造方法。
（ａ）原料化合物粉末を混合して混合物を調製する工程
（ｂ）前記混合物を成形して平均厚み５．５ｍｍ以上の成形体を調製する工程
（ｃ）前記成形体を１２８０℃以上１５２０℃以下で２時間以上９６時間以下焼結する工程
（ｄ）工程（ｃ）で得た焼結体の表面を０．３ｍｍ以上研削する工程
（ｅ）焼結体をバッキングプレートにボンディングする工程 The manufacturing method of the sputtering target of Claim 27 including the process of following (a)-(e).
(A) A step of preparing a mixture by mixing raw material compound powders (b) A step of forming the mixture to prepare a molded body having an average thickness of 5.5 mm or more (c) 1280 ° C to 1520 ° C of the molded body (D) A step of grinding the surface of the sintered body obtained in step (c) by 0.3 mm or more (e) A step of bonding the sintered body to a backing plate インジウム元素（Ｉｎ）、ガリウム元素（Ｇａ）及び錫元素（Ｓｎ）を、下記式（１）〜（３）の原子比で含み、亜鉛元素（Ｚｎ）の含有量が１００ｐｐｍ以下である酸化物半導体膜を含む薄膜トランジスタであって、移動度が３ｃｍ ２ ／Ｖｓ以上である薄膜トランジスタ。
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ （１）
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５ （２）
０．０００１＜Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ （３） An oxide semiconductor containing indium element (In), gallium element (Ga), and tin element (Sn) in an atomic ratio of the following formulas (1) to (3), and the content of zinc element (Zn) is 100 ppm or less A thin film transistor including a film and having a mobility of 3 cm 2 / Vs or more .
0.10 ≦ In / (In + Ga + Sn) ≦ 0.60 (1)
0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55 (2)
0.0001 <Sn / (In + Ga + Sn) ≦ 0.60 (3) 前記酸化物半導体膜の電子キャリア密度が１０The oxide semiconductor film has an electron carrier density of 10 １４14 ｃｍcm −３-3 以上１０10 or more １９19 ｃｍcm −３-3 以下である、Is
請求項２９に記載の薄膜トランジスタ。30. The thin film transistor according to claim 29. 前記酸化物半導体膜の前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式（８）及び（９）を満たす請求項２９に記載の薄膜トランジスタ。
０．０３≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．１５ （８）
０．３０＜Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５０ （９） 30. The thin film transistor according to claim 29, wherein an atomic ratio of In, Ga, and Sn in the oxide semiconductor film satisfies the following formulas (8) and (9).
0.03 ≦ Sn / (In + Ga + Sn) ≦ 0.15 (8)
0.30 <Ga / (In + Ga + Sn) ≦ 0.50 (9) 前記酸化物半導体膜の前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式（１０）及び（１１）を満たす請求項２９に記載の薄膜トランジスタ。
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．１１ （１０）
０．３２≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．４８ （１１） 30. The thin film transistor according to claim 29, wherein an atomic ratio of In, Ga, and Sn in the oxide semiconductor film satisfies the following formulas (10) and (11).
0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.11 (10)
0.32 ≦ Ga / (In + Ga + Sn) ≦ 0.48 (11) 前記酸化物半導体膜の前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項２９に記載の薄膜トランジスタ。
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．３０ 30. The thin film transistor according to claim 29, wherein an atomic ratio of In, Ga, and Sn in the oxide semiconductor film satisfies the following formula.
0.10 ≦ In / (In + Ga + Sn) ≦ 0.60
0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55
0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.30 前記酸化物半導体膜の前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項２９に記載の薄膜トランジスタ。
０．４０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５
０．３０≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ 30. The thin film transistor according to claim 29, wherein an atomic ratio of In, Ga, and Sn in the oxide semiconductor film satisfies the following formula.
0.40 ≦ In / (In + Ga + Sn) ≦ 0.60
0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55
0.30 ≦ Sn / (In + Ga + Sn) ≦ 0.60 前記酸化物半導体膜が非晶質膜であり、前記非晶質中に微結晶を含む請求項２９に記載の薄膜トランジスタ。 30. The thin film transistor according to claim 29, wherein the oxide semiconductor film is an amorphous film and includes microcrystals in the amorphous film . 前記酸化物半導体膜のリン酸系ウェットエッチング速度が５ｎｍ／分以下である請求項２９に記載の薄膜トランジスタ。 30. The thin film transistor according to claim 29, wherein a phosphoric acid-based wet etching rate of the oxide semiconductor film is 5 nm / min or less. 前記酸化物半導体膜の修酸系ウェットエッチングが速度２０ｎｍ／分以上であり、リン酸系ウェットエッチング速度が５ｎｍ／分以下であり、前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項２９に記載の薄膜トランジスタ。
０．１０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５
０．０４≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．３０ The oxalic acid-based wet etching of the oxide semiconductor film is at a rate of 20 nm / min or more, the phosphoric acid-based wet etching rate is at most 5 nm / min, and the atomic ratio of In, Ga, and Sn satisfies the following formula: 30. The thin film transistor according to 29.
0.10 ≦ In / (In + Ga + Sn) ≦ 0.60
0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55
0.04 ≦ Sn / (In + Ga + Sn) ≦ 0.30 前記酸化物半導体膜の修酸系ウェットエッチングが速度２０ｎｍ／分以上であり、リン酸系ウェットエッチング速度が５ｎｍ／分以下であり、前記Ｉｎ、Ｇａ及びＳｎの原子比が下記式を満たす請求項２９に記載の薄膜トランジスタ。
０．４０≦Ｉｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０
０．１０≦Ｇａ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．５５
０．３０≦Ｓｎ／（Ｉｎ＋Ｇａ＋Ｓｎ）≦０．６０ The oxalic acid-based wet etching of the oxide semiconductor film is at a rate of 20 nm / min or more, the phosphoric acid-based wet etching rate is at most 5 nm / min, and the atomic ratio of In, Ga, and Sn satisfies the following formula: 30. The thin film transistor according to 29.
0.40 ≦ In / (In + Ga + Sn) ≦ 0.60
0.10 ≦ Ga / (In + Ga + Sn) ≦ 0.55
0.30 ≦ Sn / (In + Ga + Sn) ≦ 0.60 前記酸化物半導体膜のＸ線光電子分光法（ＸＰＳ）で測定したＳｎ平均価数は、＋３．０以上、＋４．０以下である、請求項２９〜３８のいずれかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 29 to 38 , wherein an Sn average valence measured by X-ray photoelectron spectroscopy (XPS) of the oxide semiconductor film is +3.0 or more and +4.0 or less. 移動度が６ｃｍ２／Ｖｓ以上である請求項２９に記載の薄膜トランジスタ。 30. The thin film transistor according to claim 29 , wherein the mobility is 6 cm 2 / Vs or higher. 移動度が１０ｃｍ２／Ｖｓ以上である請求項２９に記載の薄膜トランジスタ。 30. The thin film transistor according to claim 29 , wherein the mobility is 10 cm 2 / Vs or higher. 請求項２９〜４１のいずれかに記載の薄膜トランジスタを用いた半導体素子。 The semiconductor element using the thin-film transistor in any one of Claims 29-41 . 請求項４２に記載の半導体素子を備えるディスプレイ。 A display comprising the semiconductor device according to claim 42 .
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