JP2017163081A - Semiconductor optical device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the lowering of the bonding strength of a semiconductor laminate to improve the mechanical strength and to stably produce it, when the semiconductor laminate is provided above a low thermal conduction region.SOLUTION: A semiconductor optical device includes above a semiconductor substrate: a first semiconductor layer made of a material substantially lattice-matched to the semiconductor substrate; a low thermal conduction region provided on the same common surface as the first semiconductor layer; a second semiconductor layer provided on the first semiconductor layer and an upper layer of the low thermal conduction region and connected to the first semiconductor layer; a waveguide layer provided in the upper layer of the low thermal conduction region; and a heating part provided in an upper layer of the waveguide layer.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor optical device applied to the field of optical communication and the like, and a method for manufacturing the same.

  With the spread of coherent optical communication, there is an increasing demand for a tunable laser element having a narrow line width. The configuration and operating principle of the wavelength tunable laser element are described in detail in Non-Patent Document 1, for example. In general, in order to narrow the laser beam output from a semiconductor laser element, it is necessary to lengthen the resonator.

  There is a distributed Bragg reflection (DBR) type wavelength tunable laser using a sampled diffraction grating (Sampled Grating) as one of the wavelength tunable laser elements and utilizing the vernier effect (for example, Patent Document 1). In this tunable laser element, two DBR mirrors in which a part of a diffraction grating is sampled in a semiconductor element are used. The reflection spectra of these two DBR mirrors have a shape having comb-like peaks with slightly different periods. Further, the refractive index change can be caused by current injection or heating in the DBR mirror, and the reflection wavelength characteristic can be made variable. By superimposing the reflection peaks of the two DBR mirrors, a resonator can be formed with this superimposed wavelength. At this time, if the resonator length is appropriately designed, the interval between the longitudinal modes, which are the resonator modes, is approximately the same as the band of the reflection peak by the two DBR mirrors, and only one resonator mode is selected. Oscillation is realized.

  As another method for realizing a laser beam having a narrow line width, there is a method of increasing the Q value of the resonator mode by increasing the resonance length using an external resonator structure. Further, for example, in a wavelength tunable laser element (for example, Non-Patent Document 2) in which a resonator is configured by using two ring resonators, a relatively sharp superposition of the filter characteristics (reflection wavelength characteristics) of the ring resonator is used. Thus, the configuration of the resonator can be freely designed.

  In the configuration described above, the wavelength selection method is realized by changing the refractive indexes of two DBR mirrors or ring resonators by current injection or heating. Further, as described in Patent Document 2 and the like, the heating method is provided with a microheater on the waveguide in the region where the refractive index change is desired to be generated, and in order to further increase the efficiency of the heating, it is provided at the lower part of the core layer of the waveguide. By providing the low thermal conductive layer, the outflow of heat to the substrate side is suppressed. As the low thermal conductive layer for suppressing thermal conduction, a mixed crystal semiconductor layer, an oxide layer obtained by oxidizing a semiconductor layer containing aluminum (Al), or the like is used. In particular, the oxide layer is said to have a great effect as a low thermal conductive layer.

US Pat. No. 6,590,924 Japanese Patent Laying-Open No. 2015-12176

Larry A. Coldren et al., “Tunable Semiconductor Lasers: A Tutorial”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 22, NO / 1, JANUARY 2004, pp.193-202 Keita Nemoto et al., “Narrow-Spectral-Linewidth Wavelength-Tunable Laser Diode with Si Wire Waveguide Ring Resonators”, Applied Physics Express 5 (2012) 082701

  However, after forming the mesa structure in which the side surface of the AlInAs layer is exposed in the structure in which the inventor includes the semiconductor layer containing Al described above, specifically, the AlInAs layer sandwiched between InP layers, the oxidation for oxidizing the AlInAs layer is performed. As a result of experiments, the following problems were discovered.

  That is, when the cross section of the sample obtained by the oxidation experiment conducted by the present inventor was observed, the present inventor found that voids were generated at the interface between the AlInAs oxide layer and the InP layer in which the AlInAs layer was oxidized. I found out. Occurrence of voids at the interface between the AlInAs layer and the InP layer may reduce the bonding strength between the AlInAs oxide layer and the upper layer or cause partial peeling.

  In a semiconductor optical device having a high mesa structure or the like, when an AlInAs oxide layer is used as a low thermal conduction region, if the bonding strength at the interface between the AlInAs oxide layer and the InP layer decreases, the portion including the core region above the AlInAs oxide layer In this case, the mechanical strength is weakened. As a result, there is a possibility that the stacked body above the AlInAs oxide layer may be peeled off.

  Further, when manufacturing a semiconductor optical device, it is necessary to form a protective layer made of a dielectric layer or a resin layer on a semiconductor laminate such as a high mesa structure or to install a heater on the top. In this case, the stress generated by the protective layer and the heater itself and the stress generated by the manufacturing process such as the photolithography process and the heat treatment process for forming the protective layer and the heater act on the high mesa structure. Therefore, the bonding strength of the semiconductor stacked body is more likely to be reduced. It should be noted that the stress resulting from these steps is more susceptible to the increase in the number of manufacturing steps when manufacturing a semiconductor optical device in which elements having other functions are integrated. Further, peeling may occur due to stress generated when the semiconductor optical element is mounted on the module, or other reliability tests such as long-term reliability, thermal shock, thermal cycle, low temperature storage, and high temperature storage.

The above-described problem is that the Al _1-xy Ga _x In _y As _1-z P _z oxide layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1) is used as the low thermal conductive layer. The same applies to the case of using 1). In addition, when a hollow layer filled with air is used as the low heat conduction region, the mechanical strength of the portion including the low heat conduction region and the core region above it becomes weak, and thus the same problem as described above occurs.

  The present invention has been made in view of the above, and an object thereof is to suppress a decrease in the bonding strength of the semiconductor stacked body when the semiconductor stacked body is provided above the low thermal conduction region. An object of the present invention is to provide a semiconductor optical device that can improve mechanical strength and can be stably manufactured, and a method for manufacturing the same.

  In order to solve the above-described problems and achieve the above object, a semiconductor optical device according to the present invention includes a first semiconductor layer made of a material substantially lattice-matched to a semiconductor substrate above the semiconductor substrate, and a first semiconductor layer. A low thermal conduction region provided on the same plane as the semiconductor layer; a second semiconductor layer provided on the first semiconductor layer and the lower thermal conduction region; and connected to the first semiconductor layer; and an upper layer on the low thermal conduction region. It has the provided waveguide layer and the heating part provided in the upper layer of the waveguide layer, It is characterized by the above-mentioned.

  The semiconductor optical device according to one embodiment of the present invention is characterized in that, in the above invention, the arrangement region along the surface direction of the low thermal conductivity region and the arrangement region of the heating portion at least partially overlap.

  In the semiconductor optical device according to one embodiment of the present invention, the first semiconductor layer is provided in at least a part of the waveguide layer along the waveguide direction in the above invention.

  In the semiconductor optical device according to one aspect of the present invention, in the above invention, the high mesa waveguide structure having the waveguide layer is provided in a region narrower than the arrangement region along the surface direction of the low thermal conductivity region. Features.

  The semiconductor optical device according to one embodiment of the present invention is characterized in that, in the above invention, the low thermal conductivity region has at least one portion that is flush with the side surface in the lower side surface of the high mesa waveguide structure.

  In this configuration, the semiconductor optical device according to one aspect of the present invention includes the first semiconductor below the high mesa waveguide structure along the surface direction of the semiconductor substrate, the high mesa waveguide structure including the ring-shaped waveguide. The layer is disposed at a position that is n times rotationally symmetric (n is an integer of 2 or more) with respect to the ring-shaped center.

  In the semiconductor optical device according to one aspect of the present invention, in the above invention, the first semiconductor layer and the second semiconductor layer are connected to the upper layer of the low thermal conductivity region and the first semiconductor layer, and the second semiconductor layer is etched. An etching stop layer having selectivity is provided.

  In the semiconductor optical device according to one aspect of the present invention, in the above invention, the low thermal conductivity region includes an oxide layer in which at least one first semiconductor layer that is substantially lattice-matched to the semiconductor substrate is oxidized. And

In the semiconductor optical device according to one embodiment of the present invention, in the above invention, the semiconductor substrate is an InP substrate, and the first semiconductor layer is an Al _1-xy Ga _x In _y As _1-z P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1).

  The semiconductor optical device according to one embodiment of the present invention is characterized in that, in the above invention, the low thermal conductivity region is formed of a cavity.

  The method for manufacturing a semiconductor optical device according to the present invention includes a first semiconductor layer made of a material substantially lattice-matched to the semiconductor substrate above the semiconductor substrate, and a first semiconductor layer connected to the upper layer of the first semiconductor layer. After sequentially laminating the second semiconductor layer, the thermal conductivity is reduced with respect to a part of the first semiconductor layer along the surface direction of the first semiconductor layer in a state where the first semiconductor layer and the second semiconductor layer are connected. It has the process of performing a process and forming a low heat conduction area | region. As a result, it is possible to deal with integrated semiconductor optical devices having a large number of processing steps and a complicated laminated structure, and it is possible to manufacture integrated semiconductor optical devices, and long-term reliability of the manufactured semiconductor optical devices. Can be secured stably.

  In the method of manufacturing a semiconductor optical device according to one aspect of the present invention, in the above invention, the low thermal conductivity treatment is an oxidation treatment in which a part of the first semiconductor layer is oxidized along the surface direction of the first semiconductor layer. It is characterized by that.

  In the method of manufacturing a semiconductor optical device according to one aspect of the present invention, in the above invention, a cavity formation is performed in which the low thermal conductivity treatment removes a part of the first semiconductor layer to form a cavity adjacent to the first semiconductor layer. It is a process.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor optical device, wherein the second semiconductor layer and the etching are formed on the first semiconductor layer after the formation of the first semiconductor layer and before the formation of the second semiconductor layer. A second semiconductor layer is formed after forming an etching stop layer having selectivity, and the second semiconductor layer is etched. As a result, when forming a high mesa waveguide structure, the height of the mesa structure at the time of manufacture, that is, the in-plane distribution of the etching depth can be improved, and further, variation between semiconductor substrates can be suppressed. Manufacturing yield can be improved.

  According to the semiconductor optical device and the manufacturing method thereof according to the present invention, in the case where the semiconductor laminated body is provided on the low heat conduction region, the mechanical strength is suppressed by suppressing the decrease in the bonding strength of the semiconductor laminated body. It can improve and it becomes possible to manufacture stably.

FIG. 1 is a cross-sectional view showing a laminated structure of a high mesa waveguide structure for explaining the problem of the present invention. FIG. 2 is a schematic perspective view of the wavelength tunable laser device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line III-III of the ring-shaped waveguide in FIG. FIG. 4 is a sectional view of a high mesa waveguide structure in a semiconductor optical device according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to the third embodiment of the present invention. FIG. 6 is a sectional view of a high mesa waveguide structure in a semiconductor optical device according to the fourth embodiment of the present invention. FIG. 7 is a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to the fifth embodiment of the present invention. FIG. 8 is a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to a sixth embodiment of the present invention. FIG. 9 is a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to a seventh embodiment of the present invention. FIG. 10 is a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to the eighth embodiment of the present invention. FIG. 11 is a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to the ninth embodiment of the present invention. FIG. 12 is a plan view and a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to the tenth embodiment of the present invention. FIG. 13 is a plan view and a cross-sectional view of a high mesa waveguide structure in a semiconductor optical device according to an eleventh embodiment of the present invention. FIG. 14 is a sectional view showing the overall configuration of an integrated semiconductor laser device according to the twelfth embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by the following embodiment. In the drawings, the same or corresponding elements are denoted by the same reference numerals as appropriate, and repeated descriptions are omitted as appropriate. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included. Further, “upper” or “upper” and “lower” or “lower” used in the description of the following embodiments indicate a direction away from the main surface of the substrate and a direction approaching the main surface of the substrate, respectively. It should also be noted that the semiconductor device is not mounted in the vertical direction when mounted. In addition, xyz coordinate axes are appropriately shown in the drawing, and directions will be described.

  First, in describing embodiments of the present invention, experiments and diligent studies conducted by the present inventors to solve the above-described problems will be described in order to facilitate understanding of the present invention. FIG. 1 is a cross-sectional view showing a semiconductor laminate for conducting an oxidation experiment on an AlInAs layer.

The inventor first formed the high mesa waveguide structure 400 as follows. That is, as shown in FIG. 1, an AlInAs layer to be an AlInAs oxide layer 402 and an InP layer to be a lower cladding layer 403 are formed on an InP substrate 401 by metal organic chemical vapor deposition (MOCVD). Then, a GaInAsP layer to be the optical waveguide layer 404 and an InP layer to be the upper cladding layer 405 are sequentially formed. Next, for example, a silicon nitride (SiN _x ) film is formed on the upper surface of the InP layer to be the upper cladding layer 405 and patterned into a high mesa waveguide structure. Subsequently, anisotropic etching is performed using the SiN _x film as an etching mask, for example, by a dry etching method using a chlorine-based gas. As a result, one end of the AlInAs layer that becomes the AlInAs oxide layer 402 is exposed.

  Then, annealing is performed at a temperature of 450 ° C. or more and 520 ° C. or less in a water vapor atmosphere for the semiconductor stacked body including the AlInAs layer whose side surface is exposed. As a result, in the AlInAs layer on the InP substrate 401, oxidation proceeds along the surface direction of the AlInAs layer from the exposed end portion, and the AlInAs oxide layer 402 is formed uniformly. Thereafter, the region of the lower cladding layer 403 composed of the InP substrate 401, the AlInAs oxide layer 402, and the InP layer was evaluated by cross-sectional observation using a scanning electron microscope (SEM). As a result, the present inventor has found that a void 407 is generated at the interface between the AlInAs oxide layer 402 and the InP substrate 401 and the lower cladding layer 403. The presence of the void 407 may decrease the bonding strength at the interface between the AlInAs oxide layer 402 and the InP substrate 401 and the lower cladding layer 403. As a result, the mechanical strength of the lower clad layer 403, the optical waveguide layer 404, and the upper clad layer 405 is reduced, and there is a possibility of peeling.

  Further, in order to heat the optical waveguide layer 404, it is necessary to form the micro heater 406 on the upper clad layer 405. In this case, the high mesa waveguide structure 400 as the semiconductor laminate is subjected to stress generated when the microheater 406 is formed or stress generated by the metal layer itself, and the layer above the lower cladding layer 403 in the void 407 portion. Becomes easy to peel.

According to the knowledge of the present inventor, the generation of the above-mentioned voids occurs not only in the AlInAs oxide layer but also in the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 ≦ x <1). , 0 <y <1, 0 ≦ z <1) is also generated in the Al _1-xy Ga _x In _y As _{1-z Pz} oxide layer oxidized.

  The present inventor has intensively studied to solve the above-mentioned problems based on the knowledge obtained by the above-described experiment. Then, the inventor provides a connection region connected to a base serving as a support in order to suppress a decrease in the bonding strength of the high mesa waveguide structure 400 above the AlInAs oxide layer 402 and improve the mechanical strength. I recalled that. It is desirable that the connection region with the base serving as the support is composed of an unoxidized AlInAs layer and an upper semiconductor layer. Furthermore, it has been recalled that the connection region is preferably provided on at least one side along the side surface direction of the high mesa waveguide structure or on a part of the optical waveguide layer along the waveguide direction. When the connection region is composed of an unoxidized AlInAs layer, the size of the low heat conduction region should be larger in order to cover the region where the microheater is disposed along the surface direction. desirable. As a result, the heat generated by the microheater can be prevented from flowing out to the semiconductor substrate side, and a desired region can be efficiently heated. The embodiment described below has been devised based on the above examination.

(First embodiment)
Next, the wavelength tunable laser device according to the first embodiment based on the above-described diligent study by the present inventors will be described. FIG. 2 is a schematic perspective view of the wavelength tunable laser device according to the first embodiment.

  As shown in FIG. 2, the wavelength tunable laser element 1 is configured to oscillate in the 1.55 μm band and output the laser light L1. The wavelength tunable laser element 1 includes a first waveguide section 10 and a second waveguide section 20 formed on a common base B. The base B is made of, for example, an n-type InP substrate. An n-side electrode 30 is formed on the back surface of the base B. The n-side electrode 30 is configured to contain AuGeNi, for example, and is in ohmic contact with the base B.

  The first waveguide section 10 includes a waveguide section 11, a semiconductor laminated section 12, a p-side electrode 13, and micro heaters 14 and 15 made of Ti. The first waveguide portion 10 is a so-called active element and constitutes an active region. The waveguide portion 11 is formed in the semiconductor stacked portion 12 so as to extend in the z direction. In the first waveguide section 10, a diffraction grating loaded gain section 11a and a phase adjustment section 11b are arranged. The semiconductor laminated portion 12 is configured by laminating semiconductor layers, and has a function of a clad portion with respect to the waveguide portion 11.

The p-side electrode 13 is disposed along the diffraction grating loaded gain section 11 a on the semiconductor multilayer section 12. Note that a SiN _x protective film is formed on the semiconductor multilayer portion 12, and the p-side electrode 13 is in contact with the semiconductor multilayer portion 12 through an opening formed in the SiN _x protective film. The microheater 14 serving as a heating unit is disposed on the SiN _x protective film of the semiconductor stacked unit 12 along the phase adjusting unit 11b. The microheater 15 as a heating unit is arranged along the p-side electrode 13 on the SiN _x protective film of the semiconductor stacked unit 12.

  The second waveguide portion 20 includes a bifurcated portion 21, two arm portions 22 and 23, a ring-shaped waveguide 24, and a micro heater 25 made of Ti. The second waveguide portion 20 is a so-called passive element and constitutes a passive region. The two-branch portion 21 is formed of a 1 × 2 type branching waveguide including a 1 × 2 type multimode interference (MMI) waveguide 21a, and the two-port side is connected to each of the two arm portions 22 and 23. In addition, one port side is connected to the first waveguide section 10 side. One end of each of the two arm portions 22 and 23 is integrated by the bifurcated portion 21 and is optically coupled to the waveguide portion 11.

Each of the arm portions 22 and 23 extends in the z direction and is disposed so as to sandwich the ring-shaped waveguide 24. The arm portions 22 and 23 are close to the ring-shaped waveguide 24, and both are optically coupled to the ring-shaped waveguide 24 with the same coupling coefficient κ. The value of κ is, for example, 0.2. The arm portions 22 and 23 and the ring-shaped waveguide 24 constitute a ring resonance filter RF1. Further, the ring resonant filter RF1 and the bifurcated portion 21 constitute a reflection mirror M1. The microheater 25 as a heating unit for heating the optical waveguide has a ring shape and is disposed on the SiN _x protective film formed so as to cover the ring-shaped waveguide 24.

  The first waveguide section 10 and the second waveguide section 20 are optically connected to each other, and the diffraction grating layer 11ab of the diffraction grating loaded gain section 11a and the reflection mirror M1 constitute a laser resonator C1. ing. The active core layer 11aa and the phase adjustment unit 11b as the gain unit of the diffraction grating loaded gain unit 11a are arranged in the laser resonator C1.

  3 is a cross-sectional view taken along line III-III, in which the ring-shaped waveguide 24 of the second waveguide section 20 is cut along a plane parallel to the yz plane of FIG. As shown in FIG. 3, the ring-shaped waveguide 24 is formed on the n-type InP substrate 41 constituting the base B, on the low thermal conductive layer 42a, the lower cladding layer 43, the optical waveguide layer 44 as a waveguide layer, and the upper cladding. It has a high mesa waveguide structure in which layers 45 are sequentially stacked.

The low thermal conductive layer 42a is an Al _1-xy Ga _x In _y As _1-z P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1) as an oxidized layer. ) Is formed by oxidation from the side end portion and formed of an Al _{1 -xy} Ga _x In _y As _{1 -z Pz} oxide layer. The low thermal conductive layer 42a is provided on the entire passive element or at least a part of the lower layer. Specifically, the low thermal conductive layer 42a as the low thermal conductive region is made of, for example, an AlInAs oxide layer in which the n-type AlInAs layer 42 in which x = z = 0 is oxidized from the side end portion. Thereby, the n-type AlInAs layer 42 and the low thermal conductive layer 42a are provided as the same layer on the same surface of the n-type InP substrate 41. The composition of the n-type AlInAs layer 42 is a composition that substantially lattice matches with the n-type InP substrate 41. For example, in the first embodiment, an Al _0.48 In _0.52 As layer (x = 1, y = 0.52, z = 0). The film thickness of the n-type AlInAs layer 42 is 0.5 times or more and less than 1.5 times the optimum film thickness that is the film thickness at which the oxidation rate is maximized when oxidized from the side surface, and preferably 1.3 times. Is less than double. Specifically, in this first embodiment, the optimum film thickness of the n-type AlInAs layer 42 is, for example, 100 nm, and the film thickness of the n-type AlInAs layer 42 is 50 nm or more and less than 150 nm, preferably 130 nm or less, here 100 nm. And

  The lower clad layer 43 is made of an n-type InP layer, and the lower portion of the lower clad layer 43 has an extended portion 43 a extending to the unoxidized n-type AlInAs layer 42. As a result, at least in the extended portion 43a on the unoxidized n-type AlInAs layer 42, the n-type AlInAs layer 42 and the upper lower cladding layer 43 are connected. That is, the connection region is constituted by the non-oxidized n-type AlInAs layer 42 and the lower cladding layer 43.

  The optical waveguide layer 44 is made of a GaInAsP layer having a band gap wavelength of 1300 nm. The upper cladding layer 45 is made of a p-type InP layer.

A low thermal conductive layer 42a, a lower cladding layer 43, an optical waveguide layer 44, and an upper cladding layer 45 constituting the high mesa waveguide structure, and an extended portion 43a extending on the n-type AlInAs layer 42 below the lower cladding layer 43; Is covered with a dielectric layer 46 as a protective film. The dielectric layer 46 is made of, for example, a SiN _x film, a silicon oxide (SiO ₂ ) film, or a laminated film of a SiO ₂ film and a SiN _x film.

  The bifurcated portion 21 and the arm portions 22 and 23 which are other components of the second waveguide portion 20 also have a high mesa waveguide structure similar to that described above, and are covered with a dielectric layer. That is, the second waveguide section 20 has a second waveguide structure that is different from the first waveguide structure of the first waveguide section 10.

  A microheater 25 is provided on the dielectric layer 46 above the high mesa waveguide structure constituting the ring-shaped waveguide 24. A resin layer 48 covering the side surface is provided on the side surface side of the high mesa waveguide structure. On the upper surface of the resin layer 48 and the upper surface of the microheater 25, a lead-out wiring 49 electrically connected on the upper surface of the microheater 25 is provided. The lead-out wiring 49 is a wiring for energizing the microheater 25 from the outside. By energizing the microheater 25, the lower part of the installation area of the microheater 25 can be heated to the upper layer of the low thermal conductive layer 42a. The low thermal conductive layer 42 a has a thermal conductivity lower than that of at least the upper cladding layer 45, the optical waveguide layer 44, and the lower cladding layer 43. Thereby, the low thermal conductive layer 42a functions as a heat insulating layer for preventing the heating by the microheater 25 from being further transmitted to the lower layer. The lead wiring 49 is made of, for example, a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, or a Mo / Au layer. Note that a so-called air bridge structure in which the lead wiring 49 is provided with the resin layer 48 in a space may be employed.

(Manufacturing method of high mesa waveguide structure)
Next, a manufacturing method of the above-described high mesa waveguide structure will be described. First, an n-type AlInAs layer 42 and a lower cladding layer 43 are formed on an n-type InP substrate 41 constituting a base B on which an n-type InP buffer layer (not shown) of about 500 nm, for example, is formed as an upper layer by, for example, MOCVD. The n-type InP layer to be, the GaInAsP layer to be the optical waveguide layer 44, and the p-type InP layer to be the upper cladding layer 45 are sequentially formed.

Next, for example, a SiN _x film is formed on the upper surface of the p-type InP layer to be the upper cladding layer 45, and is patterned into a high mesa waveguide structure such as a ring-shaped or straight arm. Subsequently, anisotropic etching is performed using the SiN _x film as an etching mask, for example, by a dry etching method using a chlorine-based gas. Here, the lower cladding layer 43 is etched by about 1500 nm below the optical waveguide layer 44. After etching with the lower portion of the lower cladding layer 43 remaining, the etching mask is removed. Subsequently, after forming an etching mask in a region including the laminated portion of the high mesa waveguide structure and the extended portion 43a below the lower clad layer 43, dry etching using, for example, a chlorine-based gas is performed. As a result, the remaining portion of the lower clad layer 43 in the desired region where the oxide layer is to be formed and the n-type AlInAs layer 42 are etched, and one end of the n-type AlInAs layer 42 as the first semiconductor layer is a high mesa waveguide structure. Exposed in a flush manner on the lower side of the body. The remaining portion of the lower clad layer 43 and the n-type AlInAs layer 42 may be etched by a wet etching method.

  After that, annealing is performed at a temperature of 450 ° C. or more and 520 ° C. or less in a water vapor atmosphere on the high mesa waveguide structure laminate including the n-type AlInAs layer 42 whose side surface is exposed. As a result, in the n-type AlInAs layer 42, oxidation proceeds along the surface direction of the n-type AlInAs layer 42 from the exposed end. This oxidation is performed until the n-type AlInAs layer 42 in the lower region of the high mesa waveguide structure is oxidized. The oxidation time in the oxidation treatment is determined based on the oxidation rate data obtained from the oxidation experiment performed to derive the optimum film thickness described above, the design value of the width of the high mesa waveguide structure, and the like. For example, when the width of the AlInAs oxide layer is about 2.2 μm, the oxidation time is about 120 minutes, for example. As a result, the n-type AlInAs layer 42 is uniformly oxidized under the high mesa waveguide structure to form a low thermal conductive layer 42a made of a uniform AlInAs oxide layer along the width direction, and the n-type AlInAs layer 42 is formed. In FIG. 4, a non-oxidized region is left in a portion other than the lower portion of the high mesa waveguide structure. The unoxidized region constitutes a connection region in which the n-type AlInAs layer 42 and the lower cladding layer 43 are firmly connected.

Next, a dielectric layer 46 is formed by, for example, forming a SiN _x film on the entire surface. Thereafter, a metal layer such as a Ti layer is formed in the shape of the microheater 25 on the dielectric layer 46 above the high mesa waveguide structure by, for example, a lift-off method using a lift-off mask. Further, a resin layer 48 is formed by embedding a resin in the side portion of the high mesa waveguide structure, and then, for example, a Ti / Au layer, a Ti / Pt / Au layer, a Cr layer on at least a part of the microheater 25 and the resin layer 48. The lead wiring 49 is formed by forming the / Au layer or the Mo / Au layer. As described above, a high mesa waveguide structure in which the low thermal conductive layer 42a is provided in the lower portion and the micro heater 25 is provided in the upper portion is manufactured.

  According to the first embodiment described above, an n-type InP substrate in which the coupling region is a support by forming the coupling region by the unoxidized n-type AlInAs layer 42 and the lower cladding layer 43. 41 will be connected. Therefore, by forming a structure that reinforces the n-type AlInAs layer 42 and the lower cladding layer 43, the low thermal conductive layer 42a, the upper layer of the n-type InP substrate 41 (n-type InP buffer layer: not shown) and the lower part Even if voids are generated between the clad layer 43 and the lower clad layer 43, a decrease in the bonding strength of the high mesa waveguide structure above the lower clad layer 43 can be suppressed, and the mechanical strength can be improved. Therefore, even when a low thermal conductive layer is provided below the high mesa waveguide structure, the mechanical strength of the high mesa waveguide structure can be improved and delamination is suppressed, and the high mesa waveguide structure is stabilized. Can be manufactured.

(Second Embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to the second embodiment of the present invention will be described. In the description and drawings after the second embodiment, in order to facilitate the understanding of the invention, a description is given of a laminated structure in which the description of the resin layer, the dielectric layer, the lead-out wiring, and the like in the high mesa waveguide structure is omitted. To do.

  FIG. 4 is a cross-sectional view showing a high mesa waveguide structure according to the second embodiment. As shown in FIG. 4, in the high mesa waveguide structure 60 according to the second embodiment, an n-type AlInAs layer 61 and an AlInAs oxide layer are formed on an n-type InP substrate 41 as in the first embodiment. The low thermal conductive layer 61a, the lower cladding layer 62, the optical waveguide layer 44, the upper cladding layer 45, and the microheater 25 are sequentially formed and provided. Further, below the lower clad layer 62, extending portions 62 a extending along the surface direction of the n-type InP substrate 41 are provided on both sides along the width direction of the high mesa waveguide structure 60. The low thermal conductive layer 61a is formed on the lower side of the extended portion 62a below the lower clad layer 62, from one end of the exposed side of the high mesa waveguide structure 60 to the lower portion on the other side of the high mesa waveguide structure 60. It is provided in the area up to. An n-type AlInAs layer 61 is provided from the lower part of the other side surface of the high mesa waveguide structure 60 to the outside of the low thermal conductive layer 61a. The n-type AlInAs layer 61 and the extended portion 62 a of the lower cladding layer 62 constitute a connection region. In this connection region, the high mesa waveguide structure 60 is held on the n-type InP substrate 41 serving as a base.

  Next, in the manufacturing method of the high mesa waveguide structure according to the second embodiment, first, similarly to the first embodiment, the n-type that forms the base portion B in which the n-type InP buffer layer is provided in the upper layer is provided. On the InP substrate 41, an n-type AlInAs layer 61, an n-type InP layer serving as the lower cladding layer 62, a GaInAsP layer serving as the optical waveguide layer 44, and a p-type InP layer serving as the upper cladding layer 45 are sequentially formed by MOCVD, for example. Form.

Next, for example, a SiN _x film is formed on the upper surface of the p-type InP layer to be the upper clad layer 45, and is patterned into a high mesa waveguide structure such as a ring-shaped or straight arm. Subsequently, anisotropic etching is performed using the SiN _x film as an etching mask, for example, by a dry etching method using a chlorine-based gas. After etching with the lower portion of the lower cladding layer 62 remaining, the etching mask is removed. Subsequently, after forming an etching mask in a region including the laminated portion of the high mesa waveguide structure and the extended portion 62a below the lower cladding layer 62, for example, dry etching using a chlorine-based gas is performed. As a result, the remaining portion of the lower cladding layer 62 in the desired region where the oxide layer is to be formed and the n-type AlInAs layer 61 are etched, and one end of the n-type AlInAs layer 61 is formed on the side surface of the high mesa waveguide structure 60. Exposed in a flush state. The remaining portion of the lower cladding layer 62 and the n-type AlInAs layer 61 may be etched by a wet etching method.

  Thereafter, annealing is performed on the high-mesa waveguide structure 60 including the n-type AlInAs layer 61 whose side surfaces are exposed at a temperature of 450 ° C. or more and 520 ° C. or less in a water vapor atmosphere. As a result, in the n-type AlInAs layer 61, oxidation proceeds along the surface direction of the n-type AlInAs layer 61 from the exposed end. The oxidation of the n-type AlInAs layer 61 is performed until the oxidation proceeds to a position below the other side surface of the high mesa waveguide structure 60 on the side opposite to the exposed end of the n-type AlInAs layer 61. As a result, the n-type AlInAs layer 61 is uniformly oxidized in the lower portion of the high mesa waveguide structure, and a low thermal conductive layer 61a composed of a uniform AlInAs oxide layer is formed along the width direction.

  According to the second embodiment, the connection region is constituted by the n-type AlInAs layer 61 in which oxidation has not progressed and the extended portion 62a of the lower cladding layer 62, and thus the same as in the first embodiment. The effect of can be obtained.

(Third embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to the third embodiment of the present invention will be described. FIG. 5 is a cross-sectional view showing a high mesa waveguide structure according to the third embodiment. As shown in FIG. 5, in the high mesa waveguide structure 70 according to the third embodiment, an n-type AlInAs layer 71 and an AlInAs oxide layer are formed on an n-type InP substrate 41 as in the first embodiment. A low thermal conductive layer 71a, a lower clad layer 72 having an extended portion 72a below, an optical waveguide layer 44, an upper clad layer 45, and a microheater 25 are sequentially formed. The low thermal conductive layer 71a is formed on the lower side of the extended portion 72a below the lower clad layer 72 from the exposed one end of the high mesa waveguide structure 70 on the other side lower portion of the high mesa waveguide structure 70. It is provided in a region further expanded to the outside. An n-type AlInAs layer 71 is provided on the outer side of the formation region of the low thermal conductive layer 71a that extends further outward from the lower portion of the other side surface of the high mesa waveguide structure 70. The n-type AlInAs layer 71 and the extended portion 72 a of the lower cladding layer 72 constitute a connection region. In this connection region, the high mesa waveguide structure 70 is held on the n-type InP substrate 41 serving as a base. Other configurations are the same as those of the second embodiment.

  Next, in the method of manufacturing the high mesa waveguide structure according to the third embodiment, unlike the second embodiment, the n-type AlInAs layer 71 with the exposed one end of the side surface is oxidized from the exposed end. I do. The oxidation of the n-type AlInAs layer 71 is performed until the oxidation progresses to a position further expanded outward from below the other side surface of the high-mesa waveguide structure 70 on the side opposite to the exposed end of the n-type AlInAs layer 71. To do. As a result, the n-type AlInAs layer 71 is uniformly oxidized in the lower part of the high mesa waveguide structure 70, and the low heat composed of a uniform AlInAs oxide layer is formed in a region wider than the high mesa waveguide structure 70 along the width direction. Conductive layer 71a is formed. Other manufacturing methods are the same as those in the second embodiment.

  According to the third embodiment, the n-type AlInAs layer 71 and the extended portion 72a of the lower cladding layer 72 form a coupling region, and the high mesa waveguide structure 70 is formed on the n-type InP substrate 41 serving as a base. By being held, the same effect as in the first and second embodiments can be obtained.

(Fourth embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to the fourth embodiment of the present invention will be described. FIG. 6 is a cross-sectional view showing a high mesa waveguide structure according to the fourth embodiment. As shown in FIG. 6, in the high mesa waveguide structure 80 according to the fourth embodiment, as in the first embodiment, an n-type AlInAs layer 81 and an AlInAs oxide layer are formed on an n-type InP substrate 41. A low thermal conductive layer 81a, a lower clad layer 82 having an extended portion 82a below, an optical waveguide layer 44, an upper clad layer 45, and a microheater 25 are sequentially formed. Similarly to the second embodiment, the low thermal conductive layer 81a is provided directly below the high mesa waveguide structure 80, below the lower clad layer 82 having the extended portion 82a below. That is, the low thermal conductive layer 81 a is provided in a region from an exposed side end portion on one side surface of the high mesa waveguide structure 80 to a lower portion on the other side surface of the high mesa waveguide structure 80. Unlike the first, second, and third embodiments, the main surface of the n-type InP substrate 41 is formed with a recess 41a that is flush with at least one exposed end of the low thermal conductive layer 81a. . The n-type AlInAs layer 81 and the extending portion 82a of the lower cladding layer 82 form a connection region, and the high mesa waveguide structure 80 is held on the n-type InP substrate 41 serving as a base. Other configurations are the same as those of the first, second, and third embodiments.

Next, in the method of manufacturing the high mesa waveguide structure according to the fourth embodiment, an n-type InP substrate having an n-type InP buffer layer (not shown) formed thereon, as in the second embodiment. On the layer 41, an n-type AlInAs layer 81, an n-type InP layer that becomes the lower cladding layer 82, a GaInAsP layer that becomes the optical waveguide layer 44, and a p-type InP layer that becomes the upper cladding layer 45 are sequentially formed. Thereafter, an etching mask made of a SiN _x film patterned in the shape of a high mesa waveguide structure is formed on the upper surface of the p-type InP layer, and anisotropic etching is performed by a dry etching method using, for example, a chlorine-based gas. Etching is performed in a state where the lower portion of the lower cladding layer 82 remains, and then the etching mask is removed. Subsequently, unlike the second embodiment, the n-type InP substrate 41 is formed using an etching mask that covers a region including the laminated portion of the high mesa waveguide structure 80 and the extended portion 82a below the lower cladding layer 82. Dry etching is performed until a recess 41a is formed in the upper portion, specifically, an n-type InP buffer layer (not shown). As a result, one end of the n-type AlInAs layer 81 is exposed flush with the inner surface of the recess 41a. Thereafter, oxidation treatment is performed along the surface direction of the n-type AlInAs layer 81 from the exposed end portion of the n-type AlInAs layer 81 whose side surfaces are exposed, and a low thermal conductive layer 81a composed of a uniform AlInAs oxide layer is formed along the width direction. To do. Other manufacturing methods are the same as those in the second embodiment.

  According to the fourth embodiment, the n-type AlInAs layer 81 and the extending portion 82a of the lower cladding layer 82 form a coupling region, and the high-mesa waveguide structure 80 is held by the n-type InP substrate 41 serving as a base. Therefore, the same effect as the first to third embodiments can be obtained.

(Fifth embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to a fifth embodiment of the present invention will be described. FIG. 7 is a sectional view showing a high mesa waveguide structure according to the fifth embodiment. As shown in FIG. 7, in the high mesa waveguide structure 90 according to the fifth embodiment, an n-type AlInAs layer 91 and a low thermal conductive layer 91a made of an AlInAs oxide layer are formed on an n-type InP substrate 41, and a lower portion extends. A lower clad layer 92 having 92a and 92b, an optical waveguide layer 44, an upper clad layer 45, and a microheater 25 are sequentially formed and provided.

  In the extended portion 92b, which is at least one side of the extended portion of the lower cladding layer 92, an etching groove 93 in which the surface of the n-type InP substrate 41 is exposed is formed. The low thermal conductive layer 91a is formed under the high mesa waveguide structure along the width direction below the high mesa waveguide structure 90 from the exposed end portion that is the inner wall surface of the etching groove 93 in the lower layer of the extending portion 92b of the lower cladding layer 92. It is provided in an area wider than the width of the body 90. In other words, the low thermal conductive layer 91a is a region extending further outward from the lower portion of the side surface opposite to the side where the etching groove 93 is formed in the high mesa waveguide structure 90 in the lower layer of the extended portion 92a along the width direction. Is provided. An n-type AlInAs layer 91 is provided further outside the formation region of the low thermal conductive layer 91a. The n-type AlInAs layer 91 and the extended portion 92 a of the lower cladding layer 92 constitute a connection region. In this connection region, the high mesa waveguide structure 90 is held on the n-type InP substrate 41 serving as a base. Other configurations are the same as those of the third embodiment.

  Next, in the manufacturing method of the high mesa waveguide structure according to the fifth embodiment, unlike the third embodiment, the n-type portion 92b in the lower portion of the lower cladding layer 92 is subjected to n by, for example, dry etching. The lower cladding layer 92 and the n-type AlInAs layer 91 are removed by etching until the surface of the type InP substrate 41 is exposed, thereby forming an etching groove 93. Thereafter, the n-type AlInAs layer 91 is oxidized from the end exposed at the inner wall surface of the etching groove 93. The oxidation of the n-type AlInAs layer 91 is performed until the oxidation progresses to a position further expanded outward from below the side surface opposite to the etching groove 93 of the high mesa waveguide structure 90. As a result, the n-type AlInAs layer 91 is uniformly oxidized at the lower part of the high mesa waveguide structure 90, and a low heat consisting of a uniform AlInAs oxide layer in a wider area than the high mesa waveguide structure 90 along the width direction. Conductive layer 91a is formed. Other manufacturing methods are the same as those in the third embodiment.

  According to the fifth embodiment, the n-type AlInAs layer 91 and the extending portion 92a of the lower cladding layer 92 form a connection region, and the high mesa waveguide structure 90 is formed on the n-type InP substrate 41 serving as a base. By being held, the same effect as the first to fourth embodiments can be obtained.

(Sixth embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to a sixth embodiment of the present invention will be described. FIG. 8 is a sectional view showing a high mesa waveguide structure according to the sixth embodiment. As shown in FIG. 8, in the high mesa waveguide structure 100 according to the sixth embodiment, a low thermal conductive layer 101a made of an n-type AlInAs layer 101 and an AlInAs oxide layer is formed on an n-type InP substrate 41, and a lower portion is extended. A lower clad layer 102 having 102a and 102b, an optical waveguide layer 44, an upper clad layer 45, and a microheater 25 are sequentially formed and provided.

  An etching groove 103 in which the low thermal conductive layer 101a is exposed is formed in the extended portion 102b on at least one side of the lower cladding layer 102. The low thermal conductive layer 101a is formed below the width of the high mesa waveguide structure 100 along the width direction below the high mesa waveguide structure 100 from the exposed portion of the etching groove 103 in the lower layer of the extended portion 102a of the lower cladding layer 102. Is also provided in a wide area. That is, the low thermal conductive layer 101a is a region that extends further outward from the lower portion of the side surface opposite to the side on which the etching groove 103 is formed in the high mesa waveguide structure 100 in the lower layer of the extended portion 102a along the width direction. Is provided. An unoxidized n-type AlInAs layer 101 is provided further outside the formation region of the low thermal conductive layer 101a. The n-type AlInAs layer 101 and the extended portion 102a of the lower cladding layer 102 constitute a connection region. In this connection region, the high mesa waveguide structure 100 is held on the n-type InP substrate 41 serving as a base. Other configurations are the same as those of the fifth embodiment.

  Next, in the method of manufacturing the high mesa waveguide structure according to the sixth embodiment, unlike the fifth embodiment, an extension mask 102b below the lower cladding layer 102 is used, for example, with an etching mask having a channel shape. Perform dry etching. Thereby, a part of the lower clad layer 102 and the n-type AlInAs layer 101 is removed by etching, and an etching groove 103 is formed. Thereafter, the n-type AlInAs layer 101 exposed on the inner wall surface of the etching groove 103 is oxidized from the exposed end. The oxidation of the n-type AlInAs layer 101 is performed until the oxidation progresses to a position further expanded outward from below the side surface opposite to the etching groove 103 of the high mesa waveguide structure 100. As a result, the n-type AlInAs layer 101 is uniformly oxidized in the lower portion of the high mesa waveguide structure 100, and the low heat composed of a uniform AlInAs oxide layer is formed in a wider area than the high mesa waveguide structure 100 along the width direction. Conductive layer 101a is formed. Other manufacturing methods are the same as those in the fifth embodiment.

  According to the sixth embodiment, the n-type AlInAs layer 101 and the extended portion 102a of the lower cladding layer 102 form a connection region, and the high mesa waveguide structure 100 is formed on the n-type InP substrate 41 serving as a base. By being held, the same effects as those of the first to fifth embodiments can be obtained.

(Seventh embodiment)
Next, a semiconductor optical device according to a seventh embodiment of the present invention will be described. As shown in FIG. 9, in the high mesa waveguide structure 110 according to the seventh embodiment, an n-type AlInAs layer is formed on an n-type InP substrate 41 having an n-type InP buffer layer (not shown) provided thereon. 111, a first low thermal conductive layer 111a, an n-type InP layer 112, an n-type AlInAs layer 113, and a second low thermal conductive layer 113a are sequentially formed. The first low thermal conductive layer 111 a is made of an AlInAs oxide layer and has a configuration sandwiched between the n-type InP substrate 41 and the n-type InP layer 112. Similar to the first embodiment, a lower cladding layer 43, an optical waveguide layer 44, an upper cladding layer 45, and a microheater 25 are sequentially formed on the second low thermal conductive layer 113a.

  The second low thermal conductive layer 113a is made of an AlInAs oxide layer, and has a configuration sandwiched between an n-type InP layer 112 as a second semiconductor layer and a lower cladding layer 43 made of an n-type InP layer. By the first low thermal conductive layer 111a, the n-type InP layer 112, and the second low thermal conductive layer 113a, a low thermal conductive layer substantially equivalent to the total thickness of the first low thermal conductive layer 111a and the second low thermal conductive layer 113a is formed. Composed. In addition, the unoxidized n-type AlInAs layers 111 and 113, the n-type InP layer 112, and the extending portion 43 a of the lower cladding layer 43 constitute a coupling region. In this connection region, the high mesa waveguide structure 110 is held on the n-type InP substrate 41 serving as a base. Other configurations are the same as those of the first embodiment.

  Next, a method for manufacturing the high mesa waveguide structure 110 shown in FIG. 9 will be described. That is, the n-type AlInAs layer 111, the n-type InP layer 112, and the n-type AlInAs layer 113 are sequentially formed on the n-type InP substrate 41 provided with an n-type InP buffer layer (not shown) as an upper layer, for example, by MOCVD. Form. Thereafter, similarly, an n-type InP layer that becomes the lower cladding layer 43, a GaInAsP layer that becomes the optical waveguide layer 44, and a p-type InP layer that becomes the upper cladding layer 45 are sequentially formed on the n-type AlInAs layer 113 by MOCVD. To do.

Next, for example, a SiN _x film is formed on the upper surface of the p-type InP layer to be the upper cladding layer 45 and patterned into the shape of the high mesa waveguide structure 110. Subsequently, anisotropic etching is performed using the SiN _x film as a mask by dry etching using, for example, a chlorine-based gas until the lower portion of the lower cladding layer 43 remains, and then the etching mask is removed. Subsequently, an etching mask is formed in a region including the stacked portion of the high mesa waveguide structure 110 and the extended portion 43 a below the lower cladding layer 43. Thereafter, the n-type AlInAs layer 113, the n-type InP layer 112, and the n-type AlInAs layer 111 are sequentially etched by, for example, a dry etching method using a chlorine-based gas until the upper surface of the n-type InP substrate 41 is exposed. As a result, the side surfaces of the n-type AlInAs layers 111 and 113 are exposed.

  Thereafter, as in the first embodiment, a uniform AlInAs oxide layer is formed by performing oxidation from the exposed end surface of the n-type AlInAs layers 111 and 113. The oxidation of the n-type AlInAs layers 111 and 113 is continued until the oxidation progresses further to the outside of the side surface opposite to the exposed surface of the n-type AlInAs layers 111 and 113 in the high mesa waveguide structure 110. Run. The n-type AlInAs layers 111 and 113 are uniformly oxidized in a region wider than the high mesa waveguide structure 110 along the width direction in the lower portion of the high mesa waveguide structure 110. Thereby, the first low thermal conductive layer 111a and the second low thermal conductive layer 113a made of a homogeneous AlInAs oxide layer are formed. The oxidation conditions for the n-type AlInAs layers 111 and 113 and the manufacturing method of the lower cladding layer 43, the optical waveguide layer 44, the upper cladding layer 45, and the microheater 25 are the same as in the first embodiment.

In the seventh embodiment, a plurality of layers, specifically two layers, are provided in a state where an AlInAs layer as an oxidized layer is sandwiched between InP layers. Thereby, the n-type InP layer 112, the first low thermal conductive layer 111a, and the second low thermal conductive layer 113a can function as the low thermal conductive layer. That is, the low thermal conductive layer may be configured to have at least one Al _{1 -xy} Ga _x In _y As _{1 -z Pz} layer. Therefore, even when there is a limit to the allowable film thickness when oxidizing like the AlInAs layer, the same function as that of the low thermal conductive layer having a large film thickness can be obtained. Furthermore, in order to ensure the heat insulation efficiency desired as the low thermal conductive layer, a predetermined number of AlInAs oxide layers of three or more layers are provided via other semiconductor layers such as an InP layer to constitute the low thermal conductive layer. It is also possible.

  In the seventh embodiment, the other semiconductor layer sandwiching the n-type AlInAs layers 111 and 113 is the n-type InP substrate 41, the n-type InP layer 112, and the lower cladding layer 43 composed of the n-type InP layer. It is also possible to use a semiconductor layer other than the n-type InP layer as the other semiconductor layer. As another semiconductor layer, it is substantially lattice-matched to the n-type InP substrate 41, has an oxidation rate selection ratio as large as possible with respect to the oxidation rate of the AlInAs layer, and has a wavelength of light transmitted through the optical waveguide layer 44. On the other hand, it is desirable to make it from a material having a transparent band gap. Specifically, as the other semiconductor layer, for example, a GaInAsP layer, a GaInAs layer, an AlGaInAs layer, an AlGaInAsP layer, or a multilayer film thereof can be used.

  According to the seventh embodiment, the n-type AlInAs layers 111 and 113, the n-type InP layer 112, and the extended portion 43 a of the lower cladding layer 43 form a connection region, and the n-type InP substrate 41 serving as a base is formed. By holding the high mesa waveguide structure 110, the same effects as those of the first to sixth embodiments can be obtained.

(Eighth embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to an eighth embodiment of the present invention will be described. Here, the problem that the present inventor has intensively studied will be described. That is, when forming a high mesa waveguide structure, generally, the thickness of the core layer of the optical waveguide having a wavelength of 1.55 μm is several hundred nm (for example, 300 nm), and the upper cladding layer and the lower cladding layer sandwiching the optical waveguide. Each film thickness is designed to be about 1500 nm. In this case, the total height of the high mesa waveguide structure may be 3.0 μm or more. That is, in forming the high mesa waveguide structure, an etching depth of 3.0 μm or more is required, and thus the etching depth needs to be precisely controlled. If the etching depth cannot be controlled precisely, the height of the mesa structure in the semiconductor substrate, that is, the in-plane distribution of the etching depth may occur or the semiconductor substrate may vary. This is a problem. The eighth embodiment described below is for solving the above-described problem.

  FIG. 10 is a cross-sectional view showing a high mesa waveguide structure according to the eighth embodiment. As shown in FIG. 10, in the high mesa waveguide structure 120 according to the eighth embodiment, on the n-type InP substrate 41, the n-type AlInAs layer 121, the low thermal conductive layer 121a made of the AlInAs oxide layer, and the GaInAsP layer are made. An etching stop layer 122 is stacked. On the etching stop layer 122, a lower cladding layer 123, an optical waveguide layer 44, an upper cladding layer 45, and a microheater 25 are sequentially formed.

  An etching groove 122 a where the surface of the n-type InP substrate 41 is exposed is formed in the low thermal conductive layer 121 a and the etching stop layer 122. The low thermal conductive layer 121a is provided in a region below the etching stop layer 122 and from the exposed end portion, which is the inner wall surface of the etching groove 122a, to the lower portion of the other side surface of the high mesa waveguide structure 120. That is, the low thermal conductive layer 121a is provided in a region from the exposed side end portion on one side where the etching groove 122a is formed in the high mesa waveguide structure 120 to the lower portion on the other side surface on the opposite side. An n-type AlInAs layer 121 is provided further outside the formation region of the low thermal conductive layer 121a. The n-type AlInAs layer 121 and the etching stop layer 122 constitute a connection region. In this connection region, the high mesa waveguide structure 120 is held on the n-type InP substrate 41 serving as a base. Other configurations are the same as those of the third and fifth embodiments.

Next, a method for manufacturing a high mesa waveguide structure according to the eighth embodiment will be described. In the eighth embodiment, in the same manner as in the second embodiment, an n-type AlInAs layer 121, an etching stop are formed on an n-type InP substrate 41 on which an n-type InP buffer layer (not shown) is formed. The layer 122, the n-type InP layer that becomes the lower clad layer 123, the GaInAsP layer that becomes the optical waveguide layer 44, and the p-type InP layer that becomes the upper clad layer 45 are sequentially formed. Since the etching stop layer 122 is preferably made of a material having etching selectivity with respect to the material of the semiconductor layer formed thereon, in the eighth embodiment, for example, it is a GaInAsP layer. Thereafter, an etching mask made of a SiN _x film patterned in a predetermined shape is formed on the upper surface of the p-type InP layer, and anisotropic etching is performed by, for example, a dry etching method using a chlorine-based gas. In this case, the position (etching depth) with the n-type InP layer provided in the upper layer can be confirmed by monitoring the Ga signal with a plasma monitor. Thereby, the accuracy of stopping etching can be improved, and the high mesa waveguide structure 120 can be manufactured with good controllability.

  When etching the high mesa waveguide structure 120 by a wet etching method, the etching can be selectively stopped by using an etching material having etching selectivity with respect to the InP layer. Specifically, in the wet etching method of the InP layer constituting the upper lower cladding layer 123 and the GaInAsP layer constituting the etching stop layer 122, it is desirable to use a hydrochloric acid-based etching solution.

  Thereafter, in the same manner as in the fifth embodiment, the etching stop layer 122 and the n-type AlInAs layer 121 are etched away by, for example, dry etching until the surface of the n-type InP substrate 41 is exposed. A groove 122a is formed. Thereafter, the n-type AlInAs layer 121 is oxidized from the exposed end of the inner wall surface of the etching groove 122a. The oxidation of the n-type AlInAs layer 121 is performed until the oxidation proceeds to a position below the side surface opposite to the etching groove 122a of the high mesa waveguide structure 120. As a result, the n-type AlInAs layer 121 is uniformly oxidized at the lower part of the high mesa waveguide structure 120, and the uniform AlInAs oxidation is performed in a region along the width direction to the lower part of the other side surface of the high mesa waveguide structure 120. A low thermal conductive layer 121a composed of layers is formed. Other manufacturing methods are the same as those in the second and fifth embodiments.

  According to the eighth embodiment, the same effect as in the first to seventh embodiments can be obtained. Furthermore, when the high mesa waveguide structure 120 is formed by etching, the etching can be performed with high accuracy. Even when the high mesa waveguide structure 120 is formed on the semiconductor substrate, the high mesa structure in the semiconductor substrate can be formed. Since the in-plane distribution and the variation between the semiconductor substrates can be improved, the manufacturing yield of the semiconductor optical device can be improved.

(Ninth embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to a ninth embodiment of the present invention is described. FIG. 11 is a cross-sectional view showing a high mesa waveguide structure according to the ninth embodiment. As shown in FIG. 11, in the high mesa waveguide structure 130 according to the ninth embodiment, unlike the first embodiment, the low thermal conduction region is adjacent to the n-type AlInAs layer 131 instead of the low thermal conduction layer. The coplanar region is constituted by a low thermal conduction cavity 132 having a cavity structure filled with air. In this case, the n-type AlInAs layer 131 and the extending portion 133a of the lower cladding layer 133 form a coupling region, and the high-mesa waveguide structure 130 is held on the n-type InP substrate 41 by this coupling region. Other configurations are the same as those of the first embodiment.

In the manufacturing method of the high mesa waveguide structure according to the ninth embodiment, first, similarly to the first embodiment, on the n-type InP substrate 41, the n-type AlInAs layer 131, the lower cladding layer 133, the optical waveguide The wave layer 44 and the upper cladding layer 45 are sequentially laminated. Thereafter, an etching mask made of a SiN _x film patterned in a predetermined shape is formed on the upper surface of the p-type InP layer that becomes the upper cladding layer 45. Subsequently, anisotropic etching is performed halfway through the lower cladding layer 133 by a dry etching method using this etching mask, and then one end of the n-type AlInAs layer 131 is exposed by a dry etching method. Subsequently, the n-type AlInAs layer 131 under the high mesa waveguide structure 130 in the n-type AlInAs layer 131 is selectively etched by a wet etching method using a hydrofluoric acid-based etchant. The low thermal conduction cavity 132 is formed by the cavity formation process as the low thermal conduction process. Note that one end of the n-type AlInAs layer 131 is exposed, and an oxidation process is performed in the same manner as in the first embodiment to form an AlInAs oxide layer. Then, the AlInAs oxide layer is formed using a hydrofluoric acid-based etching solution. It is also possible to selectively etch away to form a low thermal conduction cavity 132. In addition, since the low thermal conduction cavity 132 is formed by selectively etching the upper and lower InP layers, the InP layers such as GaInAs layers, GaInAsP layers, and AlGaInAs layers are etched instead of the n-type AlInAs layers 131. A material having a high selectivity and which can be formed on the n-type InP substrate 41 can be used. Other manufacturing methods are the same as those in the first embodiment.

  According to the ninth embodiment, the n-type AlInAs layer 131 and the extending portion 133a of the lower cladding layer 133 form a coupling region, and the high-mesa waveguide structure 130 is held on the n-type InP substrate 41 by this coupling region. Thus, the same effects as those of the first to eighth embodiments can be obtained. In addition, by providing the microheater 25 and the low thermal conduction cavity 132, the same effect as that of the first embodiment by providing the low thermal conduction region can be obtained.

  The connection region in the first to ninth embodiments described above is provided in the entire region or a partial region in the high mesa waveguide structure in which the low heat conduction region is provided in the lower part of the striped or ring-shaped waveguide. It only has to be done.

(Tenth embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to a tenth embodiment of the present invention is described. 12A and 12B are a plan view and a cross-sectional view showing the high mesa waveguide structure according to the tenth embodiment. FIG. 12A is a top view of the high mesa waveguide structure, and FIG. ) Of FIG. 12B is a cross-sectional view taken along line BB, and FIG. 12C is a cross-sectional view taken along line CC of FIG.

  As shown in FIGS. 12A to 12C, the high mesa waveguide structure 200 according to the tenth embodiment is formed in a stripe shape. Similar to the first embodiment, the high mesa waveguide structure 200 includes an n-type AlInAs layer 202 and an AlInAs oxide layer on an n-type InP substrate 201 on which an n-type InP buffer layer (not shown) is formed. A low thermal conductive layer 202a, a lower clad layer 203, an optical waveguide layer 204, an upper clad layer 205, and a microheater 206 are sequentially formed and provided. The lower cladding layer 203 and the low thermal conductive layer 202a on both sides of the high mesa waveguide structure 200 that are parallel to the longitudinal direction of the stripe shape of the high mesa waveguide structure 200 (light waveguide direction) and along the width direction of the stripe. Etching grooves 203a and 203b are provided in this portion. The microheater 206 provided on the upper part of the high mesa waveguide structure 200 is preferably on the inner side so as to at least partially overlap with the arrangement region of the low thermal conductive layer 202a along the surface direction of the n-type InP substrate 201. Are arranged as follows. Thereby, the heat generated by the microheater 206 can be efficiently confined in the optical waveguide layer 204, and the outflow of heat to the n-type InP substrate 201 side can be suppressed.

  Further, as shown in FIG. 12B, the lower clad layer 203 is extended along the surface direction of the n-type InP substrate 201 on both sides along the width direction of the high mesa waveguide structure 200 at the lower portion of the lower clad layer 203. An extending portion 203c is provided. Further, as shown in FIG. 12C, the non-oxidized n-type AlInAs layer 202 of the low mesoconductive layer 202a is formed along the stripe-shaped longitudinal direction (light guiding direction) of the high mesa waveguide structure 200. It is provided on both sides. As a result, the n-type AlInAs layer 202 and the lower cladding layer 203 constitute a coupling region. In this connection region, the high mesa waveguide structure 200 is held on the n-type InP substrate 201 serving as a base. By providing the connection region, a decrease in the bonding strength of the high mesa waveguide structure 200 in the upper layer of the low thermal conductive layer 202a is suppressed. Other configurations are the same as those of the first and fifth embodiments.

  In the manufacturing method of the high mesa waveguide structure according to the tenth embodiment, first, the middle of the lower clad layer 203 is etched so as to leave the extended portion 203c in the lower portion, as in the fifth embodiment. In the extended portion 203c below the lower cladding layer 203, the lower portion of the lower cladding layer 203 and the n-type AlInAs are exposed by dry etching using an etching mask having a stripe-shaped opening until the surface of the n-type InP substrate 201 is exposed. Etch layer 202. Thereby, etching grooves 203a and 203b are formed. Here, the length along the longitudinal direction of the etching grooves 203 a and 203 b is preferably equal to or longer than the length along the longitudinal direction of the microheater 206. Thereafter, the n-type AlInAs layer 202 is oxidized from the exposed portions on the inner wall surfaces of the etching grooves 203a and 203b. The oxidation of the n-type AlInAs layer 202 proceeds in the surface direction from the etching grooves 203a and 203b, and the region of the dot portion in FIG. 12A is oxidized. As a result, the n-type AlInAs layer 202 is uniformly oxidized at the lower part of the high mesa waveguide structure 200, and the homogeneous AlInAs oxide layer is formed in a region having a width wider than the high mesa waveguide structure 200 along the width direction. Thus, a low thermal conductive layer 202a is formed.

  In order to advance the oxidation and reduce the time of the oxidation process, it is preferable to form the two etching grooves 203a and 203b on both sides along the width direction of the high mesa waveguide structure 200. It is also possible to form only one of the grooves 203a and 203b. In this case, the low thermal conductive layer 202a can be formed in a desired region by adjusting the annealing time to be longer in the subsequent oxidation step. Further, when the two etching grooves 203a and 203b are formed on both sides along the width direction of the high mesa waveguide structure 200, the progress of oxidation is delayed over the entire longitudinal direction of the waveguide, or partially, It is also possible to form a non-oxidized region, that is, a region for forming the n-type AlInAs layer 202 in the low thermal conductive layer 202a made of an AlInAs oxide layer. Thereby, mechanical strength can be further improved. In this case, since the thermal confinement effect may be reduced, it is necessary to pay attention to the size of the non-oxidized region in the low thermal conductive layer 202a. Other manufacturing methods are the same as those in the first and fifth embodiments.

  According to the tenth embodiment, both ends of the stripe-shaped longitudinal direction (light guiding direction) of the high-mesa waveguide structure 200 in which the low thermal conduction region is formed at the lower portion are the n-type AlInAs layer 202 and the lower portion. This is a connection region constituted by the clad layer 203. Thereby, since the high mesa waveguide structure 200 can be held on the n-type InP substrate 201, the same effects as those of the first to ninth embodiments can be obtained. Further, etching grooves 203 a and 203 b in which the n-type AlInAs layer 202 is exposed are formed on both sides of the high mesa waveguide structure 200 along the width direction. As a result, the oxidation of the n-type AlInAs layer 202 below the optical waveguide layer 204 proceeds from both sides along the width direction of the high mesa waveguide structure 200, so that the etching groove is provided only on one side. Thus, the oxidation treatment time can be shortened to about half.

(Eleventh embodiment)
Next, a high mesa waveguide structure in a semiconductor optical device according to an eleventh embodiment of the present invention is described. 13A and 13B are a plan view and a cross-sectional view showing the high mesa waveguide structure according to the eleventh embodiment. FIG. 13A is a top view of the high mesa waveguide structure, and FIG. It is sectional drawing along the BB line of FIG.

  As shown in FIG. 13A, the high mesa waveguide structure 250 according to the eleventh embodiment is formed in a ring shape. Etching in a partial ring shape in the direction along the ring shape of the high mesa waveguide structure 250 (light guiding direction) and on the outer peripheral side of the high mesa waveguide structure 250 along the width direction of the ring-shaped waveguide A groove 253a is provided. Around the etching groove 253a, a region of the low thermal conductive layer 252a is provided along the shape of the etching groove 253a. Although the etching groove 253a is formed only on the outer peripheral side of the ring-shaped high mesa waveguide structure 250, it may be formed only on the inner peripheral side or on both inner and outer peripheral sides.

  As shown in FIG. 13B, the high mesa waveguide structure 250 is formed on an n-type InP substrate 251 having an n-type InP buffer layer (not shown) formed thereon as in the first embodiment. A low thermal conductive layer 252a composed of an n-type AlInAs layer 252 and an AlInAs oxide layer, a lower cladding layer 253, an optical waveguide layer 254, an upper cladding layer 255, and a microheater 256 are sequentially formed. Under the lower clad layer 253, extending portions 253 c extending along the surface direction of the n-type InP substrate 251 are provided on both sides along the width direction of the high mesa waveguide structure 250. The etching groove 253a is formed in the extending portion 253c and the low thermal conductive layer 252a below the lower cladding layer 253. An n-type AlInAs layer 252 is provided in a region where the low thermal conductive layer 252a is not formed.

  As shown in FIGS. 13A and 13B, the microheater 256 provided on the high mesa waveguide structure 250 is arranged along the surface direction of the n-type InP substrate 251 in the arrangement region of the low thermal conductive layer 252a. Are preferably arranged in a partial ring shape so as to be inside the region where the low thermal conductive layer 252a is formed. Thereby, the heat generated by the microheater 256 can be efficiently confined in the optical waveguide layer 254. Further, in the formation region of the high mesa waveguide structure 250, the portion other than the formation region of the low thermal conductive layer 252a (the dotted portion in FIG. 13A) is the lower portion of the high mesa waveguide structure 250 and is oxidized. This is a non-oxidized region where no n-type AlInAs layer 252 is provided. The n-type AlInAs layer 252 and the lower cladding layer 253 including this non-oxidized region constitute a coupling region. In this connection region, the high mesa waveguide structure 250 is held on the n-type InP substrate 251 serving as a base. Here, the non-oxidized region in the lower portion of the high mesa waveguide structure 250 rotates n times with respect to the ring-shaped center of the high mesa waveguide structure 250 in consideration of the stress generated in the formation of the high mesa waveguide structure 250. It is preferably provided at a symmetrical position (n is an integer of 2 or more). In the eleventh embodiment, the non-oxidized region is provided at an arrangement position that is twice rotationally symmetric. By the connection region including the non-oxidized region, a decrease in the bonding strength of the high mesa waveguide structure 250 in the upper layer of the low thermal conductive layer 252a is suppressed. Other configurations and manufacturing methods are the same as those in the first, fifth, and tenth embodiments.

  According to the eleventh embodiment, the ring-shaped high mesa waveguide structure 250 in which the low heat conduction region is formed in the lower portion is partially formed in the light guiding direction. In the connection region constituted by the n-type AlInAs layer 252 and the lower clad layer 253, the high-mesa waveguide structure 250 is held on the n-type InP substrate 251 serving as a base, so that the first to tenth embodiments Similar effects can be obtained. Further, as in the tenth and eleventh embodiments, it can be applied to straight waveguides and curved or ring-shaped waveguides, so that it can be applied to single elements or integrated elements having various functions. It becomes possible.

(Twelfth embodiment)
Next, an integrated semiconductor optical device according to a twelfth embodiment to which the present invention is applicable will be described. FIG. 14 is a sectional view showing a wavelength tunable laser device that is an integrated semiconductor optical device according to the twelfth embodiment.

  As shown in FIG. 14, in the integrated semiconductor laser device 300 that is a wavelength tunable laser device according to the twelfth embodiment, a first sampled grating waveguide portion 301 that is a DBR (Distributed Bragg Reflector) mirror as a back mirror. , A phase adjustment waveguide section 302, a gain waveguide section 303, a second sampled grating waveguide section 304 which is a DBR mirror as a front mirror, and a semiconductor optical amplifier (SOA) 305.

  In the integrated semiconductor laser device 300, a passive region is configured by the first sampled grating waveguide portion 301, the phase adjustment waveguide portion 302, and the second sampled grating waveguide portion 304 as passive elements. The first sampled grating waveguide part 301, the phase adjustment waveguide part 302, and the second sampled grating waveguide part 304 have a high mesa structure. An active region is constituted by the gain waveguide section 303 and the SOA 305 as active elements. The gain waveguide section 303 and the SOA 305 have a buried structure.

  In the integrated semiconductor laser device 300, an n-type AlInAs layer 320, a lower cladding layer 330, a core layer 340, and an upper cladding layer 350 are sequentially formed on the main surface of an n-type InP substrate 310. On the upper surface of the upper cladding layer 350, a p-side electrode 361 is selectively provided in the active region via an InGaAs contact layer (not shown), and a micro heater 362 is selectively provided in the passive region. ing. An n-side electrode 370 is provided on the back surface of the n-type InP substrate 310. A non-reflective film 380 is provided on the laser light emission end face of the laminated body of the n-type InP substrate 310, the n-type AlInAs layer 320, the lower cladding layer 330, the core layer 340, and the upper cladding layer 350. Here, the film thickness of the n-type AlInAs layer 320 is determined in the same manner as in the first embodiment, and is 0.5 times or more and less than 1.5 times the optimum film thickness obtained in advance by an oxidation experiment. The film thickness is preferably set to 1.3 times or less. In the twelfth embodiment, the thickness of the n-type AlInAs layer 320 is, for example, 100 nm.

  In the phase adjustment waveguide section 302 in the passive region, a low thermal conductive layer 321, a lower cladding layer 330, a waveguide core layer 343, an upper cladding layer 350, and a microheater 362 are sequentially formed on the main surface of the n-type InP substrate 310. Has been. The n-type InP substrate 310 is provided with an n-side electrode 370 on the back surface. The low thermal conductive layer 321 is composed of an oxidized n-type AlInAs layer. The low thermal conductive layer 321 is provided in at least a part or the entire lower layer of the phase adjustment waveguide section 302. The lower cladding layer 330 is composed of an n-type InP layer as an n-type semiconductor layer, and the upper cladding layer 350 is composed of a p-type InP layer as a p-type semiconductor layer. The waveguide core layer 343 is made of a GaInAsP layer whose band gap wavelength is adjusted to 1.3 μm, for example.

  The first sampled grating waveguide part 301 and the second sampled grating waveguide part 304 in the passive region are formed on the main surface of the n-type InP substrate 310 on the low thermal conductive layer 321, the lower cladding layer 330, the grating layer 342, and the upper part. A clad layer 350 and a microheater 362 are sequentially formed. The n-type InP substrate 310 provided with the n-side electrode 370 on the back surface is shared with the phase adjustment waveguide section 302. The low thermal conductive layer 321 is composed of an oxidized n-type AlInAs layer 320. The low thermal conductive layer 321 is provided in at least a part or the entire lower layer of the first sampled grating waveguide unit 301 and the second sampled grating waveguide unit 304. The lower cladding layer 330 is composed of an n-type InP layer as an n-type semiconductor layer. The upper cladding layer 350 is made of a p-type InP layer as a p-type semiconductor layer. The grating layer 342 is made of a GaInAsP layer in which grating regions in which short-period gratings are formed are arranged at a predetermined period.

  The gain waveguide section 303 and the SOA 305 in the active region are formed on the main surface of the n-type InP substrate 310 by an n-type AlInAs layer 320, a lower cladding layer 330, an active layer 341, an upper cladding layer 350, and an InGaAs contact layer (not shown). The p-side electrode 361 is formed in sequence. The n-type InP substrate 310, the lower cladding layer 330, and the upper cladding layer 350 are shared with the first sampled grating waveguide unit 301, the phase adjustment waveguide unit 302, and the second sampled grating waveguide unit 304. . The n-type AlInAs layer 320 is a non-oxidized non-oxidized region of the low thermal conductive layer 321. The active layer 341 is composed of a GaInAsP layer having a multiple quantum well (MQW) structure.

  In addition, an unoxidized n-type AlInAs layer 320 is provided between the low thermal conductive layers 321 along the longitudinal direction of the light guiding direction in the integrated semiconductor laser device 300. As a result, the n-type AlInAs layer 320 and the lower cladding layer 330 form a connection region. In this connection region, the high-mesa waveguide structure provided above the n-type AlInAs layer 320 is held on the n-type InP substrate 310 serving as a base. Thereby, the fall of the joint strength of the high mesa waveguide structure in the upper layer of the low thermal conductive layer 321 is suppressed.

  According to the twelfth embodiment, the high-mesa waveguide structure provided on the n-type InP substrate 310 above the n-type AlInAs layer 320 by the coupling region constituted by the n-type AlInAs layer 320 and the lower cladding layer 330. By holding the body, the same effects as those of the first to eleventh embodiments can be obtained. In the integrated semiconductor laser device 300, the low thermal conductive layer 321 in which the n-type AlInAs layer 320 is oxidized is provided between the microheater 362 and the n-type InP substrate 310 along the waveguide direction. Thus, the heat generated by the micro heater 362 can be efficiently confined. Furthermore, in the passive region of the integrated semiconductor laser device 300 according to the twelfth embodiment, it is possible to apply the configuration of a plurality of low thermal conductive layers according to the seventh embodiment.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible. For example, the numerical values given in the above embodiment are merely examples, and different numerical values may be used as necessary.

Further, in the above-described embodiment, the n-type AlInAs layer 42 is composed of AlInAs having a single composition, but it is not necessarily required to have a single composition. _{Specifically, Al 1-xy Ga x In} y As 1-z P z layer and the _{Al 1-pq Ga p In q} As 1-r P r layer (0 <x + y <1,0 <p + q <1, x A structure of so-called distortion compensation in which ≠ p, y ≠ q, z ≠ r) are alternately stacked may be used.

  In the above-described embodiment, the low thermal conductive layer 321 is composed of an AlInAs oxide layer obtained by oxidizing one n-type AlInAs layer 320, but is not necessarily limited to one layer. Specifically, a low thermal conductive layer can be configured by providing a plurality of AlInAs layers as layers to be oxidized sandwiched between semiconductor layers having other compositions such as an InP layer. Furthermore, the low thermal conductive layer 321 can be formed of a cavity, and in this case, the same effect as described above can be obtained.

DESCRIPTION OF SYMBOLS 1 Wavelength variable laser element 10 1st waveguide part 11 Waveguide part 11a Diffraction grating loading type gain part 11aa Active core layer 11ab Diffraction grating layer 11b Phase adjustment part 12 Semiconductor laminated part 13,361 p side electrode 14,15,25 , 206, 256, 362, 406 Microheater 20 Second waveguide portion 21 Bifurcated portion 21 a Waveguide 22, 23 Arm portion 24 Ring-shaped waveguide 30, 370 n-side electrode 41, 201, 251, 310, 401 n Type InP substrate 41a Recess 42, 61, 71, 81, 91, 101, 111, 113, 121, 131, 202, 252, 320 n-type AlInAs layer 42a, 61a, 71a, 81a, 91a, 101a, 121a, 202a, 252a, 321, 402 Low heat conductive layer 43, 62, 72, 82, 92, 102, 12 3, 133, 203, 253, 330, 403 Lower cladding layer 43a, 62a, 72a, 82a, 92a, 92b, 102a, 102b, 133a, 203c, 253c Extending portions 44, 204, 254, 404 Optical waveguide layers 45, 205 255, 350, 405 Upper clad layer 46 Dielectric layer 48 Resin layer 49 Lead-out wiring 60, 70, 80, 90, 100, 110, 120, 130, 200, 250, 400 High mesa waveguide structure 93, 103, 122a , 203a, 203b, 253a Etching groove 111a First low thermal conduction layer 112 n-type InP layer 113a Second low thermal conduction layer 122 Etching stop layer 132 Low thermal conduction cavity 220 High mesa waveguide structure 300 Integrated semiconductor laser device 301 First sampled Grating waveguide Part 302 Phase adjustment waveguide part 303 Gain waveguide part 304 Second sampled grating waveguide part 340 Core layer 341 Active layer 342 Grating layer 343 Waveguide core layer 380 Non-reflective film 407 Void C1 Laser resonator L1 Laser light M1 Reflection Mirror RF1 Ring resonant filter

Claims (14)

Above the semiconductor substrate,
A first semiconductor layer made of a material substantially lattice-matched to the semiconductor substrate, and a low thermal conduction region provided on the same plane as the first semiconductor layer;
A second semiconductor layer provided on an upper layer of the first semiconductor layer and the low thermal conductivity region and connected to the first semiconductor layer;
A waveguide layer provided in an upper layer of the low thermal conductivity region;
And a heating section provided in an upper layer of the waveguide layer.   2. The semiconductor optical device according to claim 1, wherein an arrangement region along a plane direction of the low thermal conduction region and an arrangement region of the heating unit overlap at least partially.   3. The semiconductor optical device according to claim 1, wherein the first semiconductor layer is provided on at least a part of the waveguide layer along a waveguide direction. 4.   The high mesa waveguide structure which has the said waveguide layer is provided in the area | region narrower than the arrangement | positioning area | region along the surface direction of the said low heat conductive area | region, The any one of Claims 1-3 characterized by the above-mentioned. Semiconductor optical device.   5. The semiconductor optical device according to claim 4, wherein the low thermal conduction region has at least one portion that is flush with the side surface on a lower side surface of the high mesa waveguide structure.   The high mesa waveguide structure includes a ring-shaped waveguide, and the arrangement position where the first semiconductor layer is disposed below the high mesa waveguide structure along the surface direction of the semiconductor substrate is the ring shape. 6. The semiconductor optical device according to claim 4, wherein the semiconductor optical device is n times rotationally symmetric (n is an integer of 2 or more) with respect to the center of the semiconductor optical device.   An etching stop layer connected to the first semiconductor layer and the second semiconductor layer and having etching selectivity with respect to the second semiconductor layer is provided above the low thermal conductivity region and the first semiconductor layer. The semiconductor optical device according to claim 1, wherein:   8. The low heat conduction region includes an oxide layer formed by oxidizing at least one first semiconductor layer substantially lattice-matched to the semiconductor substrate. Semiconductor optical device. The semiconductor substrate is an InP substrate, and the first semiconductor layer is an Al _1-xy Ga _x In _y As _1-z P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, The semiconductor optical device according to claim 1, wherein 0 ≦ z <1).   The semiconductor optical device according to claim 1, wherein the low thermal conductivity region is formed of a cavity. Above the semiconductor substrate,
A first semiconductor layer made of a material substantially lattice-matched to the semiconductor substrate;
After sequentially stacking a second semiconductor layer connected to the first semiconductor layer on the first semiconductor layer,
In a state where the first semiconductor layer and the second semiconductor layer are connected, a low thermal conductivity treatment is performed on a part of the first semiconductor layer along the surface direction of the first semiconductor layer to reduce the thermal conductivity. A method for manufacturing a semiconductor optical device, comprising the step of forming a region.   12. The method of manufacturing a semiconductor optical device according to claim 11, wherein the low thermal conductivity treatment is an oxidation treatment that oxidizes a part of the first semiconductor layer along a surface direction of the first semiconductor layer. .   12. The semiconductor optical device according to claim 11, wherein the low thermal conductivity process is a cavity forming process in which a part of the first semiconductor layer is removed to form a cavity adjacent to the first semiconductor layer. Manufacturing method.   After forming the first semiconductor layer and before forming the second semiconductor layer, an etching stop layer having etching selectivity with respect to the second semiconductor layer is formed on the first semiconductor layer, and then the second semiconductor layer is formed. The method of manufacturing a semiconductor optical device according to claim 11, wherein the layer is etched.

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