JP2017163080A - Semiconductor optical element, and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve in-plane uniformity and inter-batch stability in a semiconductor layer, in a semiconductor laminate structure including a semiconductor layer having film thickness dependency of oxidation speed.SOLUTION: An AlGaInAsPlayer (0<x+y<1, 0≤x<1, 0<y<1, 0≤z<1) has film thickness dependency of oxidation speed, and the oxidation speed is maximized at a predetermined film thickness. When having a process for oxidizing an AlGaInAs layer in the surface direction, after sequentially laminating an AlGaInAsPlayer and an InP layer, composed of a material substantially lattice matching with an InP substrate, above the InP substrate, the AlGaInAsPlayer is formed with a film thickness less than 1.5 times of the predetermined film thickness maximizing the oxidation speed.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor optical device applied to the field of optical communication and the like, and a method for manufacturing the same.

  With the spread of coherent optical communication, there is an increasing demand for a tunable laser element having a narrow line width. The configuration and operating principle of the wavelength tunable laser element are described in detail in Non-Patent Document 1, for example. In general, in order to narrow the laser beam output from a semiconductor laser element, it is necessary to lengthen the resonator.

  There is a distributed Bragg reflection (DBR) type wavelength tunable laser using a sampled diffraction grating (Sampled Grating) as one of the wavelength tunable laser elements and utilizing the vernier effect (for example, Patent Document 1). In this tunable laser element, two DBR mirrors in which a part of a diffraction grating is sampled in a semiconductor element are used. The reflection spectra of these two DBR mirrors have a shape having comb-like peaks with slightly different periods. Further, the refractive index change can be caused by current injection or heating in the DBR mirror, and the reflection wavelength characteristic can be made variable. By superimposing the reflection peaks of the two DBR mirrors, a resonator can be formed with this superimposed wavelength. At this time, if the resonator length is appropriately designed, the interval between the longitudinal modes, which are the resonator modes, is approximately the same as the band of the reflection peak by the two DBR mirrors, and only one resonator mode is selected. Oscillation is realized.

  As another method for realizing a laser beam having a narrow line width, there is a method of increasing the Q value of the resonator mode by increasing the resonance length using an external resonator structure. Further, for example, in a wavelength tunable laser element (for example, Non-Patent Document 2) in which a resonator is configured by using two ring resonators, a relatively sharp superposition of the filter characteristics (reflection wavelength characteristics) of the ring resonator is used. Thus, the configuration of the resonator can be freely designed.

  In the configuration described above, the wavelength selection method is realized by changing the refractive indexes of two DBR mirrors or ring resonators by current injection or heating. Further, as described in Patent Document 2 and the like, the heating method is provided with a microheater on the waveguide in the region where the refractive index change is desired to be generated, and in order to further increase the efficiency of the heating, it is provided at the lower part of the core layer of the waveguide. By providing the low thermal conductive layer, the outflow of heat to the substrate side is suppressed. As the low thermal conductive layer for suppressing thermal conduction, a mixed crystal semiconductor layer, an oxide layer obtained by oxidizing a semiconductor layer containing aluminum (Al), or the like is used. In particular, the oxide layer is said to have a great effect as a low thermal conductive layer.

US Pat. No. 6,590,924 Japanese Patent Laying-Open No. 2015-12176

Larry A. Coldren et al., “Tunable Semiconductor Lasers: A Tutorial”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 22, NO / 1, JANUARY 2004, pp.193-202 Keita Nemoto et al., “Narrow-Spectral-Linewidth Wavelength-Tunable Laser Diode with Si Wire Waveguide Ring Resonators”, Applied Physics Express 5 (2012) 082701

  However, when the inventor conducted an oxidation experiment on the above-described semiconductor layer containing Al, specifically, an AlInAs layer, the following problems were found.

  That is, from the oxidation experiment conducted by the present inventor, the present inventor has found that the oxidation rate of the AlInAs layer depends on the film thickness. Furthermore, the present inventor also finds that the AlInAs layer has a film thickness at which the oxidation rate is maximized, and that the oxidation variation with respect to the AlInAs layer increases when the film thickness at which the oxidation rate is maximized is exceeded. It came. As a result, a portion where oxidation does not proceed at all in the AlInAs layer may occur.

When oxidation does not proceed in the AlInAs layer, it becomes difficult to obtain a low thermal conductive layer formed by oxidizing the AlInAs layer. Therefore, there is a possibility that the manufacturing yield of the semiconductor device using the AlInAs oxide layer is lowered. Furthermore, there is a possibility that the thermal confinement effect in the semiconductor element by the AlInAs oxide layer is limited due to the fact that the thickness of the AlInAs oxide layer obtained by oxidizing the AlInAs layer cannot be greater than a predetermined thickness. The above-described problem is that the Al _1-xy Ga _x In _y As _1-z P _z oxide layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1) is used as the low thermal conductive layer. The same applies to the case of using 1).

  The present invention has been made in view of the above, and an object of the present invention is to provide in-plane uniformity and batch-to-batch in an oxide layer of a semiconductor layer in a semiconductor multilayer structure having a semiconductor layer having a film thickness dependence of an oxidation rate. An object of the present invention is to provide a semiconductor optical device capable of improving stability and a method for manufacturing the same.

  In order to solve the above-described problems and achieve the above object, a method of manufacturing a semiconductor optical device according to the present invention includes a first semiconductor layer made of a material substantially lattice-matched to a semiconductor substrate above the semiconductor substrate. And a step of sequentially laminating a second semiconductor layer having a composition different from that of the first semiconductor layer on the first semiconductor layer, and then oxidizing the first semiconductor layer along the surface direction of the first semiconductor layer. The first semiconductor layer is made of a material whose oxidation rate has a film thickness dependency of the first semiconductor layer and has a maximum at a predetermined film thickness in the first semiconductor layer. Is formed to a film thickness of less than 1.5 times the predetermined film thickness.

  The method for manufacturing a semiconductor optical device according to one aspect of the present invention is characterized in that, in the above invention, the method includes a step of alternately stacking a plurality of first semiconductor layers and second semiconductor layers. Accordingly, when the oxidized first semiconductor layer having an upper limit in film thickness is used as the low thermal conductive layer, a desired heat insulating effect is secured by adjusting the number of the oxidized first semiconductor layers to be stacked. be able to.

In the method of manufacturing a semiconductor optical device according to one aspect of the present invention, in the above invention, the semiconductor substrate is an InP substrate, and the first semiconductor layer is an Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer. (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1).

  According to another aspect of the invention, there is provided a method for manufacturing a semiconductor optical device, wherein the first semiconductor layer is sandwiched between at least two second semiconductor layers. Forming a band gap intermediate layer having a band gap between the band gap of the first semiconductor layer and the band gap of the second semiconductor layer in at least one of the gaps. Thereby, when the active element and the passive element are monolithically integrated on the same substrate, the operating voltage of the active element can be reduced.

  In this configuration, the method for manufacturing a semiconductor optical device according to one aspect of the present invention is such that the band gap intermediate layer includes an n-type AlGaInAs layer when the first semiconductor layer and the second semiconductor layer are n-type semiconductor layers, When the first semiconductor layer and the second semiconductor layer are p-type semiconductor layers, the p-type GaInAsP layer is used.

  According to the method of manufacturing a semiconductor optical device according to one aspect of the present invention, in this configuration, the band gap intermediate layer is moved along the moving direction of majority carriers in the first semiconductor layer and the second semiconductor layer with respect to the first semiconductor layer. It is characterized by being formed on the upstream side.

  The method for manufacturing a semiconductor optical device according to one aspect of the present invention includes the step of forming a heating portion above the waveguide layer after forming the waveguide layer above the first semiconductor layer in the above invention. It is characterized by.

The semiconductor optical device according to the present invention has an Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 ≦ x <) substantially lattice-matched to the InP substrate above the InP substrate. 1, 0 <Al in y <1,0 ≦ z <1) and the low thermal conductive layer having at least one layer of _{Al 1-xy Ga x in y} as 1-z P z oxidized layer oxidized, low thermal conducting layer ₁ a waveguide layer provided in an upper layer of a region where the _-xy Ga _x In _y As _{1-z Pz} oxide layer is uniformly provided, and a heating unit provided in the upper layer of the waveguide layer And

  The semiconductor optical element according to one embodiment of the present invention is characterized in that, in the above invention, an active element having an active function and a passive element having a passive function are monolithically provided above an InP substrate.

  In this configuration, the semiconductor optical device according to one embodiment of the present invention is characterized in that the low thermal conductive layer is selectively provided in at least a part of the lower layer of the passive device.

  The semiconductor optical device according to one embodiment of the present invention is characterized in that, in the above invention, the active element is at least one of a semiconductor optical amplifier, a DFB laser, and a DBR laser.

  The semiconductor optical device according to one embodiment of the present invention is characterized in that, in the above invention, the passive element is at least one of a waveguide and a ring resonance filter.

In the semiconductor optical device according to one embodiment of the present invention, in the above invention, an Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1), and the Al _1-xy Ga _x In _y As _1-z P _z layer is formed of Al _1-xy Ga _x In _y As _1-z P _In a structure sandwiched by another semiconductor layer having a composition different from that of the _z layer, at least one of the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer and the other semiconductor layer is provided with Al _{1 -xy} Ga A band gap intermediate layer having a band gap between the band gap of the _x In _y As _1-z P _z layer and the band gap of another semiconductor layer is provided. Thereby, in the structure where the active element and the passive element are monolithically integrated on the same substrate, the operating voltage of the active element can be reduced.

In the semiconductor optical device according to one embodiment of the present invention, in this configuration, the band gap intermediate layer is an Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer and the other semiconductor layer is an n-type semiconductor layer. And an n 1 -type AlGaInAs layer, and a p 1 -type GaInAsP layer when the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer and the other semiconductor layer are p-type semiconductor layers.

Semiconductor optical device according to an embodiment of the present invention, in the above invention, the band gap intermediate layer, with respect to _{Al 1-xy Ga x In y} As 1-z P z _{layer, Al 1-xy Ga x In} y The As _{1-z Pz} layer and another semiconductor layer are provided on the upstream side in the moving direction of majority carriers.

  According to the semiconductor optical device and the method for manufacturing the same according to the present invention, in a semiconductor multilayer structure having a semiconductor layer having a film thickness dependence of oxidation rate, in-plane uniformity and batch-to-batch stability in the semiconductor layer can be improved. It becomes possible.

FIG. 1 is a cross-sectional view showing a laminated structure of an AlInAs layer and an InP layer formed for conducting an oxidation experiment. FIG. 2 is a graph showing the film thickness dependence of the oxide layer width of the AlInAs layer. FIG. 3 is a schematic perspective view of the wavelength tunable laser device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV of the ring-shaped waveguide in FIG. FIG. 5 is a cross-sectional view showing a laminated structure before and after the oxidation treatment in the semiconductor optical device according to the second embodiment of the present invention. FIG. 6 is a plan view of an integrated semiconductor laser device according to the third embodiment of the present invention. FIG. 7 is a cross-sectional view taken along line VII-VII of the laser stripe in FIG. FIG. 8 is a sectional view showing the overall configuration of an integrated semiconductor laser device according to the fourth embodiment of the present invention. FIG. 9 is an enlarged cross-sectional view of the encircled portion of the broken line in the active region of the integrated semiconductor laser device shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by the following embodiment. In the drawings, the same or corresponding elements are denoted by the same reference numerals as appropriate, and repeated descriptions are omitted as appropriate. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included. Further, “upper” or “upper” and “lower” or “lower” used in the description of the following embodiments indicate a direction away from the main surface of the substrate and a direction approaching the main surface of the substrate, respectively. It should also be noted that the semiconductor device is not mounted in the vertical direction when mounted. In addition, xyz coordinate axes are appropriately shown in the drawing, and directions will be described.

  First, in describing embodiments of the present invention, experiments and diligent studies conducted by the present inventors to solve the above-described problems will be described in order to facilitate understanding of the present invention. FIG. 1 is a cross-sectional view showing a semiconductor stacked body for conducting an oxidation experiment of an AlInAs layer.

As shown in FIG. 1, the inventor alternately forms InP layers and AlInAs layers having different film thicknesses on an InP substrate 101 by metal organic chemical vapor deposition (MOCVD). Laminated. Thus, four AlInAs layers 102a, 102b, 102c, and 102d having different thicknesses are stacked on the InP substrate 101 through the InP layers 103a, 103b, and 103c, respectively, and the semiconductor stacked body 100 is formed. It is formed. Here, the film thicknesses of the AlInAs layers 102a, 102b, 102c, and 102d are 50 nm, 100 nm, 150 nm, and 200 nm, respectively, and the compositions thereof are substantially lattice-matched with the InP substrate 101. Specifically, for example, Al _0.48 In _0.52 As is assumed.

Further, an InP layer 103d is formed on the AlInAs layer 102d, and then a striped silicon nitride (SiN _x ) layer 104 is formed. Thereafter, using the SiN _x layer 104 as a mask, anisotropic etching is performed on the semiconductor stacked body 100 until the InP substrate 101 is exposed by, for example, a dry etching method using a chlorine-based gas to form a mesa stripe. . Thereby, the side surfaces of the four AlInAs layers 102a, 102b, 102c, and 102d are exposed.

  Thereafter, annealing is performed in a water vapor atmosphere on the semiconductor stacked body 100 in which the AlInAs layers 102a to 102d having the exposed side surfaces are stacked. Thereby, oxidation is performed from the exposed side surface of the AlInAs layers 102a to 102d. Here, in general, when the oxidation temperature is increased, the oxidation rate increases, and the manufacturing time can be shortened. However, if the oxidation temperature is too high, surface roughness considered to be phosphorus loss occurs in the exposed InP layer. Therefore, the oxidation temperature is preferably 520 ° C. or lower. On the other hand, if the oxidation temperature is too low, the oxidation rate decreases and the processing time increases in production. Therefore, the oxidation rate is preferably 450 ° C. or higher.

  Within the above-mentioned temperature range, the semiconductor laminate 100 was subjected to an oxidation treatment by annealing in a water vapor atmosphere, for example, for 60 minutes, and then a cross section of the semiconductor laminate 100 was formed by cleavage. And the width | variety of the oxidized area | region in AlInAs layer 102a-102d which appeared in the cross section was evaluated using SEM (Scanning Electron Microscope).

  FIG. 2 shows a film having a width (oxide layer width) of a region oxidized from the side surface exposed in the AlInAs layers 102a to 102d when the oxidation temperature by annealing in a water vapor atmosphere is 480 ° C., 500 ° C., and 520 ° C. It is a graph which shows thickness dependence. In addition, the oxidation width shown in the graph of FIG. 2 shows the oxidation width when oxidized from one side surface. From FIG. 2, it can be seen that the width of the oxide layer depends on the thickness of the AlInAs layer, and is maximized at a predetermined thickness of 100 nm in this oxidation experiment. That is, it was found by the oxidation experiment conducted by the present inventor that the oxidation rate of the AlInAs layer depends on the thickness of the AlInAs layer. Hereinafter, the film thickness of the AlInAs layer that maximizes the oxide layer width, that is, the oxidation rate is referred to as “optimum film thickness”.

The inventor further studied the AlInAs layer oxidized in the semiconductor stacked body 100. As a result, it has been found that when the thickness of the AlInAs layer exceeds the optimum thickness, the variation in oxidation of the AlInAs layer increases. The variation in oxidation in the AlInAs layer becomes larger when the optimum film thickness is 1.5 times or more, and the oxidation progresses completely depending on the position in the AlInAs layer, for example, the position of the cross section in the stripe direction in this experiment. It was also found that there were non-oxidized regions that were not. Further, according to the knowledge of the present inventor, the above-mentioned tendency of the oxidation rate is not only the oxidation of the AlInAs layer but also the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 In the case of the oxidation of ≦ x <1, 0 <y <1, 0 ≦ z <1), it exists similarly.

  Therefore, when a semiconductor optical device is manufactured using an oxidized AlInAs layer (AlInAs oxide layer) as a low thermal conductive layer, the manufacturing yield of the semiconductor optical device may be lowered. Moreover, since the film thickness of the AlInAs oxide layer cannot be formed more than a predetermined film thickness, there is a possibility that the thermal confinement effect in the semiconductor optical device is limited.

  The present inventor has intensively studied to solve the above-mentioned problems based on the knowledge obtained by the above-described oxidation experiment. And when this inventor uses an AlInAs oxide layer for a semiconductor element, the film thickness of an AlInAs layer exceeds 0.5 times and less than 1.5 times with respect to the film thickness with which an oxidation rate is saturated, Recalling that the film thickness is 1.3 times or less. That is, the present inventor obtains data on the film thickness dependence in the oxidation rate of the AlInAs layer in advance by the oxidation treatment described above, derives the optimum film thickness in the oxidation of the AlInAs layer, and defines the film thickness of the AlInAs layer. I came up with a way to do it. The embodiment described below has been devised based on the above examination.

(First embodiment)
Next, the wavelength tunable laser device according to the first embodiment based on the above-described diligent study by the present inventors will be described. FIG. 3 is a schematic perspective view of the wavelength tunable laser device according to the first embodiment.

  As shown in FIG. 3, the wavelength tunable laser element 1 is configured to oscillate in the 1.55 μm band and output a laser beam L1. The wavelength tunable laser element 1 includes a first waveguide section 10 and a second waveguide section 20 formed on a common base B. The base B is made of, for example, an n-type InP substrate. An n-side electrode 30 is formed on the back surface of the base B. The n-side electrode 30 is configured to contain AuGeNi, for example, and is in ohmic contact with the base B.

  The first waveguide section 10 includes a waveguide section 11, a semiconductor laminated section 12, a p-side electrode 13, and micro heaters 14 and 15 made of Ti. The first waveguide portion 10 is a so-called active element and constitutes an active region. The waveguide portion 11 is formed in the semiconductor stacked portion 12 so as to extend in the z direction. In the first waveguide section 10, a diffraction grating loaded gain section 11a and a phase adjustment section 11b are arranged. The semiconductor laminated portion 12 is configured by laminating semiconductor layers, and has a function of a clad portion with respect to the waveguide portion 11.

The p-side electrode 13 is disposed along the diffraction grating loaded gain section 11 a on the semiconductor multilayer section 12. Note that a SiN _x protective film is formed on the semiconductor multilayer portion 12, and the p-side electrode 13 is in contact with the semiconductor multilayer portion 12 through an opening formed in the SiN _x protective film. The microheater 14 serving as a heating unit is disposed on the SiN _x protective film of the semiconductor stacked unit 12 along the phase adjusting unit 11b. The microheater 15 as a heating unit is arranged along the p-side electrode 13 on the SiN _x protective film of the semiconductor stacked unit 12.

  The second waveguide portion 20 includes a bifurcated portion 21, two arm portions 22 and 23, a ring-shaped waveguide 24, and a micro heater 25 made of Ti. The second waveguide portion 20 is a so-called passive element and constitutes a passive region. The two-branch portion 21 is formed of a 1 × 2 type branching waveguide including a 1 × 2 type multimode interference (MMI) waveguide 21a, and the two-port side is connected to each of the two arm portions 22 and 23. In addition, one port side is connected to the first waveguide section 10 side. One end of each of the two arm portions 22 and 23 is integrated by the bifurcated portion 21 and is optically coupled to the waveguide portion 11.

Each of the arm portions 22 and 23 extends in the z direction and is disposed so as to sandwich the ring-shaped waveguide 24. The arm portions 22 and 23 are close to the ring-shaped waveguide 24, and both are optically coupled to the ring-shaped waveguide 24 with the same coupling coefficient κ. The value of κ is, for example, 0.2. The arm portions 22 and 23 and the ring-shaped waveguide 24 constitute a ring resonance filter RF1. Further, the ring resonant filter RF1 and the bifurcated portion 21 constitute a reflection mirror M1. The microheater 25 as a heating unit for heating the optical waveguide has a ring shape and is disposed on the SiN _x protective film formed so as to cover the ring-shaped waveguide 24.

  The first waveguide section 10 and the second waveguide section 20 constitute a laser resonator C1 by the diffraction grating layer 11ab and the reflection mirror M1 of the diffraction grating loaded gain section 11a optically connected to each other. ing. The active core layer 11aa and the phase adjustment unit 11b as the gain unit of the diffraction grating loaded gain unit 11a are arranged in the laser resonator C1.

  4 is a cross-sectional view taken along line IV-IV, in which the ring-shaped waveguide 24 of the second waveguide section 20 is cut along a plane parallel to the yz plane of FIG. As shown in FIG. 4, the ring-shaped waveguide 24 is formed on the n-type InP substrate 41 constituting the base B, on the low thermal conductive layer 42a, the lower cladding layer 43, the optical waveguide layer 44 as the waveguide layer, and the upper cladding. It has a high mesa waveguide structure in which layers 45 are sequentially stacked.

The low thermal conductive layer 42a is an Al _1-xy Ga _x In _y As _1-z P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1) as an oxidized layer. ) Is formed of an Al _{1 -xy} Ga _x In _y As _{1 -z Pz} oxide layer formed by oxidation from the side end. The low thermal conductive layer 42a is provided on the entire passive element or at least a part of the lower layer. Specifically, the low thermal conductive layer 42a is made of, for example, an AlInAs oxide layer in which an n-type AlInAs layer 42 with x = z = 0 is oxidized from the side end. The composition of the n-type AlInAs layer 42 is a composition that substantially lattice-matches with the n-type InP substrate 41. In the first embodiment, for example, an Al _0.48 In _0.52 As layer (x = 1, y = 0.52, z = 0). The film thickness of the n-type AlInAs layer 42 is 0.5 times or more and less than 1.5 times the optimum film thickness described above, and preferably 1.3 times or less. Specifically, in the first embodiment, the optimum film thickness of the n-type AlInAs layer 42 is, for example, 100 nm, and the film thickness is 50 nm or more and less than 150 nm, preferably 130 nm or less, here 100 nm. The lower clad layer 43 is made of an n-type InP layer, and the lower portion of the lower clad layer 43 has a portion extending to the unoxidized n-type AlInAs layer 42. As a result, the n-type AlInAs layer 42 and the upper lower cladding layer 43 are connected to each other at least in a portion extending on the non-oxidized n-type AlInAs layer 42. The optical waveguide layer 44 is made of a GaInAsP layer having a band gap wavelength of 1300 nm. The upper cladding layer 45 is made of a p-type InP layer.

The low thermal conductive layer 42a, the lower cladding layer 43, the optical waveguide layer 44, and the upper cladding layer 45 constituting the high mesa waveguide structure, and the portion extending on the n-type AlInAs layer 42 below the lower cladding layer 43 are protected. It is covered with a dielectric layer 46 as a film. The dielectric layer 46 is made of, for example, a SiN _x film, a silicon oxide (SiO ₂ ) film, or a laminated film of a SiO ₂ film and a SiN _x film.

  The bifurcated portion 21 and the arm portions 22 and 23 which are other components of the second waveguide portion 20 also have a high mesa waveguide structure similar to that described above, and are covered with a dielectric layer. That is, the second waveguide section 20 has a second waveguide structure that is different from the first waveguide structure of the first waveguide section 10.

  A microheater 25 is provided on the dielectric layer 46 above the high mesa waveguide structure constituting the ring-shaped waveguide 24. A resin layer 48 covering the side surface is provided on the side surface side of the high mesa waveguide structure. On the upper surface of the resin layer 48 and the upper surface of the microheater 25, a lead-out wiring 49 electrically connected on the upper surface of the microheater 25 is provided. The lead-out wiring 49 is a wiring for energizing the microheater 25 from the outside. By energizing the microheater 25, the lower part of the installation area of the microheater 25 can be heated to the upper layer of the low thermal conductive layer 42a. The low thermal conductive layer 42 a has a thermal conductivity lower than that of at least the upper cladding layer 45, the optical waveguide layer 44, and the lower cladding layer 43. Thereby, the low thermal conductive layer 42a functions as a heat insulating layer for preventing the heating by the microheater 25 from being further transmitted to the lower layer. The lead wiring 49 is made of, for example, a Ti / Au layer, a Ti / Pt / Au layer, a Cr / Au layer, or a Mo / Au layer. Note that a so-called air bridge structure in which the lead wiring 49 is provided with the resin layer 48 in a space may be employed.

(Manufacturing method of high mesa waveguide structure)
Next, a manufacturing method of the above-described high mesa waveguide structure will be described. First, as shown in FIG. 1 described above, a semiconductor stacked body is formed by stacking a plurality of semiconductor layers having mutually different film thicknesses and substantially equal compositions via another semiconductor layer having a composition different from that of the semiconductor layer. To do. Subsequently, after the oxidation process by annealing is performed on the semiconductor stacked body, the optimum film thickness is derived by evaluating the oxide layer width using the SEM. In the first embodiment, the semiconductor layer as the oxidized layer is an Al _0.48 In _0.52 As layer, and the other semiconductor layers are InP layers.

  After derivation of the optimum film thickness by the above-described oxidation experiment is completed, the n-type AlInAs layer 42 and the lower cladding layer 43 are formed on the n-type InP substrate 41 constituting the base B by, for example, the MOCVD method. An InP layer, a GaInAsP layer to be the optical waveguide layer 44, and a p-type InP layer to be the upper clad layer 45 are sequentially formed.

Next, for example, a SiN _x film is formed on the upper surface of the p-type InP layer to be the upper clad layer 45, and is patterned into a high mesa waveguide structure such as a ring-shaped or straight arm. Subsequently, anisotropic etching by dry etching using, for example, chlorine gas is performed using this SiN _x film as an etching mask. After etching with the lower portion of the lower cladding layer 43 remaining, the etching mask is removed. Subsequently, after forming an etching mask in a region including the laminated portion of the high mesa waveguide structure and the extended portion below the lower cladding layer 43, for example, dry etching using a chlorine-based gas is performed. As a result, the remaining portion of the lower cladding layer 43 in the desired region where the oxide layer is to be formed and the n-type AlInAs layer 42 are etched to expose one end of the n-type AlInAs layer 42 as the first semiconductor layer. . The remaining portion of the lower cladding layer 43 and the n-type AlInAs layer 42 may be etched by a wet etching method.

  After that, annealing is performed at a temperature of 450 ° C. or more and 520 ° C. or less in a water vapor atmosphere on the high mesa waveguide structure laminate including the n-type AlInAs layer 42 whose side surface is exposed. As a result, in the n-type AlInAs layer 42, oxidation proceeds along the surface direction of the n-type AlInAs layer 42 from the exposed end. This oxidation is performed until the n-type AlInAs layer 42 in the lower region of the high mesa waveguide structure is oxidized. The oxidation time in the oxidation treatment is determined based on the oxidation rate data obtained in the oxidation treatment for deriving the optimum film thickness described above, the design value of the width of the high mesa waveguide structure, and the like. As a result, the n-type AlInAs layer 42 is uniformly oxidized under the high mesa waveguide structure, and a low thermal conductive layer 42a made of a uniform AlInAs oxide layer is formed along the width direction.

Next, a dielectric layer 46 is formed by, for example, forming a SiN _x film on the entire surface. Thereafter, a metal layer such as a Ti layer is formed in the shape of the microheater 25 on the dielectric layer 46 above the high mesa waveguide structure by, for example, a lift-off method using a lift-off mask. Further, a resin layer 48 is formed by embedding a resin in the side portion of the high mesa waveguide structure, and then, for example, a Ti / Au layer, a Ti / Pt / Au layer or a Cr layer is formed on at least a part of the microheater 25 and the resin layer 48. The lead wiring 49 is formed by forming the / Au layer. As described above, a high mesa waveguide structure in which the low thermal conductive layer 42a is provided in the lower portion and the micro heater 25 is provided in the upper portion is manufactured.

  According to the first embodiment described above, an optimum film thickness of a semiconductor layer such as an AlInAs layer that is an oxidized layer is derived in advance by an oxidation experiment, and 0.5 times or more of this optimum film thickness is 1.5 times. After forming a semiconductor layer having a thickness less than double, oxidation treatment is performed from the exposed end of the semiconductor layer. Thereby, a semiconductor oxide layer such as an AlInAs oxide layer can be formed uniformly. Therefore, in a semiconductor laminated structure having a semiconductor layer having a film thickness dependence of oxidation rate, in-plane uniformity and batch-to-batch stability of the semiconductor oxide layer can be improved, thereby improving the manufacturing yield of the semiconductor optical device. Cost reduction can be realized.

(Second Embodiment)
Next, a semiconductor optical device according to the second embodiment of the present invention will be described. In the following description and drawings, in order to facilitate understanding of the invention, a laminated structure in which the resin layer, the dielectric layer, the lead-out wiring, and the like in the high mesa waveguide structure are omitted will be described.

  First, according to the knowledge of the present inventor, in the semiconductor optical device according to the first embodiment, in order to suppress the heat generated by the microheater 25 from being conducted to the n-type InP substrate 41 side, low heat It is desirable to increase the film thickness of the conductive layer 42a. On the other hand, as described above, when the low thermal conductive layer 42a is formed by oxidizing the n-type AlInAs layer 42 from the exposed end, considering the oxidation stability that suppresses the variation in oxidation rate and oxidation state, There is an upper limit based on the optimum film thickness in the allowable film thickness in the n-type AlInAs layer 42. In the first embodiment described above, the thickness of the low thermal conductive layer 42a is limited to less than 150 nm, which is less than 1.5 times the optimum film thickness.

  Therefore, the present inventor has conducted further studies and made the thickness of one of the semiconductor layers formed as the low thermal conductive layer less than 1.5 times the optimum film thickness, and this low thermal conductive layer was used as another semiconductor layer. A method of creating a multilayer film structure in which a plurality of layers are stacked via a substrate is recalled. Thereby, since the total film thickness of the low thermal conductive layers along the stacking direction can be increased, an effect equivalent to the effect of increasing the film thickness of the low thermal conductive layer 42a according to the first embodiment can be obtained. FIG. 5 is a cross-sectional view showing a high mesa waveguide structure according to the second embodiment.

  As shown in FIG. 5A, in the high mesa waveguide structure 50 according to the second embodiment, an n-type InP layer 51, a first low thermal conductive layer 52a, and an n-type InP layer are formed on an n-type InP substrate 41. 53 and the second low thermal conductive layer 54a are sequentially laminated. The first low thermal conductive layer 52a is made of an AlInAs oxide layer and has a configuration sandwiched between n-type InP layers 51 and 53 as second semiconductor layers. Similar to the first embodiment, the lower cladding layer 43, the optical waveguide layer 44, the upper cladding layer 45, and the microheater 25 are sequentially stacked on the second low thermal conductive layer 54a. The second low thermal conductive layer 54a is made of an AlInAs oxide layer, and has a configuration sandwiched between an n-type InP layer 53 as a second semiconductor layer and a lower cladding layer 43 made of an n-type InP layer. By the first low thermal conductive layer 52a, the n-type InP layer 53, and the second low thermal conductive layer 54a, a low thermal conductive layer substantially equivalent to the total thickness of the first low thermal conductive layer 52a and the second low thermal conductive layer 54a is formed. Composed.

  Next, a manufacturing method of the high mesa waveguide structure 50 shown in FIG. That is, as shown in FIG. 5B, an n-type InP layer 51, an n-type AlInAs layer 52, an n-type InP layer 53, and an n-type AlInAs layer 54 are sequentially formed on an n-type InP substrate 41 by, eg, MOCVD. Form. Thereafter, similarly, by MOCVD, an n-type InP layer that becomes the lower cladding layer 43, a GaInAsP layer that becomes the optical waveguide layer 44, and a p-type InP layer that becomes the upper cladding layer 45 are sequentially formed on the n-type AlInAs layer 54. To do.

Next, for example, a SiN _x film is formed on the upper surface of the p-type InP layer to be the upper cladding layer 45 and patterned into the shape of the high mesa waveguide structure 50. Subsequently, anisotropic etching is performed, for example, by dry etching using a chlorine-based gas using the SiN _x film as a mask. As a result, the side surfaces of the n-type AlInAs layers 52 and 54 are exposed.

  Thereafter, the high mesa waveguide structure 50 including the n-type AlInAs layers 52 and 54 whose side surfaces are exposed is annealed at a temperature of 450 ° C. or higher and 520 ° C. or lower in a water vapor atmosphere. As a result, oxidation proceeds from the exposed end surfaces of the n-type AlInAs layers 52 and 54, and the n-type AlInAs layers 52 and 54 as the layers to be oxidized are oxidized to form a homogeneous AlInAs oxide layer. In other words, the AlInAs oxide layer is uniformly formed along the width direction of the high mesa waveguide structure 50 to constitute the first low thermal conductive layer 52a and the second low thermal conductive layer 54a. Since the oxidation conditions for the n-type AlInAs layers 52 and 54 and the manufacturing method of the lower cladding layer 43, the optical waveguide layer 44, and the upper cladding layer 45 are the same as those in the first embodiment, description thereof will be omitted.

In the second embodiment, a plurality of layers, specifically two layers, are provided in a state where an AlInAs layer as an oxidized layer is sandwiched between InP layers. As a result, the n-type InP layer 53, the first low thermal conductive layer 52a, and the second low thermal conductive layer 54a can function as the low thermal conductive layer. That is, the low thermal conductive layer may be configured to have at least one Al _{1 -xy} Ga _x In _y As _{1 -z Pz} oxide layer. Therefore, even when there is a limit to the allowable film thickness when oxidizing like the AlInAs layer, the same function as that of the low thermal conductive layer having a large film thickness can be obtained. Furthermore, in order to ensure the heat insulation efficiency desired as the low thermal conductive layer, a predetermined number of AlInAs oxide layers of three or more layers are provided via other semiconductor layers such as an InP layer to constitute the low thermal conductive layer. It is also possible.

  In the second embodiment, the other semiconductor layer sandwiching the n-type AlInAs layers 52 and 54 is the lower cladding layer 43 composed of the n-type InP layers 51 and 53 and the n-type InP layer. It is also possible to use a semiconductor layer other than the n-type InP layer. As another semiconductor layer, it is substantially lattice-matched to the n-type InP substrate 41, has an oxidation rate selection ratio as large as possible with respect to the oxidation rate of the AlInAs layer, and has a wavelength of light transmitted through the optical waveguide layer 44. On the other hand, it is desirable to make it from a material having a transparent band gap. Specifically, as the other semiconductor layer, for example, a GaInAsP layer, a GaInAs layer, an AlGaInAs layer, an AlGaInAsP layer, or a multilayer film thereof can be used.

  According to the second embodiment, since the AlInAs oxide layer has a multilayer film structure and the low thermal conductive layer is configured, the heat conduction from the heat heated by the microheater 25 to the n-type InP substrate 41 side can be reduced. It is suppressed. Thereby, the outflow of heat from the high mesa waveguide structure 50 to the n-type InP substrate 41 can be suppressed, and the heat heated by the microheater 25 can be more efficiently confined in the waveguide. Therefore, the refractive index can be changed with a smaller amount of power input, and the wavelength of the guided light can be greatly changed. For example, low power consumption can be realized in a semiconductor optical device such as a wavelength tunable laser.

(Third embodiment)
Next, an integrated semiconductor laser element as a semiconductor optical element according to the third embodiment of the present invention will be described. FIG. 6 is a plan view of an integrated semiconductor laser device 200 according to the third embodiment. The integrated semiconductor laser element 200 is a semiconductor optical element in which an active element provided in an active region and a passive element provided in a passive region are monolithically integrated.

  As shown in FIG. 6, the integrated semiconductor laser device 200 according to the third embodiment includes laser stripes 210-1 to 210-n (n is 2 or more) of DFB (Distributed Feedback) lasers as a plurality of active devices. Integer), a plurality of optical waveguides 220-1 to 220-n as passive elements, a multi-mode interferometer (MMI) optical combiner 230 as a passive element, and a semiconductor optical amplifier (SOA: Semiconductor) Optical Amplifier) 240 is integrated on one semiconductor substrate.

  Each of the laser stripes 210-1 to 210-n is an edge-emitting DFB type laser having an embedded high mesa waveguide structure in which an active layer has a width of 2 μm and a length of 600 μm. The laser stripes 210-1 to 210-n are formed at one end of the integrated semiconductor laser element 200 in the width direction W at a pitch of 25 μm, for example. The laser stripes 210-1 to 210-n are configured such that the wavelength of the output light is different in the range of 1530 nm to 1570 nm by making the intervals of the diffraction gratings provided in each laser stripe different from each other. The laser oscillation wavelengths of the laser stripes 210-1 to 210-n can be adjusted by changing the set temperature of the integrated semiconductor laser element 200. That is, the integrated semiconductor laser device 200 realizes a wide wavelength tunable range by switching the driving laser stripes 210-1 to 210-n and controlling the temperature.

  The MMI optical combiner 230 is formed near the central portion of the integrated semiconductor laser element 200. The optical waveguides 220-1 to 220-n are formed between the laser stripes 210-1 to 210-n and the MMI optical combiner 230, and the laser stripes 210-1 to 210-n and the MMI optical combiner 230 are formed. 230 is optically connected. The semiconductor optical amplifier 240 is formed on one end side of the integrated semiconductor laser element 200 opposite to the laser stripes 210-1 to 210-n.

  Next, the operation of the integrated semiconductor laser device 200 will be described. First, one laser stripe selected from the laser stripes 210-1 to 210-n is driven. Next, one of the optical waveguides 220-1 to 220-n that is optically connected to any of the driven laser stripes 210-1 to 210-n among the plurality of optical waveguides 220-1 to 220-n. Guides the output light from the driving laser stripe. The MMI optical combiner 230 passes the light guided through the optical waveguides 220-1 to 220-n and outputs the light from the output port. The semiconductor optical amplifier 240 amplifies the light output from the MMI optical combiner 230 and outputs it from the output end. This semiconductor optical amplifier 240 is used to compensate for the loss of light by the MMI optical combiner 230 of the output light from the driven laser stripes 210-1 to 210-n and to obtain an optical output with a desired intensity from the output end. .

  FIG. 7 is a cross-sectional view taken along line VII-VII of the laser stripe in FIG. As shown in FIG. 7, the laser stripe 210 includes an embedded DFB laser unit 260. The base B of the embedded DFB laser portion 260 is formed of a region in which the n-type AlInAs layer 251 and the n-type AlInAs layer 251 are oxidized on the main surface of the n-type InP substrate 250 provided with the n-side electrode 270 on the back surface. The low thermal conductive layer 251a and the n-type InP layer 252 are sequentially stacked. On the upper layer of the n-type InP layer 252, a diffraction grating loaded gain section 253a is provided. The diffraction grating loaded gain unit 253a includes an active layer 253aa and a diffraction grating layer 253ab made of a diffraction grating with λ / 4 shift provided along the active layer 253aa in the vicinity of and immediately above the active layer 253aa.

  The active layer 253aa has a multiple quantum well structure including a plurality of well layers and a plurality of barrier layers stacked alternately, and a lower and upper optical confinement layer sandwiching the multiple quantum well structure from above and below. And emit light by current injection. The well layer and the barrier layer constituting the multiple quantum well structure of the active layer 253aa are made of InGaAsP having different compositions. The emission wavelength from the active layer 253aa is in the 1.55 μm band in the third embodiment. The lower and upper optical confinement layers are made of InGaAsP. The band gap wavelengths of the lower and upper optical confinement layers are set to be shorter than the band gap wavelength of the active layer 253aa. The diffraction grating layer 253ab has a configuration in which a diffraction grating with λ / 4 shift is formed in a p-type InGaAsP layer along the stripe direction (perpendicular to the paper surface), and a groove of the diffraction grating is buried with p-type InP. The band gap wavelength of the p-type InGaAsP layer of the diffraction grating layer 253ab is preferably shorter than the band gap wavelength of the active layer 253aa, for example, 1.2 μm.

  For example, the semiconductor stacked portion 254 including the diffraction grating loaded gain portion 253a has the following configuration. The semiconductor stacked portion 254 has an n-type semiconductor layer 254a made of n-type InP and having the function of a lower cladding layer on the n-type InP layer 252 on the n-type InP substrate 250 constituting the base B. An active layer 253aa is stacked over the n-type semiconductor layer 254a. Further, a spacer layer 254b made of p-type InP is stacked on the active layer 253aa. A diffraction grating layer 253ab is stacked over the spacer layer 254b. The active layer 253aa, the spacer layer 254b, and the diffraction grating layer 253ab have a striped mesa structure that has a width (for example, 1.8 μm) suitable for optically guiding light in a 1.55 μm band in a single mode by etching or the like. ing. Both sides of the stripe mesa structure (left and right direction in the drawing) have a buried structure having a current blocking structure including a p-type InP buried layer 254c and an n-type InP current blocking layer 254d. Further, a p-type semiconductor layer 254e is stacked on the diffraction grating layer 253ab and the buried structure. The p-type semiconductor layer 254e is composed of a clad layer 254ea made of p-type InP and a contact layer 254eb made of p-type InGaAs laminated on the clad layer 254ea and forming the uppermost layer of the semiconductor laminated portion 254. The p-type semiconductor layer 254e is provided over at least part of the buried structure on both sides from directly above the active layer 253aa. A SiN protective film 258 is formed on the semiconductor stacked portion 254 so as to cover the semiconductor stacked portion 254. The p-side electrode 255 is made of Ti / Pt / Au, is formed on the contact layer 254eb, and is in ohmic contact with the contact layer 254eb through the opening 258a of the SiN protective film 258. With the above configuration, current injection from the n-side electrode 270 and the p-side electrode 255 to the active layer 253aa is possible. Further, the microheater 257 is disposed along the p-side electrode 255 on the SiN protective film 259 provided in the semiconductor stacked portion 254 in order to insulate the p-side electrode 255 and the microheater 257 from each other.

  According to the third embodiment, in the integrated semiconductor laser device 200 in which the active device and the passive device are monolithically integrated, the low heat consisting of the region in which the n-type AlInAs layer 251 is oxidized on the n-type InP substrate 250. By providing the conductive layer 251a, the same effect as that of the first embodiment can be obtained. Note that it is also possible to apply the configuration of the plurality of low thermal conductive layers according to the second embodiment to the integrated semiconductor laser device 200 according to the third embodiment.

(Fourth embodiment)
Next, an integrated semiconductor optical device according to a fourth embodiment to which the present invention is applicable will be described. FIG. 8 is a sectional view showing a wavelength tunable laser element that is an integrated semiconductor optical element according to the fourth embodiment.

  As shown in FIG. 8, in the integrated semiconductor laser device 300 that is a wavelength tunable laser device according to the fourth embodiment, a first sampled grating waveguide portion 301 that is a DBR (Distributed Bragg Reflector) mirror as a back mirror. , A phase adjustment waveguide section 302, a gain waveguide section 303, a second sampled grating waveguide section 304 which is a DBR mirror as a front mirror, and a semiconductor optical amplifier (SOA) 305.

  In the integrated semiconductor laser device 300, a passive region is configured by the first sampled grating waveguide portion 301, the phase adjustment waveguide portion 302, and the second sampled grating waveguide portion 304 as passive elements. The first sampled grating waveguide part 301, the phase adjustment waveguide part 302, and the second sampled grating waveguide part 304 have a high mesa structure. An active region is constituted by the gain waveguide section 303 and the SOA 305 as active elements. The gain waveguide section 303 and the SOA 305 have a buried structure.

  In the integrated semiconductor laser device 300, an n-type AlInAs layer 320, a lower cladding layer 330, a core layer 340, and an upper cladding layer 350 are sequentially stacked on the main surface of an n-type InP substrate 310. On the upper surface of the upper cladding layer 350, a p-side electrode 361 is selectively provided in the active region via an InGaAs contact layer (not shown), and a micro heater 362 is selectively provided in the passive region. ing. An n-side electrode 370 is provided on the back surface of the n-type InP substrate 310. A non-reflective film 380 is provided on the laser light emission end face of the laminated body of the n-type InP substrate 310, the n-type AlInAs layer 320, the lower cladding layer 330, the core layer 340, and the upper cladding layer 350. Here, the film thickness of the n-type AlInAs layer 320 is determined in the same manner as in the first embodiment, and is 0.5 times or more and less than 1.5 times the optimum film thickness obtained in advance by an oxidation experiment. The film thickness is preferably set to 1.3 times or less. In the fourth embodiment, the film thickness of the n-type AlInAs layer 320 is, for example, 100 nm.

  The phase adjusting waveguide section 302 in the passive region has a low thermal conductive layer 321, a lower cladding layer 330, a waveguide core layer 343, an upper cladding layer 350, and a microheater 362 sequentially stacked on the main surface of the n-type InP substrate 310. Has been. The n-type InP substrate 310 is provided with an n-side electrode 370 on the back surface. The low thermal conductive layer 321 is composed of an oxidized n-type AlInAs layer 320. The low thermal conductive layer 321 is provided in at least a part or the entire lower layer of the phase adjustment waveguide section 302. The lower cladding layer 330 is composed of an n-type InP layer as an n-type semiconductor layer, and the upper cladding layer 350 is composed of a p-type InP layer as a p-type semiconductor layer. The waveguide core layer 343 is made of a GaInAsP layer whose band gap wavelength is adjusted to 1.3 μm, for example.

  The first sampled grating waveguide part 301 and the second sampled grating waveguide part 304 in the passive region are formed on the main surface of the n-type InP substrate 310 on the low thermal conductive layer 321, the lower cladding layer 330, the grating layer 342, and the upper part. A clad layer 350 and a microheater 362 are sequentially stacked. The n-type InP substrate 310 provided with the n-side electrode 370 on the back surface is shared with the phase adjustment waveguide section 302. The low thermal conductive layer 321 is composed of an oxidized n-type AlInAs layer 320. The low thermal conductive layer 321 is provided in at least a part or the entire lower layer of the first sampled grating waveguide unit 301 and the second sampled grating waveguide unit 304. The lower cladding layer 330 is composed of an n-type InP layer as an n-type semiconductor layer. The upper cladding layer 350 is made of a p-type InP layer as a p-type semiconductor layer. The grating layer 342 is made of a GaInAsP layer in which grating regions in which short-period gratings are formed are arranged at a predetermined period.

  The gain waveguide section 303 and the SOA 305 in the active region are formed on the main surface of the n-type InP substrate 310 by an n-type AlInAs layer 320, a lower cladding layer 330, an active layer 341, an upper cladding layer 350, and an InGaAs contact layer (not shown). The p-side electrode 361 is sequentially stacked. The n-type InP substrate 310, the lower cladding layer 330, and the upper cladding layer 350 are shared with the first sampled grating waveguide unit 301, the phase adjustment waveguide unit 302, and the second sampled grating waveguide unit 304. . The n-type AlInAs layer 320 is an unoxidized region of the low thermal conductive layer 321 that is not oxidized. The active layer 341 is composed of a GaInAsP layer having a multiple quantum well (MQW) structure.

  In the integrated semiconductor laser device 300, the low thermal conductive layer 321 in which the n-type AlInAs layer 320 is oxidized is provided between the microheater 362 and the n-type InP substrate 310 along the stacking direction. The same effect as that of the first embodiment can be obtained. In addition, in the passive region of the integrated semiconductor laser device 300 according to the fourth embodiment, it is possible to apply the configuration of a plurality of low thermal conductive layers according to the second embodiment.

  Further, like the integrated semiconductor laser element 300 shown in FIG. 8, an active element having an active function and a passive element (waveguide) having a passive function may be monolithically integrated on the same substrate. In this case, as shown in FIG. 8, the epitaxial layer serving as the base of the active element and the epitaxial layer serving as the base of the passive element are often shared. In the region below the active element, a part of the AlInAs layer, which is an oxidized region, is provided in a state sandwiched between semiconductor layers having other compositions such as InP layers and InP substrates (hereinafter referred to as other semiconductor layers). It is done. At the interface between the other semiconductor layer and the unoxidized AlInAs layer, a heterojunction spike is generated due to the discontinuity of the band gap. This spike becomes an obstacle to the movement of electrons that are majority carriers when the AlInAs layer is formed in an n-type, that is, when the AlInAs layer is sandwiched between other n-type semiconductor layers. Further, the spike becomes an obstacle to movement of holes that are majority carriers when the AlInAs layer is formed in a p-type, that is, when the AlInAs layer is sandwiched between other p-type semiconductor layers. Such a failure may increase the operating voltage of the active element in a monolithic integrated element in which the active element and the passive element are formed on the same substrate.

  Therefore, the inventor adopts a structure in which an AlInAs layer is sandwiched between other semiconductor layers in a semiconductor optical device in which an active device and a passive device are monolithically integrated on the same substrate as shown in FIG. Further investigations were made. The inventor has conceived a method of providing a semiconductor layer having a band gap between the band gap of another semiconductor layer and the band gap of AlGaAs at the interface between the other semiconductor layer and the AlInAs layer. Thereby, spikes generated at the interface between the other semiconductor layer and the AlInAs layer can be alleviated, so that an increase in the operating voltage of the active element can be suppressed.

  FIG. 9 is an enlarged cross-sectional view of a portion surrounded by a broken line in FIG. As shown in FIG. 9, a band gap intermediate layer 320 a is provided between a lower cladding layer 330 made of an n-type InP layer as a second semiconductor layer or another semiconductor layer and an n-type AlInAs layer 320. A band gap intermediate layer 320b is provided between the n-type InP substrate 310, which is an n-type InP layer as the second semiconductor layer or another semiconductor layer, and the n-type AlInAs layer 320. The band gap intermediate layers 320a and 320b have a band gap between the band gap of InP and the band gap of AlInAs. In the case where the band gap intermediate layers 320a and 320b are formed of an n-type semiconductor and provided on the n side as in the fourth embodiment, the band gap intermediate layer is suppressed in order to suppress the spike on the conduction band side of the heterojunction. 320a and 320b are preferably composed of an n-type AlGaInAs layer having a band gap wavelength of 0.95 to 1.10 μm. On the other hand, when the band gap intermediate layers 320a and 320b are formed of a p-type semiconductor and formed on the p side, the band gap intermediate layers 320a and 320b are formed in order to suppress spikes on the valence band side of the heterojunction. It is desirable that the p-type GaInAsP layer has a band gap wavelength of 0.85 to 1.05 μm. Note that the band gap intermediate layers 320a and 320b can also be composed of a plurality of stepped semiconductor layers having different compositions and graded layers in which the composition changes in grades.

  The semiconductor laminated body having the above configuration is manufactured as follows. That is, first, a band gap intermediate layer 320b made of an n-type AlGaInAs layer is formed on the n-type InP substrate 310 by, for example, MOCVD. Subsequently, an n-type AlInAs layer 320 is formed on the band gap intermediate layer 320b by MOCVD. Thereafter, a band gap intermediate layer 320a made of an n-type AlGaInAs layer and a lower cladding layer 330 are sequentially formed on the n-type AlInAs layer 320 by MOCVD. Thereafter, a high mesa semiconductor stacked body is formed by the same method as in the first embodiment to expose one end of the n-type AlInAs layer 320, and then passively along the surface direction of the n-type AlInAs layer 320. The low heat conductive layer 321 is formed by oxidizing the n-type AlInAs layer 320 in the region. Note that the material and composition of the band gap intermediate layers 320a and 320b are, as described above, whether an unoxidized AlInAs layer as an oxidized layer is sandwiched between n-type semiconductor layers or p-type semiconductor layers. It is decided according to either.

  As described above, in the structure in which the AlInAs layer (n-type AlInAs layer 320) is sandwiched between InP layers (n-type InP substrate 310, lower cladding layer 330), the band gap of AlInAs and the interface between the AlInAs layer and the InP layer are A band gap intermediate layer having a band gap between the InP band gap is provided. As a result, the heterojunction spike caused by the discontinuity of the band gap generated at the interface between the AlInAs layer and the InP layer can be alleviated. Therefore, in a semiconductor optical device in which an active device and a passive device are monolithically integrated, even if the epitaxial layer serving as the underlying layer is shared between the active device and the passive device, an increase in the operating voltage of the active device is suppressed by mitigating spikes. it can.

  The band gap intermediate layers 320a and 320b according to the fourth embodiment can alleviate the spike described above even when provided at least on one upstream side along the moving direction of majority carriers. An effect can be obtained. In this case, the band gap intermediate layer is more preferably provided upstream of the non-oxidized n-type AlInAs layer 320 as the oxidized layer, that is, at the position of the band gap intermediate layer 320b along the majority carrier moving direction. desirable. Thereby, the step difference of the spike of the heterojunction can be moderated between the n-type InP substrate 310 and the n-type AlInAs layer 320, so that the obstacle to the movement of majority carriers can be alleviated.

  In the fourth embodiment, band gap intermediate layers 320 a and 320 b are provided at both interfaces of the n-type AlInAs layer 320 as an oxidized layer and the lower cladding layer 330 and the n-type InP substrate 310, respectively. . As a result, unlike the case where the band gap intermediate layer is provided only at one interface, the n-type AlInAs layer 320 to be oxidized is sandwiched between the same semiconductor layers, so that the n-type AlInAs layer 320 is oxidized. Asymmetry of the AlInAs oxide layer can be relaxed.

  Note that the band gap intermediate layers 320a and 320b according to the fourth embodiment can be applied to a semiconductor optical device in which an active element and a passive element are monolithically integrated on the same substrate, and is the same as in the fourth embodiment. The effect of can be obtained. Specifically, in the wavelength tunable laser device 1 according to the first embodiment and the integrated semiconductor laser device 200 according to the third embodiment, the same effect can be obtained by applying the band gap intermediate layers 320a and 320b. Can be obtained.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible. For example, the numerical values given in the above embodiment are merely examples, and different numerical values may be used as necessary.

Further, in the above-described embodiment, the n-type AlInAs layer 42 is composed of AlInAs having a single composition, but it is not necessarily required to have a single composition. _{Specifically, Al 1-xy Ga x In} y As 1-z P z layer and the _{Al 1-pq Ga p In q} As 1-r P r layer (0 ≦ x + y <1,0 ≦ p + q <1, x A structure of so-called distortion compensation in which ≠ p, y ≠ q, z ≠ r) are alternately stacked may be used.

DESCRIPTION OF SYMBOLS 1 Wavelength variable laser element 10 1st waveguide part 11 Waveguide part 11a Diffraction grating loading type gain part 11aa, 253aa Active core layer 11ab, 253ab Diffraction grating layer 11b Phase adjustment part 12 Semiconductor laminated part 13,255,361 p side Electrode 14, 15, 25, 257, 362 Micro heater 20 Second waveguide portion 21a Multimode interference waveguide 22, 23 Arm portion 24 Ring-shaped waveguide 30, 270, 370 N-side electrode 41, 250, 310 n-type InP substrate 42, 52, 54, 61, 251 and 320 n-type AlInAs layers 42a, 61a, 251a and 321 Low thermal conductive layers 43 and 330 Lower cladding layer 44 Optical waveguide layer 45 and 350 Upper cladding layer 46 Dielectric layer 48 Resin layer 49 Lead-out wiring 50 High mesa waveguide structure 51, 53, 252 n-type In Layer 52a First low thermal conductive layer 54a Second low thermal conductive layer 200 Integrated semiconductor laser device 240 Semiconductor optical amplifier 253a Diffraction grating loaded gain unit 254 Semiconductor stacked unit 254a N-type semiconductor layer 254b, 254ea Spacer layer 254c p-type InP buried layer 254d n-type InP current blocking layer 254e p-type semiconductor layer 254eb contact layer 258, 259 SiN protective film 258a opening 260 waveguide section 300 integrated semiconductor laser device 301 first sampled grating waveguide section 302 phase adjustment waveguide section 303 Gain waveguide section 304 Second sampled grating waveguide section 320a, 320b Band gap intermediate layer 340 Core layer 341 Active layer 342 Grating layer 343 Waveguide core layer 380 Non-reflective film C1 Laser resonance L1 laser beam M1 reflection mirror RF1 ring resonance filter

Claims (15)

A first semiconductor layer made of a material substantially lattice-matched to the semiconductor substrate is disposed above the semiconductor substrate, and a second semiconductor layer having a composition different from that of the first semiconductor layer is sequentially formed on the first semiconductor layer. A method of manufacturing a semiconductor optical device comprising a step of oxidizing the first semiconductor layer along the surface direction of the first semiconductor layer after being stacked,
The first semiconductor layer is made of a material whose oxidation rate has a film thickness dependency of the first semiconductor layer and has a maximum at a predetermined film thickness in the first semiconductor layer, and the first semiconductor layer is formed into the predetermined semiconductor layer. A method of manufacturing a semiconductor optical device, wherein the film thickness is less than 1.5 times the film thickness.   The method of manufacturing a semiconductor optical device according to claim 1, comprising a step of alternately stacking a plurality of the first semiconductor layers and the second semiconductor layers. The semiconductor substrate is an InP substrate, and the first semiconductor layer is an Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1 , 0 ≦ z <1). 3. The method of manufacturing a semiconductor optical device according to claim 1, wherein:   In a configuration in which the first semiconductor layer is sandwiched between at least two second semiconductor layers, a band gap of the first semiconductor layer is provided between at least one of the first semiconductor layer and the second semiconductor layer. 4. The method of manufacturing a semiconductor optical device according to claim 1, further comprising a step of forming a band gap intermediate layer having a band gap between the second semiconductor layer and a band gap of the second semiconductor layer. .   The band gap intermediate layer includes an n-type AlGaInAs layer when the first semiconductor layer and the second semiconductor layer are n-type semiconductor layers, and the first semiconductor layer and the second semiconductor layer are p-type semiconductor layers. 5. The method of manufacturing a semiconductor optical device according to claim 4, comprising a p-type GaInAsP layer.   5. The band gap intermediate layer is formed on the upstream side of the first semiconductor layer along a moving direction of majority carriers in the first semiconductor layer and the second semiconductor layer with respect to the first semiconductor layer. 5. A method for producing a semiconductor optical device according to 5.   The semiconductor according to claim 1, further comprising a step of forming a heating portion above the waveguide layer after forming the waveguide layer above the first semiconductor layer. Manufacturing method of optical element. Above the InP substrate,
Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1) substantially lattice-matched to the InP substrate A low thermal conductive layer having at least one Al _{1 -xy} Ga _x In _y As _{1 -z} P _z oxide layer in which is oxidized;
A waveguide layer provided in an upper layer of the region where the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z oxide layer in the low thermal conductive layer is provided uniformly;
And a heating section provided in an upper layer of the waveguide layer.   9. The semiconductor optical device according to claim 8, wherein an active element having an active function and a passive element having a passive function are monolithically provided above the InP substrate.   The semiconductor optical device according to claim 9, wherein the low thermal conductive layer is selectively provided in at least a part of the lower layer of the passive device.   The semiconductor optical device according to claim 9, wherein the active device is at least one of a semiconductor optical amplifier, a DFB laser, and a DBR laser.   The semiconductor optical device according to claim 9, wherein the passive device is at least one of a waveguide and a ring resonance filter. An Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer (0 <x + y <1, 0 ≦ x <1, 0 <y <1, 0 ≦ z <1) is formed on at least a part of the lower layer of the active element. And the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer is sandwiched by another semiconductor layer having a composition different from that of the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer in the structure, at least one of between the _{Al 1-xy Ga x in y} as 1-z P z layer and the further semiconductor layer, the _{Al 1-xy Ga x in y} as 1-z P z layer The semiconductor optical device according to claim 9, further comprising a band gap intermediate layer having a band gap between a band gap and a band gap of the other semiconductor layer. The band gap intermediate layer includes an Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer and an n-type AlGaInAs layer when the another semiconductor layer is an n-type semiconductor layer, and the Al _{1 -xy Ga x in y as 1-z} P z layer and a semiconductor optical device according to claim 13 in which said another semiconductor layer is characterized by comprising a p-type GaInAsP layer when a p-type semiconductor layer. The band gap intermediate layer is different from the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer in the Al _{1 -xy} Ga _x In _y As _{1 -z} P _z layer and the other semiconductor layer. 15. The semiconductor optical device according to claim 13, wherein the semiconductor optical device is provided on an upstream side in a movement direction of majority carriers.

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