JP2017159008A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of stably achieving a diversified image performance.SOLUTION: A VDP circuit 52 receives a display list DL from a CPU circuit 51 for controlling an image performance, and generates image signals of a plurality of display devices DS3, DS4. The VDP circuit 52 outputs composite image signals for identifying all of the frames of the predetermined display devices DS3, DS4.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a gaming machine that performs a lottery process resulting from a gaming operation and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine that can stably execute a powerful image effect.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP 2013-128576 A

  In this type of gaming machine, it is desired to make various productions complicated and rich, especially for image production. Therefore, we want to use a large display device and increase the resolution of each image including high-speed moving images. Further, if the number of display devices can be increased, the image effects can be further enriched.

  However, in order to display a high-resolution video or still image on a large screen, the amount of data for one frame increases accordingly, so high-speed transmission from the image control board to the display device is necessary. If a transmission error occurs, the image production will be spoiled. Further, when the number of display devices increases, even if LVDS transmission lines are used, the number of wirings becomes enormous, which is also a problem. As described in Patent Document 1, N × 5 pairs of differential signal lines are required corresponding to the number N of display devices.

  In Japanese Patent Laid-Open No. 2004-260260, a configuration using V-by-One (registered trademark) is proposed in order to suppress an increase in the number of wirings. Since only data can be transmitted, high image quality cannot be achieved. Further, according to the inventor's study, V-by-One transmission may cause a transmission error when the transmission distance exceeds 1 m in a poor noise environment such as a gaming machine.

  This invention is made in view of said subject, Comprising: It aims at providing the game machine which can implement | achieve various image effects stably.

  In order to achieve the above object, the present invention provides a plurality of image effects corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means. A gaming machine provided with sub-control means that can be executed using a display device, wherein the sub-control means outputs a drawing instruction for specifying display contents of a plurality of display devices during a predetermined presentation, Image production control means for centrally controlling the production, data storage means for storing compressed data that constitutes still images and / or moving images constituting the image production, and the drawing instruction received from the image production control means And an image generating means for accessing the data storage means to generate an image signal, and a signal converting means for converting the image signal generated by the image generating means and outputting it. , The image generation means on the image signal generated includes a composite image signal for specifying the frame of the predetermined display device.

  The composite image signal is preferably transmitted to the predetermined display device after being divided by the signal conversion means. The plurality of display devices are divided into a main display device that mainly executes a series of image effects leading to a lottery result notification operation of a lottery process, and a sub-display device having a smaller screen than the main display device, The predetermined display device preferably belongs to the sub display device and is configured to have the same number of pixels constituting each display screen.

  In this case, the main display device receives the first signal and the second signal obtained by dividing the image data for specifying one frame from the signal conversion unit, and restores the original image data by a built-in circuit, thereby obtaining a predetermined signal. It is preferable to draw one frame composed of vertical and horizontal pixels.

  Further, the sub display device receives the image data specifying one frame as a differential signal from the signal conversion means and receives the restored image data from a receiving circuit that restores the image data, and receives a predetermined vertical and horizontal pixel. It is preferable that one constructed frame is drawn. Here, the pixel pitch of the sub display device is equal to or less than ½ of the pixel pitch of the main display device in both the horizontal direction and the vertical direction, and the pixel gradation is equal to or higher than that of the main display device. Preferably there is.

  Preferably, the predetermined display device is a plurality of N sub-display devices having the same number of vertical and horizontal pixels constituting the display screen. Preferably, the composite image signal is configured by connecting N pieces of image data for specifying a frame of each display screen in a vertical direction or a horizontal direction of the display screen for a plurality of N sub display devices. . The composite image signal includes vertical stripe information for specifying X pixel information in the vertical direction of each display screen for a plurality of N sub-display devices having a display screen having a vertical pixel number (X) and a horizontal pixel number (Y). It is preferable that the composite sprite information obtained by concatenating N is connected Y times corresponding to Y pixel columns.

  N work areas are provided corresponding to a plurality of N sub-display devices, and the image generation means assigns each image data specifying each frame of the N display devices to N work areas. It is preferable to complete them separately. On the other hand, N-1 work areas are provided corresponding to a plurality of N sub-display devices, and the image generation means stores each image data specifying each frame of the N-1 display devices, It is also preferable that the image data for specifying one frame of the remaining one sub display device is completed in the frame buffer, separately in N-1 work areas. In addition, each image data specifying each frame of a plurality of N display devices can be completed in the frame buffer without going through the work area. In addition, it is preferable that the plurality of display devices include a pair or a plurality of pairs of display devices that are movable and display a unified image when necessary.

  According to the above-described gaming machine of the present invention, high-resolution image effects can be stably realized, and by increasing the number of display devices, variations-rich image effects can be realized.

It is a perspective view of the pachinko machine shown in an example. The front view which shows the game board of the pachinko machine of FIG. 1, and the resolution of each display apparatus are illustrated. It is a block diagram which shows the whole structure of the pachinko machine of an Example. FIG. 4 is a block diagram illustrating a circuit configuration of an effect control unit and an image control unit. 2 is a diagram illustrating a configuration of a timepiece IC. It is a block diagram which shows the internal structure of the composite chip in charge of image production. It is drawing explaining the operation | movement procedure which implement | achieves the memory content of memory, and image production. 6 is a diagram illustrating an operation of a display circuit. It is drawing explaining the 1st structure from a VDP circuit to a display apparatus. It is drawing explaining the signal converter circuit TX1 regarding the LVDS signal for main display apparatuses DS1. It is drawing explaining the signal conversion circuit TX2 regarding the LVDS signal for sub display apparatus DS2. It is a figure explaining the signal conversion circuit TX3 regarding the RGB signal for sub display apparatuses DS3 and DS4, and serial receiving circuits RV2-RV4. It is a flowchart explaining the internal operation | movement of a composite chip | tip about 1st Example which does not use a preloader. 6 is a diagram for explaining the operation of the CPU and the operation of the internal circuit of the VDP circuit in the first embodiment. It is a flowchart explaining the internal operation | movement of a composite chip | tip about 2nd Example using a preloader. It is drawing explaining operation | movement of CPU and operation | movement of the internal circuit of a VDP circuit about 2nd Example. It is drawing explaining the 2nd structure from a VDP circuit to a display apparatus. It is drawing explaining the 3rd structure from a VDP circuit to a display apparatus. It is drawing explaining the 4th composition from a VDP circuit to a display. It is drawing explaining the 5th structure and 6th structure from a VDP circuit to a display apparatus. It is drawing explaining signal conversion circuit TX2 'which implement | achieves 2nd structure. It is drawing explaining another signal conversion circuit TX3 'which implement | achieves a 2nd structure. It is drawing explaining signal conversion circuit TX4, TX4 'which implement | achieves a 3rd structure and a 4th structure. It is drawing explaining the modification of a 4th structure. It is drawing explaining a stripe connection process. It is drawing explaining the 7th structure from a VDP circuit to a display apparatus. It is drawing explaining the 8th structure from a VDP circuit to a display apparatus. It is drawing explaining the signal converter circuit TX5 of 7th structure, and the serial receiver circuit RV5. It is drawing explaining a light control circuit. The internal structure of the PS converter and SP converter is illustrated. It is a figure explaining the signal converter circuit TX5 of 8th structure, and the serial receiver circuit RV5. It is drawing explaining the 9th structure from a VDP circuit to a display apparatus. It is drawing explaining the movable mechanism of a display apparatus. It is drawing explaining the movable production | presentation of a display apparatus.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  In the central opening HO, for example, a main display device DS1 composed of a large liquid crystal color display (LCD) of about 19 inches is disposed. On the right side of the main display device DS1, for example, a small liquid crystal of about 5 inches is arranged. A sub display device DS2 configured with a color display is arranged. Further, below the main display device DS1, movable sub-display devices DS3 to DS4 each having a small size of a liquid crystal color display and having a size of about 5 inches are arranged in a concealed state.

  Although not particularly limited, the main display device DS1 has an effective display area of, for example, about 376.32 (H) × 301.056 (V) mm and a pixel pitch of 0.294 (H) ×. It is about 0.294 (V) mm. Further, the sub display devices DS2 to DS4 have an effective display area of, for example, about 64.8 (H) × 108.0 (V) mm, and a pixel pitch is set to ½ or less of the main display device DS1. 0.135 (H) × 0.135 (V) mm.

  The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device DS1 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, a reach effect that expects a big hit state may be executed, and in the special symbol display portions Da to Dc and the surroundings, a notice effect such as an appropriate video is executed. The

  The sub display device DS2 is arranged in a fixed state. However, when necessary, one or both of the other two sub display devices DS3 to DS4 rise from the concealed state and cooperate with the sub display device DS2. It is configured to realize the image preview effect that worked. That is, the sub display devices DS3 to DS4 of the embodiment function not only as a display device but also as a movable effect body that executes a notice effect. Here, in the notice effect by the sub display device DS3 and / or the sub display device DS4, the reliability thereof is appropriately set high according to the number of appearances, and the player has a great expectation and the sub display device DS3. Note the appearance of DS4 and / or.

In this embodiment, not only the main display device DS1 but also the sub-display devices DS2 to DS4 perform image effects. As shown in FIG. 2B, the main display device DS1 has horizontal H = 1280 pixels, vertical Each pixel P (i, j) is configured to have 256 (= 2 ⁸ ) gradations for all three RGB colors by controlling the luminance of each of the three RBG colors with 8 bits. However, in the configuration of the present embodiment, 1024 (= 2 ¹⁰ ) gradation can be realized by controlling the luminance of the three RBG colors by 10 bits each.

  Thus, since one frame of the main display device DS1 is composed of 1280 × 1024 pixels from the upper left pixel P (1, 1) to the lower right pixel P (H, V), this is 1/60 second. The dot clock (pixel clock) in the case of updating every time is about 108 MHz corresponding to 1280 × 1024 × 60, and if this is transmitted by LVDS over a single transmission line, there is a risk of noise superimposition or erroneous transmission.

  Therefore, in this embodiment, for the pixel data of P (1, 1) to P (H, V), the odd-numbered pixels and the even-numbered pixels in the horizontal direction (H) are separated by separate transmission paths (LVDSa, LVDSb). LVDS (Low voltage differential signaling) transmission (see FIG. 4) avoids noise superposition and erroneous transmission regardless of the transmission distance. This operation is illustrated in FIG. 2B. Of the 1280 columns of vertical lines, the odd lines are transmitted by the transmission line LVDSa, while the even lines are transmitted by the transmission line LVDSb. Stable LVDS transmission is realized by suppressing the dot clock to 1/2 (54 MHz).

  In the present specification, hereinafter, for the sake of convenience, an operation for dividing one frame of the display screen into odd lines and even lines may be referred to as stripe division, and an operation for restoring the original one frame may be referred to as stripe connection. In the first configuration, the second configuration, and the fifth configuration, which will be described later, one frame is divided in the vertical direction, but there is no limitation, and horizontal stripe division and stripe connection are also possible.

  In addition, it is not always necessary to divide every horizontal line or vertical line, and it is possible to divide and divide each horizontal frame or vertical line into rectangular frames, or to conversely connect them. Is preferred. These points apply not only to the main display device DS1, but also to the sub display devices DS2 to DS4 (see the third configuration and the fourth configuration).

  Next, each of the three sub display devices DS2 to DS4 is composed of 480 pixels in the horizontal direction and 800 pixels in the vertical direction, and each pixel (pixel) is controlled in luminance by 8 bits for each of the RBG three colors. Both colors are realized in 256 shades. The dot clock when one frame is updated every 1/60 seconds is about 27 MHz corresponding to the total number of pixels.

  Here, if the image data used in the sub-display devices DS2 to DS4 is transmitted by LVDS, five pairs of differential signal paths are required even if serial transmission is performed, and wiring inside the gaming machine becomes complicated. . Therefore, in this embodiment, the transmission path to each of the sub display devices DS2 to DS4 is realized by a pair of differential signals to be described later with reference to FIG. It is greatly suppressed.

  Further, in this embodiment, a total of four display devices DS1 to DS4 are arranged, and these are mixed with one frame of each of the two display devices DS3 and DS4 to generate a single display processor (VDP). Generated composite frame. These will be further described later.

  Returning to the configuration of the game board 5, the description will be continued. In the game area where the game ball falls and moves, the first symbol starting port 15a, the second symbol starting port 15b, the first major winning port 16a, and the second major winning port. 16b, the normal winning opening 17, and the gate 18 are arrange | positioned. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  In other words, when a game ball wins the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (hit state) varies according to the jackpot symbols to be arranged, etc., which game value is given based on the lottery result according to the winning timing of the game ball in advance It is determined.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 shows a part of it in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. A main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD received from the effect control board 22 The image control board 23 that drives the two display devices DS1 and DS2 based on 'and the payout control board 24 that controls the payout motor M based on the control command CMD "received from the main control board 21 to pay out the game ball. And a launch control board 25 that launches a game ball in response to the player's operation.

  As illustrated, the control command CMD output from the main control board 21 is transmitted to the effect control board 22. The control command CMD ″ output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

  The control commands CMD, CMD ′, and CMD ”are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel every two 8 bits. On the other hand, the control command CMD ′ transmitted from the effect control board 22 to the image control board 23 is transmitted in parallel with a 16-bit length. Even when such control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  As shown in the figure, in this embodiment, a liquid crystal interface board 28 accessible from the image control board 23 and the effect control board 22 is provided. The liquid crystal interface board 28 is equipped with a clock circuit (real time clock) RTC capable of measuring the current time and a memory element (Static Random Access Memory) SRAM for storing game performance information.

  In this embodiment, the image control board 23 drives the main display device DS1 and the three sub display devices DS2 to DS4 via the liquid crystal interface board 28 on which the signal conversion unit CNV is mounted. . Here, the liquid crystal interface board 28 and the image control board 23 are directly connected to the male connector and the female connector without going through a wiring cable. Similarly, for the effect control board 23 and the liquid crystal interface board 28, the male connector and the female connector are directly connected without going through the wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  A computer circuit such as a one-chip microcomputer is mounted on each of the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24. Therefore, the control board 21 to 24 and the circuit mounted on the liquid crystal interface board 28 and the operations realized by the circuit are collectively referred to as a function. 22, image control unit 23, and payout control unit 24. Note that, with respect to the main control unit 21, all or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 become sub-control units.

  This pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display devices DS1, DS2 to DS4 and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect control unit 22 as they are. Then, the effect control unit 22 outputs the received system reset signal SYS to the image control unit 23 as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputer 40 and the image control section of the effect control unit 22 by this power supply reset signal. The built-in CPU circuit 23 is reset with a power supply together with other circuit elements and internal circuits including VDP.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the output from the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS is used.

  The reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and each CPU is provided unless a regular clear pulse is received from the CPU of each control unit 21, 24. Is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22, the image control board 23, and the liquid crystal interface board 28 are integrated by connector connection, and the effect control unit 22 is connected to the power supply board 20 via the power relay board 33. The DC voltage (5V, 12V, 32V) of each level and the system reset signal SYS are received (see FIGS. 3 and 4A).

  The effect control unit 22 receives a control command CMD and a strobe signal STB from the main control unit 21. Then, the effect control unit 22 serially transmits the lamp drive signal SDATA to the driver ICs mounted on the lamp drive board 36, the lamp drive board 29, and the motor lamp drive board 30 in synchronization with the clock signal CK. A lamp group composed of a large number of LED lamps and electric lamps is driven to realize a lamp effect based on the control command CMD.

  In the case of this embodiment, the lamp effect is executed by the three lamp groups CH0 to CH2, and the lamp driving board 36 receives the CH0 lamp driving signal SDATA0 via the frame relay boards 34 and 35 as a clock. It is received in synchronization with the signal CK0 (clock synchronous serial communication). Note that a series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, so that the lighting state is updated all at once.

  The same applies to the lamp drive board 29. The driver IC of the lamp drive board 29 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. The lighting state of the lamp group CH1 is updated all at the same time.

  On the other hand, the driver IC mounted on the motor lamp driving board 30 receives the lamp driving signal transmitted in a clock synchronous manner to drive the lamp group CH2, and receives the motor driving signal transmitted in a clock synchronous manner, The effect motor groups M1 to Mn composed of a plurality of stepping motors are driven. The lamp driving signal and the motor driving signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives the signals transmits the timing at which the operation control signal ENABLE2 changes to the active level. Thus, the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

  In addition, the effect control unit 22 sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). Is output. The image control unit 23 drives the display devices DS1 to DS4 based on the control command CMD 'to execute various image effects.

  As shown in FIGS. 3 and 4A, the image control unit 23 includes a built-in CPU circuit (image production control device) 51 having an internal configuration equivalent to that of a general-purpose one-chip microcomputer, a VDP (Video Display Processor) 52, It is comprised centering on the composite chip | tip 50 which incorporated. In addition, a control memory (PROM) 53 that stores a control program for the built-in CPU, a DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at high speed, and a CGROM 55 that stores a large amount of CG data necessary for image control. And are installed.

  The image data generated by the VDP 52 based on the CG data read from the CGROM 55 is transmitted to the liquid crystal interface board 28 as the first and second LVDS signals (LVDS_1, LVDS_2) and the RGB parallel signal RGB_P. As shown in the figure, the liquid crystal interface substrate 28 is equipped with a signal conversion unit CNV for converting the signal format of each signal (LVDS_1, LVDS_2, RGB_P). As will be described later, the signal conversion unit CNV includes three conversion circuits TX1 to TX3 (FIGS. 9 to 11).

  The first LVDS signal LVDS_1 is image data for the main display device DS1, and specifies one frame composed of 1280 × 1024 pixels as described with reference to FIG. 2B. In this embodiment, the LVDS signal LVDS_1 with a dot clock of 108 MHz is striped into two LVDS signals (LVDS_a and LVDS_b) by the signal converter CNV in order to reliably transmit the 1280 × 1024 pixel data. Thus, image data of 640 × 1024 pixels (= 655, 360) is transmitted in 1/60 seconds (see FIG. 2B).

  Therefore, the dot clocks of the two systems of LVDS signals (LVDS_a, LVDS_b) are each suppressed to about 54 MHz by passing through the conversion circuit (see FIG. 9) of the signal conversion unit CNV.

  The second LVDS signal LVDS_2 is image data for the sub display device DS2, and identifies one frame composed of 480 × 800 pixels as described with reference to FIG. In this embodiment, the LVDS signal LVDS_2 (five pairs of differential signals) transmitted to the liquid crystal interface substrate 28 is converted into a signal in order to transmit the 480 × 800 pixel data through the minimum transmission wiring. In the conversion circuit TX2 (see FIG. 9A and FIG. 11) of the part CNV, the signal is converted into a pair of differential signals SER2.

  The data transmitted by the pair of differential signals SER2 is image data (1 pixel = 24 bits long) for the sub display device DS2. In this embodiment, as will be described later with reference to FIG. 11B, scrambled 36-bit serial data is transmitted during one period of a dot clock (pixel clock) of about 27 MHz. Therefore, the communication speed is about 27 MHz × 36 = 972 MHz. Hereinafter, in this specification, such a serial signal will be referred to as a high-speed serial signal SERi for convenience (i = 1 to 5).

In this embodiment, not the V-By-One signal but the high-speed serial signal shown in FIG. 11B is used. Therefore, in the sub display devices DS2 to DS4 set to a pixel pitch of 1/2 or less of the main display device DS1, each pixel (pixel) can be controlled in 256 gradations, and the maximum is 16,777,216 (= 256). ³ ) A high-quality image effect (notice effect) with various colors is possible. Note that the image effects in the sub display devices DS2 to DS4 include moving image effects.

  Next, the RGB parallel signal RGB_P is a parallel signal including an 8-bit RGB signal having a total length of 24 bits and a synchronization signal. However, as described with reference to FIG. 2B, the VDP 52 of this embodiment outputs a composite frame obtained by mixing each frame of the display devices DS3 and DS4 in the form of a composite RGB parallel signal RGB_P. In this embodiment, the composite frame is twice as large as 480 × 800 pixels, so that the composite RGB parallel signal RGB_P specifies 960 × 800 (= 768,000) pixels, and its dot clock is about 54 MHz. It becomes.

  Upon receiving this, the conversion circuit TX3 (see FIG. 12) of the signal conversion unit CNV divides the composite RGB parallel signal RGB_P into RGB parallel data of the display device DS3 and the display device DS4, and each RGB parallel data is Each is converted into a pair of differential signals SER3 and SER4.

  Although not particularly limited, the differential signals SER3 and SER4 have the same format as the high-speed serial signal described above. Further, the configuration and operation of each of the conversion circuits TX1 to TX3 that realize the signal conversion unit CNV will be further described later with reference to FIGS.

  Continuing with FIG. 4, as shown in FIG. 4, the main display device DS1 incorporates an LVDS receiver RV1 that receives two LVDS signals (LVDS_a, LVDS_b). Then, the LVDS reception unit RV1 restores 1280 × 1024 pixel data (striped) based on the LVDS signal LVDS_a that identifies the odd lines and the LVDS signal LVDS_b that identifies the even lines shown in FIG. Connection), rendering of one frame of the main display device DS1 is realized based on the stripe-connected RGB data.

  Further, serial reception circuits RV2 to RV4 are arranged corresponding to the three high-speed serial signals SER2 to SER4 and the three sub display devices DS2 to DS4. Then, in each of the serial reception circuits RV2 to RV4, 480 × 800 pixel data is restored based on the received high-speed serial signals SER2 to SER4, and each display device DS2 to DS4 is restored based on the restored RGB data. A single frame drawing is realized.

  Next, the configuration of the effect control unit 22 will be described in more detail based on FIG. As shown in FIG. 4A, the effect control unit 22 includes a one-chip microcomputer 40 (effect control CPU 40) that executes processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer, and effect control CPU 40. A control memory (flash memory) 41 for storing the control program and various effect data EN, and a sound processor 42 for reproducing and outputting a sound signal based on the instructions of the effect control CPU 40 set in the built-in registers RG0 to RGn The audio memory 43 stores compressed audio data that is the original data of the audio signal to be reproduced, and the digital amplifier 46 receives the audio signal output from the audio processor 42.

  In the case of the present embodiment, the effect data EN stored in the control memory 41 includes scenario data for managing the effect progress of the lamp effect and the sound effect, lamp drive data for determining the blinking mode of the LED, and motor rotation. Motor drive data for determining the mode. The lamp driving data and the motor driving data are sequentially output bit by bit to become a lamp driving serial signal and a motor driving serial signal.

  The one-chip microcomputer 40 includes a plurality of serial input / output ports SIO and a plurality of parallel input / output ports PIO. The serial input / output port SIO includes a serial output port Soi that outputs a lamp driving signal of CHi or a motor driving signal SDATAi in synchronization with the clock signal CKi, and origin sensor signals (serial signals) of the motor groups M1 to Mn. And a serial port Si that receives the signal in synchronization with the clock signal CK3. Note that i = 0 to 2, and corresponds to the three groups of lamp groups CH0 to CH2 and the motor groups M1 to Mn driven together with the lamp groups of CH2.

  On the other hand, the parallel input / output port PIO is divided into output ports Po and Po 'and an input port Pi. A control command CMD and a strobe signal STB from the main control unit 21 are input to the input port Pi. On the other hand, operation control signals ENABLE0 to ENABLE2 are output from the output port Po ', and a control command CMD' and a strobe signal STB 'are output from the output port Po. Specifically, after the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are stepped down to a logic level corresponding to the power supply voltage 3.3 V of the one-chip microcomputer 40 in the buffer 44, It is supplied to the input port Pi in two in 8 bit units. The interrupt signal STB is supplied to the interrupt terminal of the effect control CPU 40, and the effect control unit 22 is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 includes (1) an abnormality notification and other notification control commands, and (2) a control command for specifying an outline of various effect operations resulting from winning at the symbol start opening. (Variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ relating to the performed image effect is output.

  In order to realize an image effect synchronized with such an effect operation, the effect control unit 22 sends a 16-bit control command CMD ′ along with a strobe signal (interrupt signal) STB ′ to the image control unit 23 through the output port Po. Output. In addition, when receiving the symbol designation command, the abnormality notification control command, and other control commands, the effect control unit 22 collects the 8-bit unit control commands in a 16-bit length, It is output to the image control unit 23 together with STB ′.

As described above, the audio processor 42 according to the present embodiment accesses the audio memory 43 based on an instruction (set value by the audio command SND) received from the effect control CPU 40 to the built-in registers (audio control registers) RG0 to RGn. The necessary audio signal is played back and output. As shown in the figure, the audio processor 42 and the audio memory 43 are connected to each other by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, 1 Gbit (= 2 ²⁶ * 16) data can be stored in the audio memory 43. In the case of the present embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a phrase number (000H to 1FFFH) having a 13-bit length, and is a sequence of background music. (BGM), a group of effect sounds (notice sounds), and the like are stored in a maximum of 8192 types (= 2 ¹³ ), each corresponding to a phrase number. The phrase number is specified by the set value of the voice command SND transmitted from the effect control CPU 40 to the voice control registers RG0 to RGn of the voice processor 42.

  The voice command SND is a plurality (2 or 3) bytes long, and is used for a write purpose of transmitting a predetermined set value to any one of the many voice control registers RG0 to RGn built in the voice processor 42. The However, the voice command SND of the present embodiment is used not only for a write application for writing a set value such as a phrase number, but also for a read application for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined audio control register RGi to be accessed is specified by a 1-byte register address.

  The setting (Write) of the set value to the sound control register RGi is not necessarily executed individually for each sound control register, and a group of sound control is performed by designating the SAC data stored in the sound memory 43. A series of setting operations for the registers RGi to RGj can be completed. Here, the SAC data is an aggregate of a maximum of 512 pieces (up to 1024 bytes) in which the register address (1 byte) of the voice control register RGi is associated with the set value (multiple bytes) in the voice control register RGi. Means. In the present embodiment, only a necessary set of such SAC data is stored in the audio memory 43 in advance, and a set of SAC data is specified by a SAC number of about 13 bits that is a single ID information. It is like that.

  Therefore, in the case of the present embodiment, the voice command SND for write use specifies a SAC number and specifies a set of SAC data, or specifies a set value and a register address individually.

  As shown in FIG. 4 (b), the connection control main part describes the effect control CPU 40 and the audio processor 42 with parallel signal lines (data buses) CD0 to CD7 capable of transmitting and receiving 1-byte data, and operation management data. Chip that selects 2-bit operation control data lines (address bus) A0 to A1 that can be transmitted, 2-bit control signal lines WR and RD that can control read / write operations, and a voice processor 42 It is connected to a select signal line CS.

  The parallel signal lines CD0 to CD7 are realized by the data bus of the effect control CPU 40, and the operation management data lines A0 to A1 are realized by the address bus of the effect control CPU 40, and are connected to the effect control CPU 40, respectively. Yes. Then, when the production control CPU 40 executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR and RD and the chip select signal CS are appropriately changed, and the audio specified by the parallel signal lines CD0 to CD7. A read / write (R / W) operation with the control register RGi is realized.

  Specifically, as shown in the time chart of FIG. 4B ', the register address of the audio control register RGi and the write data to the audio control register RGi are transmitted in parallel through the parallel signal lines CD0 to CD7, respectively. Is done. Whether the 1 byte transmitted in parallel is a register address or write data (write data) is specified by the operation management data A0 to A1.

  Accordingly, as shown in FIG. 4B, the operation management data (address data A0 to A1) is changed from [00] to [01], while 1-byte data on the data bus is changed to [voice control register RGi. A predetermined voice command SND is transmitted by transiting from “register address” → [write data to voice control register RGi]. When the write data is a plurality of bytes long as in the case of transmitting the SAC number (13 bits), the operation management data A0 to A1 of [01] are changed from [00] → [01] → [01]. → Send the data of multiple bytes while repeating [01].

  The voice command transmitted in this way is subsequently validated as long as there is no communication abnormality. However, if a communication error is recognized, such as data having a plurality of bytes inconsistent with each other, the voice command SND is not activated. Then, the error flag of the voice control register RGn is set. This error flag (status information STS) is produced by changing the operation management data A0 to A1 of the address bus from [01] to [10]. The control CPU 40 can receive it by the Read operation.

  As described above, in this embodiment, error information (abnormality of a plurality of bits) is obtained in the final cycle in which the operation management data A0 to A1 are changed from [00] → [01] →... [01] → [10]. FFH) can be obtained. Then, by retransmitting the voice command SND that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness that the sound effect suddenly stops.

  In the configuration of FIG. 4B, the effect control CPU 40 receives the status information STS including error information in parallel from the audio processor 42, but the configuration is not limited to this configuration. That is, it is also preferable to adopt a configuration in which an interrupt signal is output to the effect control CPU 40 when the sound processor 42 recognizes a communication error. In this case, the sound in which the communication error has occurred in the interrupt processing program of the effect control CPU 40. You can resend the command. If such a configuration is adopted, an error flag (status information STS) acquisition process that is a useless process in most cases, that is, a process of transitioning the operation management data A0 to A1 to [10] may be omitted. it can.

  As shown in FIGS. 3 and 4A, in this embodiment, the left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, it is necessary for the audio processor 42 to generate a 3-channel audio signal. If this is transmitted in parallel, the wiring between the audio processor 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the sound processor 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. Are suppressed to a total of 4-bit signal lines including the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SD1 and SD2.

  Here, SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SD2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The audio processor 42 transmits the audio signal L of the left channel while maintaining the channel control signal LRCLK at the L level, and outputs the audio signal R of the right channel while maintaining the channel control signal LRCLK at the H level. To transmit. Since there is one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than parallel transmission.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  4A, a buffer circuit 47 that transfers serial data SDATAi output from the serial output port Soi of the serial input / output port SIO of the one-chip microcomputer 40 and the clock signal CKi to the effect control board 22. -49 are provided (i = 0-2).

  Here, the output buffer 47 transfers the lamp drive signal SDATA0 and the clock signal CK0 output from the serial output port So0 to the shift register circuit (driver IC) of the lamp drive substrate 36. The output buffer 48 transfers the lamp drive signal SDATA1 and the clock signal CK1 output from the serial output port So1 to the driver IC of the lamp drive substrate 29. As described above, the driver ICs mounted on the lamp driving substrates 29 and 36 drive and drive the lamp groups CH0 and CH1.

  On the other hand, the buffer circuit 49 functions as an input / output buffer, and transfers the serial signal SDATA2 output from the serial output port So2 to the motor lamp driving substrate 30 together with the clock signal CK2. Further, an origin sensor signal (serial signal) indicating the origin position of the group of effect motors M1 to Mn is transferred to the serial input port Si of the one-chip microcomputer 40 in synchronization with the clock signal CK3.

  In this embodiment, the serial signal SDATA2 transferred by the buffer circuit 49 includes a lamp drive signal (serial signal) for lighting the lamp group CH2 and a motor drive signal (serial signal) for rotating the effect motors M1 to Mn. ) Are continuous. The motor lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  Next, as shown on the left side of FIG. 4A, in this embodiment, the data bus and the address bus of the effect control CPU 40 extend to the liquid crystal interface board 28. For convenience of explanation, this relationship is illustrated on the left side of FIG. 4A, but the clock circuit RTC is connected to the CPU by the lower 4 bits of the address bus of the effect control CPU 40 and the lower 4 bits of the data bus. It is configured to be arbitrarily accessible. In addition, the memory element SRAM for storing game performance information enables the effect control CPU 40 to randomly access the 16 bits of the address bus of the effect control CPU 40 and the lower 16 bits of the data bus.

  The clock circuit RTC is a clock IC (real-time clock) that measures the current date and time, and operates permanently with the secondary battery BT charged with the power supply voltage received from the effect control board 22 together with the memory element SRAM. doing. That is, while the gaming machine is powered on, the secondary battery BT (FIG. 5) is charged, and after the gaming machine is powered off, based on the charged secondary battery BT, The timekeeping operation of the clock circuit RTC is continued, and the effect data is also permanently stored (backup operation).

  As shown in FIG. 5, the clock circuit RTC of the embodiment is connected to the effect control CPU 40 through a 4-bit data bus, a 4-bit data bus, and a control bus RD + WR for Read / Write operation. Then, the effect control CPU 40 adds important game information and abnormality information related to the game operation to the memory element SRAM by adding the year / month / day information, day information and time information acquired from the clock circuit RTC. .

  This clock circuit RTC has two types of chip select terminals, CS1 and CS0 bars, and permits access from the effect control CPU 40 on condition that the input voltage to each terminal is at a normal level. It has become. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detecting unit ER, and when the CS1 terminal receives the abnormal level output Vo, the abnormality detection flag Fos of the clock circuit RTC is automatically set. To be set.

  In the case of the present embodiment, this abnormality detection flag Fos is determined by the effect control CPU 40 together with other abnormality detection flags TEMP when the power is turned on. If the abnormality detection flag Fos is set, the date and time at that time and The time is reported. Therefore, if an abnormality in the clock function is recognized, it can be dealt with quickly.

  Even if the voltage of the secondary battery BT drops when the power is shut down, the voltage level of the secondary battery BT is quickly recovered by power recovery and the CS1 terminal returns to the normal level, so access from the effect control CPU 40 is permitted. Will be. Therefore, if the configuration of the present embodiment in which the determination process for the abnormality detection flag Fos is not employed, the abnormality of the clock circuit RTC may not be detected permanently.

  Further, the clock circuit RTC of the embodiment is configured to output the interrupt signal IRQ once a week, for example, every Friday at 21:50. In the effect control CPU 40 that receives the interrupt signal IRQ, The game information and abnormality information accumulated in the memory element SRAM so far are appropriately tabulated.

  The game information to be aggregated is a summary of history information related to the big hit state. For example, (1) the number of winnings to the symbol start opening required to become the big hit state, (2) the symbol of the big hit state, Total value and statistical value of jackpot state whether or not it is probable, (3) type of notice effect or reach effect that reached the big hit state, (4) number of consecutive chants, (5) number of balls thrown out by consecutive chans Increasing trends are included. And these total information and statistical information are alert | reported suitably according to a player's request | requirement. The player's instruction is specified, for example, by pressing the chance button 11 during the demonstration effect, and the notification content is displayed on the display device DS1.

  On the other hand, the abnormal information to be tabulated includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of detection times and the detection time of the detection sensor for detecting illegal activities, This includes the number of detections, detection frequency, detection time, etc. of an act of forcibly opening the winning opening 16 with a wire or the like. The total information is displayed on the display device DS1 in response to a special operation by an attendant.

  As shown in FIG. 5A, the clock circuit RTC according to the embodiment is configured by incorporating three internal register tables Bank0 to Bank2. However, since the bank 2 register table relates to time setting and date setting, only the bank 0 and bank 1 register tables are shown in FIGS. 5 (b) and 5 (c). In any case, each register table is composed of 4 bytes × 16 registers, and the current date and time measured by the internal circuit are written in the Bank0 register table (FIG. 5B). It is configured to be.

  As shown in FIG. 5B, in the bank 0 register table, bit 3 of the first register is an abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected an abnormal temperature. This is a temperature abnormality flag TEMP shown. In this embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined, thereby preventing the abnormal timekeeping operation from continuing. In addition, the clock circuit RTC is disposed close to the effect control CPU 40, and the temperature abnormality of the effect control CPU 40 is quickly detected by repeatedly determining the value of the temperature abnormality flag TEMP at appropriate time intervals.

  In the register table of Bank0, bit 0 of the 15th register is a Busy flag indicating that the register table is being updated. In this embodiment, the current date and time are acquired from the register table of Bank 0 on the condition that the Busy flag is in a non-Busy state (update completion). For this reason, in this embodiment, there is no possibility of acquiring halfway during the updating operation or irrational clock information, and the validity of the clock information stored in the memory element SRAM is ensured. For example, if clock information that is being updated from 1:59:59 to 2: 00: 00: 00 is acquired, there is a possibility that the clock information of 1: 0: 0 is acquired.

  Further, the register table of Bank 1 is configured so that the generation time of the interrupt signal IRQ can be set. Therefore, in this embodiment, an interrupt generation is instructed by setting 1 to bit 0 of the register No. 1 of Bank 1 (Interrupt Enable), and the day of the week of Friday is designated in the registers 0 to 8 of Bank 1. Time information of 30:30 hours is set.

  Next, the image control unit 23 will be described in detail with reference to FIGS. First, FIG. 6A is a circuit block diagram illustrating the composite chip 50 constituting the image control unit 23 including related circuit elements. As illustrated, the composite chip 50 of the embodiment includes a built-in CPU circuit 51 and a VDP circuit 52. The built-in CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays mutual transmission / reception data, and a V blank interrupt signal (VBLANK) is supplied from the VDP circuit 52 to the built-in CPU circuit 51. It has come to be.

  Here, the V blank interrupt signal corresponds to the vertical synchronization signal of the display device DS1, and defines the timing at which the output of image data for one frame of the display device DS1 is completed every 1/60 seconds. In this embodiment, of the three display circuits 74A / 74B / 74C, the display circuit 74A is configured to function constantly, while the display circuits 74B to 74C function when necessary and synchronize with the display circuit 74A. As a result, the vertical synchronization signal (V blank interrupt signal) means that the output operation of the display circuit 74A has ended.

  The sequence operation based on the V blank interrupt will be described later. As shown in FIG. 6, the CPU IF circuit 56 has a control memory (PROGRAM_ROM) 53 for storing a control program and necessary control data in a nonvolatile manner, and about 2 Mbytes. Are connected to a work memory (RAM) 57 having the above storage capacity, and can be accessed from the built-in CPU circuit 51.

  The built-in CPU circuit 51 is a circuit having a performance equivalent to that of a general-purpose one-chip microcomputer. A watchdog timer (WDT) 58 forcibly resetting, a RAM 59 having a storage capacity of about 16 kbytes and used as a work area of the CPU, and a DMAC (Direct Memory Access Controller) for realizing data transfer without going through the CPU 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and output ports So, and a parallel input / output port (PIO) 62 having a plurality of input ports Pi and output ports Po. Has been.

  For the sake of convenience, the expression “input / output port” is used in this specification. However, in the image control unit 23, the input / output port includes an input port and an output port that operate independently. The same applies to the input / output circuit 64p and the input / output circuit 64s described below.

  The parallel input / output port 62 is connected to an external device (the effect control board 22) through the input / output circuit 64p, and the image control CPU 63 outputs the output from the effect control unit 22 via the input circuit 64p and the parallel input port Pi. The control command CMD ′ and the interrupt signal STB ′ to be received are received. On the other hand, in this embodiment, the serial input / output port 61 and the DMAC 60 are not used.

  Next, the VDP circuit 52 will be described. The VDP circuit 52 includes a CGROM 55 that stores compressed data that is a constituent element of a still image and a moving image that constitute an image effect, and an external DRAM (Dynamic DRAM having a storage capacity of about 4 Gbits). Random Access Memory) 54, main display device DS1, and sub display device DS2 are connected.

  Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of NAND flash memory having a storage capacity of about 62 Gbit, and compression required by serial transmission. Configured to retrieve data. Therefore, the problem of skew (difference in transmission speed for each bit data) inevitably generated in parallel transmission is solved, and an extremely high-speed transmission operation becomes possible.

  A NAND flash memory is mechanically more stable than a hard disk and can be accessed at a high speed, but is a sequential access memory, and therefore has an access speed higher than that of a DRAM or SRAM (Static Random Access Memory). Inferior, the access speed decreases in the order of built-in VRAM 71> external DRAM 54> CGROM 55. However, by executing a preload operation in which a group of compressed data (CG data) is read to the DRAM 54 prior to the drawing operation, smooth random access of the CG data during the drawing operation can be realized.

  Specifically, the VDP circuit 52 has a register group 70 in which various operation parameters that define the operation of the VDP are set, and about 48 Mbytes used when generating image data to be displayed on the display devices DS1 and DS2. A VRAM (Video RAM) 71, a data transfer circuit 72 for controlling data transmission / reception between each part in the chip and data transmission / reception outside the chip, a preloader 73 for executing a preload operation, and image data in the VRAM 71 are read out as appropriate. 3 (A / B / C) display circuits 74 that execute parallel image processing, a graphics decoder 75 that decodes compressed data read from the CGROM 55, and still image data and moving image data after decoding as appropriate A drawing circuit 76 for generating image data for one frame of each display device DS1 to DS4 in combination with As part of the operation of the drawing circuit 76, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion, an SMC unit 78 capable of transmitting and receiving serial data, and a three-line (A / B / C) display circuit 74 An output selection unit 79 that appropriately selects and outputs an output, two systems of LVDS units 80a and 80b that convert image data output by the output selection unit 79 into LVDS signals, and image data output by the output selection unit 79 are converted into digital RGB Data is transmitted / received to / from the external DRAM 54, the digital RGB unit 80c that outputs signals in parallel, the CPUIF unit 81 that relays data transmission / reception with the CPUIF circuit 56, the CG bus IF unit 82 that relays data reception from the CGROM 55, and the like. A DRAMIF unit 83 for relaying, and a VRAMIF unit 84 for relaying data transmission / reception with the VRAM 71 And it is configured to have.

  In this embodiment, the display circuit 74A corresponds to the first LVDS unit 80a and the display circuit 74B is the second LVDS unit 81b among the three systems (A / B / C) of the display circuit 74. The display circuit 74C corresponds to the digital RGB unit 80c. Then, as described with reference to FIG. 4, the first LVDS signal LVDS_1, the second LVDS signal LVDS_2, and the RGB parallel signal RGB_P are transmitted to the signal conversion unit CNV disposed on the liquid crystal interface substrate 28. Has been.

  6B illustrates the relationship among the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, and the VRAMIF unit 84, and the register group 70, CGROM 55, DRAM 54, and VRAM 71. Part of 70 is specifically described. As shown in the figure, the CGROM 55 and the CG bus IF unit 82 are connected by a serial line, and the CGROM 55 is sequentially accessed in response to transmission of the address information Tx, and a group of CG data (compressed data) Rx is sequentially read out. It is supposed to be.

  In the first embodiment, the CG data read from the CGROM 55 is stored in the VRAM 71 via the CG bus IF unit 82 → the VRAMIF unit 84. The arrow at timing T1 + δ in FIG. Show. As shown in FIG. 7, in the VRAM 71, a still picture decoding area and a moving picture decoding area are secured as work areas of the graphics decoder 75, and the CG data is compressed at a position corresponding to the type of CG data. Stored as is. Further, as shown in FIGS. 7 and 8, the VRAM 71 also has a frame buffer FB area for arranging image data for one frame after decoding.

  On the other hand, in the second embodiment in which the preloader 73 functions, the CG data is stored in the preload area of the DRAM 54 via the CG bus IF unit 82 → the DRAM IF unit 83 prior to the timing necessary for the decoding process. After that, it is randomly accessed at a necessary timing and transferred to the VRAM 71. However, in any of the embodiments, the CG data stored in the still picture decoding area or the moving picture decoding area of the VRAM 71 is decoded by the graphics decoder 75 and then placed in a proper position in the frame buffer FB area of the VRAM 71 by the drawing circuit 76. Be expanded. The arrow at timing T1 + δ ′ in FIG. 7 indicates this operation.

  Returning to FIG. 6A, the description will be continued. The data transfer circuit 72 uses a resource (storage medium) in the VDP circuit and an external storage medium as a transfer source port or a transfer destination port, and performs a data transfer operation between them. Is a circuit for executing In addition to the VRAM 71, the transfer source port includes a storage medium (resource) connected to the CPU bus, CG bus, and external DRAM bus. Similarly, the transfer destination port includes a storage medium connected to the CPU bus, CG bus, and external DRAM bus in addition to the VRAM 71. The data transfer circuit 72 is also in charge of the operation of transmitting the display list DL for specifying the display image for one frame to the drawing circuit 76 (preloader 73 when necessary) by a group of drawing commands.

  The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers the CG data on the CGROM 55 referred to in the display list DL to a preload area of the DRAM 54 designated in advance. At this time, the preloader 73 outputs the display list DL in which the reference destination of the CG data is rewritten to the address after transfer. The rewritten display list DL is transmitted to the drawing circuit 76 by the data transfer circuit 72.

  However, the preloader 73 is not used in the first embodiment. On the other hand, in the second embodiment, a sufficient preload area of the storage area is set in the external DRAM 54 based on the set value in the preloader register (see FIG. 6B). In the second embodiment, unless the storage area set as the preload area is used up, the preloaded compressed data is maintained without being overwritten and erased by the subsequent compressed data. Therefore, in the second embodiment using the preload process, the CGROM 55 is accessed only when necessary compressed data does not exist in the preload area. Since a sufficient storage area is secured in the preload area, no problem occurs even if CG data for a plurality of frames is preloaded at once.

  The drawing circuit 76 sequentially analyzes the drawing commands of the display list DL (see timing T1 ′ in FIG. 7) transferred from the internal RAM 59 to the external DRAM 54 by the data transfer circuit 72, and the graphics decoder 75 and the geometry This is a circuit that draws an image for one frame of the display devices DS1 to DS4 in a frame buffer FB formed in the VRAM 71 in cooperation with the engine 77 and the like.

  That is, the drawing circuit 76 includes a Displaylist Analyzer (hereinafter referred to as a DL analyzer) that analyzes a drawing command of the display list DL, a Geometry Pipeline that performs vertex coordinate conversion and illumination calculation, and a source address and destination at the time of triangle drawing. Triangle Rasterizer for generating addresses, Texture Sampler for sampling textures and performing bilinear filtering, Framebuffer Sampler for obtaining frame buffer and Z buffer for inter-pixel calculation, and processing such as alpha blending, frame buffer A pixel generator for generating pixel data to be written to the FB is included.

  Here, the display list DL is composed of a group of drawing commands described in the drawing order, and includes a command for specifying what image is drawn at which position in one frame. The storage position (source address) of the CGROM or the like of the power image is also specified. Then, the DL analyzer of the drawing circuit 76 interprets such a display list DL and cooperates with other Geometry Pipeline, Triangle Rasterizer, Texture Sampler, Framebuffer Sampler, and Pixel Generator to ensure the frame secured in the built-in VRAM 71. Image data for one frame of each of the display devices DS1 to DS4 is generated in the buffer FB (see FIG. 8). It should be noted that for the four display devices DS1 to DS4, only three frame buffers FBa to FBc exist and the contradiction in which the numbers do not match will be described later.

  The display list DL of the present embodiment includes a drawing command group for the display device DS1, a drawing command group for the display device DS2, a drawing command group for the display device DS3, and a drawing command group for the display device DS4. Separately, stripe connection processing JOIN for stripe connection is described in the last row or an appropriate position. Here, the stripe connection processing JOIN is a drawing command sequence created after the development of the gaming machine in order to connect the image data of the display device DS3 and the display device DS4. The drawing circuit 76 (DL analyzer) Is stored in, for example, the built-in VRAM 71 or the external DRAM 54 when the power is reset. Although it is preferable to store the drawing command sequence constituting the stripe connection processing JOIN in the CGROM 55 and the control memory 53, in the embodiment, the drawing command sequence is transferred from the control memory 53 to the built-in VRAM 71 when the power is reset.

  In any case, the operation of the stripe linking process JOIN is realized by the drawing circuit 76 executing a series of drawing command sequences stored in a predetermined memory (in the embodiment, the built-in VRAM 71). However, in the display list DL, it is only necessary to specify the position of the drawing command string (specification of being the built-in VRAM 71), the start address of the drawing command string, and the total data size of the drawing command string. The display list DL does not grow long, and the control burden on the image control CPU 63 shown in step ST3 of FIG. 13 does not increase.

  As shown in FIG. 8, the frame buffer FB of this embodiment is divided into three sections (FBa, FBb, FBc) corresponding to the display circuits 74A / 74B / 74C, but each frame buffer FB (FBa, FBb, The drawing position of FBc) is specified by a predetermined drawing command described in the display list DL. As will be described later with reference to FIG. 9, image data for one frame (1280 × 1024 pixels) of the main display device DS1 is arranged in the frame buffer FBa, and one frame (for the sub display device DS2) in the frame buffer FBb. 480 × 800 pixels) image data is arranged.

  On the other hand, in the frame buffer FBc, image data for 480 × 800 × 2 pixels of a composite frame obtained by combining one frame of the sub display device DS3 and one frame of the sub display device S4 is arranged.

  These three divided frame buffers FB (FBa, FBb, FBc) are all double buffers functionally divided into a drawing area and a display area, and two areas (area 0 and area 1) are alternately displayed. The usage is switched to. That is, when the drawing circuit 76 writes image data in one of the two areas, the display circuit 74 reads out and outputs the image data in the other area.

  Although not particularly limited, in the present embodiment, one frame of the display devices DS1 to DS4 is composed of three or more types of images (moving images and still images) in the maximum state. That is, the display devices DS1 to DS4 are configured such that, in the maximum state, one or a plurality of moving images are reproduced, while still images that change over time are superimposed on the background images. .

  The basic shape of the still image is stored in advance in the CGROM 55 as a sprite image. The basic shape is appropriately enlarged / reduced / rotated / deformed and the temporal position is changed by changing the arrangement position. ing. On the other hand, a moving image is a so-called movie that changes smoothly for a predetermined time, and a plurality of frames are compressed by a moving image compression method such as an MPEG encoding method and stored in the CGROM 55.

  Although not particularly limited, the moving image of the present embodiment is an IP stream moving image composed of I frames and P frames. Here, the P frame means a frame composed of a P picture (Predictive Picture) that encodes a difference from data predicted from a past frame, and although the compression rate is high, sequential reproduction is essential. On the other hand, an I frame means a frame composed of an I picture (Intra Picture) that can be encoded independently without depending on other frames.

  Corresponding to such a configuration, the graphics decoder 75 is divided into a still picture decoder and a moving picture decoder, and decodes a still picture and a moving picture encoded (compressed) by a predetermined compression algorithm by a decompression algorithm corresponding to each. (Stretching). For example, a still image is compressed by a predetermined algorithm for each image data constituting one still image, and a P frame of an IP stream moving image includes a plurality of still image data for realizing a series of moving images. Compressed based on data difference value.

  Next, the display circuit 74 is a circuit that reads out the image data from the frame buffer FB, performs final image processing, and outputs it (see FIG. 8). As shown in FIG. 8, the image processing in the display circuit 74 includes a scaling process in which the scaler functions to enlarge / reduce the frame image, a delicate color correction process, and a dither that minimizes the quantization error of the entire image. And ring processing. Note that the scaling processing includes frame data enlargement processing after moving image decoding for vertically reduced moving image data (vertically reduced data).

  As shown in FIG. 8, in this embodiment, there are provided three display circuits 74A / 74B / 74C that execute the above operations in parallel, and each display circuit 74A / 74B / 74C corresponds to each. Image data in the frame buffer FBa / FBb / FBc is read out and the final image processing is executed. After these image processes, digital RGB data (24 bits in total) is output to the output selection circuit 79 together with the horizontal synchronization signal and the vertical synchronization signal.

  The output selection unit 79 transmits the output signal of the display circuit 74A to the LVDS unit 80a, transmits the output signal of the display circuit 74B to the LVDS unit 80b, and outputs the output signal of the display circuit C to the digital RGB unit 80c. . As described above, the LVDS unit 80a and the LVDS unit 80b convert the image data (digital RGB data of 24 bits in total) into the LVDS signal, and add all five pairs including the pair for transmitting the clock signal. The motion signals LVDS_1 and LVDS_2 are output to the signal converter CNV of the liquid crystal interface substrate 28. Similarly, the digital RGB unit 80c outputs an RGB parallel signal RGB_P to which a synchronization signal or the like is added to the signal conversion unit CNV.

  Next, an SMC unit 78 (Serial Management Controller) is a composite controller that incorporates an LED controller and a Motor controller. Then, an LED / motor driver (driver IC with a built-in shift register) mounted on an external board outputs an LED drive signal and a motor drive signal in synchronization with the clock signal, while at the appropriate timing, a latch pulse is output. It is configured to allow output.

  Regarding the internal circuit of the VDP circuit 52 and its operation, the operation content to be executed by the internal circuit is defined by the operation parameter (setting value) set in the register group 70 by the image control CPU 63, and the execution state of the VDP circuit 52 Can be specified by reading the operation status value of the register group 70. The register group 70 means a large number of registers mapped in a memory space (0 to FFFFFH) of about 1 Mbytes on the memory map of the image control CPU 63. The image control CPU 63 passes operation parameters of the operation parameter via the CPUIF unit 81. The WRITE (setting) operation and the READ operation of the operation status value are executed (see FIG. 6B).

  In the register group 70, a “system control register” in which initial setting values related to system operations such as an interrupt operation are written, and settings related to data transfer processing by the data transfer circuit 72 between the image control CPU 63 and the internal circuit of the VDP circuit 52 are set. A “data transfer register” in which a value and the like are written, a “GDEC register” that can specify an execution status including an error occurrence of the graphics decoder 75, and a “drawing command” and a setting value related to the drawing circuit 76 are written A “register”, a “preloader register” in which setting values relating to the operation of the preloader 73 are written, a “display register” in which setting values relating to the operations of the three divided display circuits A / B / C are written, and LEDs “LED control register” in which setting values related to the controller (SMC unit 78) are written, and Moto Controller settings related (SMC unit 78) includes and a "motor control register" to be written is, these control registers is composed each of a plurality of bytes long.

  More specifically, in the “preloader register”, (1) the preload area is set in the DRAM 54 or the VRAM 84, (2) the start address of the preload area, (3) the preload data area, The number of frames used, (4) data size per frame, etc. are set. Further, the data transfer source and data transfer destination are set in the “data transfer register”, and the start position of the frame buffer FBa / FBb / FBc corresponding to the display circuit A / B / C is set in the “display register”. In addition, in each frame buffer FBa / FBb / FBc, an instruction for switching between a drawing area and a display area that changes over time, a scaler vertical / horizontal enlargement ratio, and the like are set. In addition, the “drawing register”, “preloader register”, and “data transfer register” are instructed to start execution of the drawing operation, the preload operation, and the data transfer operation.

  In any case, the internal operation of the VDP circuit 52 is realized by the image control CPU 63 writing an appropriate set value in any of the register groups 70. Therefore, the image control CPU 63 realizes an image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set value in the register constituting the register group 70 described above. In this embodiment, the lamp effect and the motor effect are handled by the effect control CPU 40 of the effect control board 22, so that the setting value is written in the LED control register and the motor control register without using the SMC unit 78. It will never happen.

  FIG. 9A positively illustrates the relationship among the frame buffers FBa to FBc built in the VDP circuit 52, the signal converter CNV of the liquid crystal interface substrate 28, and the four display devices DS1 to DS4. Is. FIG. 9B is a diagram for explaining stripe connection processing. In this specification, the circuit configuration of FIG. 9A may be referred to as a first configuration for convenience.

  As shown in FIG. 9A, the frame buffer FB includes a frame buffer FBa for the main display device DS1, a frame buffer FBb for the sub display device DS2, and a frame buffer FBc for the two sub display devices DS3 and DS4. In addition, work areas WK3 and WK4 for the sub display device DS3 and the sub display device DS4 are secured. Each frame buffer FBa / FBb / FBc has a double buffer structure, and storage areas for 1280 × 1024 pixels, 480 × 800 pixels, and 480 × 800 × 2 pixels are secured, respectively.

  In the accompanying drawings of the present specification, the work areas WK1 to WK4 are illustrated in one section for convenience, including the case of other embodiments. However, in terms of program processing, the work buffer WKi is also a frame buffer. A double buffer structure similar to FBa / FBb / FBc is preferred.

  The image data in the frame buffer FBa and the frame buffer FBb is constructed based on a group of drawing command sequences that constitute the display list DL. More specifically, the DL analyzer of the drawing circuit 76 interprets the drawing command sequence of the display list DL of the external DRAM 54, and cooperates with other Geometry Pipeline, Triangle Rasterizer, Texture Sampler, Framebuffer Sampler, and Pixel Generator. The image data necessary for the display devices DS1 and DS2 is constructed in the frame buffers FBa and FBb.

  This point is basically the same for the frame buffer FBc, but the image data of the frame buffer FBc is accurately generated in two stages. In this respect, as shown in FIG. 9B, the drawing circuit 76 interprets a group of drawing commands in the display list DL, and first, the image data of the display device DS3 and the display device DS4 is stored in the frame buffer. It is constructed separately in the work areas WK3 and WK4. Next, based on the stripe concatenation process JOIN (drawing command string) described in the last line of the display list DL, the image data of the work area WK3 and the work area WK4 is read out, and these are concatenated to the frame buffer FBc. Write to.

  FIG. 9B illustrates this relationship, and pixels P (1,1) to P (480,800) constituting one frame of the display device DS3 and one frame of the display device DS4. Image data specifying pixels P (1,1) to P (480,800) are connected to generate composite frame pixels P (1,1) to P (960,800).

  As shown in the figure, in this embodiment, the odd vertical lines of the composite frame are the vertical lines of the display device DS3, and the even vertical lines of the composite frame are the vertical lines of the display device DS4. The image data of the composite frame is read out to the display circuit 74C and transmitted to the signal conversion circuit TX3 of the signal conversion unit CNV as a composite RGB parallel signal RGB_P connected in stripes. As described above, the dot clock of the composite RGB parallel signal RGB_P is about 54 MHz.

  Returning to FIG. 9A, the description of the relationship between the signal conversion unit CNV and the display devices DS1 to DS4 will be continued. The three serial reception circuits RV2 to RV4 correspond to the three sub display devices DS2 to DS4. The serial receiving circuits RV2 to RV4 are arranged to restore the RGB parallel data from the high-speed serial signals SER2 to SER4 transmitted through the pair of differential signal lines. The main display device DS1 includes an LVDS receiver RV1, and the LVDS receiver RV1 restores RGB parallel data from the LVDS signal.

  As shown in FIG. 9A, the signal conversion unit CNV includes three signal conversion circuits TX1 to TX3, and each of the signal conversion circuit TX1 and the signal conversion circuit TX2 passes through an output selection circuit 79. The LVDS signal LDVS_1 and the LVDS signal LDVS_2 are received. Here, the LVDS signals LDVS_1 and LDVS_2 are transmitted through, for example, all six pairs or all five pairs of differential signal lines, and in any case, RGB signals, vertical / horizontal synchronization signals, and a pair of clocks. Signal.

  In the following description, for convenience, the LVDS signal LDVS_1 is set to all six pairs and the LVDS signal LDVS_2 is set to all five pairs. However, the present invention is not limited to any other configuration, for example, the LVDS signal LDVS_1 may be set to all five pairs. Of course.

  In any case, each of the signal conversion circuits TX1 and TX2 performs a necessary operation in synchronization with the clock signal. That is, for example, the signal conversion circuit TX1 performs a single-in dual-out (Single-In Dual-Out) signal conversion operation (stripe division operation) on all six pairs of LVDS signals LDVS_1.

  On the other hand, the signal conversion circuit TX2 receives, for example, all five pairs of LVDS signals LDVS_2 and converts them into a pair of high-speed serial signals SER2. As described above, the high-speed serial signal SER2 output from the signal conversion circuit TX2 means a serial signal having a dot clock of about 27 MHz and a communication speed of about 972 MHz that is transmitted at high speed through a pair of differential signal lines. That is, in the serial transmission path SER2, the scrambled serial data of 36 bits is transmitted in one cycle of the dot clock (pixel clock), so the communication speed is about 27 MHz × 36 = 972 MHz.

  The signal conversion circuit TX3 receives the stripe-connected composite RGB parallel signal RGB_P and the pixel clock PCLK via the output selection circuit 79, and after dividing the composite RGB parallel signal RGB_P into stripes, Serial signals SER3 and SER4 are converted. As described above, the high-speed serial signal is a term for convenience in this specification. As a result of dividing the composite RGB parallel signal RGB_P into stripes, the dot clocks of the two high-speed serial signals SER3 and SER4 are both It is about 27 MHz, and specifies the image data of the sub display devices DS3 and DS4, respectively.

  Next, the signal conversion circuit TX1 of the signal conversion unit CNV will be specifically described with reference to FIG. As illustrated, the signal conversion circuit TX1 includes a phase synchronization circuit PLL that receives the clock signal RCCK1 of the LVDS signal LVDS_1, a deserializer De-serialize that restores the LVDS signal LVDS_1 (RA1 to RE1) to an RGB parallel signal, and 1280 × 1024 pixels. For the RGB parallel signal, the dividing circuit Inter Link Multiplex that divides stripes into RGB data of odd pixels and even pixels, and two systems that convert and output the stripe-divided RGB data into two LVDS signals LVDS_a and LVDS_b Output circuit LVDS-TX serialize.

  In the case of adopting a configuration that realizes 256 gradations, four pairs of LVDS signals (RA1 to RD1, TA1 to TD1, out of five pairs of LVDS signals (RA1 to RE1, TA1 to TE1, TA2 to TE2), Only TA2 to TD2) are used.

  FIG. 10B and FIGS. 10C to 10D show the LVDS signal LVDS_1 input to the signal conversion circuit TX1 and the signal conversion circuit TX1 when 1024 gradations are realized. The relationship between the LVDS signals LVDS_a and LVDS_b is illustrated. As shown in the figure, pixel data 3 × 8 × 1024 × 1280 bits (see FIG. 10B) transmitted at a dot clock of about 108 MHz is relaxed to a dot clock of 54 MHz with a frequency ½, and two LVDS signals LVDS_a , LVDS_b is output.

  As described above, in this embodiment, since the frequency of the dot clock is relaxed by a factor of two in the signal conversion circuit TX1, transmission errors and noise superimposition are prevented even when high-quality image data is transmitted. be able to.

  Next, FIG. 11 is a block diagram showing an internal configuration of the signal conversion circuit TX2 of the signal conversion unit CNV. As shown in the figure, the signal conversion circuit TX2 receives the five pairs of LVDS signals LVDS_2, performs parallel conversion to restore the RGB data, and converts the synchronization signal and other control data into the restored RGB data. In addition, an encoder Encode that generates basic data of a high-speed serial signal and a PS converter PS Converter that serially converts the basic data of the high-speed serial signal and outputs the converted data as a high-speed serial signal SER2 are configured.

  FIG. 11B and FIG. 11C illustrate the relationship between five pairs of LVDS signals LVDS_2 input to the signal conversion circuit TX2 and the high-speed serial signal SER2 output from the signal conversion circuit TX2. . As shown in the figure, image data for one pixel (7 × 4 = 28 bits) is converted into serial data having a total length of 36 bits by adding other control data thereto. Therefore, the communication speed is increased to about 972 MHz (27 MHz × 36), but the dot clock frequency is about 27 MHz.

  FIG. 12A is a block diagram showing an internal configuration of the signal conversion circuit TX3 of the signal conversion unit CNV. As shown in the figure, the signal conversion circuit TX3 receives a composite RGB parallel signal RGB_P composed of 960 × 800 dots in one frame and a synchronization clock, and inputs an input buffer Input Buffer that divides this into an even pixel and an odd pixel in time sequence. A pair of encoder Encodes that generate basic data of two high-speed serial signals by adding synchronization signals and other control data to RGB parallel signals of even / odd pixels and serial conversion of two basic data And a pair of PS converters PS Converter for outputting as high-speed serial signals SER3 and SER4.

  As shown in FIG. 9, the signal conversion circuit TX3 receives the composite RGB parallel signal RGB_P connected in stripes. However, the input buffer Input Buffer cuts the RGB parallel signals into the even pixels and the odd pixels in time order, thereby reducing the stripes. Division processing is realized.

  Next, FIG. 12B is a block diagram showing an internal configuration of serial receiving circuits RV2 to RV4 that receive the high-speed serial signals SER2 to SER4. As illustrated, the serial reception circuits RV2 to RV4 are configured to include a parallel conversion unit S-P Converter that performs parallel conversion on the high-speed serial signal SERi and a decoder Decode that restores RBG data from the parallel data. Then, the restored RGB parallel data is output to the sub display device together with other synchronization signals, so that an image of one frame of 480 × 800 dots is drawn on each of the sub display devices DS2 to DS4.

  As described above, in the first configuration shown in FIG. 9, since the LVDS signal LVDS_1 to the main display device DS1 is divided into two LVDS signals LVDS_a and LVDS_b with the dot clock frequency suppressed, a large display device is used. A high-quality display operation can be realized. Further, even if the transmission distance to the main display device is long, the problem of transmission error and noise superposition does not occur.

  Further, in the first configuration shown in FIG. 9, by arranging the signal conversion circuits TX2 and TX3, the signal transmission paths toward the sub display devices DS2 to DS4 are all configured by the high-speed serial signals SER2 to SER4. Therefore, although the number of display devices is increased, wiring inside the gaming machine is simplified. Further, the dot clock is 27 MHz, and various image effects can be achieved with high image quality using the sub display devices DS2 to DS4.

  Subsequently, with reference to the flowcharts of FIGS. 13A to 13D and the operation explanatory diagrams of FIGS. 8 and 14 regarding the control operations of the image effects performed using the display devices DS1 to DS4. explain. These image effects are realized by an image control CPU 63 that receives a control command CMD 'from the effect control CPU 40, and a VDP circuit 52 that functions as instructed by the image control CPU 63. An instruction from the image control CPU 63 to the VDP circuit 52 is specified by an operation parameter written in the register group 70. In the following description, for the sake of convenience, the production timings at which all the display devices DS1 to DS4 function will be described. However, there are actually production timings at which one or both of the display devices DS3 to DS4 do not function.

  As shown in FIG. 13, the image effect operation includes display list DL update processing (FIG. 13A to FIG. 13B) executed every predetermined time by the image control CPU 63 and the display list received from the image control CPU 63. This is realized by the drawing circuit 76 operating based on the DL and the sequence operations of the display circuit 74 (FIG. 13C to FIG. 13D). Note that the image control CPU 63 sets necessary operation parameters in the register group 70 at the time of resetting the power supply or at a necessary timing thereafter so that the drawing circuit 76 and the display circuit 74 realize the sequence operation described below. doing.

  To explain the above, the image control CPU 63 starts a display list DL update process every predetermined time δ (for example, 1/30 seconds) defined by a V blank interrupt every 1/60 seconds (ST1). The sequence operation of the drawing circuit 76 and the display circuit 74 is started (ST2). As described with reference to FIG. 6, the V blank interrupt means that the output operation of the display circuit 74A has ended, but the drawing circuit 76 and the display circuits 74A / 74B / 74C are intermittent based on the processing in step ST2. In addition, its own operations are executed in parallel (see FIG. 14).

  First, a sequence operation of the drawing circuit 76 and the display circuit 74 will be schematically described with reference to FIG. First, the display list DL generated by the CPU 63 in the execution cycle starting from T1 is interpreted by the drawing circuit 76 in the execution cycle starting from T1 + δ, and the image data generated by the drawing circuit 76 is created in the frame buffers FBa to FBc. The It should be noted that at the presentation timing at which all the display devices DS1 to DS4 function, the display list DL includes a series of drawing command sequences that specify the display screens of the four display devices DS1 to DS4 divided into four sections. In the last line of the series of drawing commands, a stripe linking process JOIN for linking the image data of the display devices DS3 to DS4 is described.

  For this reason, image data for 480 × 800 × 2 pixels, in which the drawing circuit 76 stripe-connects based on the stripe connection processing JOIN, is developed in the frame buffer FBc. These image data are output by the display circuit 74 at an execution cycle starting from T1 + 2δ. Therefore, in this embodiment, one unit operation for the image effect is completed after three execution cycles.

  The above relationship is also described in FIG. 7, and based on the display list DL transferred to the DRAM 54 at the timing T1 ′, the CG data in the CGROM 55 is read to the VRAM 71 at the timing T1 + δ (however, when necessary) The image data is created in the frame buffers FBa to FBc in the same execution cycle (timing T1 + δ ′). The image data is output to the display devices DS1 to DS4 through the three communication channels shown in FIG. 9 at the timing of T1 + 2δ.

  Since the above is a schematic description, the process of step ST2 will be specifically described based on FIG. The image control CPU 63 sets a predetermined value in a predetermined display register corresponding to each of the display circuits 74A to 74C and instructs the start of the display operation in order to switch the display areas of the display circuits 74A to 74C (ST10 to ST12). ).

  As shown in FIG. 7, the frame buffers FBa to FBc have a double buffer structure (0/1), one of which is a drawing area to be accessed by the drawing circuit 76 and the other is the access of the display circuit 74. This is the target display area. Then, the drawing area and the display area are switched by the processing in steps ST10 to ST12, and the image data for one frame generated by the drawing circuit 76 in the frame buffers FBa to FBc so far is displayed in this execution cycle. The signals are output toward the display devices DS1 to DS4 by the circuits 74A to 74C.

  In this embodiment, the operation cycle of the display circuits 74A to 74C is set to 1/60 seconds, whereas the operation cycle of the image control CPU 63 is 1/30 seconds, so the display circuits 74A / 74B / 74C. In practice, the same image data is output twice and the same frame is displayed twice in succession. Note that at the timing when the display devices DS3 / DS4 do not function, the processing of steps ST11 / ST12 is skipped, as shown by the broken line. At the timing when the display devices DS3 / DS4 should finish the display operation, the display operation is stopped by setting a predetermined value in a predetermined display register corresponding to the display circuit 74B / 74C.

  Along with the above processing (ST10 to ST12) for the display circuit 74, the image control CPU 63 instructs the predetermined drawing register that defines the operation of the drawing circuit 76 to start the drawing operation (ST13). As a result, the drawing circuit 76 also starts a predetermined operation every 1/30 seconds. It should be noted that the operation contents to be executed by the drawing circuit 76 and the display circuit 74 are set in the drawing register and the display register by the image control CPU 63 at the time of resetting the power supply or at a necessary timing thereafter, as described above. is there.

  13B, returning to FIG. 13A, the image control CPU 63 instructs the sequence operation of the drawing circuit 76 and the display circuit 74 in the process of step ST2, and then the image effect scenario. Based on the above, a display list DL for the next frame is created. Here, the image effect scenario embodies an image effect specified by the control command CMD ′ received from the effect control CPU 40.

  In other words, image production scenarios include (1) a series of videos that continue for a certain period of time, and still images (including background images and preview images) where the drawing position, layout orientation, and scaling ratio are appropriately defined. The start time and end time of the video production of (2) which still image is to be drawn, at what time, at what position, and so on are defined. Note that even if it is a video effect, the drawn image on the display device only changes quickly and smoothly, and the same or different next image data (frame image data) is drawn on the display device at regular intervals. This is the same as a still image.

  Then, the image control CPU 63 refers to the effect scenario having such a configuration, and at each timing (T1, T1 + δ, T1 + 2δ,...), Outputs a group of drawing commands for specifying the display images of the display devices DS1, DS2. The listed display list DL is generated. The display list DL specifies, for moving images, which part of the moving image that progresses in time by specifying the storage location of the CGROM, and where the still image such as a sprite image is stored in the CGROM. It defines how and where the displayed image is drawn on which position of the display device.

  The drawing command sequence constituting the display list DL is divided into four sections corresponding to the four display devices DS1 to DS4 (DL = DLi1 + DLi2 + DLi3 + DLi4), and the last line of a series of drawing commands or stripes at appropriate positions The connection process JOIN is described as described above (DL = DLi1 + DLi2 + DLi3 + DLi4 + JOIN).

  The display list DL is transferred from the internal RAM 59 to the external DRAM 54 by the data transfer circuit 72 instructed by the image control CPU 63 (ST4). The arrow at timing T1 'in FIG. 7 illustrates this operation. The image control CPU 63 does not need to generate one display list DL that specifies one frame of each display device for each operation cycle, and a plurality of display lists DL1, DL2,... That specify display contents at a plurality of timings. -May be generated together in one operation cycle.

  In FIG. 14, the process of step ST13 by the image control CPU 63 is indicated by a vertical arrow from the CPU 63 to the drawing circuit 76, and the process of steps ST10 to ST12 by the image control CPU 63 is performed from the CPU 63 to the display circuit A /. It is indicated by a vertical arrow pointing to B / C.

  Subsequently, a drawing operation executed in cooperation by the drawing circuit 76, the graphics decoder 75, the geometry engine 77, and the like will be described with reference to FIGS. 13C to 13D and FIG. As shown in FIG. 14, this drawing operation is repeated every fixed time (δ). For convenience, the following description will explain the drawing operation after timing T1 + 2δ, which is executed based on the display list DL1 after rewriting. .

  The drawing circuit 76 sequentially analyzes drawing commands described in the display list DL1 which is an unprocessed and oldest display list among the display lists stored in the external DRAM 54 (FIG. 13C). SS20), the graphics decoder 75 and the geometry engine 77 are caused to function with respect to the still image or moving image specified by the drawing command.

  Then, the still image data and the moving image data decoded by the graphics decoder 75 are expanded and developed in the still image decoding area and the moving image decoding area secured in the built-in VRAM 71 (SS22 to SS23). Next, after the decoded still image data or moving image data is written in a predetermined position of the frame buffer FB (FBa, FBb, FBc) of the VRAM 71 in a drawing mode defined by a drawing command, a drawing process is executed. (SS24). The drawing mode includes the drawing position in the frame buffer FB (FBa, FBb, FBc). However, in the case of a sprite image or the like, the drawing posture, the enlargement / reduction ratio, etc. may be further defined. The geometry engine 77 functions.

  In addition, among the four-divided display lists DL1 (= DL11 + DL12 + DL13 + DL14), the image data based on the drawing command sequence DL13 in the third division and the drawing command sequence DL14 in the fourth division are in the work area WK3 and the work area WK4, respectively. After the generation, the frame is combined into the frame buffer FBc by the stripe connection process based on the final stripe connection process JOIN (see FIG. 9 and SS24). Since the frame buffers FBa / FBb / FBc each have a double buffer structure divided into a drawing area and a display area, in the drawing operation (SS24), more accurately, the drawing of the frame buffers FBa / FBb / FBc is performed. Image data is written in the area.

  In this way, when drawing processing for all the drawing commands is completed, a standby state is entered until the next drawing operation started intermittently (SS25). In FIG. 7, an arrow indicates that a necessary image is drawn in the frame buffer FB (FBa + FBb + FBc) at the timing T1 + δ ′.

  Finally, the operation of the display circuit 74 will be described with reference to FIG. Although this display operation is also repeated at regular time intervals (δ), for the sake of convenience, in the following description, the display operation after timing T1 + 2δ shown in FIG. 14 will be described. As described above, at this timing, the image data (A1, B1, C1) based on the display list DL1 is secured in the drawing area of the frame buffer FBa / FBb / FBc. The drawing area functions as a display area in display operations after timing T1 + 2δ.

  As shown in FIG. 13D, the display circuits 74A / 74B / 74C read the image data (A1, B1, C1) stored in the display areas of the corresponding frame buffers FBa / FBb / FBc, It outputs to the output selection part 79 (SS30). Here, the image data (A1) of the frame buffer FBa is image data for specifying one frame of the display device DS1, and the image data (B1) of the frame buffer FBb is image data for specifying one frame of the display device DS2. It is. The image data (C1) in the frame buffer FBc is image data connected in stripes, and specifies the composite frame of the display devices DS3 to DS4.

  Thereafter, based on the operation of the output selection unit 79, the image data (A1) of the frame buffer FBa output from the display circuit 74A is output as the LVDS signal LVDS_1 via the LVDS unit 80a, and the frame output from the display circuit 74B. The image data (B1) in the buffer FBb is output as the LVDS signal LVDS_2 via the LVDS unit 80b. The image data (C1) of the frame buffer FBc output from the display circuit 74C is output as a composite RGB parallel signal RGB_P via the digital RGB unit 80c.

  As shown in FIG. 9, the LVDS signal LVDS_1 related to the image data (A1) output from the LVDS unit 80a is striped into two LVDS signals LVDS_a and LVDS_a in which the dot clock is relaxed in the signal conversion circuit TX1. After these two systems of LVDS signals LVDS_a and LVDS_a are transmitted to the display device DS1, they are stripe-connected in the LVDS receiver RV1, thereby realizing a display screen of 1280 × 1024 pixels.

  The LVDS signal LVDS_2 related to the image data (B1) output from the LVDS unit 80b is converted into a high-speed serial signal SER2 in the signal conversion circuit TX2, and transmitted to the serial reception circuit RV2 via a pair of differential signal lines. Then, by restoring the RGB parallel signal by the serial receiving circuit RV2, a display screen of 480 × 800 pixels in the display device DS2 is realized.

  On the other hand, the image data (C1) output from the digital RGB unit 80c is a composite RGB parallel signal RGB_P for specifying a composite frame for the display devices DS3 to DS4. The signal conversion circuit TX3 performs stripe division and performs high-speed processing. The signals are converted into serial signals SER3 and SER4 and transmitted to the serial reception circuit RV3 and the serial reception circuit RV4 via each pair of differential signal lines. Then, each of the serial reception circuits RV3 to RV4 restores the RGB parallel signal, thereby realizing a display screen of 480 × 800 pixels on the display device DS3 and the display device DS4.

  The above operation is the same not only for the display operation starting from the timing T1 + 2δ but also for the display operation starting from the timing T1 + 3δ. That is, in the display operation starting from the timing T1 + 3δ, the display circuit 74A / 74B / 74C outputs the image data A2 / B2 / C2 and is displayed on each of the display devices DS1 to DS4.

  Thereafter, since the same operation is repeated, the image data Ai / Bi / Ci updated every 1/30 seconds is displayed on the display devices DS1 to DS4. Since the display circuits 74A / 74B / 74C are initially set to operate every 1/60, the same image data Ai / Bi / Ci is output twice in succession as described above. It is. Therefore, the moving image displayed on the display devices DS1 to DS4 has a playback speed of 30 fps (Frames Per Second).

  The first embodiment in which the preloader 73 does not function has been described above. However, it is preferable to use the preloader 73 in order to cover the weak point of sequential access to the CGROM 55. FIG. 15 and FIG. A second embodiment is shown. As shown in FIG. 15, the image effect operation of the second embodiment is based on the display list update process (FIG. 15A) executed every predetermined time by the image control CPU 63 and the display list received from the image control CPU 63. This is realized by each sequence operation (FIG. 15B to FIG. 15D) of the preloader 73, the drawing circuit 76, and the display circuit 74 that operate. As with the drawing circuit 76 and the display circuit 74, the image control CPU 63 also sets the necessary operation parameters for the preloader 73 at the time of resetting the power supply or at a necessary timing thereafter so as to realize the sequence operation described below. The register group 70 is set.

  The image control CPU 63 starts list update processing every predetermined time δ (ST1), and starts sequence operations of the preloader 73, the drawing circuit 76, and the display circuit 74 (ST2). As shown in FIG. 16A, the image control CPU 63, the preloader 73, the drawing circuit 76, and the display circuit 74 execute their operations in parallel intermittently at regular time intervals (δ). Become. FIG. 16B schematically shows the contents of each memory of the built-in RAM 59 of the CPU circuit, the built-in VRAM 71 of the VDP circuit, the external DRAM 54, and the CGROM 55.

  Continuing the description of the operation of the image control CPU 63, following the processing of step ST2, the image control CPU 63 updates the display list DL based on the effect scenario (ST3). Then, the image control CPU 63 lists a group of drawing commands for specifying the display image of the display device DS1 at each timing (T1, T1 + δ, T1 + 2δ,...) With reference to the effect scenario having such a configuration. Display lists DL1, DL2,... Are generated.

  Next, the display list DL configured in this way is transferred to the prescribed area of the external DRAM 54 and waits until the next list update timing is reached (ST4). FIGS. 16A and 16B show that the display list DL1 is generated as a result of the operation of the image control CPU 63 started from the timing T1, and is transferred to the external DRAM 54 at the timing T1 ′. Has been.

  In the second embodiment, the display list DL1 is rewritten by the preloader 73 at a timing T1 + δ delayed by one timing, and further at a timing T1 + 2δ delayed by one timing by the drawing circuit 76 based on the display list DL1 after rewriting. Drawing processing is performed. At a timing T1 + 3δ that is further delayed by one timing, a display screen specified by the display list DL1 appears on the display devices DS1 to DS4 based on the display operation of the display circuit 74.

  Thus, in the second embodiment, the preloader 73, the drawing circuit 76, and the display circuit 74 are configured to operate with a delay of one timing. Therefore, the preloader 73 started from the timing T1 processes the oldest display list that has not been processed by the external DRAM 54, and specifically processes the display list generated at the previous timing. become. In other words, the display list DL1 generated by the image control CPU 63 at the timing T1 is processed as follows based on the operation of the preloader 73 starting from the timing T1 + δ.

  Hereinafter, the timing after timing T1 + δ will be described. The preloader 73 analyzes the display list DL1, which is the unprocessed and oldest display list, stored in the specified area of the external DRAM 54. When a drawing command required for the CG data of the CGROM is detected in the display list DL1, necessary information is acquired in the CG bus IF unit in order to acquire the group of CG data in the CG data area of the external DRAM 54. Tell 82. In addition, the storage location of the CG data in the drawing command related to the prefetching (preload) processing is rewritten from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 (SS10).

  The above operation is repeatedly executed every time a drawing command that requires CG data of CGROM is detected, and all the CG data (compressed data) for constructing each frame of the display devices DS1 to DS4 is CGROM55. To the CG data area of the DRAM 54. Since the CG data secured once in the CG data area of the DRAM 54 is managed so as to be usable thereafter, the preload process (SS11) is skipped when the CG data secured at the previous timing is used. Then (see the broken line in FIG. 15B), only the process (SS10) of rewriting the storage location of the CG data from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 is executed.

  Then, for the display list DL1 that identifies each frame of the display devices DS1 to DS4, the transfer processing of necessary CG data to the DRAM 54 and the rewrite processing of the display list are completed for all drawing commands described therein. In this case, the system waits for the next preload operation that starts intermittently (SS12). In FIG. 16B, the state in which necessary CG data is transferred from the CGROM 55 to the external DRAM 54 at the timing T1 + δ is indicated by arrows. Note that the transferred CG data remains in a compressed state.

  The drawing operation (SS20 to SS24) and the output operation (SS30) are the same as those in the first embodiment except that the operation timing is delayed. In FIG. 16B, an arrow indicates that a necessary image is drawn in the frame buffer FBa at the timing T1 + 2δ and is output at the timing T1 + 3δ. The display operation of the display circuit 74 is also repeated at regular time intervals (δ).

  In this embodiment, the processes of steps SS10 to SS11 are not necessarily limited to a single display list DL, and can be executed in order for a plurality of n display lists DLi. In this case, the image control CPU 63 generates a plurality of display lists DLi and transfers them to the DRAM 54 in one operation cycle δ, and the preloader 73 interprets and executes the plurality of display lists DLi as early as possible. Become.

  As described above, in the second embodiment, since the preloader 73, the drawing circuit 76, and the display circuit 74 perform a series of operations in parallel with each other in parallel, the high-quality and high-speed operation is performed. It is possible to realize a large-screen image production that changes without any trouble.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. For example, with respect to the main display device DS1 and the sub display devices DS2 to DS4, the numbers of vertical and horizontal dots and the numerical values for the dot clock are merely examples, and of course are appropriately changed.

  Further, for example, in the embodiment shown in FIG. 9, (1) the LVDS signal LVDS_1 specifying one frame of the main display device DS1 is divided into two LVDS signals LVDS_1 and LVDS_2 having a dot clock of 54 MHz by the signal conversion circuit TX1. (2) The composite RGB parallel signal RGB_P for specifying the composite frame (composite pixel) of the display devices DS3 and DS4 is divided into two high-speed serial signals SER3 and SER4 with a dot clock of 27 MHz by the signal conversion circuit TX3. Is not particularly limited.

  FIG. 17 illustrates the second configuration. The image data of the display device DS2 and the display device DS3 is temporarily stored in the work area WK2 and the work area WK3 for each 480 × 800 pixels based on the display list. After the data is generated, stripe connection is performed based on the stripe connection processing JOIN described in the display list, and the composite frame image data for a total of 2 × 480 × 800 pixels is transferred to the frame buffer FBb.

  Then, the display circuit 74B reads the image data of the frame buffer FBb, and outputs the LVDS signal LVDS_2 with a dot clock of 54 MHz via the output selection unit 79. In the second configuration, the signal conversion unit CNV includes a signal conversion circuit TX2 'shown in FIG. 21 and a signal conversion circuit TX3' shown in FIG.

  As shown in FIG. 21, the signal conversion circuit TX2 ′ has a configuration similar to that of the signal conversion circuit TX2 of FIG. 11, and includes a parallel conversion unit SP Converter that converts the received LVDS signal LVDS_2 in parallel, and a parallel conversion unit SP. A buffer circuit that separates the parallel data output by the Converter into image data of odd pixels and even pixels and outputs them, and a pair that generates the basic data of the high-speed serial signal by receiving the separated odd pixel data and even pixel data And a pair of serial converters PS Converter that serially convert the output of the decoder Decode and output high-speed serial signals SER2 and SER3.

  FIG. 21B illustrates a stripe division process for dividing image data of a composite frame of the display devices DS3 and DS4 into odd and even pixels, and an image of 2 × 480 × 800 pixels connected in stripes. It is shown that the Dodd clock frequency is halved by dividing the data into stripes.

  By the way, as shown in FIG. 17, the image data of the display device DS4 is generated in the frame buffer FBc based on the display list, and this is read out by the display device 74C and passed through the output selection unit 79 to be RGB parallel. Output as signal RGB_P. This RGB parallel signal RGB_P is converted into a high-speed serial signal SER4 in the signal conversion circuit TX3 'shown in FIG.

  As shown in FIG. 22, the signal conversion circuit TX3 ′ has a configuration similar to that of the signal conversion circuit TX3 of FIG. 12, and receives an RGB parallel signal composed of 480 × 800 dots and a synchronization clock. Buffer Input Buffer, encoder Encode that generates basic data of high-speed serial signal by adding synchronization signal and other control data to RGB parallel signal, and serial conversion of basic data of high-speed serial signal as high-speed serial signal SER4 PS converter for outputting PS Converter.

  In this second configuration, by arranging the signal conversion circuit TX3 ′ and the signal conversion circuit TX2 ′, the signal transmission paths toward the sub display devices DS2 to DS4 are all configured by the high-speed serial signals SER2 to SER4. Despite increasing the number of devices, the wiring inside the gaming machine becomes simple. Further, the dot clock is 27 MHz, and various image effects can be achieved with high image quality using the sub display devices DS2 to DS4.

  FIG. 18 exemplifies the third configuration. For the image data of the display devices DS2 to DS4, based on the display list, image data for each 480 × 800 pixels is once generated in the work areas WK2 to WK4. After that, based on the horizontal horizontal connection processing JION ′ described in the display list, the image data of the composite frame of 3 × 480 × 800 pixels is transferred to the frame buffer FBb.

  The horizontal connection process JOIN ′ is a series of drawing command sequences for transferring predetermined rectangular frame data to another rectangular frame data, and is a subroutine process similar to the stripe connection process JOIN. However, as shown in FIG. 18, the work areas WK2, WK3, and WK4 store image data for 480 × 800 pixels that virtually form a rectangular frame. In principle, it ends by executing the drawing command for realizing the movement of the rectangular frame data three times.

  Then, the display circuit 74B reads the image data of the frame buffer FBb, and outputs the LVDS signal LVDS_2 with a dot clock of 81 MHz via the output selection unit 79. As shown in FIG. 18, in the third configuration, the display circuit 74C and the frame buffer FBc do not function, and only the signal conversion circuit TX4 is included in the signal conversion unit CNV in addition to the signal conversion circuit TX1. Has been placed.

  The signal conversion circuit TX4 has an internal circuit similar to the circuit configuration of FIG. 21, and as shown in FIG. 23, the parallel conversion unit SP Converter that converts the received LVDS signal LVDS_2 in parallel and the parallel conversion unit SP Converter A buffer circuit Data Buffer that outputs and outputs parallel data to be output in a maximum of four sections (1 to 4) for each predetermined pixel, and a basic high-speed serial signal that receives pixel data that is partitioned into a predetermined number of sections (1 to 4) A decoder Decode that generates data and a serial conversion unit PS Converter that serially converts an output of the decoder Decode and outputs a high-speed serial signal SERi are configured.

  The segmentation pixel unit and the number of segments within the segmentation range of 1 to 4 can be set as appropriate. However, in the embodiment, based on the set value to the signal conversion circuit TX4, the segmentation pixel unit = 480 pixels, the number of segments By setting = 3, the image data of the composite frame of 3 × 480 × 800 pixels is divided into three for every 480 pixels, and high-speed serial signals SER2 to SER4 each transmitting 480 × 800 pixel data are output. Yes.

  Next, FIG. 19 illustrates a fourth configuration. The signal conversion unit CNV includes a signal conversion circuit TX4 ′ that receives the RGB parallel signal RGB_P and performs the same operation as the signal conversion circuit TX4. Yes. Here, the signal conversion circuit TX4 'and the signal conversion circuit TX4 have a certain difference in whether the input signal is the RGB parallel signal RGB_P or the LVDS signal LVDS_2, and the apparent internal operation is exactly the same. The composite frame image data of the sub display devices DS2 to DS4 for 3 × 480 × 800 pixels generated in the frame buffer FBc is output to the sub display devices DS2 to DS4 as the high-speed serial signals SER2 to SER4. Is done.

  Note that the image data of the composite frame does not necessarily have to be generated by the horizontal connection process JOIN ′, including the case of the third configuration, and may be connected vertically and horizontally. In the conversion circuits TX4 and TX4 ′, the high-speed serial signals SER2 to SER4 can be generated by appropriate separation. Note that the signal conversion circuit TX4 ′ can handle horizontal 1 × 4 horizontal connection and vertical 2 × 2 vertical and horizontal connection, so it is also preferable to dispose the fourth sub display device DS5. is there.

  By the way, in the fourth configuration, for the image data of the main display device DS1, after generating image data for 1280 × 1024 pixels in the work area WK1 based on the display list, the stripe division processing described in the display list is performed. DIV is executed and rearranged in the frame buffer FBa and the frame buffer FBb. The stripe dividing process DIV is composed of a drawing command sequence for executing the reverse operation of the stripe connecting process. As a subroutine DIV accessible by the drawing circuit 76 (DL analyzer), for example, when the power is reset, for example, the built-in VRAM 71 Or stored in the external DRAM 54.

  The display circuit 74A and the display circuit 74B read the image data in the frame buffer FBa and the frame buffer FBb, and output the LVDS signals LVDS_1 and LVDS_2 with the dot clock frequency suppressed to 54 MHz through the output selection unit 79. This fourth configuration has an advantage that two systems of LVDS signals LVDS_1 and LVDS_2 can be output without arranging the signal conversion circuit TX1 in the signal conversion unit CNV.

  However, the configuration using the work area WK1 is not necessarily essential, and can be further simplified. FIG. 24 illustrates a modification of the fourth configuration that does not use the work area WK1.

  Here, as in the first to third and fifth configurations, image data for 1280 × 1024 pixels is directly generated in the frame buffer FBa, and the display circuit 74A reads the image data in the frame buffer FBa. ing. Then, by causing the output selection circuit 79 to perform the stripe division operation, the image data for odd stripes is output as the LVDS signal LDVS_1, and the image data for even stripes is output as the LVDS signal LDVS_2.

  Finally, FIG. 20 illustrates the fifth configuration, and shows a configuration example in which four sub-display devices DS2 to DS5 are provided. As illustrated, the image data of the display devices DS2 to DS3 is, for example, stripe-connected and arranged in the frame buffer FBb, and the image data of the display devices DS4 to DS5 is, for example, stripe-connected and arranged in the frame buffer FBc.

  These image data are read out to the display circuits 74B and 74C, and transmitted to the signal conversion unit CNV as the LVDS signal LVDS_2 and the RGB parallel signal RGB_P via the output selection unit 79. As shown in the figure, since the signal conversion circuit TX2 ′ and the signal conversion circuit TX3 are arranged in the signal conversion unit CNV, the high-speed serial signals SER2 to SER5 are converted through these circuits. And output to the sub display devices DS2 to DS5. In these third to fifth configurations, the same excellent effects as those of the first configuration can be exhibited.

  By the way, in the first to fifth configurations, stable signal transmission performance is ensured even when the signal transmission distance is long. For this purpose, it is preferable to provide a drive substrate that receives the LVDS signals LVDS_a and LVDS_b output from the signal converter CNV as in the sixth configuration shown in FIG. For example, a signal conversion circuit TX1 shown in FIG. As shown in FIG. 10, the signal conversion circuit TX1 includes an LVDS receiver LVDS-Rx and an LVDS transmitter LVDS-Tx arranged in two upper and lower stages, and outputs two sets of LVDS signals LVDS_a and LVDS_b as they are. Drive operation (Dual-In Dual-Out) is also possible.

  Therefore, in the sixth configuration, the signal conversion circuit TX1 of the signal conversion unit CNV performs the single-in dual-out operation described with reference to FIG. 10, while the signal conversion circuit TX1 of the drive board has a dual-in dual-out operation. -Deterioration of signal is prevented by executing -Out drive operation.

  In any of the first to fifth configurations, the signal conversion unit CNV is arranged on the image interface board 28, and the image data is transferred via the signal conversion unit CNV. It tends to increase in size. Therefore, in order to reduce the size of the image interface board 28 as much as possible, it is effective to reduce the number of connection connectors. Therefore, in the sixth embodiment, the outputs SER2 to SER5 of the signal conversion circuit TX2 'and the signal conversion circuit TX3 are received by a single connection connector (collective connector). The collective connector is connected to the collective connector of the signal relay board, and the transmitted high-speed serial signals SER2 to SER5 are transmitted to the four output connection connectors by the signal relay board. This configuration has an advantage that the enlargement of the image interface board 28 can be suppressed by the amount of the signal relay board.

  Finally, the stripe connection process JOIN will be specifically illustrated based on FIG. As shown again in FIG. 25, for example, in the embodiment shown in FIG. 9B, the image data for the display device DS3 (480 × 800 pixels) is completed in the work area WK3, and the image data for the display device DS4. (For 480 × 800 pixels) is completed in the work area WK4.

  After that, these completed image data need to be collected in a frame buffer FBc having a storage area of 960 × 800 pixels by stripe connection processing JOIN described at the final position of the display list.

  Therefore, in order to realize such an operation, in the embodiment shown in FIG. 25, the frame buffer FBc separates the 960 × 800 pixels P (i, j) from 3 bytes for specifying the RGB data. An α channel for specifying an α value is included. Here, the α value is transparency information set at each pixel position P (i, j), and a new image (source) to be overwritten on the frame buffer FBc and an original image (destination) of the frame buffer FBc. Is a value that specifies the α blend process that defines the transparency.

  Although not particularly limited, if the α value has a 1-byte configuration, information of each pixel position P (i, j) is specified by a total of 4 bytes, and the frame buffer FBc has a total of 960 × 800 ×. The data capacity is 4 bytes long.

  For the frame buffer FBc having such a configuration, in the stripe concatenation process JOIN, first, α value = 0 is written in the α channel that specifies the odd-numbered column pixels, while the α-channel that specifies the even-numbered column pixels is written. , Α value = 255 is written (SS51).

  Next, the image data (480 × 800 pixels) of the display device DS3 in the completed state stored in the work area WK3 is expanded in the horizontal direction and is stored in the frame buffer FBc as image data of 960 × 800 pixels. Write (SS52).

  In the double enlargement process, in a drawing command for transferring image data from the work area WK3 to the frame buffer FBc, an image area on the source side (work area WK3) and an image area on the destination side (the frame buffer FBc that is large in the horizontal direction) You only need to specify it. That is, since the destination-side frame buffer FBc is doubled in the horizontal direction as compared with the source side, the horizontal enlargement process is automatically executed in the drawing circuit (Pixel Generator).

  In this double enlargement process, the image data in the first column of the work area WK3 is copied to the first and second columns of the frame buffer FBc, and the image data in the second column of the work area WK3 is copied to the frame buffer. It is configured to be copied to the third and fourth columns of FBc. The same applies to the following, and the image data in the Nth column of the work area WK3 is copied to the 2 * N−1th column and the 2 * Nth column of the frame buffer FBc to become a destination image.

  Next, the image data of the display device DS4 in the completed state stored in the work area WK4 is doubled in the horizontal direction to obtain 960 × 800 pixel image data and the image data in the frame buffer FBc. The α blend process is executed in (SS53). Also in this case, the image data of the Nth column of the work area WK4 acts on the 2 * N−1th column and the 2 * Nth column of the frame buffer FBc by the enlargement process, and between the destination image at that position. α blend processing is performed.

  In the α blend process, for example, as shown in Equation 1 in FIG. 25, the calculation of Cr = Cd * (1−α / 255) + Cs * α / 255 is executed. In this arithmetic expression, Cd is written to the frame buffer FBc by the RGB information of the original image (Destination) written to each pixel position P (i, j) of the frame buffer FBc, that is, in the process of step SS52. This is the image data of the rare work area WK3 (for 960 × 800 pixels of the display device DS3 expanded in the horizontal direction).

On the other hand, Cs is RGB information of the source image of the horizontally expanded work area WK4 (for 960 × 800 pixels of the display device DS4), and Cr is RGB information of the frame buffer FBc after α blend processing. In the α blend processing formula, 255 is the upper limit value of the α value of the 1-byte configuration (n = 8), and changes according to the data configuration (2 ⁿ −1).

  As described above, the α value is 0 in the odd pixel column shown in FIG. 25 and 255 in the even pixel column shown in FIG. 25 by the process of step SS50. Therefore, in the frame buffer FBc corresponding to the odd pixel column, Cr = From the relationship of Cd, the original image (Destination), that is, the image data for the sub display device DS3 remains as it is.

  On the other hand, in the frame buffer FBc corresponding to the even pixel columns, the original image (Destination) disappears due to the relationship of Cr = Cs, and only the new image (Source) to be overwritten, that is, the image data for the sub display device DS4. Will be memorized.

  As a result, the frame buffer FBc stores the image data of the display device DS3 and the display device DS4 in a stripe connection.

  In the above-described α brent process, the image of the sub-display device DS4 that has been horizontally expanded is used as the source image, but instead, the image of the sub-display device DS3 that has been horizontally expanded may be used as the source image. Of course. Further, it is optional to leave the image of the sub display device DS4 or leave the image of the sub display device DS3 in the odd-numbered pixel column. Correspondingly, if the circuit connection on the output side such as the conversion circuit TX3 is changed, good.

  In the embodiment, the stripe connection process JOIN is provided with the process of step SS51, and the α value is set every time the display list is executed. However, when the α channel of the frame buffer is not overwritten, the power reset is performed. Thereafter, step SS51 may be executed only once.

  In the embodiment, two work areas WK3 and WK4 are provided corresponding to the two sub display devices DS3 and DS4. However, any one of the image data may be completed using the frame buffer FBc. . However, in this case, it is necessary to adopt a configuration in which the α channel of the frame buffer FBc is not rewritten until the image data of the sub display devices DS3 / DS4 is completed.

  As described above, the stripe linking process has been described with respect to the first configuration (FIG. 9), the second configuration (FIG. 17), and the fifth configuration (FIG. 20), but the third configuration (FIG. 18), the fourth configuration (FIG. 19, In FIG. 24), α blend processing for linking image data is not necessary.

  That is, by using a drawing command for transferring the image data of a rectangular frame completed in the work area WKi to another rectangular frame secured in the frame buffer FB, horizontal connection, vertical connection, and vertical and horizontal connection are possible. Is as described above.

  Further, the stripe dividing process DIV in the fourth configuration shown in FIG. 19 may be performed by performing the reverse operation of the stripe connecting process.

  First, a work area WK0 having a storage capacity of −1 column to 1281 column having a margin of one column (1024 pixels) before and after 1280 × 1024 pixels is secured (see FIG. 19), and the α channel of the work region WK0 is The α value 0 is written in the odd column, and the α value 255 is written in the even column. Note that the α blend process is not executed for the image data in the −1 column, and the image data in the 1281 column is not utilized, so these α values are arbitrary.

  Next, 1280 × 1024 pixel image data Gbs of the work area WK1 is written to the first to 1280 columns of the work area WK0, and the image data Gbs of the work area WK0 and the image data Gbs of the work area WK1 are set to one pixel. Α blend operation L of Cr = Cd * (1−α / 255) + Cs * α / 255 is applied to the 2nd to 1281st columns with respect to the image data Gbs ′ shifted only to the right of the screen. Run.

  Then, the image data Gbs remains in the first column of the work area WK0, and in the second and subsequent even columns, Cr = Cs and the image data Gbs disappears, and the image data Gbs ′ shifted by 1 pixel from the image data Gbs ′. Will be overwritten.

  On the other hand, in the third and subsequent odd columns, Cr = Cd and image data Gbs remains, so in the first column to 1280 columns of the work area WK0, the odd columns and the even columns on the right side are the same. Image data is arranged.

  Therefore, next, the image data (1280 × 1024 pixels) of the work area WK0 thus completed is transferred to the frame buffer FBa having a capacity of ½ in the horizontal direction. As a result, the left and right pixels are automatically reduced horizontally by this transfer process, so that odd-numbered stripe image data of 640 × 1024 pixels is completed in the frame buffer FBa.

  Subsequently, 1280 × 1024 pixel image data Gbs of the work area WK1 is written to the first to 1280 columns of the work area WK0, and the image data Gbs of the work area WK0 and the image data Gbs of the work area WK1 are set to one pixel. Α blend operation R of Cr = Cs * (1−α / 255) + Cd * α / 255 is executed for the first to 1280th column with respect to the image data Gbs ″ shifted to the left by .

  Then, in the odd-numbered column of the work area WK0, Cr = Cs and the image data Gbs ″ is overwritten, whereas in the even-numbered column, Cr = Cd and the image data Gbs remains. The same image data is arranged in the odd-numbered columns.

  Therefore, next, the image data (1280 × 1024 pixels) of the work area WK0 completed in this way is transferred to the ½ frame buffer FBb in the horizontal direction. Then, since the left and right pixels are automatically reduced horizontally by this transfer process, even-numbered stripe image data for 640 × 1024 pixels is completed in the frame buffer FBb.

  The first configuration to the sixth configuration have been exemplarily described above, but the internal configurations of the first configuration to the sixth configuration, including the configuration in which the collective connector and the relay board are arranged, may be appropriately replaced or combined. Of course, each can exhibit the same effect.

  By the way, the 1st structure-the 6th structure demonstrated so far are applied suitably, especially when the transmission distance to sub display apparatus DS2-DS4 is 1 m or less. However, there is a case where it is desired to secure a longer transmission distance, preferably 2 m or more.

  In addition, there is a case where it is desired to add a power saving mechanism to each of the display devices DS1 to DS5 regardless of the length of the transmission distance, or to make all or a part of the sub display devices DS2 to DS4 participate in the accessory effect. However, if the number of wires is increased in order to meet such a demand, the inside of the device becomes complicated, which is very inconvenient for assembly and maintenance.

  Therefore, in the seventh configuration described below, RGB image data (RGB parallel signal RGB_P) for 480 × 800 pixels to be displayed on the sub display device DS4 is striped in the signal conversion circuit TX5 to reduce the transmission speed. Serial transmission is performed as the two-path (2LANE) high-speed serial signals SER6 and SER7.

  As apparent from the comparison between the seventh configuration shown in FIG. 26 and the second configuration shown in FIG. 17, in this seventh configuration, the dot clock frequency of the image data transmitted as the high-speed serial signals SER6 and SER7 is 1. Therefore, the transmission distance can be increased by that amount.

  In the experiment of the present inventor, it has been confirmed by an eye pattern that there is no problem even with a transmission distance of about 2 m. The eye pattern is a figure obtained by sampling a large number of signal waveform transitions and overlaying them on an oscilloscope.

  As shown in FIG. 26, in the seventh configuration, a serial reception circuit RV5 is arranged corresponding to the signal conversion circuit TX5 (see FIG. 28). The serial reception circuit RV5 receives the high-speed serial signals SER6 and SER7 transmitted through the two paths, restores the parallel signals, and stripe-connected RGB image data for 480 × 800 pixels to one sub display device DS4. Supply.

  In this embodiment, in addition to signals for driving the display device DS4 such as RGB image data (24 bits), a dimming signal DIM for dimming control of the LED backlight of the display device DS4 is transmitted. . Here, the dimming signal DIM is a 1-bit PWM signal and is transmitted as a part (1 bit) of 36-bit serial data (see FIG. 11B) constituting a high-speed serial signal.

  The dimming signal DIM restored by the serial reception circuit RV5 is supplied to the dimming circuit LGH to control the gradation of the backlight of the display device DS4. Therefore, in this embodiment, for example, the power saving function of extinguishing the backlight light of the sub display device DS4 can be exhibited at the time of demonstration production, and the number of wirings is not increased for the dimming control. .

  FIG. 28 illustrates the relationship among the signal conversion circuit TX5, the serial reception circuit RV5, the dimming circuit LGH, and the backlight unit of the display device. The basic configuration of the signal conversion circuit TX5 is basically the same as that of the signal conversion circuit TX3 'shown in FIG. 22, and has an internal configuration that receives RGB image data and outputs a high-speed serial signal.

  However, in this embodiment, the 2ALE high-speed serial signals SER6 and SER7 are output by keeping the DUAL terminal at the H level (control). In addition, the signal conversion circuit TX5 is configured so that the RGB parallel signal (24 bits), the synchronization signals HS and VS (2 bits), and the data enable signal DE (1 bit) are synchronized with the 27 MHz pixel clock PCLK. The dimming signal DIM (1 bit) received from the built-in CPU circuit 51 is acquired in the same internal circuit (Input Buffer). The dimming signal DIM is output via the parallel input / output port (PIO) 62 and the output circuit 64p based on the effect control of the built-in CPU circuit 51 (see FIG. 6).

  The above 28-bit signal acquired by the signal conversion circuit TX5 is appropriately encoded and stripe-divided to prevent the DC balance from being lost due to the same logic level being continued, and a total of 36 bits. Serial transmission is performed as long serial data (see FIG. 11B).

  As shown in FIG. 11B, in the high-speed serial signals SER6 and SER7, the 36-bit serial data is updated in synchronization with the 27 MHz pixel clock PCLK in this embodiment.

  As shown in FIG. 28, the serial reception circuit RV5 has an internal configuration corresponding to the signal conversion circuit TX5, and the DUAL terminal is fixed at the H level, whereby the reception circuit for the 2LANE high-speed serial signals SER6 and SER7. Function as. After the parallel conversion in the SP converter, the RGB parallel signal (24 bits) appropriately decoded and stripe-connected, the synchronization signals HS and VS (2 bits), and the data enable signal DE (1 bit) are converted into pixels. It is output together with the clock PCLK.

  In accordance with this operation, the dimming signal DIM is also restored and output to the dimming circuit LGH. The dimming circuit LGH is composed of, for example, a white LED driver TPS6116xA (Texas Instrument), and the LED lamp group of the backlight unit based on the pulse width (duty ratio) of the dimming signal DIM as a PWM signal received at the control terminal CTRL. Dimming control.

  Therefore, according to the present embodiment, the luminance of the display device DS4 can be appropriately adjusted without increasing the number of wirings. For example, in a gaming machine that allows the sub display device DS4 to function only during a notice effect, the backlight can be extinguished not only at the demonstration effect but also at a timing other than the notice effect.

  As described above, according to the seventh configuration shown in FIG. 26, the transmission distance can be extended to 2 m or more by outputting the stripe-divided 2LANE high-speed serial signals SER6 and SER7. In addition, according to the signal conversion circuit TX5 shown in FIG. 28, the 2LANE transmission or the 1LANE transmission can be appropriately selected by the DUAL terminal, so that the signal conversion unit CNV can be applied to other types of gaming machines that do not require much transmission distance. The circuit board can be used as it is.

  FIG. 27 shows a case where the signal converter CNV of FIG. 26 is used as it is and a device configuration of 1LANE transmission with a pixel clock of 27 MHz is adopted. In the eighth configuration, the DUAL terminal is maintained (controlled) at the L level, and the motor drive signal DR is supplied to the signal conversion circuit TX5 instead of the dimming signal DIM, and transmitted as a high-speed serial signal. Thus, the sub display device DS4 is appropriately moved.

  The motor drive signal DR has, for example, an 8-bit length that can drive the pair of effect motors Mr and Mr, is converted into a 1-bit composite drive signal by the PS converter PSC, and is supplied to the signal conversion circuit TX5. . Then, the 1-bit composite drive signal extracted by the serial reception circuit RV5 is restored to an 8-bit motor drive signal by the SP converter SPC and supplied to the effect motors Mr and Mr.

  FIG. 30 illustrates the internal configuration of the PS conversion unit PSC and the SP conversion unit SPC. The PS conversion unit PSC includes a latch circuit, and the latch circuit acquires 8-bit parallel data based on input control signals CTL0 and CTL1 received from the outside. The acquired parallel data has a sampling frequency of 50 kHz and is output as a serial signal that is appropriately scrambled and ensures DC balance in a serializer that functions every 1/50 mS.

  On the other hand, in the SP converter SPC, a serial signal (single-end signal) having a transmission rate of about 2.5 MHz is restored to a parallel signal by the deserializer and transmitted to the output circuit. The parallel signal transmitted to the output circuit is output based on output control signals CTL0 and CTL1 received from the outside. However, in the embodiment, by fixing the output control signal CTL0 to the L level and the output control signal CTL1 to the H level, the acquired motor drive data is output in an uncontrolled state.

  FIG. 31 shows a circuit example in which a PS conversion unit PSC and an SP conversion unit SPC are added to transmit motor drive data as part of a high-speed serial signal. As shown on the left side of FIG. 31, in the PS conversion unit PSC of the embodiment, the input control signal CTL1 is fixed to H, while the data control is performed, the input control signal CTL0 is changed to L level to change the motor drive signal DR. The data is acquired by the latch circuit.

  Specifically, the motor drive signal DR is acquired by the latch circuit at the rising edge at which the input control signal CTL0 returns from the L level to the H level. The serializer repeats the internal operation every 1/50 mS, and repeatedly outputs the updated motor drive signal as a serial signal.

  Although not particularly limited, the transmission rate of the output serial signal (single-ended signal) is 2.5 MHz, which is 1/10 or less of the pixel clock 27 MHz that defines the transmission rate of RGB data, and is mixed with RGB data. Even if it is transmitted as a high-speed serial signal, there is no problem.

  As described above, the SP conversion unit SPC of the embodiment outputs the acquired motor drive data in an uncontrolled state by fixing the output control signal CTL0 to the L level and the output control signal CTL1 to the H level. (See right side of FIG. 31).

  Corresponding to this configuration, in the SP conversion unit SPC of the embodiment, the built-in digital filter circuit is set to the ON state (FILT = H), and the acquired data for the three sampling frequencies match. As a condition, new data is transmitted to the output circuit. Therefore, no problem occurs even if the motor drive data continues to be output in the uncontrolled state (running state).

  As described above, by appropriately controlling the dual terminal H / L, it is possible to realize the seventh configuration or the eighth configuration while sharing the circuit board on which the same signal conversion unit CNV is mounted. A difference in transmission distance to the sub display device can be dealt with. In the eighth configuration, the serial reception circuit RV5 is used. However, when the dimming signal DIM and the motor drive signal DR are not transmitted, the serial reception circuit shown in FIG. May be.

  In the seventh configuration, the dimming signal DIM need not be sent, and it is needless to say that the motor drive signal DR may be sent instead of the dimming signal DIM. Similarly, in the eighth configuration, the motor drive signal DR may not be sent, and the dimming signal DIM may be sent instead of the motor drive signal DR.

  In the seventh configuration and the eighth configuration, the sub display device DS4 has been described. However, the signal conversion circuit TX1 (LVDS_a + LVDS_b) that outputs two LVDS signals divided into stripes in response to the LVDS signal (FIG. 9, FIG. 9). 17, 18, and 20), it is also preferable to adopt a configuration in which the dimming signal DIM and other signals are transmitted together.

  As described above, the configuration in which a large number of sub-display devices DS2 to DS4 are arranged on the premise of the single main display device DS1 has been described. However, the present invention is also suitably applied to the case where the main display device DS1 is divided. be able to.

  FIG. 32 shows an embodiment in which two liquid crystal display devices DS1a and DS1b having the same shape of about 12 inches are arranged to realize the main display device DS1 and four sub display devices DS2 to DS5 of about 5 inches are provided. (9th structure) is shown. In this configuration, since the main display device DS1 is twice as large as 12 inches, a larger screen can be realized than the main display devices (first configuration to eighth configuration) configured with 19 inches. In addition, it is possible to realize a new image effect by moving the two display devices DS1a and DS1b in conjunction with each other in the vertical direction. Here, it is assumed that the display screens of the display devices DS1a and DS1b each have, for example, pixels of horizontal 800 × vertical 600 dots.

  The movable configuration of the two display devices DS1a and DS1b will be described later. First, the circuit configuration of the image interface board 28 will be described. The composite image data (for 480 × 800 × 2 pixels connected in stripes) for the display devices DS2 and DS3 in which the frame buffer FBb is constructed is transmitted in the signal conversion circuit TX2 ′ as in the case of the second configuration (FIG. 17). By dividing the stripe, it is converted into two systems of high-speed serial signals whose Dodd clock frequency is ½ times. Then, in the serial reception circuit RV2a and the serial reception circuit RV2b, the RBG parallel data is restored and supplied to the display devices DS2 and DS3.

  On the other hand, the composite image data (480 × 800 × 2 pixels connected in stripes) for the display devices DS4 and DS5 in which the frame buffer FBc is constructed is the signal conversion circuit TX3 as in the first configuration (FIG. 9). In FIG. 2, the stripe division is performed to convert the high-speed serial signal having a dod clock frequency of ½ times. Then, in the serial receiving circuit RV3 and the serial receiving circuit RV4, the RBG parallel data is restored and supplied to the display devices DS4 and DS5.

  The above configuration is similar to the first configuration and the second configuration described above, but in this ninth configuration, two liquid crystal display devices DS1a and DS1b are arranged to realize the main display device DS1, In the frame buffer FBa, image data for 800 × 600 × 2 pixels for the display devices DS1a and DS1b connected in stripes is constructed.

  The method of stripe connection is as described with reference to FIG. In the case where independent images are displayed on the display device DS1a and the display device DS1b, respectively, image data for 800 × 600 pixels corresponds to 800 × 600 × 2 pixels based on the display lists DL1a and DL1b. Are generated in the work area WK0 (see FIG. 32B).

  On the other hand, when a unified image is displayed on the display device DS1a and the display device DS1b, the display device DS1 is larger than the lower display frame FM (see FIG. 34A) of the front display device DS1, FIG. A work area WK0 for 800 × (600 × 2 + δ) pixels exemplified in ') is secured. Then, unified image data based on a single display list DL1 is generated in the drawing area of 800 × (600 × 2 + δ) pixels.

  In any case, however, the composite frame image data for a total of 2 × 800 × 600 pixels is generated in the frame buffer FBa through the processing of FIG. 25A based on the last command string in the display list (FIG. 25). 32 (e)). Specifically, the image data for the display device DS1a and the display device DS1b is respectively doubled in the horizontal direction and temporarily stored in the work areas WK1 and WK2 (see FIG. 32C), and an α blend calculation is performed. The composite image data obtained by executing is generated in the frame buffer FBa. In the unified image, composite image data in which the area (vertical width δ) of the lower display frame FM of the display device DS1 is missing is generated in the frame buffer FBa (see FIG. 34B).

  In any case, the display circuit 74A reads the image data in the frame buffer FBa and outputs an LVDS signal LVDS with a dot clock of 80 MHz. The signal conversion circuit TX1 performs two types of LVDS signals with a dot clock of 40 MHz by sprite division. Is output. Thus, in the ninth configuration, two LVDS signals with the dot clock frequency relaxed to ½ are transmitted from the image interface board 28 to the display devices DS1a and DS1b. Thus, a long transmission distance can be secured, and a freely movable effect can be achieved in each display device DS1a, DS1b.

  The signal conversion circuit TX1 arranged on the image interface board 28 is as shown in FIG. 10A. The two types of LVDS signals are image data for the display device DS1a and image for the display device DS1b, respectively. It is nothing but a signal that transmits data. Then, the RGB parallel signals are restored by the LVDS receivers RV1a and RV1b built in the display devices DS1a and DS1b, and each display screen is constructed.

  Next, the movable mechanism STR of the display device DS1a and the display device DS1b will be described with reference to FIG. FIG. 33A is a perspective view of the main part of the movable mechanism STR viewed from the back side, and FIG. 33C is a perspective view of the movable mechanism STR viewed from the front side.

  As shown in FIG. 33 (a), this movable mechanism STR is driven by two left and right drive motors MOR, MOL that rotate together in an integrated manner, and motors MOR, MOL, and passes through rotating rollers RO, RO. Circulating fan belts BT, BT, a pair of left and right rear holding pieces HLb, HLb held by the left and right fan belts BT, BT in the rear position, and a rear base plate BSb fixed to the rear holding pieces HLb, HLb, A pair of left and right front holding pieces HLa and HLa held by the left and right fan belts BT and BT in the front position, and a front base plate BSa fixed to the front holding pieces HLa and HLa, are arranged apart from each other in the front and rear positions. A total of four guide poles GDa, GDa, GDb, and GDb are provided.

  Here, the display device DS1b is fixed to the rear base plate BSb, while the display device DSa is held by being fixed by the front base plate BSa. The front holding pieces HLa and HLa and the rear holding pieces HLb and HLb are provided with receiving holes for receiving the guide poles GDa, GDa, GDb, and GDb, and are integrated with the display devices DS1a and DS1b. The holding pieces HLa and HLb are guided by the corresponding guide poles GDa and GDb so as to move up and down smoothly in the vertical direction.

  FIG. 33B shows the positional relationship between the two display devices DS1a and DS1b and the movement position. FIG. 33 (b1) shows an initial state, in which the display device DS1a located on the upper side and the display device DS1b located on the lower side are continuous in the vertical direction without being superposed. Double the display screen. Since the lower display frame FM of the display device DS1a coincides with the position of the upper display frame of the display device DS1b, the two display devices DS1a and DS1b display one display screen except for the lower display frame FM. Form.

  Here, since the two drive motors MOR and MOL are configured to rotate integrally with each other, for example, when the drive motors MOR and MOL start to rotate integrally in the illustrated counterclockwise direction, the upper display device In response to the lowering of DS1a, the lower display device DS1b is raised.

  Then, after the two display devices DS1a and DS1b are superposed in the front-rear direction, the state shown in FIG. 33 (b2) is reached, and when the display device DS1a is further lowered and reaches the limit position, the state shown in FIG. 33 (b3) is obtained. . As shown in the figure, the lowering limit of the display device DS1a is the upper limit of the display device DS1b, and a display screen twice as large as 12 inches is formed by the upper display device DS1b and the lower display device DS1a. The

  When the drive motors MOR and MOL rotate integrally in the clockwise direction from the state shown in FIG. 33 (b3), the state returns to the initial state shown in FIG. 33 (b1) via the overlapping state shown in FIG. 33 (b2). Become.

  Therefore, in this embodiment, the drive motors MOR and MOL are rotated by an appropriate amount in the clockwise or counterclockwise direction, thereby producing the rendering operation A including the initial state (b1) and the superposition state (b2), and superposition. The player is enlivened by the production operation B including the state (b2) and the descent limit (b3), the production operation C including the initial state (b1) and the descent limit (b3), and the like. These movable effects are preferably executed as a notice effect. Corresponding to the rendering operations A to C, appropriate image data is generated in the frame buffer FBa.

  FIG. 34 shows a case where independent image data for each of the display devices DS1a and DS1b is generated in the work area WK0 in the initial state (b1) of the movable effect (FIG. 34A, integrated with the work area WK0). FIG. 34B shows a case where simple image data is generated.

  In the case of FIG. 34 (a), the image control CPU 63 (FIG. 6) specifies the display list DL1a for specifying one frame image to be displayed on the display device DS1a and the one frame image to be displayed on the display device DS1b. The display list DL1b is output to the VDP circuit 52. On the other hand, in the case of FIG. 34 (b), the image control CPU 63 (FIG. 6) displays one frame image (800 × (600 × 2 + δ) pixels) displayed on the display device DS1a and the display device DS1a. The list DL1 is output to the VDP circuit 52. As described above, the 800 × δ pixel image constitutes a non-display portion corresponding to the lower display frame FM of the display device DS1a.

  In addition, the display device DS1a is also displayed during the overlapping operation of the two display devices DS1a and DS1b and the movement operations A to C shown in FIG. 33 as illustrated in FIG. 34C and FIG. 34D. And the display list DL1 specifying one frame image (800 × (600 × 2 + δ) or 800 × 600 × 2 pixels) displayed on the display device DS1a is output to the VDP circuit 52.

  However, when moving at a considerable speed, it is difficult for the player to surely view the display image, so it is preferable to display a transient image corresponding to the movement of the display device (see FIG. 34). By making a transitional image, even if the display screen collapses with the high-speed movement of the display device, the player does not feel uncomfortable. Note that the movable effects of the display devices DS1a and DS1a are also preferably cooperated with other actors, and in FIG. 34 (d), in the superposed state of the two display devices DS1a and DS1b, other actors YAKU. Appears on the front of the display screen, and opens and closes appropriately.

  In any case, the image data constructed in the work area WK0 is sprite-connected to the frame buffer FBa through the procedures of FIGS. 32B to 32E, and is sprite divided by the signal conversion circuit TX1. Then, the signals are supplied to the display devices DS1a and DS1b through the LVDS receivers RV1a and RV1b. As described above, the frequency of the LVDS signal transmitted from the image interface board 28 to the display devices DS1a and DS1b is reduced to 1/2 that in the other embodiments, so that the limit of the signal transmission distance is limited. As much as it is relaxed, it is possible to produce a flashy moving effect with a long moving distance. As described above, the moving speed can be increased by making the moving image a transitional image.

  In the embodiment of FIG. 33, the two display devices DSa and DSb are arranged up and down and moved in the vertical direction. However, the two display devices DSa and DSb are arranged in the left and right directions and are arranged in the left and right directions. It is also suitable to move. Note that the present invention is not limited to two display devices, and it is also preferable that three or more display devices are arranged appropriately and these are moved linearly or non-linearly vertically and horizontally.

  As described above, in the present specification, various configurations relating to the ball game machine have been described. However, the present invention is not limited to the ball game machine, and is also suitable for other game machines with image effects such as a spinning game machine. Of course, it can be utilized.

GM gaming machine 23 Sub-control means DS1-DS4 Display device 51 Image effect control means (built-in CPU circuit)
55 Data storage means 52 Image generation means DL Drawing instruction

Claims (8)

Sub-control means capable of executing an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal using a plurality of display devices based on a control command received from another control means A gaming machine provided with
The sub-control means includes
At the time of the predetermined effect, an image effect control means for centrally controlling the image effect by outputting a drawing instruction for specifying display contents of the plurality of display devices;
Data storage means for storing compressed data which is a constituent element of a still image and / or a moving image constituting an image effect;
An image generating means for accessing the data storage means and generating an image signal based on the drawing instruction received from the image effect control means;
Signal conversion means for signal-converting and outputting the image signal generated by the image generation means,
The gaming machine characterized in that the image signal generated by the image generation means includes a composite image signal for specifying a frame of a predetermined display device.   The gaming machine according to claim 1, wherein the composite image signal is divided by the signal conversion means and then transmitted toward the predetermined display device. The plurality of display devices are divided into a main display device that mainly executes a series of image effects leading to a notification operation of a lottery result of a lottery process, and a sub-display device having a smaller screen than the main display device,
The gaming machine according to claim 1 or 2, wherein the predetermined display device belongs to a sub-display device and has the same number of pixels constituting each display screen. The main display device
One frame composed of predetermined vertical and horizontal pixels by receiving from the signal conversion means the first signal and the second signal obtained by dividing image data specifying one frame into two, and restoring the original image data by a built-in circuit. The gaming machine according to claim 3, wherein Sub display device
Receiving image data specifying one frame as a differential signal from the signal converting means and receiving the restored image data from a receiving circuit for restoring the image data, drawing one frame composed of predetermined vertical and horizontal pixels The gaming machine according to claim 3 or 4.   The pixel pitch of the sub display device is ½ or less of the pixel pitch of the main display device in both the horizontal direction and the vertical direction, and the gradation of the pixel is equal to or greater than that of the main display device. A gaming machine according to any one of 3 to 5.   4. The gaming machine according to claim 3, wherein the predetermined display device is a plurality of N sub-display devices having the same number of vertical and horizontal pixels constituting a display screen.   The gaming machine according to any one of claims 1 to 7, wherein the plurality of display devices include a pair or a plurality of pairs of display devices that are movable and display a unified image when necessary.