JP2017157929A - Solid-state image pickup device and image reading device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of reducing reset noise, without lowering charge conversion efficiency.SOLUTION: A solid-state image pickup device includes a pixel circuit having a photoelectric conversion element generating charges according to incident light, a transfer element for transferring charges to a floating diffusion region, a first amplifier element for outputting the charges, transferred to the floating diffusion region, while amplifying, and a first reset element for initializing the floating diffusion region and photoelectric conversion element, a capacitance circuit connected with the output side of the first reset element, and provided with a capacitive element for accumulating the reset level and signal level of the photoelectric conversion element, and a control circuit for controlling operation of the pixel circuit and capacitance circuit. Before the control circuit controls the capacitive element to accumulate the reset level or signal level, initialization is executed by the first reset element.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state imaging device and an image reading device.

  In an apparatus equipped with an image scanner such as a copying machine, a solid-state imaging device such as a CMOS sensor used as a photoelectric conversion device includes a pixel circuit including a photoelectric conversion device that constitutes a pixel, a drive circuit that drives the pixel circuit, and a signal processing circuit Etc. The solid-state imaging device employs a column configuration including a plurality of pixel circuits, and is configured so that a drive circuit and a signal processing circuit correspond to each column.

  A CMOS (Complementary Metal Oxide Semiconductor) sensor operates with a single low voltage like a CMOS logic, and can be manufactured by applying a general-purpose CMOS process.

  In a line sensor using a CMOS sensor, pixel circuits are arranged one-dimensionally in the main scanning direction, and an image is read while relatively moving the scan target in the sub-scanning direction. In this case, while the position of the line sensor is advanced by one line in the sub-scanning direction (time), photoelectric conversion of all pixels (light receiving elements) for the one line and readout of the accumulated charges are sequentially performed. .

  As described above, when acquiring the image data while moving the line sensor, it is necessary to accelerate the charge accumulation to the charge readout. Therefore, a line sensor using a CMOS sensor uses a global shutter system as an electronic shutter system.

  In the line sensor, since the arrangement of pixels is one-dimensional, a charge storage capacitor for holding the accumulated charge can be arranged in a peripheral region near the pixel. For this reason, the global shutter type line sensor can have a larger charge storage capacity than the area sensor. When this charge storage capacitor is inserted into a floating diffusion (FD) region, the relationship between charge conversion efficiency and charge retention time is a trade-off.

  Therefore, in order to achieve both charge conversion efficiency and charge retention time, a solid-state imaging device is known in which a charge retention capacitor is provided between an amplification transistor and a selection transistor to increase the charge storage capacitance (for example, Patent Document 1). See).

  However, when the charge storage capacity is increased as in the solid-state imaging device of Patent Document 1, reset noise generated during charge storage increases.

  The present invention has been made to solve such a problem, and an object thereof is to reduce reset noise without lowering charge conversion efficiency.

  The present invention relates to a solid-state imaging device, a photoelectric conversion element that generates a charge in response to incident light, a transfer element that transfers the charge to a floating diffusion region, and amplifies the charge transferred to the floating diffusion region. A pixel circuit including a first amplifying element to be output, a floating diffusion region and a first reset element for initializing the photoelectric conversion element, and a reset circuit for the photoelectric conversion element connected to an output side of the first amplifying element. A capacitor circuit including a capacitor element for storing a level and a signal level; and a control circuit for controlling the operation of the pixel circuit and the capacitor circuit, wherein the control circuit sets the reset level or the signal level to the capacitor element. And performing initialization by the first reset element before storing in the memory. .

  According to the present invention, reset noise can be reduced without lowering the charge conversion efficiency.

1 is a block diagram schematically showing a configuration of a solid-state imaging device according to an embodiment of the present invention. 1 is a circuit diagram schematically showing a circuit configuration of a solid-state imaging device according to an embodiment of the present invention. It is a circuit diagram showing an example of circuit composition of a pixel circuit and a memory circuit concerning an embodiment of the present invention. It is a circuit diagram which shows another example of the circuit structure of the pixel circuit and memory circuit which concern on embodiment of this invention. It is a timing chart which shows the example of the operation timing of the solid-state imaging device concerning the embodiment of the present invention. It is a timing chart which shows another example of the operation timing of the solid-state imaging device concerning the embodiment of the present invention. It is a timing chart which shows the further another example of the operation timing of the solid-state imaging device concerning the embodiment of the present invention. It is a timing chart which shows the further another example of the operation timing of the solid-state imaging device concerning the embodiment of the present invention. It is a timing chart which shows the further another example of the operation timing of the solid-state imaging device concerning the embodiment of the present invention. It is a timing chart which shows the further another example of the operation timing of the solid-state imaging device concerning the embodiment of the present invention. It is a figure explaining the example of the initialization level of the solid-state imaging device which concerns on embodiment of this invention. It is a figure explaining another example of the initialization level of the solid-state imaging device concerning the embodiment of the present invention. It is a figure explaining the further example of the initialization level of the solid-state imaging device which concerns on embodiment of this invention. 1 is a perspective view illustrating an appearance of an image reading apparatus according to an embodiment of the present invention.

Configuration of Solid-State Imaging Device Hereinafter, embodiments of the solid-state imaging device according to the present invention will be described. FIG. 1 is a block diagram schematically showing a solid-state imaging device according to this embodiment. In FIG. 1, a CMOS (Complementary Metal Oxide Semiconductor) sensor 1 is a solid-state imaging device formed by a CMOS process. The CMOS sensor 1 includes a pixel array unit 10, a memory array unit 20, a column signal processing unit 30, a horizontal drive circuit 40, a vertical drive circuit 50, a control unit 60, a first constant current unit 70, 2 constant current unit 80.

  The pixel array unit 10 is a pixel circuit including a plurality of light receiving elements. The light receiving element is a photoelectric conversion element that converts incident light into electrical energy and generates electric charge according to the intensity of the incident light. The charge generated by the light receiving element is transferred to the float diffusion region. The charges transferred to the float diffusion region are output to the memory array unit 20 through an amplifier circuit that operates with a power supply from the first constant current unit 70. A detailed configuration of the pixel array unit 10 will be described later.

  The memory array unit 20 includes a capacitive element that accumulates charges related to “reset level” and “signal level” output from the pixel array unit 10. This capacitive element is also called a charge storage capacitor. In addition, the memory array unit 20 includes a switching element for executing charge accumulation in the capacitor element and reading of the charge accumulated in the capacitor element at a predetermined operation timing.

  The memory array unit 20 outputs the electric charge read from the capacitive element to the column signal processing unit 30 via an amplifier circuit that is operated by a power supply from the second constant current unit 80. The detailed configuration of the memory array unit 20 will be described later.

  The column signal processing unit 30 includes a circuit that performs various signal processing on the reset level and signal level output from the memory array unit 20. For example, a correlated double sampling (CDS) circuit, an analog-digital conversion circuit, and a buffer circuit that temporarily holds a digital signal are provided.

  The horizontal driving circuit 40 reads out the digital signal held in the buffer circuit of the column signal processing unit 30 and transfers it in the horizontal direction. The digital signal transferred (output) from the horizontal drive circuit 40 is used as image data for subsequent processing.

  The vertical driving circuit 50 transfers the reset level and signal level of the pixel array unit 10 to the memory array unit 20, and outputs the reset level and signal level accumulated in the memory array unit 20 to the column signal processing unit 30. And control. The timing at which the reset level and signal level of the pixel array unit 10 are transferred to the memory array unit 20 is also referred to as charge write timing. The timing at which the reset level and the signal level stored in the memory array unit 20 are output to the column signal processing unit 30 is also referred to as charge read timing.

  Further, the vertical drive circuit 50 controls reset and signal level accumulation and output timings in the memory array unit 20 and initialization timings of the pixel array unit 10 and the memory array unit 20. Further, the vertical drive circuit 50 controls the signal processing timing of the reset level and the signal level output from the memory array unit 20 with respect to the column signal processing unit 30.

  The control unit 60 is a control circuit that controls the timing of each processing operation of the vertical drive circuit 50 and the horizontal drive circuit 40. That is, the control of the operation timing of each of the above-described units and circuits related to the CMOS sensor 1 is based on the control unit 60.

  The first constant current unit 70 is a constant current source for the amplifier circuit included in the pixel array unit 10. The second constant current unit 80 is a constant current source for the amplifier circuit included in the memory array unit 20.

Detailed Configuration of Solid-State Imaging Device FIG. 2 is a circuit diagram schematically showing a circuit configuration of the CMOS sensor 1 according to this embodiment. In FIG. 2, the pixel array unit 10 included in the CMOS sensor 1 includes a plurality of pixel blocks 11. Each of the pixel blocks 11 includes a plurality of pixels 110. One pixel block 11 includes a plurality of (six in FIG. 1) pixels 110 to form a set.

  If the CMOS sensor 1 is a line sensor, the arrangement of the pixel blocks 11 in the pixel array unit 10 is a one-dimensional arrangement. The arrangement is, for example, several thousand pixels in the column direction. When the CMOS sensor 1 is mounted on an image reading device such as a scanner, the object to be read is relatively moved in the sub-scanning direction while reading image data for one line in the main scanning direction. With such relative movement, a plurality of line data are acquired one after another, and two-dimensional image data is acquired. Note that each of the pixels 110 included in the pixel array unit 10 functions as a photoelectric conversion unit.

  The memory array unit 20 includes a plurality of memory blocks 21. Each of the memory blocks 21 includes a plurality of memory circuits 210. One memory block 21 corresponds to one pixel block 11. Each of the plurality of memory circuits 210 included in one memory block 21 corresponds to the plurality of pixels 110 included in one pixel block in a one-to-one relationship, and constitutes one set.

  Further, the memory block 21 includes a selection switch 120 that selects the operation timing of the pixel 110 and the memory circuit 210 in accordance with the timing control from the vertical drive circuit 50. Note that each of the memory circuits 210 provided in the memory block 21 functions as a charge storage unit.

As shown in FIG. 2, the set of the pixel block 11 and the memory block 21 has a function of outputting signals corresponding to the three primary colors red (R), green (G), and blue (B). . For example, the pixel block 11 includes six pixels 110 (R pixel 110 _R0 , R pixel 110 _R1 , G pixel 110 _G0 , G pixel 110 _G1 , B pixel 110 _B0 , B pixel 110 _B1 ). Corresponding to this, the memory block 21 includes six memory circuits 210 (R memory circuit 210 _R0 , R memory circuit 210 _R1 , G memory circuit 210 _G0 , G memory circuit 210 _G1 , B memory circuit 210 _B0 , B A memory circuit 210 _B1 ).

The R pixel 110 _R0 and the R pixel 110 _R1 include a color filter that transmits red light and an on-chip microlens. Similarly, the G pixel 110 _G0 and the G pixel 110 _G1 include a color filter that transmits green light and an on-chip microlens. The B pixel 110 _B0 and the B pixel 110 _B1 include a color filter that transmits blue light and an on-chip microlens.

  One pixel block 11 is a set of three color filters, and two pixels 110 corresponding to each color are used as one unit. The memory block 21 has a unit corresponding to one unit of the pixel 110 as one unit. With these configurations, the CMOS sensor 1 can read a color image.

The configurations of the R pixel 110 _R0 and the R pixel 110 _R1 are the same. Further, the configurations of the G pixel 110 _G0 , the G pixel 110 _G1 , the B pixel 110 _B0 , and the B pixel 110 _B1 are the same as those of the R pixel 110 _{R0 except} that the color filters that determine the color of light to be received are different. Similarly, the configurations of the R memory circuit 210 _R0 and the R memory circuit 210 _R1 are the same, and the G memory circuit 210 _G0 , the G memory circuit 210 _G1 , the B pixel 110 _B0 , and the B pixel 110 _B1 are also the same.

Therefore, in the following description, a set of the R pixel 110 _R0 and the R memory circuit 210 _R0 is used as a representative example. In the following description, when the matters common to all the pixels 110 and the memory circuit 210 are described, they may be simply referred to as “pixel 110” and “memory circuit 210”.

  In FIG. 1, six pixels 110 and six memory circuits 210 included in the configuration of one column in the CMOS sensor 1 are illustrated. The number of pixels 110 included in the column configuration of the pixels 110 in the CMOS sensor 1 according to the present embodiment is not limited to this example.

  The pixel 110 and the memory circuit 210 operate integrally. Here, an outline of operations of the pixel 110 and the memory circuit 210 will be described. The pixel 110 generates a charge corresponding to the reading target. The pixel 110 transfers the signal level based on this charge and the reset level based on the state when the pixel 110 is initialized to the memory circuit 210.

  The memory circuit 210 stores the signal level and the reset level transferred from the pixel 110 in the capacitor. At a predetermined timing, the data is read from the capacitive element and output to the column signal processing unit 30. The timing of these operations is based on the control of the control unit 60 via the vertical drive circuit 50.

  A global shutter method is used as a method (charge reading method) for transferring the reset level and the signal level from the pixel 110 to the memory circuit 210. A rolling shutter method is used as a method (charge reading method) for transferring the reset level and the signal level from the memory array unit 20 to the column signal processing unit 30.

  The global shutter method is a method in which the exposure start and the exposure end are simultaneously performed for all the pixel blocks 11 included in the pixel array unit 10, and the charges are simultaneously read from all the pixels 110 and transferred to the memory array unit 20. The rolling shutter method is a method in which exposure and charge reading are performed for each pixel row in the pixel block 11 included in the pixel array unit 10, and the charge is sequentially read for each pixel row and transferred to the memory array unit 20.

  The column signal processing unit 30 performs CDS processing by amplifying the reset level and the signal level output from the memory circuit 210 by the gain amplifier 301. Thereafter, the AD conversion circuit 302 converts it into a digital signal. The converted digital signal is temporarily held in the line buffer 303. The digital signals held in the line buffer 303 are sequentially read out by the horizontal drive circuit 40 at the operation timing based on the control of the control unit 60.

  The horizontal drive circuit 40 transfers the read digital signal in the horizontal direction. Thereby, image data for one line in the main scanning direction is obtained. By repeating this operation while scanning in the sub-scanning direction, two-dimensional image data can be obtained. In this case, the reset level and the signal level from the pixel 110 are transferred to the memory circuit 210, accumulated, read out, processed in the column signal processing unit 30, and output from the horizontal drive circuit 40 in the main scanning direction. This is a cycle (line cycle) for extracting data for one line.

The reset level and the signal level stored in the memory block 21 are read in the following order under the control of the vertical drive circuit 50. First, after the reset level accumulated in the R memory circuit 210 _R0 is read, the signal level stored in the same R memory circuit 210 _R0 is read. Subsequently, the reset level stored in the R memory circuit 210 _R1 is read out, and then the signal level stored in the same R memory circuit 210 _R1 is read out.

In the same order, the reset level and the signal level are read in the order of the G memory circuit 210 _G0 , the G memory circuit 210 _G1 , the B memory circuit 210 _B0 , and the B memory circuit 210 _B1 .

Example of Configuration of Pixel 110 and Memory Circuit 210 Next, a detailed configuration of the pixel 110 and the memory circuit 210 will be described with reference to the circuit diagram of FIG. In FIG. 3, since the pixel 110 exemplifies the pixel corresponding to the R element, “R” is added to the end of the reference numeral. The pixel 110 </ b> R includes a photodiode 111, a transfer gate 112, an FD region 113, a first reset transistor 114 that initializes the FD region 113 and the like, and a first amplification that operates by a supply current from the first constant current unit 70. Circuit 115.

  The pixel 110G corresponding to the G element and the pixel 110B corresponding to the B element also have the same configuration as the pixel 110R and are configured to be supplied with the current from the first constant current unit 70. . These descriptions are omitted.

  The photodiode 111 is a light receiving element and a photoelectric conversion element. The photodiode 111 is an element that generates an electric charge according to light energy in incident light. The charge generated in the photodiode 111 is transferred to the FD region 113 through the transfer gate 112. The transfer gate 112 is a transfer element. The charge transferred to the FD region 113 is output as an electrical signal through the first amplifier circuit 115 having the first amplifier element. The electric signal output at this time is called “signal level”.

  The first reset transistor 114 is a first reset element. The FD region 113 is a floating diffusion region. When the first reset voltage (VRT1) is applied to the FD region 113 by the operation of the first reset transistor 114, the charges generated and accumulated in the FD region 113 and the photodiode 111 are initialized.

  The potential of the initialized FD region 113 is output as an electrical signal from the pixel 110 via the first amplifier circuit 115. The electric signal output at this time is called “reset level”.

  That is, the signal level is an electric signal output in accordance with the image reading state in the photodiode 111 in the pixel 110. In addition, the reset level is an electric signal that is output in accordance with the initialized state of the pixel 110, not the image reading state of the photodiode 111.

  Hereinafter, the charge accumulated in and read from the capacitive element of the memory array unit 20 according to the signal level is also expressed as “signal level”. Similarly, the charge stored in and read from the capacitor element of the memory array unit 20 by the reset level is also expressed as “reset level”.

  In FIG. 3, the memory circuit 210 constituting the memory array unit 20 exemplifies a circuit corresponding to the R element, so that “R” is added to the end of the reference numeral. The memory circuit 210R includes a selection switch 120, a reset level capacitor 211, a signal level capacitor 212, a reset level selection switch 213, a signal level selection switch 214, a memory circuit selection switch 215, and a configuration shared by RGB. Is provided.

  The memory circuit selection switch 215 of the memory circuit 210 </ b> R is connected to a second amplifier circuit 221 that is operated by a current supplied from the second constant current unit 80. A second reset transistor 220 is disposed between the memory circuit selection switch 215 and the second amplifier circuit 221.

  Note that the memory circuit 210G corresponding to the G element and the memory circuit 210B corresponding to the B element also have the same configuration as that of the memory circuit 210R, and are configured so that the current from the second constant current unit 80 is supplied. Has been. These descriptions are omitted.

  The selection switch 120 is a switch element for selecting the memory circuit 210 to which the reset level and signal level from the pixel 110 are transferred. In accordance with the operation of the selection switch 120, the transfer timing from the pixel 110R, the pixel 110B, and the pixel 110G to the corresponding memory circuit 210 is controlled.

  The reset level selection switch 213 is a switch that operates when the reset level is stored in the reset level capacitor 211 or when the reset level is read from the reset level capacitor 211. The signal level selection switch 214 is a switch that operates when the signal level is accumulated in the signal level capacitor 212 or when the signal level is read from the signal level capacitor 212. The operation timing of the reset level selection switch 213 and the signal level selection switch 214 is based on a control signal from the vertical drive circuit 50 based on the control of the control unit 60.

  The memory circuit selection switch 215 is a switch that operates when the reset level or signal level is read from the memory circuit 210 and output to the column signal processing unit 30 at the subsequent stage. The operation timing of the memory circuit selection switch 215 is also based on a control signal from the vertical drive circuit 50 based on the control of the control unit 60.

  The second reset transistor 220 is a second reset element for initializing contribution capacitance in each capacitor element and circuit wiring by applying a second reset voltage (VRT2) to the capacitor element included in the memory circuit 210.

  The memory circuit 210 is a capacitor circuit that is connected to the output side of the first amplifier circuit 115 included in the pixel 110 and includes a plurality of capacitor elements.

[Operation of Pixel 110R and Memory Circuit 210R] Here, the operation flow of the pixel 110R and the memory circuit 210R will be briefly described. The operations of the pixel 110R and the memory circuit R are performed based on the control of the control unit 60 as already described. First, the control unit 60 operates the transfer gate 112 or the first reset transistor 114 of the pixel 110R at a predetermined timing to output a reset level or a signal level from the pixel 110R to the memory circuit 210.

  Further, the control unit 60 operates the selection switch 120 of the memory circuit 210R in accordance with the output timing from the pixel 110R, and similarly operates the reset level selection switch 213 or the signal level selection switch 214. As a result, the reset level or signal level is stored in the corresponding capacitive element.

  Further, the control unit 60 operates the memory circuit selection switch 215 and the reset level selection switch 213 or the signal level selection switch 214 of the memory circuit 210R at a predetermined timing. Accordingly, the reset level or the signal level is output to the gain amplifier 301 provided in the column signal processing unit 30 via the second amplifier circuit 221.

  Further, based on the control of the control unit 60, the second reset transistor 220 is operated at a predetermined timing. Specifically, the second reset voltage (VRT2) is applied to each capacitor of the memory circuit 210, and the charge accumulated in each capacitor is initialized.

  As described above, in the CMOS sensor 1, the control unit 60 controls the operation timing of each switch element, so that the overall initialization including the capacitive element, the output of the reset level based on the initialization, or the signal level Are controlled at a predetermined timing.

  The reset level and signal level output from the pixel 110 to the memory circuit 210 are required to be synchronized. That is, the reset level and the signal level are transferred from all the pixels 110 to the memory circuit 210. Therefore, the transfer (reset level and signal level) from the pixel 110 to the memory circuit 210 is based on the global shutter method.

  Note that simultaneity is unnecessary after the reset level and the signal level are accumulated in the memory circuit 210. Therefore, the operation is based on the rolling readout method so that the reset level and the signal level accumulated in each capacitor element are sequentially read out.

  According to the CMOS sensor 1 according to the present embodiment described above, the initialization is performed separately from the initialization for extracting the reset level at a timing different from the process of executing the accumulation and reading of the reset level and the signal level. Can be executed. Thereby, reset noise at the time of reading the reset level or signal level (during sampling) can be reduced, and a sufficient reset state can be secured. That is, it is possible to suppress deterioration in image quality.

  Further, according to the CMOS sensor 1 according to the present embodiment, the influence of the remaining component in the previous line cycle can be suppressed. This is because the initialization is executed before the reset level and the signal level sampling to prevent the remaining components from being mixed due to insufficient initialization.

  Further, according to the CMOS sensor 1 according to the present embodiment, all charges are accumulated by the capacitive element outside the pixel circuit, so that the capacity of the float diffusion region can be minimized. As a result, the influence of reset noise can be reduced without reducing the charge conversion efficiency.

Another Example of Configuration of Pixel 110 and Memory Circuit 210 Here, a CMOS sensor 1a according to another embodiment of the solid-state imaging device according to the present invention will be described. FIG. 4 is a circuit diagram showing a configuration of the pixel 110R and the memory circuit 210aR included in the CMOS sensor 1a. The description of the same configuration as that of the CMOS sensor 1 already described is omitted. In FIG. 4, the memory circuit 210aG corresponding to the G element and the memory circuit 210aB corresponding to the B element also have the same configuration as that of the memory circuit 210aR, and thus the description thereof is omitted.

  The memory circuit 210aR provided in the CMOS sensor 1a is provided with a common capacitive element without providing a capacitive element for a reset level and a capacitive element for a signal level, and this common capacitive element is stored and read out of a reset level and a signal level. It is comprised so that it may be used. In this case, the control unit 60 controls the timing of accumulation and writing of the reset level and the signal level in time series.

  The memory circuit 210a does not transfer and store the signal level or reset level from the pixel 110 until the reading of the reset level or signal level stored in the common capacitor 216 is completed. This is because if the capacitive elements for storing the reset level and the signal level are shared, the reset level and the signal level cannot be stored separately and simultaneously. Therefore, the CMOS sensor 1a is not suitable for high-speed processing, but has an effect in reducing the circuit area because the capacitance element can be halved.

First Control Method for Solid-State Imaging Device Next, an embodiment of a control method for the solid-state imaging device according to the present invention will be described. Here, a method for controlling the operation of the CMOS sensor 1 (see FIG. 3) already described will be described. FIG. 5 is a timing chart showing an example of a control method of the CMOS sensor 1. First, reference numerals used in the description will be described. The operation of the CMOS sensor 1 is divided into a pre-reset period, a memory global write period, and a memory rolling read period. The code indicating the pre-reset period is “A”, the code indicating the memory global write period is “B”, and the code indicating the memory rolling read period is “C”.

  The pre-reset period A is a period in which the entire elements (mainly capacitive elements) constituting the CMOS sensor 1 or a part of the elements are initialized. Initialization in the CMOS sensor 1 can also be performed in the memory global write period B. However, by providing the pre-reset period A, “initialization” can be performed independently of “reset” in other periods. Thereby, so-called reset noise can be reduced.

  The memory global writing period B is a period during which the reset level or signal level from the pixel 110 to the capacitor element of the memory circuit 210 is accumulated. The memory rolling read period C is a period during which the reset level or signal level stored in the capacitor element of the memory circuit 210 is read and output to the column signal processing unit 30.

  In FIG. 5, the symbol “RT1” indicates the operation timing of the first reset transistor 114. The symbol “TX” indicates the operation timing of the transfer gate 112. The symbol “SL” indicates the operation timing of the selection switch 120. The symbol “Sres” indicates the operation timing of the reset level selection switch 213. The symbol “Ssig” indicates the operation timing of the signal level selection switch 214. The symbol “RT2” indicates the operation timing of the second reset transistor 220. A symbol “SW” indicates an operation timing of the memory circuit selection switch 215.

  In each of the above symbols, in a section where the line segment indicating each timing chart is “Hi”, the corresponding switch and gate (see FIG. 3) operate to maintain the conductive state. That is, the element corresponding to each code is in an “on” state. In other sections, the switch and the gate do not operate and the non-conducting state is maintained. That is, the element corresponding to each code is in an “off” state.

  First, the pre-reset period A will be described. In the control method according to the present embodiment, the pre-reset period A is a period immediately before the memory global write period B. Therefore, the period from the pre-reset period A to the memory rolling read period C is a line period. In the conventional solid-state imaging device, there is no period corresponding to the pre-reset period A, and the memory global writing period B and the memory rolling reading period C are line cycles.

  In the pre-reset period A, the capacitor elements included in the pixel 110 and the memory circuit 210 are initialized. Therefore, first, the control unit 60 turns on the SW of the memory circuit 210 that is the target of subsequent memory global writing (time t1). Thereby, for example, the memory circuit selection switch 215 included in the memory circuit 210R operates. At time t1, both Sres and Ssig are turned on, and the reset level capacitor 211 and the signal level capacitor 212 included in the memory circuit 210 are made conductive. RT2 is already on.

  Accordingly, the second reset voltage (VRT2) is applied to the reset level capacitor 211 and the signal level capacitor 212 via the second reset transistor 220. As a result, the parasitic capacitance of the capacitive element and signal wiring of the memory circuit 210 is initialized by the second reset voltage (VRT2).

  In addition, the control unit 60 turns on RT1 between time t1 and time t2. At this time, the capacitance of the pixel 110 (FD region 113) and the parasitic capacitance of the signal wiring are initialized by the first reset voltage (VRT1).

  In the pre-reset period A, all of the parasitic capacitance and charge storage capacitance of the signal wiring can be reset. As a result, the CMOS sensor 1 eliminates the influence of the charges accumulated in the preceding line cycle, and outputs a signal based on the image data using a more accurate reset level and signal level.

  Next, the memory global write period B will be described. First, the control unit 60 turns on SL (time t2). Accordingly, the selection switch 120 is operated to determine the memory circuit 210 that performs charge writing. In addition, the control unit 60 turns on Sres at time t2, and then turns on RT1.

  As a result, the reset voltage (VRT1) of the pixel 110 is connected to the FD region 113, and the FD region 113 is initialized. At the same time, the reset level is accumulated in the reset level capacitor 211 via the first amplifier circuit 115, the selection switch 120, and the reset level selection switch 213. Thereafter, RT1 is turned off and Sres is turned off.

  In addition, after turning off Sres, the control unit 60 turns on Ssig, and subsequently turns on TX. As a result, the charge from the photodiode 111 of the pixel 110 is transferred to the FD region 113 via the transfer gate 112. At the same time, the signal level is accumulated in the signal level capacitor 212 via the first amplifier circuit 115, the selection switch 120, and the signal level selection switch 214. Thereafter, TX is turned off, Ssig is turned off, and SL is turned off at time t3 which is the cycle of the memory global write period B.

  From time t2 to time t3 described above, all the pixels 110 and the memory circuit 210 corresponding to the pixels 110 complete the accumulation (writing) of the reset level and the signal level in the capacitor. The process so far uses a global shutter system that performs electronic shutter control performed simultaneously in all the pixels 110 of the pixel array unit 10.

  Next, the memory rolling read period C will be described. After the control unit 60 turns off SL at time t3, it turns on SW and selects the corresponding memory circuit 210 (time t4). At the same time, the control unit 60 turns off RT2.

  Next, the control unit 60 turns on Sres (time t5). Thereafter, until the time t6, the reset level stored in the reset level capacitor 211 is read and output to the column signal processing unit 30 via the second amplifier circuit 221. When reading of the reset level is completed (time t6), RT2 is then turned on (time t7).

  Control unit 60 turns on RT2 until time t8. During this time, the input level of the second amplifier circuit 221 is initialized by the second reset voltage (VRT2). The controller 60 turns off RT2 again after a period (time t7 to time t7) necessary for initializing the input level of the second amplifier circuit 221 has elapsed. Subsequently, the control unit 60 turns on Ssig (time t9).

  While Ssig is on (until time t10), the signal level is read from the signal level capacitor 212. The read signal level is output to the column signal processing unit 30 via the second amplifier circuit 221. When the signal level reading is completed, the control unit 60 turns off Ssig (time t10).

  Thereafter, the control unit 60 turns on SW and turns on RT2 (time t11). Thereafter, the memory rolling read period C is performed until the start of the next pre-reset period A (time t12). With the above control, reading of the reset level and the signal level is completed. The read reset level and signal level are subjected to correlated double sampling (CDS) for extracting a difference. Note that the read order of the reset level and the signal level may be exactly the reverse of the above description.

  Thereafter, the control unit 60 turns on RT2 again (time t12). As a result, the input level of the second amplifier circuit 221 is initialized by the second reset voltage (VRT2). The above control is a rolling readout method because the reset level and the signal level relating to the plurality of pixels 110 are sequentially read out. The reason for performing the processing as described above is that more column circuits are required by simultaneously processing a plurality of pixels in parallel. From the viewpoint of circuit area, it is advantageous to use rolling readout that sequentially processes a plurality of pixels.

  In the above control, the start from the pre-reset period A (time t1) to the end of the memory rolling readout period C (time t12) are sequentially performed for all the pixels 110 in one line cycle. Accordingly, the reset level and the signal level can be accumulated and read out from the state in which the reset level and the signal level accumulated in the reset level capacitor 211 and the signal level capacitor 212 are sufficiently initialized.

  As described above, the CMOS sensor 1 includes a dedicated circuit (second reset transistor 220) for initializing the reset level capacitor 211 and the signal level capacitor 212. Further, the CMOS sensor 1 is provided with a “pre-reset period A” before the memory global write period B. During the pre-reset period A, the capacitor elements included in the pixel 110 and the memory circuit 210, the contribution capacitance of the circuit wiring, and the like can be initialized. Therefore, the influence of the residual signal in the preceding line cycle can be reduced when reading out in one line cycle.

Description of Effects According to this Embodiment It is advantageous that each of the reset level capacitor 211 and the signal level capacitor 212 has a larger capacitance value in consideration of capacitance variation and leakage of the capacitor element itself. However, if these capacitances are simply increased, there is a possibility that the influence of the residual charge that should have been read out in the previous process (previous line cycle) in which charges are stored may remain.

  That is, in the capacitive elements such as the reset level capacitor 211 and the signal level capacitor 212, the data at the previous processing timing cannot be sufficiently reset, which affects the reset level and the signal level stored at the next storage timing. This will adversely affect the image data output from the CMOS sensor 1.

  The CMOS sensor 1 is provided with a first reset transistor 114 for resetting the storage capacitor included in the pixel 110. This reset period is preferably a period sufficient to initialize parasitic capacitance components related to the FD region 113 and the first amplifier circuit 115. The reset process by the first reset transistor 114 can also be used for the capacitor element included in the memory circuit 210. However, in that case, it is necessary to take a long time for sufficient initialization.

  Therefore, the CMOS sensor 1 further includes a dedicated reset circuit (second reset transistor 220) used for initializing the memory circuit 210. The CMOS sensor 1 has a pre-reset period. Thus, the capacitor element included in the memory circuit 210 can be sufficiently initialized before the memory global write period B.

  The above-described effects in the CMOS sensor 1 are particularly exhibited in the following cases. This is particularly effective when the signal level difference is large depending on the line period, such as when a white level signal is handled in the previous line period and a black level signal is handled in the next line period.

  That is, as described above, when the difference in the signal level handled by the line period is large, there is a high possibility that sufficient initialization cannot be performed only by the normal reset process. In order to solve this problem, the CMOS sensor 1 executes a pre-reset that initializes the whole at a timing independent of normal initialization. That is, a pre-reset period A is provided. Thereby, a sufficient reset level at the time of memory writing can be secured.

Example of Reset Operation in FD Here, the relationship between initialization by the first reset transistor 114 and pre-reset will be described with reference to FIG. In FIG. 11, symbol RT <b> 1 indicates the operation timing of the first reset transistor 114. When RT1 is on, the first reset transistor 114 operates and a reset voltage (VRT1) is applied to the FD region 113. As a result, the FD area 113 is initialized.

  Reference numeral FD indicates an example of a reset level in the FD area 113. If the first reset transistor 114 is hard reset, the reset level of the FD region 113 should rise to the line of VRT1. However, when the history of the previous stage signal in FD is low as shown in FIG. 11, if the first reset transistor 114 is soft reset, the reset level of the FD region 113 is only increased to the level increased by the threshold value of the first reset transistor 114. Does not rise. In this case, if the tring time is insufficient, it is difficult to ensure a sufficient reset level.

  Therefore, the CMOS sensor 1 according to the present embodiment performs pre-reset before a period in which the reset level needs to be extracted. As a result, the reset level can be raised to a higher reset level with a minimum reset period. In addition, the dynamic range can be widened by raising the reset level.

  At the time of writing to the capacitor element included in the memory circuit 210, a large capacitor element is connected, so that reset noise that occurs during writing time and capacitor writing may occur. However, by initializing the capacitive element in the pre-reset period A, it is possible to minimize interference and noise generation caused by the residual in the previous line cycle of the next reset level writing and signal level writing. Can

Example of Reset Operation in Capacitance Element Here, an example of the relationship between initialization by the second reset transistor 220 and pre-reset in the control method according to the present embodiment will be described with reference to FIG. In FIG. 12, symbol SW indicates the operation of the memory circuit selection switch 215. Reference symbol RT2 indicates the operation of the second reset transistor 220. Symbol Ssig shows an example of the operation of the signal level selection switch 214.

  The code Csig illustrates the level when the signal level capacitor 212 is initialized and the level when the signal level is accumulated. The lower line of the symbol Csig represents the level when the signal level capacitor 212 is initialized in the pre-reset by the second reset transistor 220. The upper line of the symbol Ccig represents the level of the signal level capacitor 212 when the signal level is accumulated.

  As shown in FIG. 12, when Ssig is turned on after SW is turned on, the signal level stored in signal level capacitor 212 rises. In this case, as shown in FIG. 12, the initialization level of the signal level capacitor 212 may be set to the median value (DR / 2) of the dynamic range (DR) of the signal level. This may be the reset level. That is, if the median value of the dynamic range calculated based on the gain setting value is set to the reset level so as to be an intermediate value of the dynamic range of the signal level, efficient initialization can be performed.

  Note that the first reset level (VRT1) of the first reset transistor 114 and the second reset level (VRT2) of the second reset transistor 220 can be supplied from the outside, and can be set to arbitrary values. The dynamic range of the second reset level (VRT2) varies depending on the gain value to be selected. In this case, the control unit 60 controls the gain setting to switch the second reset level (VRT2) to an optimum value.

Second Control Method for Solid-State Imaging Device Next, another example of the control method for the CMOS sensor 1 according to the present embodiment will be described. Similar to the embodiment already described, the control method will be described based on the configuration of the CMOS sensor 1. The timing chart of FIG. 6 showing the control method according to the present embodiment has portions in common with the timing chart already described. Therefore, a part different from the timing chart already described will be described. Since the reference numerals used in FIG. 6 are the same as the reference numerals used in FIG.

  As shown in FIG. 6, in the present embodiment, the reset level capacitor 211 and the signal level capacitor 212 are not initialized in the pre-reset period A (from time t1 to time t2).

  In the present embodiment, the control in the memory global write period B is the same as that in the embodiment already described, and thus detailed description thereof is omitted (from time t2 to time t3).

  In the memory rolling read period C according to this embodiment, the control unit 60 first turns off RT2 and simultaneously turns on SW (time t4). Subsequently, the control unit 60 turns on Sres and reads the reset level (time t5).

  Subsequently, the control unit 60 turns on RT2 (time t6). When RT2 is turned on at time t6, the input level of the reset level capacitor 211 and the second amplifier circuit 221 is initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off Sres (time t7). Therefore, the reset level capacitor 211 is initialized between time t6 and time t7.

  Subsequently, the control unit 60 turns off RT2 (time t8), and then turns on Ssig (time t9). As a result, the signal level is read from the signal level capacitor 212. Subsequently, the control unit 60 turns on RT2 (t10).

  When RT2 is turned on at time t10, the input level of the signal level capacitor 212 and the second amplifier circuit 221 is initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off Ssig (time t11). Therefore, the signal level capacitor 212 is initialized between time t10 and time t11.

  As described above, the reset processing of the reset level capacitor 211 and the signal level capacitor 212 is performed in the memory rolling read period C. In this case, after the reset level and the signal level are read from the reset level capacitor 211 and the signal level capacitor 212, RT2 is turned on before Sres or Ssig is turned off. That is, before the connection between the reset level capacitor 211 and the second reset transistor 220 is disconnected, or before the connection between the signal level capacitor 212 and the second reset transistor 220 is disconnected, these capacitor elements are initialized.

  According to the control method of the CMOS sensor 1 described above, initialization similar to the initialization in the pre-reset period A already described can be performed at time t6 and time t10. In this case, the FD region 113 of the pixel 110 and the parasitic capacitance component between the pixel 110 and the capacitor element of the memory circuit 210 are to be initialized.

  Therefore, the initialization in the pre-reset period A and the initialization of the capacitor can be performed at the same time, so that the time required for initialization can be shortened compared to the case where the pre-reset period A is provided separately.

  As described above, according to the control method of the CMOS sensor 1 according to the present embodiment, the reset process in the pre-reset period A is not necessary. Therefore, reset noise can be reduced while reducing the overall time required for initialization.

Third Control Method for Solid-State Imaging Device Next, still another example of the control method for the CMOS sensor 1 according to this embodiment will be described. The timing chart of FIG. 7 showing the control method according to the present embodiment has parts in common with the timing charts already shown in FIGS. 5 and 6. Therefore, a part different from the timing chart already described will be described. Note that the reference numerals used in FIG. 7 are the same as those used in FIG. 5 and FIG.

  As shown in FIG. 7, also in the present embodiment, in the pre-reset period A, the reset level capacitor 211 and the signal level capacitor 212 are not initialized (from time t1 to time t2). Since the control in the memory global write period B is the same as in the embodiment already described, detailed description thereof is omitted (from time t2 to time t3).

  In the memory rolling read period C according to this embodiment, the control unit 60 first turns off RT2 and simultaneously turns on SW (time t4). Subsequently, the control unit 60 turns on Sres and reads the reset level (time t5).

  Subsequently, the control unit 60 turns Sres off and simultaneously turns RT2 on (time t6). Thereafter, the control unit 60 turns off RT2 (time t7). Thereafter, the control unit 60 turns on Ssig (time t8). As a result, the signal level is read from the signal level capacitor 212.

  Subsequently, the control unit 60 turns on RT2 while keeping Ssig on (time t9). At the same time, Sres is turned on. Accordingly, from time t9, the reset level capacitor 211, the signal level capacitor 212, and the input level of the second amplifier circuit 221 are initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off Sres, Ssig, and SW (time t10). Therefore, the reset level capacitor 211 and the signal level capacitor 212 are initialized simultaneously from time t9 to time t10.

  As described above, according to the control method of the CMOS sensor 1 according to the present embodiment, the initialization is simultaneously performed immediately after reading the reset level and the signal level. Thereby, the read interval between the reset level and the signal level can be shortened. Therefore, compared with the other embodiments already described, the transition to the CDS process executed in the subsequent stage can be accelerated.

Another Example of Reset Operation in Capacitance Element Here, another example of the relationship between the initialization by the second reset transistor 220 and the pro reset in the control method according to the present embodiment will be described with reference to FIG. In FIG. 13, symbol SW indicates the operation of the memory circuit selection switch 215. Reference symbol RT2 indicates the operation of the second reset transistor 220. Reference numeral Sres indicates an example of the operation of the reset level selection switch 213. Symbol Ssig shows an example of the operation of the signal level selection switch 214.

  The code Csig illustrates the level when the signal level is accumulated in the signal level capacitor 212. Symbol Cres represents a level when the signal level capacitor 212 is initialized in the pre-reset by the second reset transistor 220.

  When the signal level in all the pixels 110 included in the CMOS sensor 1 is the white level, the reset current for the signal level capacitor 212 has a large value due to the potential difference from the second reset voltage (VRT2). Therefore, as shown in FIG. 13, after the reset level and signal level are read, the reset level capacitor 211 and the signal level capacitor 212 that hold the reset level in the previous line cycle are short-circuited to each other.

  That is, the signal level stored in the signal level capacitor 212 is raised by capacitively coupling the reset level capacitor 211 and the signal level capacitor 212. As a result, the potential difference from the second reset voltage (VRT2) is reduced, and an excessive reset current can be prevented from flowing.

  Note that the level of the second reset voltage (VRT2) can be set to an optimum value for suppressing current concentration, considering that the reset level is always written as the capacity of the signal level capacitor 212. .

Fourth Control Method for Solid-State Imaging Device Next, still another example of the control method for the CMOS sensor 1 according to this embodiment will be described. The timing chart of FIG. 8 showing the control method according to the present embodiment has a part in common with the timing charts shown in FIGS. 5, 6 and 7 already described. Therefore, a part different from the timing chart already described will be described. Since the reference numerals used in FIG. 8 are the same as those used in FIG.

  As shown in FIG. 8, in the pre-reset period A, the control unit 60 turns on both Sres and Ssig. While maintaining this state, the control unit 60 turns the RT1 on and off. As a result, the first reset voltage (VRT1) is applied to the FD region 113 via the first reset transistor 114. Then, the first reset voltage (VRT1) initializes the reset level capacitor 211 and the signal level capacitor 212 via the first amplifier circuit 115.

  Also, as shown in FIG. 8, the control in the memory global write period B according to the present embodiment is the same as that in the embodiment already described, and thus detailed description is omitted (from time t2 to time t3).

  In the memory rolling read period C according to the present embodiment, the control unit 60 first turns off RT2 and turns on SW (time t4). Subsequently, Sres is turned on (time t5). As a result, the reset level is read out and output to the column signal processing unit 30 via the second amplifier circuit 221.

  Next, the control unit 60 turns off RTs and simultaneously turns on RT2 (time t6). As a result, the input node of the second amplifier circuit 221 is initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off RT2 (time t7).

  Next, the control unit 60 turns on Ssig (time t8). As a result, the signal level is read out and output to the column signal processing unit 30 via the second amplifier circuit 221. Subsequently, the control unit 60 turns off Ssig, turns on RT2, and turns off SW (time t9).

  As described above, in the control method according to this embodiment, the capacitor element included in the memory circuit 210 is initialized using the reset level of the pixel 110 from the first reset transistor 114 of the pixel 110 via the first amplifier circuit 115. Do it. The initialization of the input node of the second amplifier circuit 221 is performed using the second reset voltage (VRT2) via the second reset transistor 220.

  That is, in this embodiment, the initial values of the capacitive elements (reset level capacitor 211 and signal level capacitor 212) included in the memory circuit 210 can be set to the reset level of the pixel 110. As a result, the initial state of the reset level writing and the signal level writing in the next line cycle is the reset level of the pixel 110, which is an optimum value as the initial state at the time of writing.

Next, yet another example of the control method of the CMOS sensor 1 according to the present embodiment will be described. The timing chart of FIG. 9 showing the control method according to the present embodiment has a part in common with the timing chart shown in FIG. Therefore, a part different from the timing chart already described will be described. Note that the reference numerals used in FIG. 9 are the same as the reference numerals used in FIG.

  As shown in FIG. 9, in the pre-reset period A, RT1 is turned on and off while only Sres is turned on and maintained. As a result, the first reset voltage (VRT1) is applied to the FD region 113 via the first reset transistor 114. Then, the first reset voltage (VRT1) initializes the reset level capacitor 211 via the first amplifier circuit 115.

  Further, as shown in FIG. 9, the control in the memory global write period B according to the present embodiment is the same as that of the embodiment already described, and thus detailed description is omitted (from time t2 to time t3).

  In the memory rolling read period C according to this embodiment, the control unit 60 first turns off RT2 and simultaneously turns on SW (time t4). Subsequently, the control unit 60 turns on Sres and reads the reset level (time t5).

  Subsequently, the control unit 60 turns Sres off and simultaneously turns RT2 on (time t6). Thereafter, the control unit 60 turns off RT2 (time t7). Thereafter, the control unit 60 turns on Ssig (time t8). As a result, the signal level is read from the signal level capacitor 212.

  Subsequently, the control unit 60 turns on RT2 while keeping Ssig on (time t9). Therefore, from time t9, the input level of the signal level capacitor 212 and the second amplifier circuit 221 is initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off Sres, Ssig, and SW (time t10). Therefore, the signal level capacitor 212 is initialized at the same time from time t9 to time t10.

  The control method according to the present embodiment controls the reset level capacitor 211 to be initialized by the first reset transistor 114 and the signal level capacitor 212 to be initialized by the second reset transistor 220. In the control method according to the present embodiment, the signal level can be adjusted to the initial value of the signal level capacitor 212 near the center of the dynamic range. That is, an initial value can be set according to the use for each of the reset level and the signal level.

[Sixth Control Method of Solid-State Imaging Device] Next, an example of a control method related to the CMOS sensor 1a already described will be described with reference to a timing chart shown in FIG. As already described, in the CMOS sensor 1a, the capacitive element that accumulates the reset level and the signal level is configured by a single capacitive element. That is, it is necessary to write and read the reset level and the signal level with respect to a single capacitive element in time series.

  Therefore, in the control method according to the present embodiment, as shown in FIG. Thereafter, the signal level writing period D2 is started, and subsequently, the memory rolling reading period C is started again.

  First, the controller 60 turns on RT1 in the pre-reset period A from time t1 to time t2. As a result, the FD region 113 is initialized by the action of the first reset transistor 114. In the CMOS sensor 1 a, writing control to the common capacitor 216 is performed by the selection switch 120. Therefore, when the SL is turned on, writing to the common capacitor 216 is performed (time t2). While SL is on, the reset level is accumulated in the common capacitor 216 and initialized (from time t2 to time t3).

  Next, in the memory rolling read period C (from time t3 to time t8), the control unit 60 first turns off RT2 (time t4). This corresponds to preprocessing for extracting the reset level from the common capacitor 216. Subsequently, the control unit 60 turns on the SW (time t5). As a result, the reset level is read from the common capacitor 216 of the target memory circuit 210.

  Subsequently, the control unit 60 turns on RT2 (time t6). As a result, the common capacitor 216 is initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off the SW (time t7). As a result, the selection of the target memory circuit 210a is released.

  Subsequently, in the signal level writing period D2 (from time t8 to time t9), the control unit 60 turns on SL and maintains TX in the state, and turns on TX. As a result, charges are transferred from the photodiode 111 to the FD region 113, and a signal level is accumulated in the common capacitor 216 via the first amplifier circuit 115.

  Subsequently, in the memory rolling read period C after time t9, RT2 is turned off (time t10), SW is turned on (time t11), and stored in the common capacitor 216 of the target memory circuit 210. Read the signal level. Subsequently, the control unit 60 turns on RT2 (time t12). Thereby, the common capacitor 216 is initialized by the second reset voltage (VRT2). Subsequently, the control unit 60 turns off the SW (time t13). As a result, the selection of the target memory circuit 210a is released.

  By completing the above control within one line cycle, data transfer for one line is completed. Note that the control in the pre-reset period A according to the present embodiment is similar to the control method described with reference to FIG. 6, but is not limited thereto. In the present embodiment, the common capacitor 216 may be initialized during the pre-reset period A. In that case, it is necessary to provide a period for initializing the common capacitor 216 before writing the signal level.

  Next, an embodiment of an image reading apparatus according to the present invention will be described. FIG. 14 is a perspective view showing an external appearance of an MFP (Multi Function Printer) 1000 according to the present embodiment. The MFP 1000 is a multifunction machine that can be used as a printer, a facsimile machine, a scanner, and a copying machine. The MFP 1000 includes a solid-state imaging device for reading a document placed on a document table.

  In the MFP 1000, each embodiment (CMOS sensor 1 or the like) related to the solid-state imaging device according to the present invention described above can be used. In this case, the image on the document can be read by repeating the scanning in the sub-scanning direction while moving the CMOS sensor 1 relative to the document in the main scanning direction.

  As a result, an image reading apparatus with less noise and good reading accuracy can be obtained.

DESCRIPTION OF SYMBOLS 1 CMOS sensor 10 Pixel array part 20 Memory array part 30 Column signal processing part 40 Horizontal drive circuit 50 Vertical drive circuit 60 Control part 110 Pixel 114 1st reset transistor 210 Memory circuit 211 Reset level capacity | capacitance 212 Signal level capacity | capacitance switch 215 Memory circuit selection switch 220 Second reset transistor

JP 2010-219974 A

Claims (10)

A photoelectric conversion element that generates charge in response to incident light, a transfer element that transfers the charge to a floating diffusion region, a first amplification element that amplifies and outputs the charge transferred to the floating diffusion region, and the floating diffusion region And a pixel circuit including a first reset element that initializes the photoelectric conversion element;
A capacitor circuit connected to the output side of the first amplifying element and including a capacitor element that accumulates a reset level and a signal level of the pixel circuit;
A control circuit for controlling operations of the pixel circuit and the capacitor circuit;
With
The control circuit performs initialization by the first reset element before the reset level is accumulated in the capacitor element;
A solid-state imaging device. The capacitive circuit includes a second reset element that initializes the capacitive element,
The control circuit performs initialization by the second reset element before the reset level is accumulated in the capacitor element;
The solid-state imaging device according to claim 1. The capacitive circuit includes a second reset element that initializes the capacitive element,
The control circuit executes initialization by the second reset element after the readout of the reset level and the signal level accumulated in the capacitive element is completed.
The solid-state imaging device according to claim 1. The capacitive circuit includes a second reset element that initializes the capacitive element,
The control circuit, after the read of the reset level and the signal level from the capacitive element is completed, short-circuit the capacitive elements to each other and capacitively coupled, and then perform initialization by the second reset element.
The solid-state imaging device according to claim 1. The capacitive circuit includes a second reset element that initializes the capacitive element,
The control circuit executes initialization of the capacitive element by the second reset element simultaneously with initialization by the first reset element;
The solid-state imaging device according to claim 1. The control circuit sets an initialization level in the first reset element or an initialization level in the second reset element to an arbitrary value.
The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided. The control circuit is set so that an initialization level in the second reset element is an intermediate value of a dynamic range related to the photoelectric conversion element,
The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided. The control circuit executes initialization by the first reset element for the capacitive element in which the reset level or the signal level is accumulated.
The solid-state imaging device according to claim 1. The control circuit performs initialization by the second reset element with respect to the capacitive element for the reset level or the signal level.
The solid-state imaging device according to claim 2.   An image reading apparatus comprising the solid-state imaging device according to claim 1.