JP2017152643A - Electronic apparatus and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a contact resistance between an ohmic electrode and a graphene layer.SOLUTION: An electronic apparatus is provided, which includes a graphene layer 12 disposed on a substrate 10, and an ohmic electrode 25 containing nickel disposed on the graphene layer 12. A ratio of a nickel-carbon bond to a carbon-carbon bond on a surface of the graphene layer 12 where the ohmic electrode 25 is in contact with is 30% or more.SELECTED DRAWING: Figure 1D

Description

  The present invention relates to an electronic device and a manufacturing method thereof, for example, an electronic device having a graphene layer and a manufacturing method thereof.

  Graphene is a carbon material in which a six-membered ring formed by carbon is formed into a sheet. Graphene has very high electron mobility. Thus, a transistor using graphene as a channel is known (Patent Document 1).

JP 2011-192667 A

  In an electronic device such as a transistor, an ohmic electrode is formed on a graphene layer. However, the contact resistance between the ohmic electrode and the graphene layer is increased.

  This invention is made | formed in view of the said subject, and it aims at reducing the contact resistance of an ohmic electrode and a graphene layer.

  The present invention comprises a graphene layer provided on a substrate and an ohmic electrode including nickel provided on the graphene layer, and a carbon-carbon bond on a surface of the graphene layer in contact with the ohmic electrode The electronic device has a ratio of nickel-carbon bonds to 30% or more.

  The present invention includes a step of forming a graphene layer on a substrate, a step of performing ultraviolet ozone treatment or oxygen ashing treatment on the surface of the graphene layer, and the surface of the graphene layer subjected to the ultraviolet ozone treatment or oxygen ashing treatment. Forming an ohmic electrode containing nickel in the electronic device.

  The present invention includes a step of forming a graphene layer on a substrate, a step of performing a surface treatment on the surface of the graphene layer, and a step of forming an ohmic electrode containing nickel on the surface-treated surface of the graphene layer And the surface treatment is such that the ratio of nickel-carbon bonds to carbon-carbon bonds on the surface of the graphene layer in contact with the ohmic electrode is 30% or more after the ohmic electrode is formed. This is a method of manufacturing an electronic device that is a serious process.

  According to the present invention, the contact resistance between the ohmic electrode and the graphene layer can be reduced.

FIG. 1A is a sectional view (No. 1) illustrating the method for manufacturing the electronic device according to the first embodiment. FIG. 1B is a cross-sectional view (part 2) illustrating the method of manufacturing the electronic device according to the first embodiment. FIG. 1C is a cross-sectional view (part 3) illustrating the method for manufacturing the electronic device according to the first embodiment. FIG. 1D is a sectional view (No. 4) illustrating the method for manufacturing the electronic device according to the first embodiment. FIG. 2 is a cross-sectional view showing a method for analyzing a sample produced in Example 1. FIG. 3A is a diagram showing an evaluation result of the sample A using hard X-ray photoelectron spectroscopy. FIG. 3B is a diagram illustrating an evaluation result of the sample B using hard X-ray photoelectron spectroscopy. FIG. 4A is a diagram showing an evaluation result using a hard X-ray photoelectron spectroscopy in sample C. FIG. FIG. 4B is a diagram showing an evaluation result using a hard X-ray photoelectron spectroscopy in sample D. FIG. 5 is a diagram showing electrical resistance with respect to Ni ₃ C / sp ₂ . FIG. 6A is a cross-sectional view (part 1) illustrating the method of manufacturing the FET according to the second embodiment. FIG. 6B is a sectional view (No. 2) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 6C is a cross-sectional view (part 3) illustrating the method of manufacturing the FET according to the second embodiment. FIG. 6D is a cross-sectional view (part 4) illustrating the method of manufacturing the FET according to the second embodiment. FIG. 7A is a cross-sectional view (part 5) illustrating the method of manufacturing the FET according to the second embodiment. 7B is a sectional view (No. 6) showing the method for manufacturing the FET according to Embodiment 2. FIG. FIG. 7C is a sectional view (No. 7) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 7D is a sectional view (No. 8) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 8A is a sectional view (No. 9) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 8B is a cross-sectional view (part 10) illustrating the method of manufacturing the FET according to the second embodiment. FIG. 8C is a cross-sectional view (No. 11) illustrating the method for manufacturing the FET according to the second embodiment. FIG. 8D is a sectional view (No. 12) illustrating the method for manufacturing the FET according to the second embodiment.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
The present invention comprises a graphene layer provided on a substrate and an ohmic electrode including nickel provided on the graphene layer, and a carbon-carbon bond on a surface of the graphene layer in contact with the ohmic electrode The electronic device has a ratio of nickel-carbon bonds to 30% or more. Since the ratio of nickel-carbon bonds to carbon-carbon bonds is 30% or more, the amount of bonds between the ohmic layer and the graphene layer increases. Therefore, the contact resistance between the ohmic electrode and the graphene layer can be reduced.

  The ohmic electrode preferably includes a nickel layer in contact with the graphene layer. This increases the amount of bonding between the nickel layer and the graphene layer. Therefore, the contact resistance between the nickel layer and the graphene layer can be reduced.

  It is preferable that the gate electrode provided on the graphene layer is provided, and the ohmic electrode includes a source electrode and a drain electrode sandwiching the gate electrode. Thus, a transistor having a graphene layer as a channel can be formed.

  The present invention includes a step of forming a graphene layer on a substrate, a step of performing ultraviolet ozone treatment or oxygen ashing treatment on the surface of the graphene layer, and the surface of the graphene layer subjected to the ultraviolet ozone treatment or oxygen ashing treatment. Forming an ohmic electrode containing nickel in the electronic device. By performing ultraviolet ozone treatment or oxygen ashing treatment on the surface of the graphene layer, the bond between oxygen atoms and carbon atoms on the surface of the graphene layer can be cut. Therefore, when an ohmic electrode is formed on the surface of the graphene layer, the amount of bonding between nickel and carbon can be increased.

  The step of performing the ultraviolet ozone treatment or the oxygen ashing treatment preferably includes a step of performing the ultraviolet ozone treatment. Thereby, the bond between the oxygen atom and the carbon atom on the surface of the graphene layer can be cut.

  Forming a mask having an opening exposing the surface of the graphene layer on the graphene layer, and performing the ultraviolet ozone treatment or oxygen ashing treatment on the surface of the graphene layer through the opening It is preferable to include a step of performing ultraviolet ozone treatment or oxygen ashing treatment.

  A step of forming a gate electrode on the graphene layer, and in the step of performing the ultraviolet ozone treatment or the oxygen ashing treatment, a region of the surface of the graphene layer in which the gate electrode is formed includes the ultraviolet ozone treatment or oxygen It is preferable not to perform the ashing process. Thereby, deterioration of the graphene layer under the gate electrode is suppressed.

  The present invention includes a step of forming a graphene layer on a substrate, a step of performing a surface treatment on the surface of the graphene layer, and a step of forming an ohmic electrode containing nickel on the surface-treated surface of the graphene layer And the surface treatment is such that the ratio of nickel-carbon bonds to carbon-carbon bonds on the surface of the graphene layer in contact with the ohmic electrode is 30% or more after the ohmic electrode is formed. This is a method of manufacturing an electronic device that is a serious process. Thereby, the contact resistance between the ohmic electrode and the graphene layer can be reduced.

[Details of the embodiment of the present invention]

  Specific examples of the semiconductor device according to the embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to a claim are included.

An ohmic electrode was formed on the graphene layer, and the contact resistance between the ohmic electrode and the graphene layer was evaluated. 1A to 1D are cross-sectional views illustrating the method for manufacturing the electronic device according to the first embodiment. As shown in FIG. 1A, the surface of the 6H—SiC substrate 10 is cleaned. Washing conditions are 5 minutes for acetone treatment, 5 minutes for ethanol treatment, and 5 minutes for water washing. As shown in FIG. 1B, a graphene layer 12 is formed on a substrate 10 by using a thermal sublimation method. The SiC substrate 10 is heat-treated at 1600 ° C. for 1 minute in an Ar atmosphere. Thereby, a graphene layer 12 having a film thickness of 0.35 nm to 0.7 nm is formed on the substrate 10. Thus, by heat-treating SiC, Si atoms in SiC substrate 10 are sublimated, and C atoms are sp ₂ bonded together. Thereby, the graphene layer 12 is formed from SiC.

As shown in FIG. 1C, the surface of the graphene layer 12 is treated with ultraviolet (UV) ozone (O ₃ ). The ultraviolet ozone treatment is, for example, the following surface treatment. Ozone is generated by irradiating oxygen (O ₂ ) with ultraviolet rays having a wavelength of about 185 nm. Further, active oxygen is generated by irradiating ozone with ultraviolet rays of about 254 nm. When the surface of the object is exposed to the generated ozone and active oxygen, the surface of the object is altered. The UV light source was a high-pressure mercury lamp. The flow rate of oxygen gas is 10 sccm.

  As shown in FIG. 1D, an ohmic electrode 25 is formed on the surface of the graphene layer 12 subjected to ultraviolet ozone treatment. The ohmic electrode 25 includes a nickel (Ni) layer 25a having a thickness of about 5 nm formed on the graphene layer 12 and a gold (Au) layer 25b having a thickness of about 5 nm formed on the nickel layer 25a. The ohmic electrode 25 is formed by a vapor deposition method. The nickel layer 25a is a layer for making electrical contact with the graphene layer 12, and the gold layer 25b is a layer for suppressing oxidation of the nickel layer 25a.

  Samples were produced in which the time of ultraviolet ozone treatment in FIG. 1C was changed. The bonding state of the interface between the graphene layer 12 and the ohmic electrode 25 of the prepared sample was analyzed by a hard X-ray photoelectron spectroscopy (SP) -8 (Super Photon ring-8 GeV) method. .

  FIG. 2 is a cross-sectional view showing a method for analyzing a sample produced in Example 1. As shown in FIG. 2, the sample of FIG. 1D is prepared. An X-ray 60 having an energy of 8 keV is irradiated from above the ohmic electrode 25. Photoelectrons 62 from the sample are detected. Photoelectron detection angle (TOA: Take Off Angle) makes it possible to evaluate the bonding state of the buried interface. The TOA was set to detect photoelectrons from the interface between the ohmic electrode 25 and the graphene layer 12.

表１に示すように、サンプルＡは、紫外線オゾン処理を行なっていない。サンプルＢからサンプルＤの紫外線オゾン処理の処理時間は２分、５分および１０分である。 Table 1 is a table showing the time of ultraviolet ozone treatment, Ni ₃ C / sp ₂ and CO / sp ₂ for each sample.

As shown in Table 1, sample A is not subjected to ultraviolet ozone treatment. The treatment times of the ultraviolet ozone treatment of Sample B to Sample D are 2 minutes, 5 minutes, and 10 minutes.

FIGS. 3A to 4B are diagrams showing evaluation results using hard X-ray photoelectron spectroscopy in samples A to D. FIGS. The horizontal axis represents the binding energy, and the vertical axis represents the signal intensity. 3A to 4B, black circles indicate measurement points, solid lines indicate approximate lines, and dotted lines are lines obtained by separating the solid lines into Gaussian curves for each connection. CO represents a bond between carbon (C) atoms and oxygen (O) atoms on the surface of the graphene layer 12. sp ₂ represents an sp ₂ bond between carbon atoms in the graphene layer 12. Ni ₃ C represents a bond between a carbon atom of the graphene layer 12 and a nickel atom of the ohmic electrode 25. SiC indicates a bond between silicon (Si) atoms and carbon atoms in the substrate 10. The amount of coupling is proportional to the area of each Gaussian curve.

In Table 1, Ni ₃ C / sp ₂ represents the ratio of the area of the Ni ₃ C signal curve to the area of the signal curve of sp ₂ , and represents the ratio of the nickel-carbon bond to the carbon-carbon bond. CO / sp ₂ indicates the ratio of the area of the signal curve of CO to the area of the signal curve of sp ₂ and indicates the ratio of oxygen-carbon bonds to carbon-carbon bonds.

As shown in Table 1 and FIGS. 3A to 4B, in sample A, Ni ₃ C / sp ₂ and CO / sp ₂ are 28.3% and 31.8%, respectively. In sample B, Ni ₃ C / sp ₂ and CO / sp ₂ are 32.3% and 23.7%, respectively. In sample C, Ni ₃ C / sp ₂ and CO / sp ₂ are 58.2% and 24.1%, respectively. In sample D, Ni ₃ C / sp ₂ and CO / sp ₂ are 57.5% and 12.8%, respectively.

  As shown in FIG. 3A, when the ultraviolet ozone treatment is not performed, carbon atoms and oxygen atoms on the surface of the graphene layer 12 are bonded in the state shown in FIG. 1B. In this state, when the nickel layer 25a is formed on the graphene layer 12 as shown in FIG. 1D, it is considered that carbon atoms to which oxygen atoms on the surface of the graphene layer 12 are bonded are not easily bonded to nickel atoms.

As shown in FIG. 3B to FIG. 4B, the time of the ultraviolet ozone treatment becomes longer. Ni ₃ C bonds increase and CO bonds decrease. This is because the bond between the carbon atom and the oxygen atom on the surface of the graphene layer 12 is cut by the ultraviolet ozone treatment in FIG. 1C. Thereafter, as shown in FIG. 1D, it is considered that the carbon layer and the nickel atom are bonded by forming the nickel layer 25 a on the graphene layer 12.

FIG. 5 is a diagram showing electrical resistance with respect to Ni ₃ C / sp ₂ . The horizontal axis represents Ni ₃ C / sp ₂ evaluated using hard X-ray photoelectron spectroscopy. The vertical axis represents the electrical resistance measured using a sample prepared under the same conditions as the sample evaluated for Ni ₃ C / sp ₂ . The electrical resistance corresponds to the contact resistance measured using TLM (Transfer Length Method). In FIG. 5, black circles indicate measurement points, and dotted lines indicate approximate lines. The broken line is a straight line having an electric resistance of 500Ω.

As shown in FIG. 5, when Ni ₃ C / sp ₂ increases, the electrical resistance decreases. This is presumably because the amount of bonds between nickel atoms in the nickel layer 25a and carbon atoms in the graphene layer 12 increases. When Ni ₃ C / sp ₂ is 30% or more, the electric resistance can be 500Ω or less. When Ni ₃ C / sp ₂ is 40% or more, the electric resistance can be 50Ω or less, and when Ni ₃ C / sp ₂ is 50% or more, the electric resistance can be 10Ω or less.

  The second embodiment is an example in which the first embodiment is applied to a field effect transistor (FET). 6A to 8D are cross-sectional views illustrating the method of manufacturing the FET according to the second embodiment. As shown in FIG. 6A, a substrate 10 is prepared as in FIG. 1A. As the cleaning of the substrate 10, for example, an RCA process may be performed. The substrate 10 may be a Si substrate on which a SiC layer is formed. When the graphene layer 12 is formed using the SiC thermal sublimation method, the uppermost surface of the substrate 10 is an SiC layer. For example, when the graphene layer 12 is formed using a CVD (Chemical Vapor Deposition) method, the outermost surface of the substrate 10 may be a material layer other than SiC. Similarly to FIG. 1B, the graphene layer 12 is formed on the substrate 10 by using a thermal sublimation method. The heat treatment atmosphere, the heat treatment temperature, and the heat treatment time can be appropriately set according to the film thickness and film quality of the graphene layer 12. For example, the heat treatment atmosphere can be a vacuum. In order to make the graphene layer 12 thin, heat treatment in an inert gas that slows the growth rate is preferable. For example, the CVD method can be used to form the graphene layer 12.

As shown in FIG. 6B, an Al (aluminum) film 15 having a film thickness of 5 nm is formed on the graphene layer 12 by vapor deposition. The Al film 15 can be formed by using, for example, a sputtering method. As shown in FIG. 6C, the Al film 15 is exposed to the atmosphere for 24 hours, for example. As a result, the Al film 15 is naturally oxidized, and an aluminum oxide (Al ₂ O ₃ ) film 16 is formed on the graphene layer 12. As the film in contact with the graphene layer 12 in the gate insulating film 14, an aluminum oxide film obtained by oxidizing an Al film by a method other than natural oxidation, an aluminum oxide film formed by a method other than oxidation, or a film other than an aluminum oxide film is used. May be.

  As shown in FIG. 6D, a photoresist 50 is applied on the aluminum oxide film 16. The photoresist 50 is exposed and developed. As a result, the photoresist 50 on the active region remains, and the photoresist 50 in the non-active region is removed. The aluminum oxide film 16 is removed by an alkaline developer for developing the photoresist 50. Further, the graphene layer 12 is removed using the photoresist 50 as a mask. Oxygen plasma is used to remove the graphene layer 12. The conditions for removing the graphene layer 12 are a pressure of 4 Pa and a power of 200 W. Thereafter, the photoresist 50 is removed.

  As shown in FIG. 7A, a silicon oxide film 18 having a thickness of 30 nm is formed on the substrate 10 using a CVD method so as to cover the aluminum oxide film 16. The silicon oxide film 18 is a film for thickening the gate insulating film 14. It is difficult to form a thick aluminum oxide film 16 with good film quality. On the other hand, the gate insulating film 14 is preferably thick in order to prevent contact with the ohmic electrode 25 and the gate electrode 20. Therefore, a silicon oxide film 18 is formed on the aluminum oxide film 16. A film other than the silicon oxide film 18 may be used as such a film, but the silicon oxide film 18 is preferable as an insulating film having a low dielectric constant and easy to form.

  As shown in FIG. 7B, a gate electrode 20 is formed on the silicon oxide film 18 by vapor deposition and lift-off. The gate electrode 20 is, for example, a Ti (titanium) film having a thickness of 10 nm and a gold film having a thickness of 100 nm from the gate insulating film 14 side. The gate electrode 20 may be formed using, for example, a sputtering method. As the gate electrode 20, a film other than the gold film may be used. A material having a low resistivity is preferable from the viewpoint of suppression of gate resistance.

  As shown in FIG. 7C, the silicon oxide film 18 and the aluminum oxide film 16 are removed using a dry etching method. Thereby, the gate insulating film 14 is formed from the aluminum oxide film 16 and the silicon oxide film 18.

  As shown in FIG. 7D, the side surface of the silicon oxide film 18 is etched using a buffered hydrofluoric acid solution. At this time, the side surface of the aluminum oxide film 16 is also etched. Thereby, the gate insulating film 14 becomes thinner than the gate electrode 20. Thus, the gate insulating film 14 and the gate electrode 20 are formed in a bowl shape. Thereby, when the ohmic electrode 25 including the source electrode 24 and the drain electrode 26 is formed, a short circuit between the ohmic electrode 25 and the gate electrode 20 can be suppressed.

  As shown in FIG. 8A, a mask layer 52 is formed on the substrate 10. The mask layer 52 is, for example, a photoresist layer, and has an opening 54 through which the surface of the graphene layer 12 is exposed. As shown in FIG. 8B, the opening 54 is subjected to ultraviolet ozone treatment on the surface of the starting graphene layer 12. The conditions of the ultraviolet ozone treatment are, for example, an oxygen flow rate of 10 sccm and a treatment time of 5 minutes. The processing conditions can be appropriately selected within a range where the effect can be obtained. The ultraviolet ozone treatment may be a treatment in which at least one of ozone and active oxygen generated by irradiating the oxygen gas with ultraviolet rays touches the surface of the graphene layer 12.

  In addition to ultraviolet ozone treatment, oxygen ashing treatment can be performed. The oxygen ashing treatment is a surface treatment in which oxygen plasma is generated by applying high-frequency power to oxygen gas, and the surface of the object (graphene layer 12) is exposed to the generated oxygen plasma. When the graphene layer 12 is exposed to high energy oxygen plasma, the graphene layer 12 is etched. Therefore, it is preferable to expose the surface of the graphene layer 12 to oxygen plasma with low energy and / or low density so that the oxygen-carbon bond is cut and the carbon-carbon bond is not cut. The oxygen ashing treatment time is 5 minutes. The processing conditions can be appropriately selected within a range where the effect can be obtained.

  As shown in FIG. 8C, an ohmic electrode 25 including a source electrode 24 and a drain electrode 26 is formed in a self-aligned manner with the gate electrode 20 by using an evaporation method. The ohmic electrode 25 is a nickel layer having a thickness of 15 nm. The planetary method is used for vapor deposition. The mask layer 52 and the metal layer on the mask layer 52 are removed using a lift-off method. Thereby, the ohmic electrode 25 can be formed so that the upper surface of the graphene layer 12 is not exposed between the gate insulating film 14 and the gate insulating film 14. The gate insulating film 14 is formed in a bowl shape, and the gate insulating film 14 is thicker than the ohmic electrode 25. Thereby, the short circuit with the ohmic electrode 25 and the gate electrode 20 can be suppressed. The ohmic electrode 25 may include a gold layer on the nickel layer.

  A pad 30 is formed on the source electrode 24 and the drain electrode 26 by vapor deposition and lift-off. The pad 30 is a titanium film having a thickness of 10 nm and a gold film having a thickness of 100 nm from the source electrode 24 and drain electrode 26 sides. Thereby, the FET of Example 2 is completed.

  Although the example in which the ohmic electrode 25 is formed after the gate electrode 20 is formed on the graphene layer 12 has been described as illustrated in FIGS. 7B to 8D, the gate electrode 20 is formed after the ohmic electrode 25 is formed on the graphene layer 12. May be formed.

  According to Examples 1 and 2, the ratio of the nickel-carbon bond to the carbon-carbon bond on the surface of the graphene layer 12 with which the ohmic electrode 25 containing nickel is in contact is 30% or more. Thereby, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced as shown in FIG. The ratio of nickel-carbon bond to carbon-carbon bond is preferably 40% or more, and more preferably 50% or more. Since it is difficult to make all the atoms bonded to carbon atoms nickel, the ratio of nickel-carbon bonds to carbon-carbon bonds is preferably 70% or less, and more preferably 60% or less.

  The ohmic electrode 25 may include nickel, but preferably includes a nickel layer 25a in contact with the graphene layer 12 as illustrated in FIG. 1D. Thereby, the contact resistance between the nickel layer 25a and the graphene layer 12 can be further reduced.

  As illustrated in FIG. 8D, the gate electrode 20 is provided on the graphene layer 12. The source electrode 24 and the drain electrode 26 are provided on the graphene layer 12 so as to sandwich the gate electrode 20. Thereby, an FET having the graphene layer 12 as a channel can be formed.

  As a method of setting the ratio of nickel-carbon bonds to carbon-carbon bonds on the surface of the graphene layer 12 to 30% or more, as shown in FIGS. 1C and 8B, the surface of the graphene layer 12 is subjected to ultraviolet ozone treatment or oxygen ashing treatment. Do. Thereby, the bond between the oxygen atom and the carbon atom on the surface of the graphene layer 12 is cut. As shown in FIGS. 1D and 8C, the ohmic electrode 25 is formed on the surface of the graphene layer 12 that has been subjected to the ultraviolet ozone treatment or the oxygen ashing treatment. Thereby, the bond of the unbonded carbon atom on the surface of the graphene layer 12 is bonded to the nickel atom. This increases the nickel-carbon bond ratio. Therefore, the contact resistance between the ohmic electrode 25 and the graphene layer 12 can be reduced.

  The surface treatment in FIG. 8B may be an oxygen ashing treatment, but an ultraviolet ozone treatment is preferable so that the graphene layer 12 is not removed.

  As shown in FIG. 8A, a mask layer 52 having an opening 54 through which the surface of the graphene layer 12 is exposed is formed on the graphene layer 12. As shown in FIG. 8B, the surface of the graphene layer 12 is subjected to ultraviolet ozone treatment or oxygen ashing treatment through the opening 54. Thereby, the desired surface of the graphene layer 12 can be subjected to ultraviolet ozone treatment or oxygen ashing treatment.

  As shown in FIG. 8B, in the step of performing ultraviolet ozone treatment or oxygen ashing treatment, it is preferable not to perform ultraviolet ozone treatment or oxygen ashing treatment on the region of the graphene layer 12 where the gate electrode 20 is formed. Thereby, deterioration of the graphene layer under the gate electrode 20 is suppressed.

  The film thickness of the graphene layer 12 is preferably 0.35 nm or more in order to obtain a film thickness of one atomic layer or more. The thickness of the graphene layer 12 is preferably 3.5 nm or less in order to have a thickness of 10 atomic layers or less. The thickness of the nickel layer of the ohmic electrode 25 is preferably 2 nm or more, and preferably 50 nm or less. The ohmic electrode 25 may be a nickel layer alone or may include a metal layer having a lower resistivity than the nickel layer, such as a gold layer or an aluminum layer, on the nickel layer. Although the FET has been described as an example of the electronic device, the first embodiment can be used for other transistors or electronic devices.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

(Additional remark 1) The graphene layer provided on the board | substrate, The ohmic electrode which is provided on the said graphene layer and contains nickel is comprised, The carbon-carbon bond in the surface of the said graphene layer which the said ohmic electrode contacts An electronic device having a ratio of nickel-carbon bonds to 30% or more.
(Supplementary note 2) The electronic device according to supplementary note 1, wherein the ohmic electrode includes a nickel layer in contact with the graphene layer.
(Supplementary note 3) The electronic device according to supplementary note 1, including a gate electrode provided on the graphene layer, wherein the ohmic electrode includes a source electrode and a drain electrode sandwiching the gate electrode.
(Appendix 4) A step of forming a graphene layer on a substrate, a step of performing ultraviolet ozone treatment or oxygen ashing treatment on the surface of the graphene layer, and the surface of the graphene layer subjected to ultraviolet ozone treatment or oxygen ashing treatment Forming an ohmic electrode containing nickel on the substrate.
(Supplementary note 5) The method for manufacturing an electronic device according to supplementary note 4, wherein the step of performing the ultraviolet ozone treatment or the oxygen ashing treatment includes a step of performing the ultraviolet ozone treatment.
(Additional remark 6) The process of forming the mask which has the opening which the said surface of the said graphene layer exposes on the said graphene layer, The process of performing the said ultraviolet ozone process or an oxygen ashing process includes the said graphene layer through the said opening The manufacturing method of the electronic device according to appendix 4, including a step of performing the ultraviolet ozone treatment or the oxygen ashing treatment on the surface.
(Supplementary Note 7) In the step of forming the gate electrode on the graphene layer, and performing the ultraviolet ozone treatment or the oxygen ashing treatment, a region of the surface of the graphene layer in which the gate electrode is formed includes the ultraviolet ray The method for manufacturing an electronic device according to attachment 4, wherein the ozone treatment or the oxygen ashing treatment is not performed.
(Appendix 8) A step of forming a graphene layer on a substrate, a step of performing a surface treatment on the surface of the graphene layer, and a step of forming an ohmic electrode containing nickel on the surface-treated surface of the graphene layer And the surface treatment is such that the ratio of nickel-carbon bonds to carbon-carbon bonds on the surface of the graphene layer in contact with the ohmic electrode is 30% or more after the ohmic electrode is formed. Method of manufacturing an electronic device which is a complicated process.
(Supplementary note 9) The electronic device according to supplementary note 1, wherein a ratio of a nickel-carbon bond to a carbon-carbon bond on the surface of the graphene layer in contact with the ohmic electrode is 70% or less.
(Additional remark 10) The process of performing the said ultraviolet ozone process or an oxygen ashing process is a manufacturing method of the electronic device of Additional remark 4 including the process of performing the said oxygen ashing process.
(Additional remark 11) The process of forming the said ohmic electrode is a manufacturing method of the electronic device of Additional remark 4 including the process of forming the nickel layer which contact | connects the said graphene layer.
(Additional remark 12) The manufacturing method of the electronic device of Additional remark 4 whose ratio of the nickel-carbon bond with respect to a carbon-carbon bond in the surface of the said graphene layer which the said ohmic electrode contacts is 30% or more.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Graphene layer 14 Gate insulating film 15 Al film 16 Aluminum oxide film 18 Silicon oxide film 20 Gate electrode 24 Source electrode 25 Ohmic electrode 25a Nickel layer 25b Gold layer 26 Drain electrode 30 Pad 50 Photoresist 52 Mask layer 54 Opening 60 X Line 62 photoelectrons

Claims (8)

A graphene layer provided on a substrate;
An ohmic electrode provided on the graphene layer and containing nickel;
Comprising
An electronic device in which a ratio of a nickel-carbon bond to a carbon-carbon bond on the surface of the graphene layer in contact with the ohmic electrode is 30% or more.   The electronic device according to claim 1, wherein the ohmic electrode includes a nickel layer in contact with the graphene layer. Comprising a gate electrode provided on the graphene layer;
The electronic device according to claim 1, wherein the ohmic electrode includes a source electrode and a drain electrode that sandwich the gate electrode. Forming a graphene layer on the substrate;
A step of performing ultraviolet ozone treatment or oxygen ashing treatment on the surface of the graphene layer;
Forming an ohmic electrode containing nickel on the ultraviolet ozone treatment or oxygen ashing surface of the graphene layer;
A method of manufacturing an electronic device including:   The method for manufacturing an electronic device according to claim 4, wherein the step of performing the ultraviolet ozone treatment or the oxygen ashing treatment includes a step of performing the ultraviolet ozone treatment. Forming a mask having an opening exposing the surface of the graphene layer on the graphene layer;
6. The method of manufacturing an electronic device according to claim 4, wherein the step of performing the ultraviolet ozone treatment or the oxygen ashing treatment includes a step of performing the ultraviolet ozone treatment or the oxygen ashing treatment on the surface of the graphene layer through the opening. . Forming a gate electrode on the graphene layer,
7. The ultraviolet ozone treatment or the oxygen ashing treatment is performed without performing the ultraviolet ozone treatment or the oxygen ashing treatment on a region of the surface of the graphene layer where the gate electrode is formed. The manufacturing method of the electronic device as described in a term. Forming a graphene layer on the substrate;
Performing a surface treatment on the surface of the graphene layer;
Forming an ohmic electrode containing nickel on the surface-treated surface of the graphene layer;
Including
The surface treatment is an electron whose ratio of nickel-carbon bonds to carbon-carbon bonds is 30% or more on the surface of the graphene layer in contact with the ohmic electrode after the ohmic electrode is formed. Device manufacturing method.

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