JP2017152500A - Coil component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain desired self-resonance frequency characteristics, while minimizing increase in the number of conductor layers, in a coil component formed by laminating planar spiral conductors.SOLUTION: A coil component includes planar spiral conductors 41, 42 formed, respectively, on conductor layers M1, M2, capacitor electrodes 51, 52 formed, respectively, on conductor layers M3, M4, and connected with the outer peripheral end 41a and inner peripheral end 41b of the planar spiral conductor 41, and a lead-out conductor 61 formed on the conductor layer M3 or M4, and connecting the inner peripheral end 41b of the planar spiral conductor 41 and a terminal electrode E3. Since a capacitor is added across the planar spiral conductor 41, the self-resonance frequency can be shifted to the low frequency side by increase in the capacitor component. Furthermore, since the capacitor electrode and lead-out conductor are formed on the same conductor layer, increase in the number of the conductor layers can be minimized.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a coil component, and more particularly to a coil component in which two planar spiral conductors are laminated.

  A general common mode filter has a configuration in which two planar spiral conductors are laminated on a magnetic substrate, and thereby the two planar spiral conductors are magnetically coupled to each other. However, in recent years, since the chip size has been further reduced, it is inevitably necessary to reduce the width of the planar spiral conductor. When the conductor width is narrowed, the parasitic capacitance component is reduced, so that the self-resonant frequency (SRF) tends to increase. For this reason, when the target self-resonant frequency band is in a lower frequency region, it is necessary to lower the self-resonant frequency by some method.

  As a method for reducing the self-resonance frequency, there is a method of increasing the number of windings. In this case, however, the conductor width needs to be further reduced, so that the DC resistance is greatly increased. Another method for lowering the self-resonance frequency is to increase the number of conductor layers, for example, to laminate four planar spiral conductors. In this case, the Scd21 characteristic (due to the influence of stray capacitance generated between the layers) The characteristic that the differential component of the signal is converted into the common mode component) is deteriorated.

  As another method for reducing the self-resonance frequency, a method of adding a capacitor electrode to the conductor layer is also conceivable. Although not intended to reduce the self-resonance frequency, Patent Document 1 discloses a coil component including a capacitor electrode.

JP 2007-159069 A

  However, since the coil component described in Patent Document 1 uses a three-dimensional spiral conductor, a large number of conductor layers are required, and a conductor layer for a capacitor electrode is added to this. The number of conductor layers is further increased. Here, if a planar spiral conductor is used instead of a three-dimensional spiral conductor, the number of conductor layers can be reduced. In this case, a lead conductor for connecting the inner peripheral end of the planar spiral conductor and the terminal electrode is used. It is necessary to form in another conductor layer, and the number of conductor layers increases.

  Accordingly, an object of the present invention is to obtain a desired self-resonant frequency characteristic while minimizing an increase in the number of conductor layers in a coil component in which planar spiral conductors are laminated.

  A coil component according to the present invention includes first, second, third, and fourth conductor layers stacked on each other via an insulating layer, and first, second, third, and fourth terminal electrodes. The first conductor layer is formed with a first planar spiral conductor having an outer peripheral end connected to the first terminal electrode and an inner peripheral end connected to the third terminal electrode. A second planar spiral conductor that has an outer peripheral end connected to the second terminal electrode, an inner peripheral end connected to the fourth terminal electrode, and is magnetically coupled to the first planar spiral conductor. And the third conductor layer includes a first capacitor electrode connected to the outer peripheral end of the first planar spiral conductor, the outer peripheral end of the second planar spiral conductor, and the inner periphery. A third capacitor electrode connected to one of the ends, and forming the fourth conductor Includes a second capacitor electrode connected to the inner peripheral end of the first planar spiral conductor and overlapping the first capacitor electrode in plan view, the outer peripheral end of the second planar spiral conductor, and the A fourth capacitor electrode connected to the other of the inner peripheral ends and overlapping the third capacitor electrode in plan view is formed, and the first planar spiral is formed on one of the third and fourth conductor layers. A first lead conductor connecting the inner peripheral end of the conductor and the third terminal electrode is formed, and the inner periphery of the second planar spiral conductor is formed on one of the third and fourth conductor layers. A second lead conductor connecting the end and the fourth terminal electrode is formed.

  According to the present invention, since the capacitor is added between both ends of the first planar spiral conductor and between both ends of the second planar spiral conductor, the capacitance component is balanced while balancing the characteristics of the pair of signal components. By increasing this, the self-resonant frequency can be moved to the low frequency side. As a result, even when the self-resonant frequency becomes higher than the target frequency band due to downsizing, the self-resonant frequency can be moved to a desired frequency band. Further, since the capacitor electrode is formed on a conductor layer different from the planar spiral conductor, the planar size of the coil component does not increase. In addition, since the capacitor electrode and the lead conductor are formed in the same conductor layer, an increase in the number of conductor layers can be minimized.

  In the present invention, the first lead conductor is formed on one of the third and fourth conductor layers, and the second lead conductor is formed on the other of the third and fourth conductor layers. Preferably it is. According to this, since the first lead conductor and the second lead conductor are formed in different conductor layers, the degree of freedom in layout of the third and fourth conductor layers is increased.

  Further, when the wiring length of the second lead conductor is longer than that of the first lead conductor, it is preferable that the width of the first lead conductor is narrower than that of the second lead conductor. According to this, since the difference in DC resistance is reduced, it is possible to balance the characteristics for a pair of signal components.

  In the present invention, the insulating layer is a rectangle having first and second short sides and first and second long sides in a plan view, and the first and second capacitor electrodes are the first and second capacitor electrodes. Preferably, the third and fourth capacitor electrodes are arranged along the short side, and the third and fourth capacitor electrodes are arranged along the second short side. According to this, it becomes possible to reduce the planar size of the coil component while reducing the eddy current generated in the first to fourth capacitor electrodes.

  In this case, the first and second capacitor electrodes include a first portion that overlaps a formation region of the first and second planar spiral conductors in plan view, and the first and second planar spirals in plan view. A second portion that does not overlap the conductor formation region, and the third and fourth capacitor electrodes include a third portion that overlaps the formation region of the first and second planar spiral conductors in a plan view. It is preferable to have a fourth portion that does not overlap with the first and second planar spiral conductor formation regions in plan view. According to this, eddy current loss is suppressed without causing a substantial characteristic difference between the first planar spiral conductor and the second planar spiral conductor, and the planar size of the coil component is reduced. It becomes possible.

  In the present invention, the first, second, third, and fourth conductor layers are laminated on a magnetic substrate, and the third and fourth conductor layers are formed from the first and second conductor layers. Is preferably located in the upper layer. According to this, since the first and second planar spiral conductors are arranged at the lower layer positions with higher flatness, it becomes easier to form the first and second planar spiral conductors that require higher accuracy.

  According to the present invention, it is possible to obtain desired self-resonant frequency characteristics while minimizing an increase in the number of conductor layers in a coil component in which planar spiral conductors are laminated.

FIG. 1 is a schematic perspective view showing an appearance of a coil component 10 according to a preferred embodiment of the present invention. FIG. 2 is a diagram for explaining the structure of the laminated structure 20. FIG. 3 is an equivalent circuit diagram of the coil component 10. FIG. 4 is a perspective view of the conductor layers M1 to M4 viewed from the stacking direction. FIG. 5 is an enlarged perspective view showing a portion where the capacitor electrodes 51 to 54 are formed. FIG. 6 is a process diagram for explaining a method of forming the laminated structure 20. FIG. 7 is a process diagram for explaining a method of forming the laminated structure 20.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic perspective view showing an appearance of a coil component 10 according to a preferred embodiment of the present invention, and is a diagram that is vertically inverted with respect to a mounted state.

  As shown in FIG. 1, the coil component 10 according to the present embodiment is a surface-mounted common mode filter having a substantially rectangular parallelepiped shape, and includes a magnetic substrate 11, a laminated structure 20 provided on the magnetic substrate 11, The first to fourth terminal electrodes E1 to E4 and the magnetic resin layer 12 provided on the laminated structure 20 are provided. A specific configuration of the laminated structure 20 will be described later. Although not particularly limited, the size of the coil component 10 is 0.45 mm in length in the x direction, 0.3 mm in width in the y direction, and 0.23 mm in height in the z direction. At the time of mounting, it is inverted upside down from the state shown in FIG. 1, and is mounted so that the xy surface provided with the first to fourth terminal electrodes E1 to E4 faces the printed board. The coil component 10 according to the present embodiment is a laminated thin-film coil component in which a laminated structure 20 is laminated on a magnetic substrate 11, and is a so-called wound-type coil component obtained by winding a wire around a magnetic core or bobbin. Are of different types.

  The magnetic substrate 11 is a substrate for laminating the laminated structure 20, physically protects the laminated structure 20, and constitutes a magnetic path of the coil component 10. As the material of the magnetic substrate 11, sintered ferrite, composite ferrite (ferrite powder-containing resin), and the like can be used, and it is particularly preferable to use sintered ferrite having high mechanical strength and excellent magnetic properties.

  The first to fourth terminal electrodes E1 to E4 are all arranged at the corners. For this reason, the terminal electrodes E <b> 1 to E <b> 4 are exposed on the three side surfaces (xy surface, xz surface, yz surface) of the coil component 10. Although not particularly limited, the terminal electrodes E1 to E4 are formed by a thick film plating method, and the thickness thereof is sufficiently thicker than an electrode pattern formed by a sputtering method or screen printing.

  The magnetic resin layer 12 physically protects the laminated structure 20, and fixes and supports the first to fourth terminal electrodes E1 to E4. The magnetic resin layer 12 includes the first to fourth terminal electrodes E1 to E4. It is provided to embed the surroundings. The upper surface (xy surface) of the magnetic resin layer 12 constitutes the same plane as the upper surfaces (xy surface) of the first to fourth terminal electrodes E1 to E4. As a material of the magnetic resin layer 12, it is preferable to use composite ferrite. The magnetic resin layer 12 has high magnetic properties and constitutes a magnetic path together with the magnetic substrate 11.

  FIG. 2 is a schematic exploded perspective view of the coil component 10, and in particular, is a view for explaining the structure of the laminated structure 20.

  As shown in FIG. 2, the laminated structure 20 includes insulating layers 31 to 35 that are sequentially stacked from the magnetic substrate 11 side toward the magnetic resin layer 12 side, and four insulating layers 31 to 35 are provided between the insulating layers 31 to 35. Conductor layers M1 to M4 are formed. The insulating layers 31 to 35 are made of, for example, a resin and serve to separate the first to fourth conductor layers M1 to M4 from each other.

  The first conductor layer M1 includes a first planar spiral conductor 41 and a connection conductor 72. The first planar spiral conductor 41 is wound clockwise (clockwise) from the outer peripheral end 41a toward the inner peripheral end 41b in plan view. The outer peripheral end 41a of the first planar spiral conductor 41 is connected to the first terminal electrode E1 via connection conductors 71, 81, 91.

  The second conductor layer M2 includes a second planar spiral conductor 42 and connection conductors 71 and 75. The second planar spiral conductor 42 is wound clockwise (clockwise) from the outer peripheral end 42a toward the inner peripheral end 42b in plan view. The outer peripheral end 42a of the second planar spiral conductor 42 is connected to the second terminal electrode E2 via the connection conductors 82 and 92.

  Although not particularly limited, in the present embodiment, the number of turns of the first and second planar spiral conductors 41 and 42 is 15 turns. Since the first planar spiral conductor 41 and the second planar spiral conductor 42 are laminated via the insulating layer 32, they are magnetically coupled to each other.

  The third conductor layer M3 includes a first capacitor electrode 51, a third capacitor electrode 53, a first lead conductor 61, and connection conductors 81 to 83, 85. The first capacitor electrode 51 is connected to the first terminal electrode E 1 (that is, the outer peripheral end 41 a of the first planar spiral conductor 41) via the connection conductors 81 and 91. On the other hand, the third capacitor electrode 53 is connected to the second terminal electrode E <b> 2 (that is, the outer peripheral end 42 a of the second planar spiral conductor 42) via the connection conductors 82 and 92. One end of the first lead conductor 61 is connected to the inner peripheral end 41 b of the first planar spiral conductor 41 via the connection conductor 75, and the other end is connected to the third terminal via the connection conductors 83 and 93. It is connected to the electrode E3. That is, the first lead conductor 61 serves to connect the inner peripheral end 41b of the first planar spiral conductor 41 and the third terminal electrode E3.

  The fourth conductor layer M4 includes a second capacitor electrode 52, a fourth capacitor electrode 54, a second lead conductor 62, and connection conductors 91 to 94. The second capacitor electrode 52 overlaps the first capacitor electrode 51 in plan view, and is connected to the third terminal electrode E3 (that is, the inner peripheral end 41b of the first planar spiral conductor 41) via the connection conductor 93. It is connected. On the other hand, the fourth capacitor electrode 54 overlaps the third capacitor electrode 53 in plan view, and the fourth terminal electrode E4 (that is, the inner peripheral end 42b of the second planar spiral conductor 42) via the connection conductor 94. )It is connected to the. One end of the second lead conductor 62 is connected to the inner peripheral end 42 b of the second planar spiral conductor 42 via the connection conductor 85, and the other end is connected to the fourth capacitor electrode 54 and the connection conductor 94. Connected to the fourth terminal electrode E4. That is, the second lead conductor 62 serves to connect the inner peripheral end 42b of the second planar spiral conductor 42 and the fourth terminal electrode E4.

  As described above, the first capacitor electrode 51 and the second capacitor electrode 52 overlap with each other through the insulating layer 34, and the third capacitor electrode 53 and the fourth capacitor electrode 54 pass through the insulating layer 34. overlapping. Thereby, as shown in FIG. 3 which is an equivalent circuit diagram, a capacitance component C1 parallel to the first planar spiral conductor 41 is inserted between the first terminal electrode E1 and the third terminal electrode E3. Thus, a capacitance component C2 parallel to the second planar spiral conductor 42 is inserted between the second terminal electrode E2 and the fourth terminal electrode E4. Since the first planar spiral conductor 41 and the second planar spiral conductor 42 are magnetically coupled and have the same number of turns, the coil component 10 according to the present embodiment constitutes a common mode filter circuit.

  As shown in FIG. 2, the magnetic resin layer 12 has a shape in which portions corresponding to the first to fourth terminal electrodes E1 to E4 are cut out. Further, the insulating layers 31 to 35 are provided with through holes 31H to 35H, respectively, and the magnetic resin layer 13 is provided so as to fill the through holes 31H to 35H. The magnetic resin layer 13 is a part of the magnetic resin layer 12, and both have an integral structure.

  In the example shown in FIG. 2, the first and third capacitor electrodes 51 and 53 are formed on the third conductor layer M3, and the second and fourth capacitor electrodes 52 and 54 are formed on the fourth conductor layer M4. However, the present invention is not limited to this. That is, as long as the first capacitor electrode 51 and the second capacitor electrode 52 are formed in different conductor layers, and the third capacitor electrode 53 and the fourth capacitor electrode 54 are formed in different conductor layers. Each of the capacitor electrodes 51 to 54 may be formed on any conductor layer.

  In the example shown in FIG. 2, the first lead conductor 61 is formed in the third conductor layer M3, and the second lead conductor 62 is formed in the fourth conductor layer M4. It is not limited to. Therefore, contrary to FIG. 2, the first lead conductor 61 may be formed in the fourth conductor layer M4, and the first lead conductor 61 may be formed in the third conductor layer M3. The second lead conductors 61 and 62 may be formed on the same conductor layer M3 or M4.

  Furthermore, in the example shown in FIG. 2, the first and second planar spiral conductors 41 and 42 are located in the lower layer, and the first to fourth capacitor electrodes 51 to 54 are located in the upper layer. However, the present invention is not limited to this, and conversely, the first to fourth capacitor electrodes 51 to 54 may be located in the lower layer and the first and second planar spiral conductors 41 and 42 may be located in the upper layer. Absent.

  FIG. 4 is a perspective view of the conductor layers M1 to M4 viewed from the stacking direction.

  As shown in FIG. 4, the first planar spiral conductor 41 and the second planar spiral conductor 42 are almost exactly overlapped when viewed from the stacking direction. In other words, each turn of the second planar spiral conductor 42 is aligned with the same turn of the first planar spiral conductor 41 at a position that almost exactly overlaps in plan view. In addition, the first capacitor electrode 51 and the second capacitor electrode 52 are almost exactly overlapped when viewed from the stacking direction. Similarly, the third capacitor electrode 53 and the fourth capacitor electrode 54 are also almost exactly overlapped when viewed from the stacking direction.

  Here, when the short sides of the insulating layers 31 to 35 having a rectangular shape in plan view are L1 and L2, and the long sides are L3 and L4, the first and second capacitor electrodes 51 and 52 are short sides L1. The third and fourth capacitor electrodes 53 and 54 have a shape extending in the y direction along the short side L2. A portion of each of the first to fourth capacitor electrodes 51 to 54 is disposed at a position overlapping the formation region of the first and second planar spiral conductors 41 and 42.

  More specifically, as shown in FIG. 5 (a), which is an enlarged view, the first and second capacitor electrodes 51 and 52 are formed with regions where the first and second planar spiral conductors 41 and 42 are formed. It has the 1st part A1 which overlaps, and 2nd part A2 which does not overlap with the formation area of the 1st and 2nd planar spiral conductors 41 and 42. FIG. Similarly, as shown in FIG. 5B, which is an enlarged view, the third and fourth capacitor electrodes 53 and 54 overlap with the formation regions of the first and second planar spiral conductors 41 and 42, respectively. A portion A3 and a fourth portion A4 that does not overlap the formation region of the first and second planar spiral conductors 41 and 42 are provided. Here, the formation region of the first and second planar spiral conductors 41 and 42 indicates the outermost outer periphery of the first and second planar spiral conductors 41 and 42 and the region located on the inner peripheral side of the outermost periphery. . Therefore, a space region existing between adjacent turns is also included in the formation region of the first and second planar spiral conductors 41 and 42.

  As described above, in the present embodiment, the first to fourth capacitor electrodes 51 to 54 are arranged on the short side L1 or L2 so as to overlap the formation region of the first and second planar spiral conductors 41 and 42. Since they are arranged adjacent to each other, the eddy current generated in the first to fourth capacitor electrodes 51 to 54 can be suppressed while reducing the planar size of the coil component 10. That is, if the first and third portions A1 and A3 that overlap the formation region of the first and second planar spiral conductors 41 and 42 are too large, the first and third capacitor electrodes 51 and 53 and the second plane The stray capacitance generated between the spiral conductor 42 is increased, and a characteristic difference is generated between the first planar spiral conductor 41 and the second planar spiral conductor 42. On the other hand, if the second and fourth portions A2 and A4 that do not overlap the formation region of the first and second planar spiral conductors 41 and 42 are too large, they are applied to the first to fourth capacitor electrodes 51 to 54. Eddy current loss increases due to magnetic flux. Further, when the second and fourth portions A2 and A4 are large, the planar size of the coil component 10 needs to be increased.

  Considering this point, in the present embodiment, the first portion A1 is 30% to 70% and the second portion A2 is 70% with respect to the areas of the first and second capacitor electrodes 51 and 52. % To 30%. Similarly, the third portion A3 is designed to be 30% to 70% and the fourth portion A4 is designed to be 70% to 30% with respect to the areas of the third and fourth capacitor electrodes 53 and 54. Thereby, eddy current loss is suppressed without causing a substantial characteristic difference between the first planar spiral conductor 41 and the second planar spiral conductor 42. Further, it is possible to adjust the self-resonant frequency low range while reducing the planar size of the coil component 10.

  Although not particularly limited, as shown in FIG. 4, in the present embodiment, the second lead conductor 62 has a longer wiring length than the first lead conductor 61. This is due to the fact that the through holes 31H to 35H are arranged offset to the right side (short side L2 side). In such a case, it is preferable to make the wiring width of the first lead conductor 61 smaller than the wiring width of the second lead conductor 62. According to this, since the difference between the DC resistance of the first lead conductor 61 and the DC resistance of the second lead conductor 62 is reduced, it is possible to balance the characteristics for a pair of signal components. Become.

  In the present invention, the “width” of the conductor refers to the length of the side parallel to the xy plane, which is the side of the cross section in the stacking direction of the spiral conductor. In the present invention, the “film thickness” or “height” of the conductor refers to the side of the cross section in the stacking direction of the spiral conductor and the length of the side in the z direction.

  Next, a method for forming the laminated structure 20 will be described.

  6 and 7 are process diagrams for explaining a method of forming the laminated structure 20 shown in FIG.

  First, a magnetic substrate 11 made of sintered ferrite or the like having a predetermined thickness is prepared, and an insulating layer 31 is formed on the upper surface thereof. Next, as illustrated in FIG. 6A, a conductor layer M <b> 1 including the first planar spiral conductor 41 and the connection conductor 72 is formed on the upper surface of the insulating layer 31. As a method for forming these conductors, it is preferable to form a base metal film using a thin film process such as a sputtering method, and then to perform plating growth to a desired film thickness using an electrolytic plating method. The same applies to the method of forming other conductors formed thereafter.

  Next, as illustrated in FIG. 6B, the insulating layer 32 is formed on the upper surface of the insulating layer 31 so as to cover the conductor layer M <b> 1, and then the through holes 32 a to 32 c are formed in the insulating layer 32. Specifically, the insulating layer 32 having the through holes 32a to 32c can be formed by applying a resin material by a spin coating method and then forming a predetermined pattern by a photolithography method. The same applies to a method for forming an insulating layer to be formed later. The through holes 32a and 32c shown in FIG. 6B are formed at positions where the outer peripheral end 41a and the inner peripheral end 41b of the first planar spiral conductor 41 are exposed, and the through holes 32b are positions where the connecting conductor 72 is exposed. Formed.

  Next, as shown in FIG. 6C, the conductor layer M <b> 2 including the second planar spiral conductor 42 and the connection conductors 71 and 75 is formed on the upper surface of the insulating layer 32. As described with reference to FIG. 4, each turn of the second planar spiral conductor 42 is aligned with the same turn of the first planar spiral conductor 41. The outer peripheral end 42a of the second spiral conductor is formed at a position corresponding to the through hole 32b, and the connection conductors 71 and 75 are formed at positions corresponding to the through holes 32a and 32c, respectively. Thereby, the outer peripheral end 42a of the second planar spiral conductor is connected to the connection conductor 72, and the connection conductors 71 and 75 are connected to the outer peripheral end 41a and the inner peripheral end 41b of the first planar spiral conductor 41, respectively.

  Next, as illustrated in FIG. 6D, the insulating layer 33 is formed on the upper surface of the insulating layer 32 so as to cover the conductor layer M <b> 2, and then the through holes 33 a to 33 d are formed in the insulating layer 33. The through holes 33b and 33d shown in FIG. 6D are formed at positions where the outer peripheral end 42a and the inner peripheral end 42b of the second planar spiral conductor 42 are exposed, and the through holes 33a and 33c are respectively connected to the connection conductor 71, It is formed at a position where 75 is exposed.

  Next, as shown in FIG. 7A, a conductor comprising a first capacitor electrode 51, a third capacitor electrode 53, a first lead conductor 61, and connection conductors 81 to 83, 85 on the upper surface of the insulating layer 33. Layer M3 is formed. As described with reference to FIG. 4, the first and third capacitor electrodes 51 and 53 have short sides L <b> 1 and L <b> 2, respectively, so as to overlap part of the formation region of the first and second planar spiral conductors 41 and 42. It is arranged along. The connection conductors 81, 82, and 85 are formed at positions corresponding to the through holes 33a, 33b, and 33d, respectively, and one end of the first lead conductor 61 is formed at a position corresponding to the through hole 33c. Thus, the connection conductors 82 and 85 are connected to the outer peripheral ends 42a and 42b of the second planar spiral conductor 42, the connection conductor 81 is connected to the connection conductor 71, and one end of the first lead conductor 61 is connected to the connection conductor 71 75.

  Next, as illustrated in FIG. 7B, the insulating layer 34 is formed on the upper surface of the insulating layer 33 so as to cover the conductor layer M <b> 3, and then the through holes 34 a to 34 d are formed in the insulating layer 34. The through holes 34a to 34d shown in FIG. 7B are formed at positions where the connection conductors 81 to 83 and 85 are exposed, respectively.

  Next, as shown in FIG. 7C, a conductor layer M4 including a second capacitor electrode 52, a fourth capacitor electrode 54, a second lead conductor 62, and connection conductors 91 to 94 on the upper surface of the insulating layer 34. Form. As described with reference to FIG. 4, the second and fourth capacitor electrodes 52 and 54 are arranged at positions overlapping the first and third capacitor electrodes 51, respectively. The connection conductors 91 to 93 are formed at positions corresponding to the through holes 34a to 34c, respectively, and one end of the second lead conductor 62 is formed at a position corresponding to the through hole 34d. Accordingly, the connection conductors 91 to 93 are connected to the connection conductors 81 to 83, respectively, and one end of the second lead conductor 62 is connected to the connection conductor 85.

  Next, as illustrated in FIG. 7D, an insulating layer 35 is formed on the upper surface of the insulating layer 34 so as to cover the conductor layer M <b> 4, and then through holes 35 a to 35 d are formed in the insulating layer 35. The through holes 35a to 35d shown in FIG. 7D are formed at positions where the connection conductors 91 to 94 are exposed, respectively.

  Next, as illustrated in FIG. 7E, first to fourth terminal electrodes E <b> 1 to E <b> 4 are formed on the surface of the insulating layer 35. A method of forming the first to fourth terminal electrodes E1 to E4 is as follows. First, a Cu film as a base is formed on the entire surface of the insulating layer 35 where the connection conductors 91 to 94 are exposed by electroless plating. Thereafter, the sheet resist is pasted, exposed and developed to selectively remove the sheet resist in the region where the first to fourth terminal electrodes E1 to E4 are to be formed, and expose the Cu film in the region. . In this state, thick first to fourth terminal electrodes E1 to E4 are formed by electroplating. Thereafter, by removing the sheet resist and removing the unnecessary Cu film by etching the entire surface, columnar first to fourth terminal electrodes E1 to E4 are formed.

  Next, as shown in FIG. 7F, an ion milling mask 36 having an opening 36H is formed, and ion milling is performed in this state. As a result, through holes 31H to 35H are formed in the insulating layers 31 to 35, and the magnetic substrate 11 is exposed at the positions. Then, if a composite ferrite paste is formed on the entire surface and cured, the magnetic resin layer 12 that fills the periphery of the first to fourth terminal electrodes E1 to E4 and the magnetic resin layer embedded in the through holes 31H to 35H 13 is formed. Thereafter, if unnecessary composite ferrite on the first to fourth terminal electrodes E1 to E4 is removed, the coil component 10 according to the present embodiment is completed.

  As described above, in the coil component 10 according to the present embodiment, the capacitance component C1 parallel to the first planar spiral conductor 41 and the capacitance component C2 parallel to the second planar spiral conductor 42 are added. Therefore, the self-resonant frequency can be moved to the low frequency side. Thus, even when the self-resonant frequency becomes higher than the target frequency due to the reduction in the planar size, the self-resonant frequency can be moved to a desired frequency band. Further, since the first to fourth capacitor electrodes 51 to 54 are formed on the conductor layers M3 and M4 different from the first and second planar spiral conductors 41 and 42, the planar size of the coil component 10 is increased. I don't have to. In addition, the first lead conductor 61 is formed in the same conductor layer M3 as the first and third capacitor electrodes 51 and 53, and the second lead conductor 62 is the same conductor as the second and fourth capacitor electrodes 52 and 54. Since it is formed on the layer M4, an increase in the number of conductor layers can be minimized.

  In addition, in the present embodiment, the first and second capacitor electrodes 51 and 52 are arranged along the short side L1, and the third and fourth capacitor electrodes 53 and 54 are arranged along the short side L2. Therefore, the planar size of the coil component 10 can be reduced while reducing eddy currents generated in the first to fourth capacitor electrodes 51 to 54.

  In the present embodiment, since the first and second planar spiral conductors 41 and 42 are located in the lower layer and the first to fourth capacitor electrodes 51 to 54 are located in the upper layer, higher accuracy is achieved. It becomes easy to form the required first and second planar spiral conductors 41 and 42.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the embodiment described above, the terminal electrodes E1 to E4 have a bump shape embedded in the magnetic resin layer 12, but the shape and structure of the terminal electrode are not limited to this in the present invention. Therefore, a terminal electrode formed by baking a silver paste or the like on the surface of the substrate may be used, or a terminal electrode formed by bonding a terminal fitting to the substrate may be used.

  In the above-described embodiment, the first and second planar spiral conductors 41 and 42 are octagonal in a plan view, but the present invention is not limited to this, and a rectangular shape whose corners are gently curved. The shape may be sufficient, and the whole may be elliptical shape.

DESCRIPTION OF SYMBOLS 10 Coil components 11 Magnetic substrate 12, 13 Magnetic resin layer 20 Laminated structure 31-35 Insulating layer 31H-35H Through hole 32a-32c, 33a-33d, 34a-34d, 35a-35d Through hole 36 Ion milling mask 36H Opening Portions 41, 42 Planar spiral conductors 41a, 42a Outer peripheral ends 41b, 42b Inner peripheral ends 51-54 Capacitor electrodes 61, 62 Lead conductors 71, 72, 75, 81-83, 85, 91-94 Connection conductor A1 First portion A2 2nd part A3 3rd part A4 4th part E1-E4 Terminal electrode L1, L2 Short side L3, L4 Long side M1-M4 Conductor layer

Claims (6)

First, second, third and fourth conductor layers laminated together via an insulating layer;
First, second, third and fourth terminal electrodes,
The first conductor layer is formed with a first planar spiral conductor having an outer peripheral end connected to the first terminal electrode and an inner peripheral end connected to the third terminal electrode;
The second conductor layer has an outer peripheral end connected to the second terminal electrode, an inner peripheral end connected to the fourth terminal electrode, and a second magnetically coupled to the first planar spiral conductor. A planar spiral conductor is formed,
The third conductor layer includes a first capacitor electrode connected to the outer peripheral end of the first planar spiral conductor, and one of the outer peripheral end and the inner peripheral end of the second planar spiral conductor. A connected third capacitor electrode is formed;
The fourth conductor layer is connected to the inner peripheral end of the first planar spiral conductor and overlaps the first capacitor electrode in plan view, and the second planar spiral conductor A fourth capacitor electrode connected to the other of the outer peripheral end and the inner peripheral end of the first capacitor electrode and overlapping the third capacitor electrode in plan view,
One of the third and fourth conductor layers is formed with a first lead conductor that connects the inner peripheral end of the first planar spiral conductor and the third terminal electrode,
One of the third and fourth conductor layers is formed with a second lead conductor connecting the inner peripheral end of the second planar spiral conductor and the fourth terminal electrode. Coil parts to play. The first lead conductor is formed on one of the third and fourth conductor layers,
The coil component according to claim 1, wherein the second lead conductor is formed on the other of the third and fourth conductor layers. The wiring length of the second lead conductor is longer than that of the first lead conductor,
The coil component according to claim 1 or 2, wherein the first lead conductor has a wiring width narrower than that of the second lead conductor. The insulating layer is a rectangle having first and second short sides and first and second long sides in plan view,
The first and second capacitor electrodes are disposed along the first short side,
4. The coil component according to claim 1, wherein the third and fourth capacitor electrodes are arranged along the second short side. 5. The first and second capacitor electrodes have a first portion that overlaps a formation region of the first and second planar spiral conductors in plan view, and formation of the first and second planar spiral conductors in plan view. A second portion that does not overlap the region;
The third and fourth capacitor electrodes include a third portion that overlaps with the formation region of the first and second planar spiral conductors in plan view, and formation of the first and second planar spiral conductors in plan view. The coil component according to claim 4, further comprising a fourth portion that does not overlap the region.   The first, second, third and fourth conductor layers are laminated on a magnetic substrate, and the third and fourth conductor layers are positioned above the first and second conductor layers. The coil component according to claim 1, wherein the coil component is a coil component.

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