JP2017152438A - Solid state image pickup device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device capable of suppressing a decrease in capacity of a floating diffusion layer or residual transfer.SOLUTION: A solid state image pickup device of an embodiment comprises: a first diffusion layer 18 of a second conductivity type; a first gate insulating film 11d; a first gate electrode 35; a second diffusion layer 19 of the second conductivity type; a second gate insulating film 11b; a second gate electrode 22; and a third diffusion layer 20 of the second conductivity type. A gate length L2 of the first gate electrode is substantially the same as a gate length L1 of the second gate electrode. A gate width W2 of the first gate electrode is substantially the same as a gate width W1 of the second gate electrode. A threshold voltage of a first transistor including the first gate electrode 35 is substantially the same as a threshold voltage of a second transistor including the second gate electrode 22.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof.

  In a conventional solid-state imaging device, photoelectric conversion carriers generated by a photodiode are transferred to a floating diffusion layer for temporary storage by a transfer gate electrode, and the carriers temporarily stored in the floating diffusion layer are transferred to a diffusion layer by a reset gate electrode. It is made to discharge | release (for example, refer patent document 1). The transfer gate electrode, the storage layer of the photodiode, and the floating diffusion layer constitute a transfer transistor, and the reset gate electrode, the floating diffusion layer, and the high concentration diffusion layer constitute a reset transistor.

  In the above-described solid-state imaging device, when the transfer gate electrode and the reset gate electrode have different potential heights when they are turned off, the capacity of the floating diffusion layer may be reduced or the transfer residue may occur.

  Details are shown in FIG. 16 (A) and FIG. 16 (B). Here, the deeper the potential well, the higher the potential height and the higher the potential. As shown in FIG. 16A, when the potential height 40 when the transfer gate electrode is off is lower than the potential height 41 when the reset gate electrode is off, each of the transfer gate electrode and the reset gate electrode is off. Sometimes, some of the carriers accumulated in the floating diffusion layer are released and fall to the diffusion layer of the reset transistor. Therefore, the capacity of the floating diffusion layer is reduced. In addition, as shown in FIG. 16B, when the potential height 41 when the reset gate electrode is off is lower than the potential height 40 when the transfer gate electrode is off, the capacitance of the floating diffusion layer does not decrease. However, a part of the carrier transferred from the transfer source to the floating diffusion layer by the transfer gate electrode may flow backward to leave a transfer residue left at the transfer source.

JP 2008-108916 A

  Some embodiments of the present invention relate to a solid-state imaging device or a method of manufacturing the same that can suppress the capacity reduction or transfer residue of the floating diffusion layer.

  One embodiment of the present invention includes a first second conductivity type diffusion layer, a first gate insulating film formed on the first second conductivity type diffusion layer, and the first gate insulating film. The first gate electrode formed, the second second conductivity type diffusion layer formed in the first second conductivity type diffusion layer, and the first second conductivity type diffusion layer formed on the first gate electrode. A second gate insulating film; a second gate electrode formed on the second gate insulating film; and a third second conductive type diffusion layer formed on the first second conductive type diffusion layer. The first second conductivity type diffusion layer is connected to the second second conductivity type diffusion layer by the first gate electrode, and the second second conductivity type diffusion layer is connected to the second second conductivity type diffusion layer. The layer is connected to the third second conductivity type diffusion layer by the second gate electrode, and the gate length of the first gate electrode is the second gate electrode. A gate width of the first gate electrode is substantially the same as a gate width of the second gate electrode, and the first second conductivity type diffusion layer, The threshold voltage of the first transistor including the second second conductivity type diffusion layer and the first gate electrode is set to be the second second conductivity type diffusion layer, the third second conductivity type diffusion layer, and The solid-state imaging device is characterized by being substantially the same as a threshold voltage of a second transistor including the second gate electrode.

  According to one embodiment of the present invention, the gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode, and the gate width of the first gate electrode is set to be the second gate. The threshold voltage of the first transistor including the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the first gate electrode is substantially the same as the gate width of the electrode. The threshold voltage of the second transistor including the second second conductivity type diffusion layer, the third second conductivity type diffusion layer, and the second gate electrode is substantially the same. Thereby, the potential height when the first gate electrode is off and the potential height when the second gate electrode is off can be made substantially the same. As a result, it is possible to suppress a decrease in capacity or transfer residue of the second second conductivity type diffusion layer.

  In the aspect of the present invention described above, the first second conductivity type diffusion layer may be formed in a first conductivity type well. Also in this aspect, it is possible to suppress the capacity drop or the transfer residue of the second second conductivity type diffusion layer.

  One embodiment of the present invention includes a first conductivity type well, a fourth second conductivity type diffusion layer formed in the first conductivity type well, and a first gate formed on the first conductivity type well. An insulating film; a first gate electrode formed on the first gate insulating film; a fifth second conductive type diffusion layer formed on the first conductive type well; and the first conductive type well. A second gate insulating film formed thereon; a second gate electrode formed on the second gate insulating film; and a sixth second conductivity type diffusion formed in the first conductivity type well. And the fourth second conductivity type diffusion layer is connected to the fifth second conductivity type diffusion layer by the first gate electrode, and the fifth second conductivity type. The diffusion layer is connected to the sixth second conductivity type diffusion layer by the second gate electrode, and the first gate electrode The gate length of the second gate electrode is substantially the same as the gate length of the second gate electrode, and the gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode. The threshold voltage of the first transistor including the second conductivity type diffusion layer, the fifth second conductivity type diffusion layer, and the first gate electrode is set to be the fifth second conductivity type diffusion layer, the first 6 is a solid-state imaging device characterized by being substantially the same as the threshold voltage of the second transistor including the second conductive type diffusion layer 6 and the second gate electrode.

  According to one embodiment of the present invention, the gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode, and the gate width of the first gate electrode is set to be the second gate. The threshold voltage of the first transistor including the fourth second conductivity type diffusion layer, the fifth second conductivity type diffusion layer, and the first gate electrode is substantially the same as the gate width of the electrode. The threshold voltage of the second transistor including the fifth second conductivity type diffusion layer, the sixth second conductivity type diffusion layer, and the second gate electrode is substantially the same. Thereby, the potential height when the first gate electrode is off and the potential height when the second gate electrode is off can be made substantially the same. As a result, it is possible to suppress a decrease in capacity or transfer residue of the fifth second conductivity type diffusion layer.

  In the above embodiment of the present invention, the thickness of the first gate insulating film is preferably substantially the same as the thickness of the second gate insulating film. Also in this aspect, it is possible to suppress the capacity reduction or transfer residue of the fifth second conductivity type diffusion layer.

  In the aspect of the present invention described above, the concentration of the impurity region located below the first gate electrode in the first second conductivity type diffusion layer may be the same as that in the first second conductivity type diffusion layer. The concentration of the impurity region located below the second gate electrode is preferably substantially the same. Also in this aspect, it is possible to suppress the capacity reduction or transfer residue of the fifth second conductivity type diffusion layer.

  In the aspect of the present invention described above, the concentration of the impurity region located below the first gate electrode in the first conductivity type well is below the second gate electrode in the first conductivity type well. It is preferable that the concentration is substantially the same as the concentration of the impurity region located in the region. Also in this aspect, it is possible to suppress the capacity reduction or transfer residue of the fifth second conductivity type diffusion layer.

  One embodiment of the present invention includes a step of forming a second second conductivity type diffusion layer in the first second conductivity type diffusion layer, and a first gate insulating film on the first second conductivity type diffusion layer. And forming a second gate insulating film, and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film. And forming a third second conductivity type diffusion layer in the first second conductivity type diffusion layer in a self-aligned manner with respect to the second gate electrode. The second conductivity type diffusion layer is connected to the second second conductivity type diffusion layer by the first gate electrode, and the second second conductivity type diffusion layer is connected to the second gate electrode by the second gate electrode. The gate length of the first gate electrode is connected to the third second conductivity type diffusion layer, and the second gate electrode The gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode, and the first second conductivity type diffusion layer, the second second gate electrode, The threshold voltage of the first transistor including the two-conductivity type diffusion layer and the first gate electrode is the second second-conductivity type diffusion layer, the third second-conductivity type diffusion layer, and the second transistor. A method for manufacturing a solid-state imaging device, characterized in that the threshold voltage of the second transistor including the gate electrode is substantially the same.

  According to one embodiment of the present invention, the gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode, and the gate width of the first gate electrode is set to be the second gate. The threshold voltage of the first transistor including the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the first gate electrode is substantially the same as the gate width of the electrode. The threshold voltage of the second transistor including the second second conductivity type diffusion layer, the third second conductivity type diffusion layer, and the second gate electrode is substantially the same. Thereby, the potential height when the first gate electrode is off and the potential height when the second gate electrode is off can be made substantially the same. As a result, it is possible to suppress a decrease in capacity or transfer residue of the second second conductivity type diffusion layer.

  According to one embodiment of the present invention, a step of forming a fourth second conductivity type diffusion layer and a fifth second conductivity type diffusion layer in the first conductivity type well, and a first gate on the first conductivity type well Forming an insulating film and a second gate insulating film; forming a first gate electrode on the first gate insulating film; and forming a second gate electrode on the second gate insulating film And a step of forming a sixth second conductivity type diffusion layer in the first conductivity type well in a self-aligned manner with respect to the second gate electrode, and the fourth second conductivity. The type diffusion layer is connected to the fifth second conductivity type diffusion layer by the first gate electrode, and the fifth second conductivity type diffusion layer is connected to the sixth gate electrode by the second gate electrode. A gate length of the first gate electrode is the second gate type diffusion layer. The gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode, and the fourth second conductivity type diffusion layer, The threshold voltage of the first transistor including the second conductivity type diffusion layer 5 and the first gate electrode is set to the fifth second conductivity type diffusion layer, the sixth second conductivity type diffusion layer, and The solid-state imaging device manufacturing method is characterized in that the threshold voltage of the second transistor including the second gate electrode is substantially the same.

  According to one embodiment of the present invention, the gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode, and the gate width of the first gate electrode is set to be the second gate. The threshold voltage of the first transistor including the fourth second conductivity type diffusion layer, the fifth second conductivity type diffusion layer, and the first gate electrode is substantially the same as the gate width of the electrode. The threshold voltage of the second transistor including the fifth second conductivity type diffusion layer, the sixth second conductivity type diffusion layer, and the second gate electrode is substantially the same. Thereby, the potential height when the first gate electrode is off and the potential height when the second gate electrode is off can be made substantially the same. As a result, it is possible to suppress a decrease in capacity or transfer residue of the fifth second conductivity type diffusion layer.

(A) is a plan view showing a solid-state imaging device according to one embodiment of the present invention, (B) is a cross-sectional view taken along line aa ′ shown in (A), and (C) is b- shown in (A). Sectional drawing along b 'line. 2 is a cross-sectional view of the N-type floating diffusion layer shown in FIG. 1C in which the P-type surface diffusion layer 16 and the P-type high concentration well 15 are removed from the N-type low concentration region 18. FIG. 1 is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention. 1 is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention. (A) is a top view which shows the solid-state imaging device which concerns on 1 aspect of this invention, (B) is sectional drawing along the aa 'line shown to (A). (A) is a plan view showing a solid-state imaging device according to one embodiment of the present invention, (B) is a cross-sectional view taken along line aa ′ shown in (A), and (C) is b- shown in (A). Sectional drawing along b 'line. (A), (B) is sectional drawing for demonstrating the manufacturing method of the solid-state imaging device shown in FIG. (A)-(C) are sectional drawings for demonstrating the manufacturing method of the solid-state imaging device shown in FIG. (A) is a plan view showing a solid-state imaging device according to one embodiment of the present invention, (B) is a cross-sectional view taken along line aa ′ shown in (A), and (C) is b- shown in (A). Sectional drawing along b 'line. The figure for demonstrating the charge transfer operation | movement of the solid-state imaging device shown in FIG. The figure for demonstrating the charge transfer operation | movement of the solid-state imaging device shown in FIG. The figure for demonstrating the charge transfer operation | movement of the solid-state imaging device shown in FIG. The figure for demonstrating the charge transfer operation | movement of the solid-state imaging device shown in FIG. FIG. 7 is a drive sequence diagram for explaining a charge transfer operation of the solid-state imaging device shown in FIG. 6. FIG. 2B is a cross-sectional view of the solid-state imaging device shown in FIG. (A), (B) is a figure which shows the potential height at the time of each of the transfer gate electrode and reset gate electrode in the conventional solid-state image sensor.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

[Embodiment 1]
1A is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line aa ′ illustrated in FIG. FIG. 1C is a cross-sectional view taken along the line bb ′ shown in FIG.

  A P-type well 12 is formed in an N-type silicon substrate 11 as a semiconductor substrate, and a LOCOS oxide film 13 as an element isolation film is formed in the P-type well 12. An active region 14 is formed inside the LOCOS oxide film 13. A P-type high concentration well 15 is formed under the LOCOS oxide film 13 and on the active region 14 side (element region side). The P-type high concentration well 15 is a well having a higher concentration than the P-type well 12. As a result, the P-type high concentration well 15 can also serve as a well for forming a pixel isolation region, and the element isolation function can be enhanced. In this embodiment, the LOCOS oxide film 13 is used as the element isolation film. However, the present invention is not limited to this, and other element isolation films such as a trench element isolation film can also be used.

  An N-type accumulation layer 17 is formed in the P-type well 12 located inside the P-type high concentration well 15. The N-type accumulation layer 17 is a layer for accumulating photoelectric conversion carriers, and constitutes a part of the photoelectric conversion element (photodiode) 23.

  A transfer gate electrode (hereinafter also referred to as “transfer electrode”) 21 is formed on the surface of the P-type well 12 via a gate insulating film 11 a, and the gate insulating film 11 b is formed on the surface of the P-type well 12. A reset gate electrode (hereinafter, also referred to as “reset electrode”) 22 is formed through the.

  An N-type low concentration diffusion layer 18 is formed in the P-type well 12 located inside the P-type high concentration well 15, and the N-type low concentration diffusion layer 18 is positioned between the transfer electrode 21 and the reset electrode 22. To do. The N-type low concentration diffusion layer 18 is formed in a self-aligned manner with respect to the LOCOS oxide film 13, the transfer electrode 21, and the reset electrode 22 positioned between the transfer electrode 21 and the reset electrode 22. An N-type medium concentration diffusion layer 19 is formed on the surface of the N-type low concentration diffusion layer 18, and an N-type floating diffusion layer 24 is formed by the N-type low concentration diffusion layer 18 and the N-type medium concentration diffusion layer 19. . That is, the N-type floating diffusion layer 24 is positioned between the LOCOS oxide films 13 and between the transfer electrode 21 and the reset electrode 22.

  The N-type floating diffusion layer 24 is connected to the N-type storage layer 17 by the transfer electrode 21. That is, the transfer electrode 21, the N-type storage layer 17, and the N-type floating diffusion layer 24 constitute a transfer transistor, and photoelectric conversion carriers are stored in the N-type storage layer 17 of the photoelectric conversion element 23. 21 is transferred to the N-type floating diffusion layer 24.

  An N-type high concentration diffusion layer 20 is formed in the P-type well 12 located inside the P-type high concentration well 15, and the N-type high concentration diffusion layer 20 is formed in a self-aligned manner with respect to the reset electrode 22. ing. The depth increases in the order of the N-type high-concentration diffusion layer 20, the N-type low-concentration diffusion layer 18, and the N-type storage layer 17 (see FIG. 1B).

  The N-type floating diffusion layer 24 is connected to the N-type high concentration diffusion layer 20 by the reset electrode 22. That is, the reset electrode 22, the N-type floating diffusion layer 24, and the N-type high concentration diffusion layer 20 constitute a reset transistor, and carriers temporarily stored in the N-type floating diffusion layer 24 are transferred to the N-type high concentration diffusion layer by the reset electrode 22. 20 is released.

  A P-type surface diffusion layer 16 is formed on the surface of the N-type accumulation layer 17 and the surface of the P-type high concentration well 15 adjacent to the N-type accumulation layer 17. The concentration of the P-type surface diffusion layer 16 is higher than the concentration of the P-type well 12. The P-type surface diffusion layer 16 also serves as a pinning layer provided to suppress dark current generated by thermally excited carriers that do not depend on light in the photoelectric conversion element 23.

  The P-type surface diffusion layer 16 is also formed on the surface of the N-type low concentration diffusion layer 18 and is continuously formed from the transfer electrode 21 to the reset electrode 22. The P-type surface diffusion layer 16 is formed by ion implantation using the transfer electrode 21, the reset electrode 22, the LOCOS oxide film 13 and a resist mask (not shown) as a mask. The opening area 16a of this resist mask is shown in FIG. The P-type surface diffusion layer 16 is formed on the active region 14 side (element region side) of the LOCOS oxide film 13. The P-type surface diffusion layer 16 is electrically connected to the P-type high concentration well 15, and the P-type high concentration well 15 is electrically connected to the P-type well 12. Thereby, the potential of the P-type well 12 can be transmitted to the surface.

  Further, the P-type surface diffusion layer 16 formed on the surface of the N-type low concentration diffusion layer 18 and the P-type surface diffusion layer 16 formed on the surface of the N-type accumulation layer 17 are formed by the same ion implantation process. The manufacturing process can be simplified and the manufacturing cost can be reduced.

  As shown in FIG. 1C, the P-type high concentration well 15 is formed at the boundary between the side surface of the N-type low concentration diffusion layer 18 of the N-type floating diffusion layer 24 and the P-type well 12. It is not formed on the bottom surface of the low concentration diffusion layer 18.

  The P-type high concentration well 15 has a direction perpendicular to the end of the active region 14 in the channel width direction of the transfer transistor, the end of the active region 14 in the channel width direction of the reset transistor, and the carrier transfer direction of the N-type floating diffusion layer 24. The active region 14 is continuously formed at the end.

  The P-type surface diffusion layer 16 has a direction perpendicular to the end of the active region 14 in the channel width direction of the transfer transistor, the end of the active region 14 in the channel width direction of the reset transistor, and the carrier transfer direction of the N-type floating diffusion layer 24. Including the end of the active region 14 and extending to the vicinity of the N-type medium concentration diffusion layer 19.

  According to the present embodiment, as shown in FIG. 1C, the N-type floating diffusion layer 24 is sandwiched between the P-type surface diffusion layer 16 and the P-type high-concentration well 15 of the opposite conductivity type. The periphery of the carrier accumulation region of the diffusion layer 24 can be depleted, and the capacity of the carrier accumulation region can be reduced. Therefore, the capacity of the N-type floating diffusion layer 24 can be reduced without sacrificing the transfer efficiency (regardless of the width of the transfer path).

  That is, even if the width of the transfer path is increased to increase the transfer efficiency, the N-type floating diffusion layer 24 is sandwiched between the P-type surface diffusion layer 16 and the P-type high concentration well 15, so The capacity of the carrier storage region can be reduced by depleting the periphery of the carrier storage region. Therefore, the conversion gain for converting the photoelectric conversion carrier into a voltage can be increased.

The above effect will be described in more detail.
FIG. 2 is a sectional view of the N-type low-concentration region 18 of the N-type floating diffusion layer 24 shown in FIG. 1C in which the P-type surface diffusion layer 16 and the P-type high concentration well 15 are eliminated.

  A depletion layer is formed by the P-type surface diffusion layer 16 and the P-type high-concentration well 15 in the N-type low-concentration diffusion layer 18 shown in FIG. 1C, whereas the N-type low-concentration diffusion layer shown in FIG. 18 does not have the P-type surface diffusion layer 16 and the P-type high-concentration well 15, such a depletion layer is not formed. Thereby, in the N-type floating diffusion layer 24 shown in FIG. 1C, the capacity (cross-sectional area) of the carrier accumulation region can be reduced. Since the relationship between the amount Q of accumulated carriers, the capacitance C of the carrier accumulation region, and the output voltage V is V = Q / C, if the capacitance C is reduced, the output voltage V can be obtained even if the number of carriers accumulated in the carrier accumulation region is the same. Can be high. Therefore, the conversion gain for converting the photoelectric conversion carrier into voltage can be increased.

  In order to realize a reduction in the capacity of the N-type floating diffusion layer 24, the concentration of each of the P-type surface diffusion layer 16 and the P-type high-concentration well 15 may not be higher than the concentration of the P-type well 12.

  The N-type storage layer 17 is connected to the N-type floating diffusion layer 24 by the transfer electrode 21. The N-type floating diffusion layer 24 is connected to the N-type concentration diffusion layer 20 by the reset electrode 22. The gate length L4 of the transfer electrode 21 is substantially the same as the gate length L3 of the reset electrode 22. Here, “L4 is substantially the same as L3” means that when the dimension L3 of the reset electrode 22 and the dimension L4 of the transfer electrode 21 are set to predetermined dimensions, they are within ± 14% of the predetermined dimension. It means that L3 and L4 are included.

  The gate width W4 of the transfer electrode 21 is substantially the same as the gate width W3 of the reset electrode 22. The gate width W3 and the gate width W4 correspond to the dimensions W3 and W4 of the active region 14 shown in FIG. Here, “W4 is substantially the same as W3” means that when W3 and W4 are set to predetermined dimensions, W3 and W4 are included within a range of ± 11% of the predetermined dimensions. means.

  The threshold voltage Vth3 of the transfer transistor including the N-type storage layer 17, the N-type floating diffusion layer 24, and the transfer electrode 21 includes the N-type floating diffusion layer 24, the N-type high concentration diffusion layer 20, and the reset electrode 22. This is substantially the same as the threshold voltage Vth4 of the reset transistor. Here, “Vth3 and Vth4 are substantially the same” means that when Vth3 and Vth4 are set to predetermined threshold values, Vth3 and Vth4 are within a range of ± 3.0% with respect to the predetermined threshold values. Means included.

  The film thickness T4 of the gate insulating film 11a is substantially the same as the film thickness T3 of the gate insulating film 11b. Here, “T4 is substantially the same as T3” means that when T3 and T4 are set to a predetermined thickness, T3 and T4 are included in a range within ± 10% of the predetermined thickness. Means that.

  The concentration of the impurity region 12 a located below the transfer electrode 21 in the P-type well 12 is substantially the same as the concentration of the impurity region 12 b located below the reset electrode 22 in the P-type well 12. Here, “the concentration of the impurity region 12a is substantially the same as the concentration of the impurity region 12b” means that the concentration of the impurity region 12a located below the transfer electrode 21 and the concentration of the impurity region 12b located below the reset electrode 22 are predetermined. When the concentration is set to, the concentration of the impurity region 12a and the concentration of the impurity region 12b are included in a range within ± 3% of the predetermined concentration.

Next, a method for manufacturing the solid-state imaging device shown in FIG. 1 will be described.
First, the LOCOS oxide film 13 is formed on the N-type silicon substrate 11. As a result, an active region 14 is formed inside the LOCOS oxide film 13. Next, the P-type well 12 is formed by ion implantation of impurities into the N-type silicon substrate 11. Next, impurities are ion-implanted into the P-type well 12 to form the P-type high concentration well 15. The P-type high concentration well 15 also functions as an isolation region.

  Next, the N-type accumulation layer 17, the N-type low concentration diffusion layer 18 of the N-type floating diffusion layer 24, and the N-type medium concentration diffusion layer 19 are formed by ion implantation of impurities into the P-type well 12.

  Thereafter, the surface of the N-type silicon substrate 11 is thermally oxidized to form gate oxide films to be the gate insulating films 11a and 11b on the surface of the N-type silicon substrate 11. Next, a polysilicon film is formed on the gate oxide film, and this polysilicon film is patterned by a photolithography technique and a dry etching technique. Thereby, the transfer electrode 21 is formed on the gate insulating film 11a, and the reset electrode 22 is formed on the gate insulating film 11b.

  Next, using the transfer electrode 21, the reset electrode 22, the LOCOS oxide film 13, and a resist mask (not shown) as a mask, impurities are ion-implanted into the N-type accumulation layer 17, thereby forming the P-type surface diffusion layer 16. Further, the N-type high concentration diffusion layer 20 is formed in the P-type well 12 in a self-aligning manner using the reset electrode 22 as a mask.

  According to the present embodiment, the gate length L4 of the transfer electrode 21 is substantially the same as the gate length L3 of the reset electrode 22, and the gate width W4 of the transfer electrode 21 is substantially the same as the gate width W3 of the reset electrode 22. In addition, the threshold voltage Vth3 of the transfer transistor including the N-type storage layer 17, the N-type floating diffusion layer 24, and the transfer electrode 21 is included in the N-type floating diffusion layer 24, the N-type high-concentration diffusion layer 20, and the reset electrode 22. It is substantially the same as the threshold voltage Vth4 of the reset transistor. As a result, as shown in FIG. 15, the potential height 38 when the transfer electrode 21 is off and the potential height 39 when the reset electrode 22 is off can be made substantially the same. As a result, it is possible to suppress a reduction in the capacitance of the N-type floating diffusion layer 24 by releasing some of the carriers accumulated in the N-type floating diffusion layer 24 when the transfer electrode 21 and the reset electrode 22 are off. In other words, the capacity of the N-type floating diffusion layer 24 can be maximized within a predetermined diffusion concentration. Further, when each of the transfer electrode 21 and the reset electrode 22 is turned off, it is possible to suppress a transfer residue in which a part of the carriers transferred from the transfer source to the N-type floating diffusion layer 24 by the transfer electrode 21 remains in the transfer source. FIG. 15 is a cross-sectional view of the solid-state imaging device illustrated in FIG. 1B and a diagram illustrating a charge transfer operation of the solid-state imaging device.

  Further, by making the film thickness T4 of the gate insulating film 11a substantially the same as the film thickness T3 of the gate insulating film 11b, the potential height when the transfer electrode 21 is off and the potential height when the reset electrode 22 is off are more identical. Can be approached. Thereby, the capacity | capacitance fall or transfer remaining of the N type floating diffusion layer 24 can be suppressed more.

  Further, the concentration of the impurity region 12 a located below the transfer electrode 21 in the P-type well 12 is made substantially the same as the concentration of the impurity region 12 b located below the reset electrode 22 in the P-type well 12. Thereby, the potential height when the transfer electrode 21 is off and the potential height when the reset electrode 22 is off can be made closer to the same. Thereby, the capacity | capacitance fall or transfer remaining of the N type floating diffusion layer 24 can be suppressed more.

  In the first embodiment, the P-type well 12 is replaced with the first conductivity type well, the N-type storage layer 17 is replaced with the fourth second-conductivity type diffusion layer, and the N-type floating diffusion layer 24 is replaced with the fifth conductivity type well. The second conductivity type diffusion layer is replaced with the N-type high concentration diffusion layer 20 as the sixth second conductivity type diffusion layer, the transfer electrode 21 is replaced with the first gate electrode, and the reset electrode 22 is replaced with the second gate electrode. May be read as:

[Embodiment 2]
FIG. 3 is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention, in which the same portions as those in FIG.

  The N-type low-concentration diffusion layer 18a of the N-type floating diffusion layer parallel to the longitudinal direction of the side surface of the reset electrode 22 facing the transfer electrode 21 has a width 51 on the reset electrode 22 side rather than a width 52 on the transfer electrode 21 side. Is wide. That is, the widths 51 and 52 of the N-type low concentration diffusion layer 18a correspond to the mutual interval of the P-type high concentration well 15a. By making the reset electrode 22 side wider, the width 51 of the N-type low concentration diffusion layer 18a on the reset electrode 22 side can be made wider than the width 52 of the N-type low concentration diffusion layer 18a on the transfer electrode 21 side.

Also in the present embodiment, the same effect as in the first embodiment can be obtained.
In addition, the width from the end of the active region 14 forming the P-type high concentration well 15a is decreased toward the reset transistor from the transfer transistor, thereby depleting the N-type low concentration diffusion layer 18a of the N-type floating diffusion layer. The area (cross-sectional area) to be converted can be increased. As a result, a potential profile in which carriers can easily flow can be formed. Therefore, carrier transfer is facilitated.

[Embodiment 3]
FIG. 4 is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention. The same portions as those in FIG.

  In the P-type surface diffusion layer parallel to the longitudinal direction of the side surface of the reset electrode 22 facing the transfer electrode 21, the width 53 on the reset electrode 22 side is narrower than the width 54 on the transfer electrode 21 side. Thereby, the width of the N-type low concentration diffusion layer 18 located between the P-type surface diffusion layers can be made wider on the reset electrode 22 side than on the transfer electrode 21 side.

  The P-type surface diffusion layer is formed by ion implantation using the transfer electrode 21, the reset electrode 22, the LOCOS oxide film 13 and a resist mask (not shown) as a mask. The resist mask opening region 16b is shown in FIG.

Also in the present embodiment, the same effect as in the first embodiment can be obtained.
In addition, the width from the end of the active region 14 forming the P-type surface diffusion layer is decreased toward the reset transistor from the transfer transistor, thereby depleting the N-type low concentration diffusion layer 18 of the N-type floating diffusion layer. The area (cross-sectional area) to be enlarged can be increased. As a result, a potential profile in which carriers can easily flow can be formed. Therefore, carrier transfer is facilitated.

[Embodiment 4]
5A is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line aa ′ illustrated in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

  The solid-state imaging device according to the present embodiment is different from the first embodiment in that the temporary carrier storage layer 32 and the transfer electrode 31 are disposed between the transfer electrode 21 and the N-type floating diffusion layer 24. That is, the transfer electrode 31 is formed on the surface of the P-type well 12 via the gate insulating film 11c, and the N-type accumulation layer 33 for temporarily accumulating carriers is formed in the P-type well 12. A P-type surface diffusion layer 16 is formed on the surface of the N-type accumulation layer 33.

  The N-type storage layer 33 is connected to the N-type storage layer 17 by the transfer electrode 21 and is connected to the N-type floating diffusion layer 24 by the transfer electrode 31. That is, the transfer electrode 21, the N-type storage layer 17, and the N-type storage layer 33 constitute a transfer transistor, and photoelectric conversion carriers are stored in the N-type storage layer 17 of the photoelectric conversion element 23. Is transferred to the N-type storage layer 33. The transfer electrode 31, the N-type floating diffusion layer 24 and the N-type storage layer 33 constitute a transfer transistor, and the carriers temporarily stored in the N-type storage layer 33 are transferred to the N-type floating diffusion layer 24 by the transfer electrode 31. The

Also in the present embodiment, the same effect as in the first embodiment can be obtained.
Further, by temporarily accumulating carriers in the N-type accumulation layer 33, it is possible to save time for performing other processes such as a reading process, and it becomes easy to control the operation of the batch electronic shutter and the resolution.

[Embodiment 5]
6A is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along the line aa ′ illustrated in FIG. 6C is a cross-sectional view taken along the line bb ′ shown in FIG. 6A. The same reference numerals are given to the same portions as those in FIG. 5, and only different portions will be described.

  The solid-state imaging device according to the present embodiment differs from the fourth embodiment in that a barrier electrode 35 is formed on the surface of the N-type low concentration diffusion layer 18 of the N-type floating diffusion layer via the gate insulating film 11d. The barrier electrode 35 is located next to the transfer electrode 31.

  In the present embodiment, by fixing the barrier electrode 35 to the ground potential (GND), a barrier for transferring carriers temporarily stored in the N-type storage layer 33 to the N-type floating diffusion layer 24 by the transfer electrode 31 is provided. Can be made. This facilitates high-speed processing such as shortening the readout time and helps reduce noise.

  The N-type low concentration diffusion layer 18 is connected to the N-type medium concentration diffusion layer 19 by a barrier electrode 35. That is, the transfer electrode (first transistor) is configured by the barrier electrode 35, the N-type low concentration diffusion layer 18, and the N-type medium concentration diffusion layer 19. The N-type medium concentration diffusion layer 19 is connected to the N-type high concentration diffusion layer 20 by a reset electrode 22. That is, the reset electrode 22, the N-type medium concentration diffusion layer 19, and the N-type high concentration diffusion layer 20 constitute a reset transistor (second transistor). The gate length L2 of the barrier electrode 35 is substantially the same as the gate length L1 of the reset electrode 22. Here, “L2 is substantially the same as L1” means that when the dimension L1 of the reset electrode 22 and the dimension L2 of the barrier electrode 35 are set to predetermined dimensions, they are within ± 14% of the predetermined dimension. It means that L1 and L2 are included.

  The gate width W2 of the barrier electrode 35 is substantially the same as the gate width W1 of the reset electrode 22. The gate width W1 and the gate width W2 correspond to the dimensions W1 and W2 of the active region 14 shown in FIG. Here, “W2 is substantially the same as W1” means that when W1 and W2 are set to predetermined dimensions, W1 and W2 are included in a range within ± 11% of the predetermined dimensions. means.

  The threshold voltage Vth1 of the first transistor including the N-type low-concentration diffusion layer 18, the N-type medium-concentration diffusion layer 19 and the barrier electrode 35 is the N-type medium-concentration diffusion layer 19 and the N-type high-concentration diffusion layer 20. The threshold voltage Vth2 of the second transistor including the reset electrode 22 is substantially the same. Here, “Vth1 is substantially the same as Vth2” means that when Vth1 and Vth2 are set to predetermined threshold values, Vth1 and Vth2 are within a range of ± 3.0% with respect to the predetermined threshold values. Means included.

  The film thickness T2 of the gate insulating film 11d is substantially the same as the film thickness T1 of the gate insulating film 11b. Here, “T2 is substantially the same as T1” means that when T1 and T2 are set to a predetermined thickness, T1 and T2 are included in a range within ± 10% of the predetermined thickness. Means that.

  The concentration of the impurity region 18 b located below the barrier electrode 35 in the N-type low concentration diffusion layer 18 is substantially the same as the concentration of the impurity region 18 c located below the reset electrode 22 in the N-type low concentration diffusion layer 18. Here, “the concentration of the impurity region 18 b is substantially the same as the concentration of the impurity region 18 c” means that the concentration of the impurity region 18 b located below the barrier electrode 35 and the concentration of the impurity region 18 c located below the reset electrode 22 are predetermined. When the concentration is set to, the concentration of the impurity region 18b and the concentration of the impurity region 18c are included in a range within ± 3% of the predetermined concentration.

  7 and 8 are cross-sectional views for explaining a method of manufacturing the solid-state imaging device shown in FIG.

  First, as shown in FIG. 7A, a LOCOS oxide film 13 is formed on an N-type silicon substrate 11. As a result, an active region 14 is formed inside the LOCOS oxide film 13. Next, the P-type well 12 is formed by ion implantation of impurities into the N-type silicon substrate 11. Next, impurities are ion-implanted into the P-type well 12 to form the P-type high concentration well 15. The P-type high concentration well 15 also functions as an isolation region.

  Next, as shown in FIG. 7B, by implanting impurities into the P-type well 12, the N-type accumulation layers 17, 33, the N-type low-concentration diffusion layer 18 of the N-type floating diffusion layer, and the N-type medium A concentration diffusion layer 19 is formed.

  Thereafter, as shown in FIG. 8A, the surface of the N-type silicon substrate 11 is thermally oxidized to form gate insulating films 11a, 11b, 11c, and 11d on the surface of the N-type silicon substrate 11. Form. Next, a polysilicon film is formed on the gate oxide film, and this polysilicon film is patterned by a photolithography technique and a dry etching technique. As a result, the transfer electrode 21 is formed on the gate insulating film 11a, the reset electrode 22 is formed on the gate insulating film 11b, the transfer electrode 31 is formed on the gate insulating film 11c, and the gate electrode 11d is formed on the gate insulating film 11d. A barrier electrode 35 is formed.

  Next, as shown in FIGS. 8B and 8C, N-type accumulation is performed using the transfer electrodes 21 and 31, the barrier electrode 35, the reset electrode 22, the LOCOS oxide film 13 and a resist mask (not shown) as a mask. Impurity ions are implanted into the layers 17 and 33 and the N-type low-concentration diffusion layer 18 to form the P-type surface diffusion layer 16. The resist mask used at this time has an opening region 16c shown in FIG. Further, the N-type high concentration diffusion layer 20 is formed in the N-type low concentration diffusion layer 18 in a self-aligning manner using the reset electrode 22 as a mask.

  According to the present embodiment, the gate length L2 of the barrier electrode 35 is substantially the same as the gate length L1 of the reset electrode 22, and the gate width W2 of the barrier electrode 35 is substantially the same as the gate width W1 of the reset electrode 22. Further, the threshold voltage Vth1 of the first transistor including the N-type low-concentration diffusion layer 18, the N-type medium-concentration diffusion layer 19, and the barrier electrode 35 is set to the N-type medium-concentration diffusion layer 19 and the N-type high-concentration diffusion layer 20. The threshold voltage Vth2 of the second transistor including the reset electrode 22 is substantially the same. Thereby, the potential height when the barrier electrode 35 is off and the potential height when the reset electrode 22 is off can be made substantially the same. As a result, it is possible to suppress a reduction in the capacity of the N-type medium concentration diffusion layer 19 due to the emission of some of the carriers accumulated in the N-type medium concentration diffusion layer 19 when the barrier electrode 35 and the reset electrode 22 are off. In other words, the capacity of the N-type medium concentration diffusion layer 19 can be maximized within a predetermined diffusion concentration. Further, when each of the barrier electrode 35 and the reset electrode 22 is off, it is possible to suppress a transfer residue in which a part of the carriers transferred from the transfer source to the N-type medium concentration diffusion layer 19 by the barrier electrode 35 is left at the transfer source.

  Further, by making the film thickness T2 of the gate insulating film 11d substantially the same as the film thickness T1 of the gate insulating film 11b, the potential height when the barrier electrode 35 is off and the potential height when the reset electrode 22 is off are more identical. Can be approached. Thereby, the capacity | capacitance fall of the N type medium concentration diffusion layer 19 or a transfer remainder can be suppressed more.

  In addition, the concentration of the impurity region 18 b located below the barrier electrode 35 in the N-type low concentration diffusion layer 18 is substantially the same as the concentration of the impurity region 18 c located below the reset electrode 22 in the N-type low concentration diffusion layer 18. To do. Thereby, the potential height when the barrier electrode 35 is off and the potential height when the reset electrode 22 is off can be made closer to the same. Thereby, the capacity | capacitance fall of the N type medium concentration diffusion layer 19 or a transfer remainder can be suppressed more.

  In the present embodiment, the P-type surface diffusion layer 16 also serves as a P-type surface diffusion layer 16 formed on the surface of the N-type low-concentration diffusion layer 18 and a pinning layer formed on the surfaces of the N-type accumulation layers 17 and 33. By forming the layer 16 in the same ion implantation process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[Embodiment 6]
9A is a plan view illustrating a solid-state imaging device according to one embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along the line aa ′ illustrated in FIG. 9A. 9C is a cross-sectional view taken along the line bb ′ shown in FIG. 9A. The same reference numerals are given to the same portions as FIG. 6, and only different portions will be described.

  In the solid-state imaging device according to the present embodiment, the opening region 16d of the resist mask when forming the P-type surface diffusion layer 16 is as shown in FIG. 9A, and the opening region 16c shown in FIG. And different. That is, in the resist mask opening region 16d shown in FIG. 9A, the N-type intermediate concentration diffusion layer 19 and its periphery are not opened, whereas in the resist mask opening region 16c shown in FIG. The N-type intermediate concentration diffusion layer 19 and its periphery and the barrier electrode 35 to the reset electrode 22 are not continuously opened.

  Also in this embodiment, the same effect as in the fifth embodiment can be obtained.

[Embodiment 7]
10 to 13 are diagrams for explaining the charge transfer operation of the solid-state imaging device shown in FIG. FIG. 14 is a drive sequence for explaining the charge transfer operation of the solid-state imaging device shown in FIG.

  As shown in FIG. 10, charges are accumulated in the photodiode, and charges are temporarily accumulated in the N-type accumulation layer 33 (0). Next, the charge accumulated in the N-type floating diffusion layer is reset by the reset transistor Rst Tr (1). This corresponds to the reset operation of the first pixel shown in FIG.

  Next, as shown in FIG. 11, the charge accumulated in the N-type accumulation layer 33 is turned on by turning the second transfer gate over the low-density accumulation region of the second transfer gate and the N-type low-concentration diffusion layer 18. Transfer to the wrap area (2). This corresponds to the second transfer operation of the first pixel shown in FIG. Next, with the second transfer gate remaining On, the potential level of the N-type floating diffusion layer is read by the source follower of the amplification transistor, and the Noise level is read (3). This corresponds to the noise readout of the first pixel shown in FIG.

  Next, as shown in FIG. 12, the charge of the overlap region of the second transfer gate and the low concentration accumulation region of the N type low concentration diffusion layer 18 is turned off by turning off the second transfer gate. Transfer to the N-type low concentration diffusion layer 18 (4). At this time, the potential height 36 when the barrier electrode 35 is off and the potential height 37 when the reset electrode 22 is off are substantially the same. For this reason, it is possible to suppress a reduction in the capacity of the N-type floating diffusion layer due to the release of some of the carriers accumulated in the N-type floating diffusion layer. Further, when each of the barrier electrode 35 and the reset electrode 22 is off, it is possible to suppress a transfer residue in which a part of the carriers transferred from the transfer source to the N-type floating diffusion layer by the barrier electrode 35 remains in the transfer source. This corresponds to the third transfer operation of the first pixel shown in FIG. Next, when the second transfer gate is turned off, the potential level of the N-type floating diffusion layer is read by the source follower of the amplification transistor to read the signal level (5). This corresponds to the signal readout of the first pixel shown in FIG.

  Next, as shown in FIG. 13, the charge accumulated in the photodiode is transferred to the N-type accumulation layer 33, which is a temporary accumulation layer, by turning off the first transfer gate (6). Next, charges are accumulated in the photodiode (0).

  In various aspects of the present invention, when a specific B (hereinafter referred to as “B”) is formed above (or below) a specific A (hereinafter referred to as “A”) (B is formed), It is not limited to the case where B is formed directly on (or below) A (B is formed). It includes the case where B is formed (otherwise B) is formed on the upper side (or the lower side) of A through other things as long as the effects of the present invention are not inhibited.

  In the first to seventh embodiments, the P-type well 12 is replaced with the first conductivity type well, the N-type low concentration diffusion layer 18 is replaced with the first second conductivity type diffusion layer, and the N-type medium concentration diffusion is obtained. The layer 19 is read as the second second conductivity type diffusion layer, the N-type high concentration diffusion layer 20 is read as the third second conductivity type diffusion layer, the barrier electrode 35 is read as the first gate electrode, and the reset electrode 22 May be read as the second gate electrode.

  Moreover, it is also possible to implement combining said Embodiment 1-7 suitably.

  DESCRIPTION OF SYMBOLS 11 ... N-type silicon substrate, 11a, 11b, 11c, 11d ... Gate insulating film, 12 ... P-type well, 13 ... LOCOS oxide film, 14 ... Active region, 15, 15a ... P-type high concentration well, 16 ... P-type Surface diffusion layer, 16a, 16b, 16c, 16d ... opening region of resist mask, 17 ... N-type accumulation layer, 18, 18a ... N-type low concentration diffusion layer, 18b, 18c ... impurity region, 19 ... N-type medium concentration diffusion 20 ... N-type high-concentration diffusion layer, 21 ... Transfer electrode, 22 ... Reset electrode, 23 ... Photoelectric conversion element (photodiode), 24 ... N-type floating diffusion layer, 31 ... Transfer electrode, 32 ... Temporary carrier accumulation layer 33 ... N-type storage layer, 35 ... barrier electrode, 36, 37, 38, 39 ... potential height, 51 ... width on the reset electrode side of the N-type low concentration diffusion layer, 52 ... transfer of the N-type low concentration diffusion layer Electrode side Width, 53... P-type surface diffusion layer on the reset electrode side, 54... P-type surface diffusion layer on the transfer electrode side, L 1, L 3, reset electrode gate length, L 2, barrier electrode gate length, L 4. Transfer electrode gate length, W1, W3 ... Reset electrode gate width, W2 ... Barrier electrode gate width, W4 ... Transfer electrode gate width, T1, T3 ... Gate insulating film 11b thickness, T2 ... Gate insulating film 11d , T4... The thickness of the gate insulating film 11a.

Claims (8)

A first second conductivity type diffusion layer;
A first gate insulating film formed on the first second conductivity type diffusion layer;
A first gate electrode formed on the first gate insulating film;
A second second conductivity type diffusion layer formed in the first second conductivity type diffusion layer;
A second gate insulating film formed on the first second conductivity type diffusion layer;
A second gate electrode formed on the second gate insulating film;
A third second conductivity type diffusion layer formed in the first second conductivity type diffusion layer;
Have
The first second conductivity type diffusion layer is connected to the second second conductivity type diffusion layer by the first gate electrode;
The second second conductivity type diffusion layer is connected to the third second conductivity type diffusion layer by the second gate electrode,
The gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode;
The gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode;
The threshold voltage of the first transistor including the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the first gate electrode is the second second conductivity type diffusion. A solid-state imaging device having substantially the same threshold voltage as a second transistor including a layer, the third second conductivity type diffusion layer, and the second gate electrode. In claim 1,
The solid-state imaging device, wherein the first second conductivity type diffusion layer is formed in a first conductivity type well. A first conductivity type well;
A fourth second conductivity type diffusion layer formed in the first conductivity type well;
A first gate insulating film formed on the first conductivity type well;
A first gate electrode formed on the first gate insulating film;
A fifth second conductivity type diffusion layer formed in the first conductivity type well;
A second gate insulating film formed on the first conductivity type well;
A second gate electrode formed on the second gate insulating film;
A sixth second conductivity type diffusion layer formed in the first conductivity type well;
Have
The fourth second conductivity type diffusion layer is connected to the fifth second conductivity type diffusion layer by the first gate electrode;
The fifth second conductivity type diffusion layer is connected to the sixth second conductivity type diffusion layer by the second gate electrode;
The gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode;
The gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode;
The threshold voltage of the first transistor including the fourth second conductivity type diffusion layer, the fifth second conductivity type diffusion layer, and the first gate electrode is the fifth second conductivity type diffusion. The solid-state imaging device is characterized by being substantially the same as a threshold voltage of a second transistor including a layer, the sixth second conductivity type diffusion layer, and the second gate electrode. In any one of Claims 1 thru | or 3,
The film thickness of the first gate insulating film is substantially the same as the film thickness of the second gate insulating film. In claim 1 or 2,
The concentration of the impurity region located below the first gate electrode in the first second conductivity type diffusion layer is located below the second gate electrode in the first second conductivity type diffusion layer. A solid-state imaging device having substantially the same concentration as an impurity region. In claim 3,
The concentration of the impurity region located below the first gate electrode in the first conductivity type well is substantially the same as the concentration of the impurity region located below the second gate electrode in the first conductivity type well. There is a solid-state imaging device. Forming a second second conductivity type diffusion layer in the first second conductivity type diffusion layer;
Forming a first gate insulating film and a second gate insulating film on the first second conductivity type diffusion layer;
Forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film;
Forming a third second conductivity type diffusion layer in the first second conductivity type diffusion layer in a self-aligned manner with respect to the second gate electrode;
Have
The first second conductivity type diffusion layer is connected to the second second conductivity type diffusion layer by the first gate electrode;
The second second conductivity type diffusion layer is connected to the third second conductivity type diffusion layer by the second gate electrode,
The gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode;
The gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode;
The threshold voltage of the first transistor including the first second conductivity type diffusion layer, the second second conductivity type diffusion layer, and the first gate electrode is the second second conductivity type diffusion. A method of manufacturing a solid-state imaging device, wherein the threshold voltage of a second transistor including a layer, the third second conductivity type diffusion layer, and the second gate electrode is substantially the same. Forming a fourth second conductivity type diffusion layer and a fifth second conductivity type diffusion layer in the first conductivity type well;
Forming a first gate insulating film and a second gate insulating film on the first conductivity type well;
Forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film;
Forming a sixth second conductivity type diffusion layer in the first conductivity type well in a self-aligned manner with respect to the second gate electrode;
Have
The fourth second conductivity type diffusion layer is connected to the fifth second conductivity type diffusion layer by the first gate electrode;
The fifth second conductivity type diffusion layer is connected to the sixth second conductivity type diffusion layer by the second gate electrode;
The gate length of the first gate electrode is substantially the same as the gate length of the second gate electrode;
The gate width of the first gate electrode is substantially the same as the gate width of the second gate electrode;
The threshold voltage of the first transistor including the fourth second conductivity type diffusion layer, the fifth second conductivity type diffusion layer, and the first gate electrode is the fifth second conductivity type diffusion. A method of manufacturing a solid-state imaging device, wherein the threshold voltage of a second transistor including a layer, the sixth second conductivity type diffusion layer, and the second gate electrode is substantially the same.

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