JP2017146878A - Difference analysis device, difference analysis method, and difference analysis program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set the content of a difference after making them change according to the necessity when performing the extraction of the difference between a plurality of drawings.SOLUTION: A difference analysis device receives a rule for defining equivalence of a logic, receives a first logic drawing and a second logic drawing created by using the logic, converts the first logic drawing into a first directed graph by extracting an element and a signal line from the first logic drawing, converts the second logic drawing into a second directed graph by extracting the element and the signal line from the second logic drawing, corrects the first directed graph or the second directed graph converted based on a received rule, and compares the first directed graph with the second directed graph after the conversion or compares the second directed graph with the first directed graph after the conversion, and thereby extracting a difference between the first logic drawing and the second logic drawing so as to display the extracted difference on the screen.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a difference analysis apparatus, a difference analysis method, and a difference analysis program.

  Drawings related to equipment are frequently revised at the time of design and delivery. The corrected drawing is often created by partially correcting the drawing before correction, and at first glance, it cannot be distinguished from the drawing before correction. Therefore, it is extremely important to know the difference between similar drawings from the viewpoint of preventing device design errors and defects.

  The logic drawing processing apparatus of Patent Literature 1 compares a plurality of logic drawings that indicate the contents of monitoring control performed by a monitoring control system on a device. Specifically, the logic drawing processing apparatus of Patent Document 1 extracts different control logic between two logic drawings to be compared, and positions of operation elements of the extracted control logic (coordinate values on the logic drawing). Is detected. Then, the calculation elements are rearranged so that the outer shapes of the calculation elements overlap, the two logic drawings are superimposed, and a common part or a difference of the calculation elements is displayed in a predetermined method.

Japanese Patent No. 5591271

  In actual design sites, the definition of differences between drawings becomes a problem. For example, when creating a logic drawing for controlling a plant, the content of the difference that should be substantially differentiated varies in each stage of design. Even if the arithmetic functions of the entire logic are equivalent, it may be determined that there is a difference if the configuration of the arithmetic elements that realize the logic is different, but it may not be determined as such. Also, when an attribute value is set for a certain calculation element, the difference in attribute value is ignored in the upstream design stage, while the difference in set value is ignored in the downstream site adjustment stage. I don't get it. Furthermore, even if the configuration of the calculation elements is the same, it may be determined that a difference has occurred if the positions of the calculation elements on the logic drawing are different.

The logic drawing processing apparatus of Patent Document 1 displays a difference between two arithmetic elements having different control logics, for example, “OR (logical sum)” and “NOT (negative)”. However, the logic drawing processing apparatus of Patent Document 1 does not assume that the contents of differences that should be substantially differentiated are changed in various ways depending on the design stage. It has become. For example, a difference to be distinguished may not be displayed at a certain stage of design, and a difference that does not need to be distinguished may be displayed at another stage.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to change and set the contents of differences as necessary when extracting differences between a plurality of drawings.

The difference analysis apparatus of the present invention includes a rule receiving unit that receives a rule that defines logic equivalence, a logic drawing receiving unit that receives a first logic drawing and a second logic drawing created using the logic, The first logic drawing is converted into a first directed graph by extracting elements and signal lines from the first logic drawing, and the second logic drawing is extracted by extracting elements and signal lines from the second logic drawing. A directed graph creating unit for converting to a second directed graph, an equivalent correcting unit for correcting the converted first directed graph or correcting the converted second directed graph based on the received rule, and a first directed graph and correction By comparing the second directed graph afterwards, or by comparing the second directed graph with the corrected first directed graph, A difference extracting part for extracting first logic drawing and the difference between the second logic drawing, a difference display processing unit for displaying the extracted difference in the screen, characterized in that it comprises a.
Other means will be described in the embodiment for carrying out the invention.

  According to the present invention, when extracting a difference between a plurality of drawings, the contents of the difference can be changed and set as necessary.

It is a figure explaining a logic drawing. (A) And (b) is a figure explaining a directed graph. (A) And (b) is a figure explaining the equivalent correction by a partial directed graph. It is an example of the directed graph used as a difference extraction object. It is an example of node corresponding information. It is a figure explaining the structure of a difference analyzer. (A) And (b) is an example of the logic drawing used as a difference extraction object. (A) and (b) are examples of element information. (A) And (b) is an example of signal line information. (A) and (b) are examples of node information. (A) and (b) are examples of link information. It is a flowchart of a processing procedure. It is an example of an equivalence rule input screen. It is another example of an equivalence rule input screen. It is an example of a similarity evaluation rule input screen. (A) is an example of node information at the time of equivalent correction, and (b) is an example of link information at the time of equivalent correction. It is an example of node correction information. It is an example of a difference display screen. It is another example of a difference display screen. It is a figure explaining the modification 1. FIG.

  Hereinafter, a mode for carrying out the present invention (referred to as “the present embodiment”) will be described in detail with reference to the drawings. In the present embodiment, the difference analysis apparatus compares a plurality of logic drawings used for plant control.

(Logic drawing)
The logic drawing will be described with reference to FIG. In general, a “logic drawing” is a drawing that schematically represents a logic process for a signal. The logic drawing LG (FIG. 1) of the present embodiment is for generating a signal output to a display circuit and a device control circuit of a plant based on a signal input from a plant operating device. The logic drawing LG has a plurality of elements 51c and the like and a plurality of signal lines L03 and the like (details will be described later immediately). A signal is propagated through the signal line. The signal in this embodiment is either “0” or “1”.

  The “element” is a general term for graphics that mean operations / operations such as input / output, operations on signals, device configuration, and the like, and corresponds to reference numerals 51a to 51p in FIG. Among them, when an element means an operation on a signal as indicated by reference numerals 51f to 51j, the element is particularly called an “operation element”. Elements and calculation elements may have various shapes (rectangles, circles, triangles, and the like) depending on the contents of the calculation and the like, but the shapes here are unified into rectangles for simplicity. The “type” of an element is a character string (such as “OR”) attached to the element, and the character string indicates the contents of operations / operations such as input / output, operations on signals, and device configuration. . A specific example of the element type will be described below.

(Element type)
Among the elements, “IN” 51c and the like are input points from the operation unit or the like. Among the elements, “OUT” 51k and the like are output points to the display circuit 51n and the device control circuit. Note that “51A01” or the like written in the vicinity of “IN” and “OUT” is the name of the signal. Among the elements, “open” 51a is an operation for setting the operating device to “open”. “Lock” 51b among the elements is an operation of “locking” the operating device. Among the elements, “OPEN” 51o is an operation in which the device control circuit becomes “OPEN”. Among the elements, “LOCK” 51p is an operation in which the device control circuit becomes “LOCK”.

  Among the calculation elements, “AND” (not applicable in FIG. 1) outputs a signal “1” when all of a plurality of input signals are “1”, and outputs “0” otherwise. This is the operation (logical product) to be output. Among the calculation elements, “OR” 51j outputs a signal “1” when at least one of a plurality of input signals is “1”, and outputs “0” otherwise. Sum). Among the computation elements, “NOT” 51f and the like output a signal “0” when the input signal is “1”, and output a signal “1” when the input signal is “0”. Operation (negative). “T” 51i is a calculation (timer) that temporarily holds an input signal and outputs the signal as it is when a predetermined time (standby time) has elapsed from the time the signal is input. is there.

  A “signal line” is a graphic showing a path when a signal is propagated from one element to another. The signal line L03 and the like may have various shapes (a solid line, a broken line, a dotted line, and the like) depending on the content of the propagated signal. However, for the sake of simplicity, the shape here is unified with a solid line arrow.

  The “port” of an element is a receiving port of the element defined for each other element when the element receives signals from a plurality of other elements. For example, in FIG. 1, one arithmetic element “OR” 51j receives a signal from each of three different arithmetic elements “NOT” 51f, “NOT” 51g, and “NOT” 51h. In this case, the arithmetic element “OR” 51j includes “port 1”, “port 2”, and “port 3”. Port 1 receives a signal from "NOT" 51f, port 2 receives a signal from "NOT" 51g, and port 3 receives a signal from "NOT" 51h.

  Similarly to such an input side port, when an element outputs a signal to a plurality of other elements, an outlet of the element defined for each other element is referred to as a “port” (output side port). ).

(Directed graph)
A directed graph will be described with reference to FIG. The “directed graph” is a drawing obtained by extracting features such as each element, each element type, and each signal line in the logic drawing. The logic drawing LG (FIG. 1) is intended to be drawn and visually recognized by the user to the last, and as a result, the difference analysis device has somewhat redundant data (image data, etc.) for high-speed processing. ing. The directed graph has a minimum amount of data suitable for high-speed processing by the differential analyzer, and can be displayed with a simple configuration of “node” and “link” (details will be described later immediately).

  The directed graph BG in FIG. 2A is an example in which the features of the logic diagram LG in FIG. 1 are extracted. A “node” is a figure corresponding to an element in a logic drawing. The element can have various shapes, but any shape element is usually converted into a node 51c or the like having one type of shape (for example, a circle). A “link” is a figure corresponding to a signal line in a logic drawing. The signal line can have various shapes, but any shape of the signal line is usually converted into a link L03 having one type of shape (for example, a solid arrow).

  The node describes the type of element in the logic drawing. The type described in this way (such as “IN”) is also called the “type” of the node. Nodes can also be associated with attributes of elements in the logic drawing. The attribute associated in this way is called a “label” of the node. The link may be associated with a port on the input side or a port on the output side of the signal line in the logic drawing. The attribute associated in this way is called a “label” of the link. FIG. 2B will be described later.

(Equivalent transformation in directed graph)
The equivalent transformation by the partial directed graph will be described with reference to FIGS. 3 (a) and 3 (b). A part of the directed graph is called a “partially directed graph”. The partial directed graph includes a part of many nodes and links constituting the directed graph. The partially directed graph BGa in FIG. 3A and the partially directed graph BGb in FIG. 3B are examples of the partially directed graph. The following can be seen from the partially directed graph BGa.

There are a node “NOT” 61a, a node “NOT” 61b, a node “NOT” 61c, and a node “OR” 61d.
There is a link 62a that ends at the node “NOT” 61a. It is unknown which other node the link 62a starts from.
Similarly, there is a link 62b that ends with the node “NOT” 61b and a link 62c that ends with the node “NOT” 61c. It is unknown which other node the link 62b and the link 62c starts from.
There is a link 62d starting from the node “NOT” 61a and ending at the node “OR” 61d.
Similarly, there is a link 62e starting from the node "NOT" 61b and ending with the node "OR" 61d, and a link 62f starting from the node "NOT" 61c and ending with the node "OR" 61d.

The partial digraph BGb shows the following.
Node “AND” 63a and node “NOT” 63b exist.
There are three links 64a, 64b, and 64c that end at the node “AND” 63a. It is unknown which other node the link 64a, the link 64b, and the link 64c starts from.
There is a link 64d starting from the node “AND” 63a and ending at the node “NOT” 63b.

  Actually, the partially directed graph BGa in FIG. 3A and the partially directed graph BGb in FIG. 3B are logically completely equivalent. In the partially directed graph BGa, the signal to the node “NOT” 61a, the signal to the node “NOT” 61b, and the signal to the node “NOT” 61c are “1”, “0”, and “1”, respectively. And Then, the signal from the node “NOT” 61a to the node “OR” 61d, the signal from the node “NOT” 61b to the node “OR” 61d, and the signal from the node “NOT” 61c to the node “OR” 61d are: They are “0”, “1”, and “0”, respectively. Further, the node “OR” 61d receives these signals and outputs “1”.

  In the partially directed graph BGb, it is assumed that the three signals to the node “AND” 63a are “1”, “0”, and “1”, respectively. Then, the signal output from the node “AND” 63a to the node “NOT” 63b is “0”. Further, the node “NOT” 63b receives these signals and outputs “1”.

  Even if other signal examples (there are six combinations) are used, as a result, the signal output from the node “OR” 61d is equal to the signal output from the node “NOT” 63b. In other words, it is logically guaranteed that “logical OR of negation is equivalent to negation of AND”. The broken-line rectangle and “N” in FIGS. 3A and 3B will be described later.

  Often, one partially directed graph changes to another partially directed graph that is equivalent to each other. This is because even if the overall function of the logic drawing is the same, the portion of the logic drawing changes according to other design conditions given to the user (designer). For example, assume that the number of nodes is limited to a maximum of four as a condition for performing certain processing on a signal. In this case, the designer can connect the node and the link as in the partially directed graph BGa in FIG. However, when the number of nodes is limited to a maximum of two, the designer may consider connecting nodes and links as in the partially directed graph BGb in FIG. In addition, since the number of ports on the input side of a certain node (for example, node 61d) is not particularly limited, the user designed as shown in FIG. However, when the number of ports on the input side of the port is limited to “1”, the user may change the design to FIG.

  When the difference analysis device considers that “the partial directed graph BGa is equivalent to the partial directed graph BGb”, even if there is a difference between the two, strictly speaking, the difference analysis device regards this as a difference. Do not extract. The user applies such an equivalence rule if it can ignore such a difference in detail (a slight difference in design). That is, when the above-described minute difference may be ignored, the difference analysis apparatus corrects the directed graph BG in FIG. 2A to the directed graph BGm in FIG.

  The directed graph BGd in FIG. 4 is one of the two directed graphs to be compared (comparison destination). The following explanation is made by comparing the case where the other (comparison source) of the two directed graphs to be compared is the directed graph BG in FIG. 2A and the directed graph BGm in FIG. to continue.

(Comparison of FIG. 2 (a) and FIG. 4)
The difference analyzer extracts the following differences.
Difference ♭ 1: In the directed graph BG, three nodes “NOT” 51f, 51g, and 51h are connected to the node “OR” 51j, while in the directed graph BGd, the node “AND” 52i has three links. And connected to the node “NOT” 52k.
Difference ♭ 2: The number of nodes “IN” is three in the directed graph BG, while it is four in the directed graph BGd.
Difference ♭ 3: A node “OR” 53g that does not exist in the directed graph BG exists in the directed graph BGd.

(Comparison between FIG. 2B and FIG. 4)
The difference analysis apparatus extracts the difference ♭ 2 and the difference ♭ 3, but does not extract the difference ♭ 1. This is because the difference ♭ 1 is set in the equivalence rule as a slight design difference.

(Similarity and difference extraction)
FIG. 5 is an example of the node correspondence information 36. The difference analysis apparatus creates node correspondence information 36 when comparing two directed graphs. Here, for the sake of simplicity of explanation, the difference analysis apparatus determines that each of the three nodes “IN” of the directed graph BGm (FIG. 2B) has four nodes “IN” of the directed graph BGd (FIG. 4). An example of determining which one of them corresponds to will be described.

  The difference analysis apparatus assigns the correspondence on the premise that “each node“ IN ”of the directed graph BGm and each node“ IN ”of the directed graph BGd correspond one-to-one”. Then, one of the four nodes “IN” of the directed graph BGd is extracted as “difference” having no counterpart. There are 4 × 3 × 2 = 24 candidates for such combinations of correspondence relationships. The difference analysis apparatus determines a candidate having the maximum similarity among the 24 candidates, and extracts a node having no counterpart as a difference in the candidate combination.

  In FIG. 5, for example, “<51c, 52c>” indicates the correspondence between the node 51c of the directed graph BGm and the node 52c of the directed graph BGd. For this “<51c, 52c>”, “I <51c, 52c>” and “W <51c, 52c>” are defined.

I <51c, 52c> is either “1” or “0”. “1” indicates that the difference analysis apparatus considers that the node 51c and the node 52c correspond to each other. “0” indicates that the difference analysis apparatus considers that the node 51c and the node 52c do not correspond to each other. Similarly, when “I <51c, 52d>”, “I <51c, 52e>” and “I <51c, 52f>” are defined, the following constraint equation is established between them.
I <51c, 52c> + I <51c, 52d> + I <51c, 52e> + I <51c, 52f> ≦ 1

The meaning of the constraint equation is as follows.
• The left side of the constraint expression must be “1” or “0”.
That is, the node 51c corresponds to any one of the nodes 52c, 52d, 52e, and 52f, or the node 51c does not correspond to any of the nodes 52c, 52d, 52e, and 52f.
The constraint equation is a constraint equation based on the node 51c. Since there are seven nodes (nodes 51c, 51d, 51e, 52c, 52d, 52e, and 52f), there are also seven constraint equations.

W <51c, 52c> is an “evaluation coefficient” obtained by quantifying how similar the two nodes 51c and 52c are, and the evaluation coefficient is calculated based on the following similarity evaluation rule, for example. .
Similarity evaluation rule # 1: If the type of the link destination node is the same, W = “10”. If the type of the link destination node is different, W = “0”.

Similarity evaluation rule # 2: If the type of the link destination node belongs to the same group, W = “2”. If the link destination node does not belong to the same group, W = “0”. The difference analysis apparatus accepts a user setting ““ AND ”,“ OR ”, and“ NOT ”form a group as a logical operator”. Similarity evaluation rule # 2 may or may not overlap with similarity evaluation rule # 1. For example, W = 10 may be given to the correspondence relationship between the node “AND” and the node “AND”, or W = 12.
Similarity evaluation rule # 3: When there are a plurality of link destination nodes, the type difference is calculated for each link destination node, and the calculation results are added.

On the horizontal axis in FIG. On the vertical axis, correspondence combination candidates are arranged. A value “I × W” is stored in the cell at the intersection of the horizontal axis and the vertical axis. As a whole, FIG. 5 shows the following.
Each row contains three “I × W” values, each of which is one of “1 × 0”, “1 × 10”, and “1 × 20” The position of the cell satisfies the condition of the constraint equation described above. That is, one of the four nodes of the directed graph BGd corresponds to each of the three nodes of the directed graph BGm so as not to overlap each other.
A blank cell in each row is a correspondence cell in which I = “0” in the candidate according to the constraint equation. Therefore, no matter what value W takes, “I × W = 0” is always obtained, and the cell is blank.
For each row, the sum of three “I × W” values is calculated as the similarity.

Further, for example, when attention is paid to the row of candidate 4 in FIG. 5 and FIGS.
In the row of candidate 4 in FIG. 5, the node 52c corresponds to the node 51c, the node 52e corresponds to the node 51d, and the node 52f corresponds to the node 51e.
In the row of candidate 4 in FIG. 5, there are three columns for node 52d, all of which are blank. That is, the node 52d has no counterpart.
In FIG. 2 (b), there are two nodes whose links originate from the node 51e and whose end points are “T” and “OUT”. In FIG. 4, there are two nodes whose links originate from the node 52 f and whose end points are “T” and “OUT”. As a result, W <51e, 52f> = 10 + 10 = 20 in the row of candidate 4 in FIG.

In FIG. 2B, the type of the node whose end point is the link starting from the node 51d is “AND”. In FIG. 4, the type of the node whose end point is the link starting from the node 52e is also “AND”. As a result, W <51d, 52e> = 10 in the row of candidate 4 in FIG.
In FIG. 2B, the type of the node whose end point is the link starting from the node 51c is “AND”. In FIG. 4, the type of a node whose end point is a link starting from the node 52c is “OR”. As a result, W <51c, 52c> = 0 in the row of candidate 4 in FIG.

  Again referring to FIG. Of the 24 combinations of correspondences, the candidate having the maximum similarity is candidate 4, candidate 14 and candidate 16, and the similarity is both “30”. As a result of the simple example, such a result of “first place in the tie” was obtained. However, for example, by devising the setting of the group of similarity evaluation rule # 2, the similarity of candidate 4 may be “32”, and the similarity of both candidate 14 and candidate 16 may be “30”. is there. Then, the combination of correspondences having the highest degree of similarity is specified only as the candidate 4.

  As described above, the row of candidate 4 in FIG. 5 indicates that the node 52d has no counterpart. Therefore, in the comparison between the directed graph BGm and the directed graph BGd, the node 52d is extracted as “difference”. In the above description, the method of extracting the difference between the directed graph BGm in FIG. 2B and the directed graph BGd in FIG. 4 by the difference analysis apparatus is limited to the node “IN”. However, for other types of nodes, The information processing performed by the difference analyzer is essentially the same.

(Configuration of differential analysis device)
The configuration of the difference analysis apparatus 1 will be described with reference to FIG. The difference analysis apparatus 1 is a general computer. The differential analysis device 1 includes a central control device 11, an input device 12, an output device 13, a main storage device 14, and an auxiliary storage device 15. These are connected to each other by a bus. The auxiliary storage device 15 includes a logic drawing 31 (for example, corresponding to the symbol LG in FIG. 1), a directed graph 32 (for example, corresponding to the symbol BG in FIG. 2A), an equivalence rule 33, a similarity evaluation rule 34, and node correction information 35. , Node correspondence information 36, element information 37, signal line information 38, node information 39, and link information 40 are stored (details will be described later).

  The rule reception unit 21, the logic drawing reception unit 22, the directed graph creation unit 23, the equivalent correction unit 24, the difference extraction unit 25, and the difference display processing unit 26 in the main storage device 14 are programs. Thereafter, when the subject is described as “XX section is”, the central controller 11 reads the XX section from the auxiliary storage device 15 and loads it into the main storage device 14, and then the function of the XX section (details) (See below).

  FIG. 7A is a logic diagram LG1. FIG. 7B is a logic diagram LG2. The logic drawing LG1 in FIG. 7A is the same as the logic drawing LG in FIG. 1, but is reprinted for easy comparison with the logic drawing LG2. Hereinafter, each information and processing procedure used by the difference analysis apparatus 1 to extract a difference between the logic drawing LG1 and the logic drawing LG2 will be described.

(Element information)
The element information 37 will be described with reference to FIGS. 8A and 8B. In the element information 37, in association with the drawing ID stored in the drawing ID column 101, the element ID column 102 has an element ID, the type column 103 has a type, the X coordinate column 104 has an X coordinate, and a Y coordinate. The column 105 stores the Y coordinate, the region column 106 stores the region flag, the attribute column 107 stores the attribute, and the attribute value column 108 stores the attribute value.

The drawing ID in the drawing ID column 101 is an identifier that uniquely identifies a logic drawing.
The element ID in the element ID column 102 is an identifier that uniquely identifies an element in the logic drawing.
The type in the type column 103 is an element type.
The X coordinate in the X coordinate field 104 is an X-axis coordinate value of the element in the logic drawing (the right direction is the positive direction).
The Y coordinate in the Y coordinate column 105 is the coordinate value of the element's Y axis in the logic drawing (upward is the positive direction).

The region flag in the region column 106 is either “TRUE” indicating that the coordinate value of the element is included in the region designated by the user, or “FALSE” indicating that it is not included.
The attribute in the attribute column 107 is an element parameter. For example, “WT” indicates that the timer parameter is the waiting time “Waiting Time”.
The attribute value in the attribute value column 108 is a parameter value. For example, “1.0” indicates that the waiting time is 1 hour.
Note that the user can arbitrarily set values in the attribute column 107 and the attribute value column 108 according to the content of the difference to be extracted.

  Element information 37 exists for each logic drawing. The number of records in the element information 37 is equal to the number of elements in each logic drawing. The element information 37 in FIG. 8A is for the logic drawing LG1 (FIG. 7A). The element information 37 in FIG. 8B is for the logic drawing LG2 (FIG. 7B), and detailed description thereof is omitted.

(Signal line information)
The signal line information 38 will be described with reference to FIGS. 9A and 9B. In the signal line information 38, in association with the drawing ID stored in the drawing ID column 111, the signal line ID column 112 has a signal line ID, the starting element ID column 113 has a starting element ID, and an ending element ID column 114. , The start port ID column 115 stores the start port ID, and the end port ID column 116 stores the end port ID.

The drawing ID in the drawing ID column 111 is the same as the drawing ID in FIGS. 8A and 8B.
The signal line ID in the signal line ID column 112 is an identifier that uniquely identifies the signal line in the logic drawing.
The starting element ID in the starting element ID column 113 is the element ID of the element that is the starting point of the signal line.
The end element ID in the end element ID column 114 is the element ID of the element that is the end point of the signal line.
The starting port ID in the starting port ID column 115 is an identifier that uniquely identifies the port of the element that is the starting point of the signal line.
The end point port ID in the end point port ID column 116 is an identifier that uniquely identifies the port of the element that is the end point of the signal line.

  The signal line information 38 exists for each logic drawing. The number of records of the signal line information 38 is equal to the number of signal lines in each logic drawing. The signal line information 38 in FIG. 9A is for the logic drawing LG1 (FIG. 7A). The signal line information 38 in FIG. 9B is for the logic drawing LG2 (FIG. 7B), and detailed description thereof is omitted.

(Node information)
The node information 39 will be described with reference to FIGS. 10 (a) and 10 (b). In the node information 39, in association with the drawing ID stored in the drawing ID column 121, the node ID column 122 has a node ID, the type column 123 has a type, the label column 124 has a label, and a label value column 125. Stores a label value.

The drawing ID in the drawing ID column 121 is the same as the drawing ID in FIGS. 8A and 8B.
The node ID in the node ID column 122 is an identifier that uniquely identifies a node in a directed graph (hereinafter, referred to as “transformed directed graph”) converted from the logic drawing. Here, for ease of understanding, the node ID of a certain node matches the element ID (FIGS. 8A and 8B) of the element that is the conversion source of the node.
The type in the type column 123 is a type of a node in the converted directed graph.
The label in the label column 124 is an attribute of the node in the converted directed graph.
The label value in the label value column 125 is an attribute value of a node in the converted directed graph.
Note that the type, label, and label value of a certain node are the same as the type, attribute, and attribute value (FIGS. 8A and 8B) of the element that is the conversion source of the node.

  The node information 39 exists for each transformed directed graph. The record of the node information 39 corresponds to only the element whose region is “TRUE” among the elements of the logic diagram of the conversion source. The node information 39 in FIG. 10A is for the directed graph converted from the logic drawing LG1 (FIG. 7A). The node information 39 in FIG. 10B is for the directed graph converted from the logic drawing LG2 (FIG. 7B), and detailed description thereof is omitted.

(Link information)
The link information 40 will be described along FIGS. 11 (a) and 11 (b). In the link information 40, in association with the drawing ID stored in the drawing ID column 131, the link ID column 132 has a link ID, the start node ID column 133 has a start node ID, and the end node ID column 134 has an end point. The node ID, the label value 1 in the label 1 column 135, and the label value 2 in the label 2 column 136 are stored.

The drawing ID in the drawing ID column 131 is the same as the drawing ID in FIGS. 8A and 8B.
The link ID in the link ID column 132 is an identifier that uniquely identifies a link in the converted directed graph. Here, for ease of understanding, the link ID of a certain link matches the signal line ID (FIGS. 9A and 9B) of the signal line that is the conversion source of the link.
The starting node ID in the starting node ID column 133 is the node ID of the node that is the starting point of the link in the converted directed graph.
The end node ID in the end node ID column 134 is the node ID of the node that is the end point of the link in the converted directed graph.

The label value 1 in the label 1 column 135 is the port ID of the node that is the starting point of the link in the converted directed graph.
The label value 2 in the label 1 column 136 is the port ID of the node that is the end point of the link in the converted directed graph.
The starting point (end point) node ID and label value 1 (2) of a link are the starting point (end point) element ID and starting point (end point) port ID (FIG. 9A and FIG. It corresponds to FIG. 9 (b)).

  The link information 40 exists for each converted directed graph. The record of the link information 40 corresponds to only the signal line of the conversion source logic drawing whose start and end element areas are both “TRUE”. The link information 40 in FIG. 11A relates to the directed graph converted from the logic drawing LG1 (FIG. 7A). The link information 40 in FIG. 11B is for the directed graph converted from the logic drawing LG2 (FIG. 7B), and detailed description thereof is omitted.

(Processing procedure)
FIG. 12 is a flowchart of the processing procedure. Hereinafter, the description of FIGS. 13 to 19 will be added at an appropriate timing along the description of FIG.
In step S201, the rule receiving unit 21 of the difference analysis apparatus 1 receives an equivalence rule. Specifically, first, the rule receiving unit 21 displays an equivalent rule input screen 71 a (FIG. 13) on the output device 13. At this time, the pre-correction column 72a and the post-correction column 72b are blank.

  Second, the rule receiving unit 21 accepts that the user draws a partial directed graph before correction and a partial directed graph after correction in the pre-correction column 72a and the post-correction column 72b, respectively. The user draws a node or the like by copying the icon displayed in the editing icon field 73. In the example of FIG. 13, the user has input that “a negative logical sum is equivalent to a negative logical product”. Note that the user can set the number of repetitions (symbols 74a and / or 74b) after designating a region of a certain node and / or link (symbols 75a and / or 75b). Then, the rule receiving unit 21 repeats the same drawing for the designated number of times “N”.

Thirdly, the rule receiving unit 21 receives that the user inputs the title of the equivalence rule in the title column 76 and presses the apply button 77.
Fourthly, the rule receiving unit 21 associates the partially directed graph 72a before correction, the partially directed graph 72b after correction, and the title 76 with each other and stores them in the auxiliary storage device 15 as the equivalent rule 33 (see FIG. 6).
Each time the user presses the rule addition button 78, the rule receiving unit 21 repeats the “first” to “fourth” processes in step S201. Then, a plurality of equivalence rules 33 are accumulated in the auxiliary storage device 15.
Fifth, the rule receiving unit 21 receives the user pressing the setting end button 79.

(Input logic drawing)
Note that a logic screen is input in step S202 described later. However, prior to that, the user can also register two logic drawings including portions that should be regarded as equivalent to each other as preparation for the processing in step S201 or subsequent confirmation. When the user selects the equivalent case setting tab 80, the equivalent rule input screen 71a (FIG. 13) transitions to the equivalent case input screen 71b (FIG. 14). The user inputs storage positions of arbitrary two logic drawings in the equivalent logic file reading columns 81a and 81b (or selects an icon linked to the storage position). Then, the rule receiving unit 21 retrieves the logic drawing from the auxiliary storage device 15 or an external storage device and displays it in the logic drawing display fields 82a and 82b. The user inputs the title of the equivalent logic drawing in the title column 76 and presses the apply button 77. Then, the rule reception unit 21 associates the two logics displayed in the logic drawing display fields 82a and 82b and the drawing title 76 with each other, and stores them in the auxiliary storage device 15 as an equivalent logic drawing.

(Editing / deleting equivalence rules)
When the user selects an arbitrary title from the list 83 on the equivalent rule input screen 71a (FIG. 13), the rule receiving unit 21 displays a partial directed graph 72a before correction and a partial directed graph 72b after correction associated with the title. indicate. When the user presses the pre-correction edit button 84a and / or the post-correction edit button 84b, the rule receiving unit 21 activates the partial directed graph 72a before correction and / or the partial directed graph 72b after correction. In this state, the rule accepting unit 21 accepts that the user edits the partial digraph 72a before correction and / or the partial digraph 72b after correction, and then presses the setting end button 79. Then, the rule receiving unit 21 stores the edited equivalent rule in the auxiliary storage device 15. When the user presses the non-application button 85 in the active state, the rule receiving unit 21 deletes the equivalent rule from the auxiliary storage device 15. Thus, the user can change the level of the difference to be detected.

(Edit / delete equivalent logic drawings)
The rule accepting unit 21 can also edit / delete the equivalent logic drawing by the same method.

In step S202, the rule receiving unit 21 receives a similarity evaluation rule. Specifically, first, the rule receiving unit 21 displays a similarity evaluation rule input screen 91 (FIG. 15) on the output device 13.
Second, the rule receiving unit 21 receives a user input of the first evaluation coefficient in the node type column 92a. The first evaluation coefficient corresponds to the similarity evaluation rule # 1.
Thirdly, the rule receiving unit 21 receives a user input of the second evaluation coefficient in the node group column 92b. The second evaluation coefficient corresponds to the similarity evaluation rule # 2. At this time, the rule accepting unit 21 accepts that the user inputs a plurality of groups and types belonging to each group.

4thly, the rule reception part 21 receives that a user selects arbitrary types from the setting column 92c for every node type. Now, assume that the user selects “T”. Then, the rule reception part 21 displays the timer attribute setting column 92d.
Fifth, the rule receiving unit 21 receives that the user inputs an attribute in the attribute column 93a and inputs a third evaluation coefficient given when the attributes match in the attribute value column 93b.
Sixth, the rule receiving unit 21 stores the information received in “second” to “fifth” in step S202 in the auxiliary storage device 15 as the similarity evaluation rule 34 (FIG. 6).

  In step S203, the logic drawing receiving unit 22 of the difference analysis apparatus 1 receives a logic drawing. Specifically, first, the logic drawing receiving unit 22 is configured so that the user can compare two logic drawings (the logic drawing LG1 in FIG. 7A and the drawing) through the input device 12 (scanner or the like). 7 (b) logic drawing LG2) is received. In some cases, the logic drawing already exists as electronic data such as CAD (Computer Added Design). In this case, the logic drawing receiving unit 22 does not need to acquire image data with a scanner. The logic drawing receiving unit 22 displays a “logic drawing selection field” in which the storage position of the logic drawing (or an icon linked to the storage position) is selected as an option on the equivalent case input screen 71b of FIG. Just accept it. The received two logic drawings are called “first logic drawing” and “second logic drawing”.

Secondly, the logic drawing receiving unit 22 displays the two received logic drawings on the output device 13, and the user selects a comparison target area for each of the first logic drawing and the second logic drawing. Accept to specify. This area is called a “designated area”.
Third, the logic drawing receiving unit 22 creates element information 37 (FIG. 8A) and signal line information 38 (FIG. 9A) based on the first logic drawing and its designated area.
Fourth, the logic drawing receiving unit 22 creates element information 37 (FIG. 8B) and signal line information 38 (FIG. 9B) based on the second logic drawing and its designated area.

In step S204, the directed graph creating unit 23 of the difference analysis apparatus 1 creates a directed graph. Specifically, first, the directed graph creating unit 23 uses the element information 37 (FIG. 8A) and the signal line information 38 (FIG. 9A) created in “third” in step S203, respectively. Node information 39 (FIG. 10A) and link information 40 (FIG. 11A) are converted. The directed graph drawn based on the node information 39 and the link information 40 converted here is the “first directed graph”.
Secondly, the directed graph creating unit 23 uses the element information 37 (FIG. 8B) and the signal line information 38 (FIG. 9B) created in the “fourth” in step S203 as node information 39 (FIG. 10). (B)) and link information 40 (FIG. 11B). The directed graph drawn based on the node information 39 and the link information 40 converted here is a “second directed graph”.

In step S205, the equivalent correction unit 24 of the difference analysis apparatus 1 performs equivalent correction. Specifically, first, the equivalence correction unit 24 reads the equivalence rule 33 from the auxiliary storage device 15.
Secondly, the equivalent correction unit 24 matches the node information 39 and the link information 40 created in “first” in step S204 with the partially directed graph before correction included in the equivalence rule. Then, the equivalent correction unit 24 replaces a portion of the node information 39 and the link information 40 that matches the partial directed graph before correction with the corrected partial directed graph included in the equivalence rule. At this time, a part of the first directed graph is replaced with the corrected partially directed graph. The first directed graph after the replacement is referred to as a “first directed graph after correction”.

The directed graph BG (FIG. 2 (a)) is corrected to the directed graph BGm (FIG. 2 (b)) by applying the above-described equivalence rule “logical OR of negation is equivalent to negation of logical product”. Will be. Correcting the directed graph is nothing but changing the contents of the node information 39 and the link information 40.
At the time of the correction, the equivalent correction unit 24 changes the node information 39 (FIG. 10A) to the node information 39 in FIG. The changes are as follows (see also FIG. 2 (a) and FIG. 2 (b)).
The records for the nodes 51f, 51g, 51h and 51j in FIG. 10 (a) are deleted in FIG. 16 (a).
In FIG. 16A, records for the nodes 51x and 51y are newly provided.

At the time of the correction, the equivalent correction unit 24 changes the link information 40 (FIG. 11A) to the link information 40 in FIG. The changes are as follows (see also FIG. 2 (a) and FIG. 2 (b)).
The records for the links L06, L07, and L08 in FIG. 11 (a) are deleted in FIG. 16 (b).
In FIG. 16B, a record for the link L13 is newly established.
In FIG. 16B, the end node IDs for the links L03, L04, and L09 are changed.
In FIG. 16B, the starting node IDs for the links L11 and L12 are changed.
In FIG. 16B, the label value 2 for the links L04 and L09 is changed.

  Returning to the description of step S205, thirdly, the equivalent correction unit 24 stores the correction result in the auxiliary storage device 15 as node correction information 35 (FIG. 17). In the node correction information 35 of FIG. 17, the node ID of the node before correction, the node ID of the node after correction, and the title of the applied equivalence rule are stored in association with the drawing ID.

  In step S206, the difference extraction unit 25 of the difference analysis apparatus 1 extracts the difference. Specifically, the difference extraction unit 25 compares the corrected first directed graph and the second directed graph, and extracts the difference. At this time, as described above in the description of FIG. 5, the difference extraction unit 25 connects the nodes and links included in the corrected first directed graph and the nodes and links included in the second directed graph. Based on the above, by calculating the evaluation coefficient between the nodes, the directed graphs of both are compared.

  In step S207, the difference display processing unit 26 of the difference analysis apparatus 1 displays the difference. Specifically, first, the difference display processing unit 26 displays a difference display screen 94 (FIG. 18) on the output device 13. On the difference display screen 94, a first logic drawing LG1 and a second logic drawing LG2 are displayed. At this time, the difference display processing unit 26 highlights the difference extracted in step S206 (reference numeral 95).

  As a result of visually recognizing the first logic drawing LG1 and the second logic drawing LG2, the user can easily understand that the element 52g is a difference. However, it is difficult for the user to easily understand why the elements 52j and 52k are not highlighted as differences. Therefore, the user designates an area including the element 52j and the element 52k with the input device 12 such as a mouse (reference numeral 96a). This designation is called “explanation request”. The difference display processing unit 26 receives an explanation request.

  Second, the difference display processing unit 26 acquires records including “52j” and “52k” as the node IDs of the corrected nodes among the records of the node correction information 35 (FIG. 17). Then, the difference display processing unit 26 displays the title of the equivalence rule of the acquired record in the explanation column 96c, and highlights the element of the first logic drawing corresponding to the node before correction of the acquired record (reference numeral 96b). . The user understands the content of the equivalence rule, and understands that the symbol 96b of the first logic drawing LG1 and the symbol 96a of the second logic drawing LG2 are logically equivalent. Next, the user wants to know which element of the second logic drawing LG2 corresponds to which element of the first logic drawing LG1 and how similar.

FIG. 19 also shows a difference display screen 94 (same as FIG. 18). For example, the user designates an area including the element 52f with the input device 12 such as a mouse (reference numeral 97a). This designation is called “evaluation request”. The difference display processing unit 26 receives an evaluation request.
Returning to the description of step S207, thirdly, the difference display processing unit 26 sets the value “20” of the evaluation coefficient W <51e, 52f> of the row of candidate 4 in FIG. 5 to “the element evaluation coefficient is large”. Along with the comment, it is displayed in the evaluation column 97c.
Thereafter, the processing procedure ends.

  In the above example, the equivalent correction unit 24 replaces a part of the first directed graph with the corrected partial directed graph to obtain the corrected first directed graph, and the difference extraction unit 25 performs the corrected first directed graph. The directed graph of 1 is compared with the second directed graph. However, after the equivalent correction unit 24 replaces a part of the second directed graph with the corrected partial directed graph to obtain a corrected second directed graph, the difference extraction unit 25 uses the corrected second directed graph. And the first directed graph may be compared. In the above example, the user designates an area on the second logic drawing LG2 when making an explanation request and an evaluation request. However, the user may designate an area on the first logic drawing LG1.

(Modification 1)
In step S206 of FIG. 5 and FIG. 12, the difference extraction unit 25 compares the first directed graph and the second directed graph, and gives an evaluation coefficient “W” for the correspondence between the two nodes. did. Modification 1 for performing the comparison with higher accuracy is shown in FIG. Now, the node that is the comparison target in the comparison source and the comparison destination is anthropomorphized and called “principal”. Similarly, a node to which a signal is directly propagated from the person is called a “child”, and a node to which a signal is directly propagated from the child is called a “grandchild”. This is shown in FIG.

Similar to the above example, the difference extraction unit 25 gives an evaluation coefficient “E ₁ ” such as “20” to the correspondence between the principal 1 and the principal 2. However, the difference extraction unit 25 may, for example, give an evaluation coefficient “E ₂ ” to the correspondence between the child 11 and the child 21 and add it to the evaluation coefficient “E ₁ ” of the correspondence between the individuals. . Further, the difference extraction unit 25 may give the evaluation coefficient “E ₂ ” to the correspondence between the grandchild 111 and the grandchild 211, for example, and add it to the evaluation coefficient “E ₁ ” of the correspondence between the individuals. The calculation method of “E ₂ ” is the same as the calculation method of “E ₁ ” (based on the difference in node type / group, the difference in node type / group connected to the node, etc.). Follow.

  As described above, “I” is defined in the correspondence between the comparison source node and the comparison destination node. When “I = 1”, the difference extraction unit 25 considers that both nodes correspond to each other. When “I = 0”, the difference extraction unit 25 considers that both nodes do not correspond. Therefore, the difference extraction unit 25 determines that the correspondence between the individuals is “I = 1” and the correspondence between the children or grandchildren is “I = 1”, or the correspondence between the individuals is “I = 0”. And the correspondence between the children or grandchildren is also “I = 0”, which is referred to as “enhancement case”.

On the other hand, the difference extraction unit 25 determines that the correspondence between the individuals is “I = 1” and the correspondence between the children or grandchildren is “I = 0”, or the correspondence between the individuals is “I = 0”. "And the correspondence between the children or grandchildren is" I = 1 "is referred to as" relaxation case ". Then, the difference extraction unit 25 gives an evaluation coefficient larger than a predetermined reference value in the strengthened case and an evaluation coefficient smaller than the predetermined reference value in the relaxed case with respect to the correspondence between the persons. Such an evaluation coefficient is set to “E ₃ ”. For example, the correspondence between the individuals is “I = 1”, and there is one “I = 1” correspondence between the comparison source child and the comparison destination child, and “I = 0”. Assume that there is one correspondence. The large evaluation coefficient is “20” and the small evaluation coefficient is “5”. In this case, “E ₃ ” given to the correspondence between the principals is “20 + 5 = 25”.

  Similarly, the original node from which the signal is directly propagated to the person is called “parent”, and the original node from which the signal is directly propagated to the parent is called “parent”. In the above description, “child” may be read as “parent”, and “grandchild” may be read as “parent”.

Furthermore, when the distance between the position (coordinate value) of the element corresponding to the person at the comparison source and the position of the element corresponding to the person at the comparison destination is smaller than a predetermined threshold, the correspondence between these persons On the other hand, an evaluation coefficient “E ₄ ” may be given. Eventually, the difference extraction unit 25 gives “W = k ₁ E ₁ + k ₂ E ₂ + k ₃ E ₃ + k ₄ E ₄ ” to the correspondence between the individuals. k ₁ , k ₂ , k ₃ and k ₄ are weights. The user can arbitrarily set the weight value.

(Modification 2)
The user may change the type or attribute of an element at various stages of design while taking over an identifier (element ID) of the element. For example, the element type may be changed from “OR” to “AND” while keeping the element ID “51 _t ”. Such an element is called an “identity maintaining element”. In such a case, the difference extraction unit 25 maintains the same without changing the node ID of the node corresponding to the identity maintaining element. And when the difference extraction part 25 gives an evaluation coefficient with respect to the correspondence of nodes, regarding the correspondence of a node with the same node ID, regardless of other information associated with the node, Gives the maximum evaluation coefficient. That is, the difference extraction unit 25 considers such a combination of nodes to be the same.

(Modification 3)
The difference analysis apparatus 1 may change a part of the order of the steps of the processing procedure as desired by the user. Specifically, before the processing procedure starts, the difference analysis apparatus 1 includes an “equivalence rule setting” button, a “similarity evaluation rule setting” button, a “logic drawing input” button, and a “difference evaluation execution / confirmation” button. It is displayed on the output device 13.

  When the user presses the “equal rule setting” button, the difference analysis apparatus 1 executes step S201 described above. When the user presses the “similarity evaluation rule setting” button, the difference analysis apparatus 1 executes step S202 described above. When the user presses the “logic drawing input” button, the difference analysis apparatus 1 executes the above-described step S203. When the user presses the “difference evaluation execution / confirmation” button, the difference analysis apparatus 1 executes steps S204 to S207 described above. Note that the user can press the “equivalent rule setting” button, the “similarity evaluation rule setting” button, and the “logic drawing input” button in any order. The user can only press the “Execution / Confirmation of Difference” button after pressing all three buttons.

(Modification 4)
In the above, the difference analysis apparatus 1 demonstrated the example which does not make the difference which should display the difference of the shape of the element of a logic drawing, and the difference of the shape of a signal line. However, by reflecting these differences in the equivalence rule and reflecting the evaluation coefficients for these matches in the similarity evaluation rule, the difference analysis apparatus 1 can recognize these differences as the differences to be displayed.

(Modification 5)
For example, if the evaluation coefficient for the coincidence of the element positions is reduced in the upstream stage of the design, the difference analysis apparatus 1 does not display the difference between the minute positions of the elements. If the evaluation coefficient is gradually increased in the downstream stage of the design, the difference analysis apparatus 1 displays the difference in the fine position of the element.

  In the above description, the example in which the end element (“open”, “OPEN”, etc.) is not included in the designated area has been described. However, if a virtual element “NULL” is created and the terminal element is connected to “NULL”, the terminal element can also be included in the designated area.

  It should be noted that mathematical programming methods such as mixed integer programming and linear programming can be used to set variables, constraints, evaluation functions, etc. in order to easily realize the information processing of this embodiment.

(Effect of embodiment)
This embodiment has the following effects.
(1) The difference analysis apparatus can change the difference between logic drawings to be extracted by changing the equivalence rule flexibly as necessary.
(2) The differential analysis apparatus can allow the user to define the equivalence rule easily and reliably.
(3) By substituting a part of the directed graph with a partially directed graph, the difference analysis apparatus can reliably ignore the difference between the directed graphs that does not need to be extracted.
(4) The difference analysis apparatus can make the user easily recognize which part of the logic drawing is the difference.
(5) The difference analysis apparatus can objectively and highly accurately extract a difference between directed graphs.
(6) The difference analysis apparatus can regard the nodes to which the user has assigned the same identifier as the same one unconditionally.
(7) The difference analysis apparatus can allow the user to specify the part of the logic screen that the user really wants to compare.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files that realize each function can be stored in a recording device such as a memory, a hard disk, or an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
In addition, the control lines and information lines are those that are considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. In practice, it may be considered that almost all the components are connected to each other.

DESCRIPTION OF SYMBOLS 1 Difference analyzer 11 Central controller 12 Input device 13 Output device 14 Main memory (storage part)
15 Auxiliary storage device (storage unit)
DESCRIPTION OF SYMBOLS 21 Rule reception part 22 Logic drawing reception part 23 Directed graph preparation part 24 Equivalent correction part 25 Difference extraction part 26 Difference display process part 31 Logic drawing 32 Directed graph 33 Equivalence rule 34 Similarity evaluation rule 35 Node correction information 36 Node corresponding information 37 Element information 38 Signal line information 39 Node information 40 Link information

Claims (9)

A rule reception unit that accepts a rule that defines logic equivalence;
A logic drawing receiving unit for receiving a first logic drawing and a second logic drawing created using the logic;
The first logic drawing is converted to a first directed graph by extracting elements and signal lines from the first logic drawing, and the second logic drawing by extracting elements and signal lines from the second logic drawing. A directed graph creation unit for converting the logic drawing of FIG. 2 into a second directed graph;
An equivalent correction unit that corrects the converted first directed graph based on the accepted rule, or corrects the converted second directed graph;
By comparing the first directed graph and the corrected second directed graph, or by comparing the second directed graph and the corrected first directed graph, the first logic drawing. And a difference extraction unit for extracting a difference between the second logic drawing and the second logic drawing;
A difference display processing unit for displaying the extracted difference on a screen;
A difference analysis apparatus comprising: The rule reception unit
Accepting a user to draw on the screen a partial directed graph that is considered equivalent to each other in the portion of the directed graph;
The difference analysis apparatus according to claim 1. The equivalent correction unit is
Correcting the converted first directed graph or the converted second directed graph by replacing a part of the converted first directed graph or the converted second directed graph with the received partial directed graph. ,
The difference analysis apparatus according to claim 2. The difference display processing unit
Displaying the extracted difference together on a screen for displaying the first logic drawing and the second logic drawing;
The difference analysis apparatus according to claim 3. The difference extraction unit
Comparing the directed graphs by calculating an evaluation coefficient that quantifies the degree of similarity between the nodes based on the connection relationship between the nodes and links included in the directed graph;
The difference analysis apparatus according to claim 4. The difference extraction unit
If the information identifying the node matches, considering the node to be the same regardless of other information associated with the node;
The difference analysis apparatus according to claim 5. The logic drawing receiving unit
The user accepts designation of a comparison target region for each of the first logic drawing and the second logic drawing,
The difference extraction unit
Extracting the difference in the accepted region;
The difference analysis apparatus according to claim 6. The rule reception unit of the differential analysis device
Accepts rules that define logic equivalence,
The logic drawing accepting unit of the difference analysis device is
Accepting a first logic drawing and a second logic drawing created using the logic;
The directed graph creation unit of the differential analysis device is
The first logic drawing is converted to a first directed graph by extracting elements and signal lines from the first logic drawing, and the second logic drawing by extracting elements and signal lines from the second logic drawing. Convert the logic drawing into a second directed graph,
The equivalent correction unit of the difference analyzer is
Based on the accepted rule, correct the converted first directed graph, or correct the converted second directed graph,
The difference extraction unit of the difference analysis device includes:
By comparing the first directed graph and the corrected second directed graph, or by comparing the second directed graph and the corrected first directed graph, the first logic drawing. And the difference between the second logic drawing and
The difference display processing unit of the difference analyzer is
Displaying the extracted difference on a screen;
The difference analysis method of the difference analysis apparatus characterized by the above-mentioned. For the rule reception part of the difference analysis device,
Execute a process that accepts rules that define logic equivalence,
For the logic drawing receiving unit of the difference analysis device,
Executing a process of accepting a first logic drawing and a second logic drawing created using the logic;
For the directed graph creation unit of the difference analysis device,
The first logic drawing is converted to a first directed graph by extracting elements and signal lines from the first logic drawing, and the second logic drawing by extracting elements and signal lines from the second logic drawing. To perform the process of converting the logic drawing of
For the equivalent correction unit of the difference analyzer,
Based on the accepted rule, correct the converted first directed graph, or execute the process of correcting the converted second directed graph,
For the difference extraction unit of the difference analysis device,
By comparing the first directed graph and the corrected second directed graph, or by comparing the second directed graph and the corrected first directed graph, the first logic drawing. And a process of extracting the difference between the second logic drawing and
For the difference display processing unit of the difference analyzer,
Causing the extracted difference to be displayed on the screen;
A difference analysis program for causing the difference analysis apparatus to function.

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