JP2017143193A - Wiring board, wiring board design method, wiring board design assisting device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily reduce adverse effect of connection of a test pad.SOLUTION: Referring to manufacturing data 115 indicating the result of a layout design carried out by component arrangement and wiring part 145, and also referring to observation target data 114 indicating inter-terminals to be an observation target for a signal, a test pad arranging and wiring part 146 determines a position where a test pad is to be arranged, and a connection path connecting the test pad and a wiring pattern arranged between the terminals to be an observation target. To determine the connection path, a veer arrangement part 1462 in the test pad arranging and wiring part 146 determines a position where a veer used for connecting the test pad and the target wiring patter is to be arranged. The veer wiring part 1463 determines the shape and arrangement of the wiring pattern for connecting the test pad and the target wiring pattern via the veer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board, a wiring board design method, a wiring board design support apparatus, and a program.

  At present, in a product development of a printed circuit board such as a PCB (Printed Circuit Board), a verification process for confirming whether the product satisfies the specifications is important. In the verification process, a signal is actually observed, and it may be confirmed (tested) whether or not the voltage value of the signal, the timing at which the signal changes, the manner of change, and the like satisfy the specifications. Thereby, some wiring boards are provided with a test pad for observing such signals.

  In recent years, wiring boards have been mounted with higher density, and the number of wirings has increased. As a result, there is less room for placing test pads. For this reason, in the conventional wiring board, priority is given to the arrangement of components and wiring, and the location of the test pad can be arranged from the remaining area (for example, a place where it can be arranged so as to overlap with the wiring). There is one that is determined by searching (for example, Patent Document 1). Thereby, in this conventional wiring board, the operation for arranging the test pad is not performed with respect to the arrangement of the components or the wiring, so that a more desirable wiring can be formed.

  The test pads on the wiring board are basically unnecessary after the verification is completed. However, a wiring board provided with a test pad is usually shipped as a product while leaving the test pad.

  Depending on the placement of the test pad, the wiring to which it is electrically connected, that is, the signal is to be observed, and the wiring is adversely affected. In the wiring, the signal deteriorates not a little due to discontinuity of impedance accompanying the placement of the test pad. Therefore, the conventional wiring board has a problem that it is difficult to cope with deterioration of a signal propagating through the wiring to which the test pad is connected.

  In general, the wiring that needs to be verified on the wiring board has a high demand for the waveform quality of the signal, or the waveform deterioration tends to occur. For this reason, the adverse effects of connecting test pads are likely to surface. For this reason, it seems important to be able to easily reduce the adverse effects caused by the connection of the test pads.

  The present invention has been made to solve such problems, and an object of the present invention is to make it possible to easily reduce the adverse effects caused by connection of test pads.

  In order to solve the above problems, one embodiment of the present invention is a multilayer wiring board, which is a wiring selected from the wirings formed on the wiring board, and the target wiring is transmitted over the wiring. A test pad for observing a signal to be transmitted, and a connection path including at least one via and electrically connecting the test pad and the target wiring.

  According to the present invention, it is possible to easily reduce adverse effects caused by connection of test pads.

It is a figure explaining the example of functional composition of the wiring board design support device by this embodiment. It is a figure explaining the hardware structural example of the data processing apparatus which can be used as the wiring board design assistance apparatus by this embodiment. It is a figure explaining the wiring board by 1st Embodiment. It is a figure explaining the connection path | route between the object wiring pattern and test pad in 1st Embodiment on a cross section. It is a figure explaining the wiring board by 2nd Embodiment. It is a figure explaining the wiring board by 3rd Embodiment. It is a figure explaining the connection path | route between the object wiring pattern and test pad in 3rd Embodiment. It is a figure explaining the wiring board by 4th Embodiment. It is a figure explaining the wiring board by 5th Embodiment. It is a figure explaining the connection path | route between the object wiring pattern and test pad in 5th Embodiment. It is a figure explaining the processing content performed with respect to the wiring board by 5th Embodiment in order to produce the wiring board by 6th Embodiment. It is a figure explaining the processing content performed with respect to the wiring board by 5th Embodiment in order to produce the wiring board by 7th Embodiment. It is a figure explaining the processing content performed with respect to the wiring board by 5th Embodiment in order to produce the wiring board by 8th Embodiment. It is a figure explaining the processing content performed with respect to the wiring board by 5th Embodiment in order to produce the wiring board by 9th Embodiment. It is a flowchart which shows a test pad arrangement | positioning / wiring process. It is a flowchart which shows a test pad arrangement | positioning / wiring process (continuation).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating an example of a functional configuration of the wiring board design support apparatus according to the present embodiment. First, a functional configuration example of the wiring board design support apparatus 1 according to the present embodiment will be specifically described with reference to FIG.

  The wiring board design support apparatus 1 is a data processing apparatus (computer) for supporting the design of a multilayer wiring board on which wiring such as a printed board is formed. As shown in FIG. 1, the wiring board design support device 1 is used by connecting an input device 2 and a display device 3. Accordingly, a user (wiring board designer, etc.) designs the wiring board by operating the input device 2 as necessary while confirming the image displayed on the display device 3. Yes. The wiring board according to the present embodiment is realized by designing using the wiring board design support apparatus 1 and manufacturing according to the design result.

  As shown in FIG. 1, the wiring board design support apparatus 1 includes a storage unit 11, an input control unit 12, an output control unit 13, a wiring board design support unit 14, and a main control unit 15.

  The storage unit 11 is a storage device used for storing various data necessary for designing the wiring board. Examples of the data include the library 111, the substrate data 112, the net list 113, the observation target data 114, and the manufacturing data 115.

  The library 111 stores component data related to various components arranged on the wiring board. Each component data includes data representing the shape of the corresponding component, data representing the arrangement of terminals (pins), and the like. As a result, the library 111 is referred to in layout design for determining the arrangement of parts.

  The board data 112 is data related to the wiring board such as the outer shape of the wiring board and the number of layers. The net list 113 is data obtained as a result of logical design. The net list 113 describes the connection relationship between terminals (pins). The observation target data 114 is data that represents between terminals that are signal observation targets among the terminals (nets) in which the net list 113 describes the connection relationship. This observation target data 114 is generated, for example, by designating a terminal (net) that the user desires to observe.

  The manufacturing data 115 is data representing the design result of the wiring board, and is used for actual manufacturing of the wiring board. Similar to the net list 113, the manufacturing data 115 is associated with observation target data.

  The input control unit 12 is a function that allows various data to be input by operating the input device 2. Various data includes commands and the like. The output control unit 13 is a function that enables image display by the display device 3.

  The wiring board design support unit 14 is a function for supporting the design of the wiring board. As shown in FIG. 1, the wiring board design support unit 14 includes a circuit design support unit 141 and a layout design support unit 142.

  The circuit design support unit 141 is a function for supporting function design, logic design, and the like of an electric circuit manufactured using a wiring board. The library 111 is created with components that can be employed in the electrical circuit, or updated as necessary. As described above, the net list 113 is created as a result of logical design. The specifications are created at the stage of circuit design.

  The layout design support unit 142 is a function for supporting layout design for determining the positions of components to be arranged on the wiring board and the wiring connecting the components. Hereinafter, in order to avoid confusion, the wiring formed on the wiring board is referred to as a “wiring pattern”.

  As shown in FIG. 1, the layout design support unit 142 includes a component placement / wiring unit 145 and a test pad placement / wiring unit 146.

  The component placement / wiring unit 145 refers to the library 111, the board data 112, and the net list 113, and performs layout design that determines the position of the component, the position of the wiring pattern, and the shape within the shape represented by the board data 112. . For the layout design, the layout design support unit 142 has a function of supporting the creation of the board data 112.

  Manufacturing data 115 for manufacturing a wiring board is created by the layout design performed by the component placement / wiring unit 145. The test pad placement / wiring unit 146 refers to the manufacturing data 115 and the observation target data 114, and electrically determines the position where the test pad is to be placed and the wiring pattern and the test pad placed between the terminals to be observed. This is a function for determining a connection path to connect to. When the test pad is added, the manufacturing data 115 is updated according to the addition. Hereinafter, “connection” is used to mean electrical connection unless otherwise specified.

  As shown in FIG. 1, the test pad placement / wiring unit 146 includes a test pad placement unit 1461, a via placement unit 1462, and a via wiring unit 1463.

  The test pad placement unit 1461 has a function of referring to the manufacturing data 115 and determining a position where the test pad is to be placed. The via placement unit 1462 determines a position where a via used for connecting the test pad and the target wiring pattern is to be placed. The via wiring unit 1463 determines the shape and arrangement of the wiring pattern for connecting the test pad and the target wiring pattern through the via.

  In this embodiment, the rule (premise) is that one or more vias are used for connection between the test pad and the target wiring pattern. Therefore, when the target wiring pattern and the test pad are arranged in different layers, the position of at least one via is determined. When the target wiring pattern and the test pad are arranged in the same layer, the positions of at least two vias are determined. Will be.

  According to this rule, in the determination of the position where the test pad is to be arranged, options for searching for the layer on which the test pad is arranged are increased. Therefore, compared to a conventional arrangement method (for example, Patent Document 1) in which a touch pad is arranged so as to overlap with a wiring pattern to be observed (hereinafter referred to as “target wiring pattern”), the test pad is arranged in a different manner. The degree of freedom increases.

  The two wiring patterns for transmitting the differential signal are usually arranged at a narrow interval (wiring pitch). The test pad is usually larger than the width of the wiring pattern. Therefore, when a differential signal is to be observed, it is unlikely that this conventional arrangement method can be applied. This means that it is necessary to perform an operation in consideration of the placement of the test pad on the target wiring pattern.

  However, when the target wiring pattern and the test pad are connected via the via, there is no restriction in arrangement due to the relationship between the size of the test pad and the wiring pitch. Even in this respect, the degree of freedom in the arrangement of the test pad is increased. Therefore, the target wiring pattern can be more reliably connected to the test pad without performing an operation in consideration of the placement of the test pad on the target wiring pattern.

  In the present embodiment, one of the vias connecting the target wiring pattern and the test pad is brought into direct contact with the target wiring pattern. More specifically, the vias are arranged so that the end portions thereof overlap the target wiring pattern. Accordingly, the wiring patterns determined by the via wiring portion 1463 are roughly classified into two types, that is, a wiring pattern that connects a via and a test pad, and a wiring pattern that connects two vias.

  The reason for arranging the vias so that the end portion overlaps the target wiring pattern is to make it possible to more effectively reduce the adverse effects that occur in the target wiring pattern by connecting to the test pad, as will be described in detail later. is there. By reducing the adverse effect, the signal quality on the target wiring pattern can be made higher.

  Currently, a method for cutting and removing excess portions of vias has been developed. The construction method is a back drill. When the back drill is used, the via connected to the target wiring pattern can be easily cut and removed. By the cutting and removal, the target wiring pattern and the test pad are electrically separated, and the length in the depth direction of the via connected to the target wiring pattern is minimized. It is not necessary to form a wiring pattern that directly connects the target wiring pattern and the via. From these things, the signal deterioration accompanying connecting the object wiring pattern to the test pad can be eliminated or suppressed. As such, there are many advantages in arranging the vias so that the end portions overlap the target wiring pattern.

  In the present embodiment, one test pad is basically arranged for one target wiring pattern. However, depending on the wiring board, the number of target wiring patterns (signals) may be relatively large. The number of test pads that can be arranged depends on the number and type of components arranged on the wiring board. For this reason, it is not always possible to place a test pad for each target wiring pattern.

  When a test pad cannot be arranged for each target wiring pattern, at least the layout design must be performed again. However, when the layout design is performed again, a long time is required. Therefore, in the present embodiment, priority is given to enabling observation of signals to be observed, and a plurality of target wiring patterns are connected to one test pad as necessary.

  By connecting a plurality of target wiring patterns to one test pad, the margin required for test pad arrangement and further via arrangement becomes smaller. By back drilling vias connected to each target wiring pattern, only one of the signals on each target wiring pattern can be transmitted to the test pad. A signal to be transmitted to the test pad can be selected according to a via for performing a back drill, a cutting amount by the back drill, and the like. For this reason, all signals to be observed can be observed without redesigning the layout.

  The differential signal is two signals transmitted using two wiring patterns. Therefore, the two signals constituting the differential signal are each treated as one signal to be observed and transmitted to different test pads.

  FIG. 2 is a diagram illustrating a hardware configuration example of a data processing apparatus that can be used as the wiring board design support apparatus according to the present embodiment. Next, a hardware configuration example of the data processing apparatus that can be used as the wiring board design support apparatus 1 according to the present embodiment will be specifically described with reference to FIG.

  In FIG. 2, the components corresponding to those in FIG. Accordingly, the data processing device (computer) is assigned “1” as a code. FIG. 2 shows a program according to the present embodiment and a storage destination thereof.

  As shown in FIG. 2, the data processing device 1 includes a CPU (Central Processing Unit) 21, a RAM (Random Access Memory) 22, a ROM (Read Only Memory) 23, an optical disk device 24, a hard disk device (HDD: Hard Disk Drive). ) 25, NIC (Network Interface Card) 26, GC (Graphic Card) 27, I / F (InterFace) card 28, and bus 29.

  The ROM 23 is a read-only nonvolatile storage medium and stores firmware and various data. The RAM 22 is a volatile storage medium capable of reading and writing information at high speed, and is used as a work area when the CPU 21 processes information.

  The optical disk device 24 is a recording medium driving device corresponding to various optical disks such as a CD (Compact Disk), a CD-ROM, and a DVD (Digital Versatile Disk). The hard disk device 25 is a storage device capable of reading and writing information, and one or more hard disks 250 are mounted as a recording medium. In addition to various data, the hard disk 250 stores various programs such as an OS (Operating System), various control programs, and various application programs (hereinafter abbreviated as “application”).

  The NIC 26 is a communication device that enables communication via a network. The GC 27 develops the image data from the CPU 21 into a bitmap pattern, converts it into data in a format that can be handled by the display device 3, and outputs the data. The I / F card 28 is a device for connection with other peripheral devices. The I / F card 28 performs communication with a keyboard 2a used as the input device 2 and a PD (Pointing device) 2b typified by a mouse. The bus 29 connects the above-described components 21 to 28 to each other.

  Various applications stored in the hard disk 250 include a design support program 251 that is software for supporting the design of the wiring board. The design support program 251 is prepared as a CAD (Computer-Aided Design) tool, for example, and corresponds to the program according to the present embodiment in a broad sense. The wiring board design support apparatus 1 shown in FIG. 1, that is, the wiring board design support unit 14 is realized by the CPU 21 executing the design support program 251 under the control of the OS. Thereby, the wiring board design support unit 14 is realized by the CPU 21, the RAM 22, the ROM 23, the hard disk device 25, and the bus 29, for example.

  The design support program 251 includes a test pad placement support program 252 as a subprogram. The test pad placement / wiring unit 146 is realized by the CPU 21 executing the test pad placement support program 252. The test pad arrangement support program 252 corresponds to the program according to the present embodiment in a narrow sense.

  The storage unit 11 corresponds to, for example, the hard disk device 25 and the RAM 22. This is because data stored in the hard disk device 25 is read into the RAM 22 and processed. The GC 27 corresponds to the output control unit 13.

  Data can be input via the optical disc device 24 and the NIC 26 in addition to the input device 2. Data input requires processing by the CPU 21. Thus, the input control unit 12 is realized by the CPU 21, RAM 22, ROM 23, optical disk device 24, hard disk device 25, NIC 26, I / F card 28, and bus 29.

  The main control unit 15 controls the wiring board design support unit 14, that is, controls execution of the design support program 251. Therefore, the main control unit 15 is realized by the CPU 21 executing the OS. Thereby, the main control unit 15 is realized by, for example, the CPU 21, the RAM 22, the ROM 23, the hard disk device 25, and the bus 29.

  As described above, the wiring board according to the present embodiment is realized by performing design using the wiring board design support apparatus 1 according to the present embodiment and manufacturing according to the design result. A specific example of the wiring board according to the present embodiment will now be described in detail with reference to FIGS.

  First, the wiring board according to the first and second embodiments will be described in detail with reference to FIGS. 3A and 3B are diagrams for explaining the wiring board according to the first embodiment. FIG. 3A shows a top view and FIG. 3B shows a rear view.

  In FIG. 3, for convenience of explanation, the target wiring pattern and the components connected to the target wiring pattern are emphasized together with the structure formed so that a signal transmitted on the target wiring pattern can be taken out. It is represented by Accordingly, FIG. 3 shows that four wiring patterns 33 (33a to 33d) for connecting between two components of an IC (Integrated Circuit) 31 and a connector 32 are used as target wiring patterns. Note that “wiring board (front surface)” shown in FIG. 3A represents the first layer of the wiring board 30, and “wiring board (back face)” shown in FIG. Represents.

  The four wiring patterns 33 are for transmitting two differential signals. One differential signal is transmitted by, for example, two wiring patterns 33a and 33b, and the other differential signal is transmitted by two wiring patterns 33c and 33d.

  As shown in FIG. 3A, the two wiring patterns 33a and 33b are formed with vias 34a and 34b overlapping at the same or substantially the same position in the direction connecting the IC 31 and the connector 32. . Similarly, vias 34c and 34d are also formed on the two wiring patterns 33c and 33d in the same or substantially the same position in the direction connecting the IC 31 and the connector 32. In this way, the positions of the vias 34 are aligned in the direction in which the wiring pattern 33 extends, which suppresses the difference in characteristics (for example, impedance discontinuity) between the paired wiring patterns 33 and This is in order to suppress problems in observation due to the position where the signal is extracted via the via 34.

  The size of the via 34 in the width direction of the wiring pattern 33 can be equal to or less than the width of the wiring pattern 33. In the present embodiment, the width of the wiring pattern 33 and the size of the via 34 are the same. Therefore, the degree of freedom in the arrangement of the vias 34 is high, and the vias 34 can be arranged at desired positions due to the characteristics of the wiring patterns 33. Also from such an advantage, the via 34 is arranged so as to be directly connected to the wiring pattern 33.

  As shown in FIG. 3B, each via 34 (34a to 34d) penetrates from the first layer to the lowermost fourth layer. In the fourth layer, four test pads 35 (35a to 35d) for taking out signals transmitted through the wiring patterns 33 are formed, and the vias 34 (34a to 34d) are respectively connected to the wiring patterns 36 (36a to 36d). ) To each test pad 35. In this way, vias 34, test pads 35, and wiring patterns 36 are formed in each wiring pattern 33 as structures for extracting signals.

  FIG. 4 is a diagram illustrating a connection path between the target wiring pattern and the test pad in the first embodiment on a cross section. FIG. 4 schematically shows a connection path between the wiring pattern 33a and the test pad 35a as an example.

  The wiring board 30 according to the present embodiment is a four-layer multilayer board as shown in FIG. The first layer and the lowermost fourth layer are, for example, signal layers on which signal wiring patterns are formed and components are to be mounted. Thereby, the formation object of the test pad 35 is the first layer and the fourth layer. The second layer is a ground layer on which a ground (GND) plane 41 is formed, and the third layer is a power supply layer on which a power supply plane 42 is formed. The via 34a is formed so as not to be connected to the ground plane 41 and the power supply plane 42, like the other vias 34b to 34d.

  In the present embodiment, the test pad 35 is formed on the fourth layer. This is because, in the fourth layer, there is a margin for arranging the test pads 35, and defects (deterioration of signal quality, etc.) in extracting signals are relatively small. As a result, in determining the position where the test pad 35 is to be placed, in addition to the space where the test pad 35 can be placed, importance is placed on the quality of the signal to be extracted.

  In the wiring pattern 33a, the via 34a is formed so that the end thereof overlaps the wiring pattern 33a, and the via 34a is connected to the wiring pattern 36a in the fourth layer. Thereby, the structure constituting the connection path for connecting the wiring pattern 33a and the test pad 35a is the via 34a and the wiring pattern 36a.

  FIG. 5 is a diagram for explaining a wiring board according to the second embodiment. The wiring board 30 according to the second embodiment is manufactured by processing the wiring board 30 according to the first embodiment. Therefore, FIG. 5 shows the details of processing performed on the wiring board 30 according to the first embodiment. Since the wiring board 30 according to the first embodiment is a base, the reference numerals given in the first embodiment are used as they are in FIG.

  The connection between the wiring pattern 33a and the test pad 35a degrades the quality of a signal transmitted through the wiring pattern 33a. The connection does not need to be maintained after the observation. The connection can be cut off by removing the via 34a as shown in FIG.

  A back drill can be used to remove the via 34a. The arrows shown in FIG. 5 indicate the direction in which the via 34a is removed by back drilling and the depth thereof. Accordingly, FIG. 5 shows that the via 34a is removed by back drilling from the fourth layer side to the second layer.

  As a result, in the wiring substrate 30 according to the second embodiment, only a part of the via 34a and the wiring pattern 36a remain in the structure constituting the connection path connecting the wiring pattern 33a and the test pad 35a. Yes. In other words, these structures enable the electrical connection between the wiring pattern 33a and the test pad 35a when a hole formed by cutting and removing the via 34a is regarded as a conductor. This is the same between the other wiring patterns 33 and the test pads 35.

  As shown in FIG. 3, when the via 34 is arranged so that the end portion overlaps the target wiring pattern 33, no new restriction occurs when the target wiring pattern 33 is arranged. Because of the connection path to be connected to the test pad, it is not necessary to perform an operation on the target wiring pattern 33 to deteriorate the characteristics. Further, as shown in FIG. 5, the connection between the wiring pattern 33 (33a) and the test pad 35 (35a) can be cut off by cutting and removing unnecessary portions of the via 34a. By the cutting and removal, a portion (here, the length of the via 34a) connected to the wiring pattern 33a in the connection path to the test pad 35a can be further shortened.

  For this reason, in the wiring board 30 according to the second embodiment, the characteristics of each wiring pattern 33 are improved to be more desirable as compared with the wiring board 30 according to the first embodiment. Thereby, the transmitted signal quality is also higher.

  When the connection between the target wiring pattern 33 and the test pad 35 is cut off, the characteristics of the target wiring pattern 33 can be expected to be improved as compared with the case where the connection is maintained. For this reason, the via 34 may be formed so that the end thereof does not overlap the target wiring pattern 33. Since the connection between the target wiring pattern 33 and the test pad 35 is cut off by cutting and removing the via 34, the wiring board to be designed using the wiring board design support apparatus 1 according to the present embodiment has two or more layers. good. Accordingly, the term “multilayer” is used to mean two or more layers.

  In this embodiment, each test pad 35 is connected to each via 34 via a wiring pattern 36, but each test pad 35 may be directly connected to each via 34. In the removal of the via 34 by cutting, it is desirable to remove as much as possible as much as possible. However, the cutting can be cut off by cutting and removing one layer or more. For this reason, the hole formed by cutting and removing the via 34 only needs to penetrate one or more layers.

  In the following description of the wiring board according to another embodiment, attention is paid to a different part from the wiring board 30 according to the first and second embodiments. In addition, the same reference numerals are given to structures that can be regarded as the same or basically the same. In addition, when there is no need to particularly limit the embodiment, the reference numerals are not used.

  Next, the wiring boards according to the third and fourth embodiments will be described in detail with reference to FIGS.

  6A and 6B are views for explaining a wiring board according to the third embodiment, in which FIG. 6A shows a top view and FIG. 6B shows a rear view. In FIG. 6 as well, for convenience of explanation, the target wiring pattern and the components to which the target wiring pattern is connected are highlighted together with the structure formed so that signals transmitted on the target wiring pattern can be taken out. It is represented by

  In the wiring board 30 according to the second embodiment, the two wiring patterns 61 (61a and 61b) that connect the two components of the IC 31 and the connector 32 are set as target wiring patterns. The two wiring patterns 61 are for transmitting one differential signal.

  As shown in FIG. 6A, the two wiring patterns 61a and 61b are formed with vias 62a and 62b overlapping at the same or substantially the same position in the direction connecting the IC 31 and the connector 32. . In the first layer, two test pads 63 (63a, 63b), two vias 64 (64a, 64b), and two wiring patterns 65 (65a, 65b) are formed.

  The four vias 62 and 64 are both penetrated from the first layer to the fourth layer. As shown in FIG. 6B, the via 62a and the via 64a are connected via a wiring pattern 66a formed in the fourth layer. Similarly, the via 62b and the via 64b are connected via a fourth-layer wiring pattern 66b.

  FIG. 7 is a diagram for explaining a connection path between a target wiring pattern and a test pad in the third embodiment. FIG. 7 schematically shows a connection path between the wiring pattern 61a and the test pad 63a as an example. The connection path is shown by paying attention to the connection relationship in each layer.

  In the third embodiment, the test pad 63 is formed in the same layer as the wiring pattern 61 that is the target wiring pattern. This is a result of arranging the test pad 63 in consideration of a margin for arranging the test pad 63, a defect in extracting a signal (deterioration of signal quality, etc.), and the like. Thereby, the connection path connecting the wiring pattern 61a and the test pad 63a is realized by the respective structures of the via 62a, the wiring patterns 65a and 66a, and the via 64a. This is the same between the wiring pattern 61b and the test pad 63b.

  FIG. 8 is a view for explaining a wiring board according to the fourth embodiment. The wiring board 30 according to the fourth embodiment is manufactured by processing the wiring board 30 according to the third embodiment, similarly to the wiring board 30 according to the second embodiment. Therefore, FIG. 8 also shows the details of processing performed on the wiring board 30 according to the third embodiment. Since the wiring board 30 according to the third embodiment is a base, the reference numerals given in the third embodiment are used as they are.

  In the fourth embodiment, as shown in FIG. 8, the connection between the wiring pattern 61a and the test pad 63a is blocked by cutting and removing the via 34a from the fourth layer side to the second layer with a back drill. . The via 64a is not removed by cutting. This is because the connection between the via 62a and the test pad 63a is interrupted by cutting and removing the via 62a, and the characteristics of the wiring pattern 61a can be greatly improved (improved) by the disconnection. The reason for cutting and removing from the fourth layer to the second layer is to further improve the characteristics of the wiring pattern 61a. These are the same between the wiring pattern 61b and the test pad 63b.

  The improvement of the characteristics of the wiring pattern 61a can also be realized by cutting and removing the via 64a. For this reason, if it is difficult to remove the via 62a for some reason, the via 64a may be removed. Since the cut off itself can be performed by deleting one or more layers, the hole formed by cutting and removing penetrates one or more layers regardless of whether the via 62a or the via 64a is targeted. Anything is fine.

  Finally, the wiring boards according to the fifth to ninth embodiments will be specifically described with reference to FIGS. Each of the wiring boards 30 according to the sixth to ninth embodiments is manufactured by processing the wiring board 30 according to the fifth embodiment.

  9A and 9B are diagrams for explaining a wiring board according to the fifth embodiment, in which FIG. 9A shows a top view and FIG. 9B shows a rear view. In FIG. 9 as well, for convenience of explanation, the object wiring pattern and the components connected to the object wiring pattern are emphasized, as well as the structure formed so that signals transmitted on the object wiring pattern can be taken out. It is represented by

  In the wiring board 30 according to the fifth embodiment, the three wiring patterns 91 (91a to 91c) for connecting the two components of the IC 31 and the connector 32 are set as target wiring patterns. These three wiring patterns 91 are for transmitting one independent signal.

  As shown in FIG. 9A, the three wiring patterns 91 are formed with vias 92 (92a to 92c) overlapping at the same or substantially the same position in the direction connecting the IC 31 and the connector 32. In addition, one test pad 93, one via 94, and a wiring pattern 95 that connects the test pad 93 and the via 94 are formed in the first layer.

  The four vias 92 and 94 are both penetrated from the first layer to the fourth layer. As shown in FIG. 9B, the via 92c and the via 94 are electrically connected by a wiring pattern 96c formed in the fourth layer. The via 92b and the via 94 are electrically connected by a wiring pattern 96b formed in the third layer. The via 92a and the via 94 are electrically connected by a wiring pattern 96a formed in the second layer. Since the wiring patterns 96a and 96b are formed in the second layer and the third layer, respectively, in FIG. 9B, the wiring pattern 96a is drawn by a broken line, and the wiring pattern 96b is drawn by an alternate long and short dash line.

  FIG. 10 is a diagram for explaining a connection path between a target wiring pattern and a test pad in the fifth embodiment. Similar to FIGS. 4 and 7, the connection path is shown in a form focusing on the connection relationship in each layer.

  In the fifth embodiment, as described above, each of the vias 92a to 92c is connected to the via 94 via the wiring patterns 96a to 96c. Thereby, all the three wiring patterns 91a to 91c are connected to one test pad 93, and the test pad 93 is shared by the three wiring patterns 91a to 91c.

  The connection path between the wiring pattern 91a and the test pad 93 is realized by each structure of the via 92a, the wiring pattern 96a, the via 94, and the wiring pattern 95. The connection path between the wiring pattern 91b and the test pad 93 is realized by each structure of the via 92b, the wiring pattern 96b, the via 94, and the wiring pattern 95. The connection path between the wiring pattern 91c and the test pad 93 is realized by the structures of the via 92c, the wiring pattern 96c, the via 94, and the wiring pattern 95.

  As shown in FIG. 10, when each wiring pattern 91 is connected to one test pad 93, the selection of the via 92 that performs cutting removal in each via 92 and the adjustment of the depth for performing the cutting removal The signal that can be extracted from the test pad 93 can be changed. All the wiring patterns 91 can be insulated from the test pad 93. The wiring boards 30 according to the sixth to eighth embodiments respectively test only signals transmitted on the wiring pattern 91a, the wiring pattern 91b, and the wiring pattern 91c with respect to the wiring board 30 according to the fifth embodiment. It is processed so that it can be taken out from the pad 93. The wiring board 30 according to the ninth embodiment is obtained by processing all the wiring patterns 91 with respect to the test pads 93 with respect to the wiring board 30 according to the fifth embodiment.

  FIG. 11 is a diagram for explaining processing contents performed on the wiring board according to the fifth embodiment in order to produce the wiring board according to the sixth embodiment. In the wiring board 30 according to the sixth embodiment, as shown in FIG. 11, the fourth layer for the vias 92a and 94 and the third layer for the third layer are cut and removed, and the fourth layer for the vias 92b and 92c. Cutting and removal of three layers of the second layer are performed. As a result, only the signal on the wiring pattern 91 a can be taken out from the test pad 93 via the via 92 a, the wiring pattern 96 a, the via 94, and the wiring pattern 95.

  FIG. 12 is a diagram for explaining processing contents performed on the wiring board according to the fifth embodiment in order to manufacture the wiring board according to the seventh embodiment. In the wiring board 30 according to the seventh embodiment, as shown in FIG. 12, the removal of three layers from the fourth layer to the second layer with respect to the vias 92 a and 92 c and the first layer of the fourth layer with respect to the vias 92 b and 94 are provided. Each layer is cut and removed. Thereby, only the signal on the wiring pattern 91 b can be taken out from the test pad 93 through the via 92 b, the wiring pattern 96 b, the via 94, and the wiring pattern 95.

  FIG. 13 is a diagram for explaining processing contents performed on the wiring board according to the fifth embodiment in order to produce the wiring board according to the eighth embodiment. As shown in FIG. 13, the wiring board 30 according to the eighth embodiment is cut and removed from the vias 92 a and 92 b by three layers from the fourth layer to the second layer. As a result, only the signal on the wiring pattern 91 c can be taken out from the test pad 93 via the via 92 c, the wiring pattern 96 c, the via 94, and the wiring pattern 95.

  FIG. 14 is a diagram for explaining the contents of processing performed on the wiring board according to the fifth embodiment in order to produce the wiring board according to the ninth embodiment. As shown in FIG. 14, the wiring substrate 30 according to the ninth embodiment is subjected to cutting and removing for three layers from the fourth layer to the second layer with respect to the vias 92 a to 92 c. Thereby, the connection between each wiring pattern 91 and the test pad 93 is cut off, and each wiring pattern 91 is insulated from the test pad 93.

  When each wiring pattern 91 is connected to one test pad 93, each wiring pattern 91 is selected by selecting the via 92 to be cut and removed from each via 92 and adjusting the depth to be cut and removed. The connection relationship between the pattern 91 and the test pad 93 can be arbitrarily changed. By sharing a plurality of wiring patterns 91 with one test pad 93, all necessary test pads including the test pad 93 can be more reliably arranged. For this reason, the wiring board 30 capable of observing all the signals desired to be observed can be more reliably designed without redesigning the layout.

  In the fifth embodiment, the vias 92 and the vias 94 are connected by different wiring patterns 96, but they may be connected by the same wiring pattern 96, for example, the wiring pattern 96c. This is because even if such a connection is made, the connection relationship between each wiring pattern 91 and the test pad 93 can be arbitrarily changed by selecting the via 92 to be cut and removed in the via 92. For this reason, the connection path of each wiring pattern 91 for sharing the test pad 93 can be variously modified.

  The wiring board 30 according to the first, third, and fifth embodiments is realized by causing the test pad arrangement support program 252 to process the manufacturing data 115 in which the design results of the multilayer, that is, two or more wiring boards are stored. Is done. Through the processing, the manufacturing data 115 is updated to contents including the test pad and the structure (connection path) that connects the test pad to the target wiring pattern. Next, test pad placement / wiring processing realized by the CPU 21 executing the test pad placement support program 252 will be described in detail with reference to the flowcharts shown in FIGS. 15 and 16.

  In the present embodiment, the updated manufacturing data 115 is stored separately from the pre-update manufacturing data 115. This is because there is a possibility that the target wiring pattern is changed, that is, the target wiring pattern is deleted or added. The updated manufacturing data 115 is hereinafter referred to as “manufacturing data 115m” in order to distinguish it from the manufacturing data 115 before the update.

  The test pad arrangement support program 252 is executed in accordance with, for example, a user instruction or setting. For example, the user can instruct execution at the end of layout design by the component placement / wiring unit 145 and can instruct execution by designating the existing manufacturing data 115.

  The test pad arrangement support program 252 refers to the observation target data 114 at the time of execution. As described above, the observation target data 114 is generated by designating the terminals (nets) that the user desires to observe, and is associated with the net list 113 and the manufacturing data 115. When the test pad placement support program 252 is executed, the target manufacturing data 115 is fixed. As a result, the test pad arrangement support program 252 can specify the observation target data 114 to be referred to.

  When the control is passed to the test pad arrangement support program 252, first, the CPU 21 reads the observation target data 114 via the RAM 22 (S1501). Next, the CPU 21 refers to the read observation target data 114 and determines whether there is a target wiring pattern (net) to be processed (S1502). If there is a target wiring pattern to be processed, the determination in S1502 is YES and the process proceeds to S1503. If not, that is, if there is no target wiring pattern to be processed, the determination in S1502 is NO, and after the updated manufacturing data 115 is stored, this test pad placement / wiring process ends.

  In S1503, the CPU 21 selects one of the unprocessed target wiring patterns. Next, the CPU 21 refers to the manufacturing data 115 and searches for the number of test pad placement locations corresponding to the type of the selected target wiring pattern (S1504). The number of test pads whose location is to be searched is 2 if the selected target wiring pattern is for a differential signal, and one target wiring pattern is for transmitting one independent signal. 1 for example.

  In step S <b> 1505, which is performed after the placement location search, the CPU 21 determines whether there is a place where the test pad can be placed. If a place where the test pad can be placed can be found, the determination in S1505 is YES and the process proceeds to S1506. If the location where the test pad can be placed cannot be found, the determination in S1505 is NO and the process proceeds to S1510.

  In S1506, the CPU 21 determines whether or not the found location is the same layer, that is, whether or not the found location is the same as the layer where the selected target wiring pattern is arranged. When the test pad is to be arranged in the same layer as the target wiring pattern (see FIGS. 6 and 9), the determination in S1506 is YES and the process proceeds to S1507, and the CPU 21 arranges two vias in one target wiring pattern. A place search is performed (see FIGS. 7 and 10). Thereafter, the process proceeds to S1509. When the test pad is to be arranged in a layer different from the target wiring pattern (see FIG. 3), the determination in S1506 is NO and the process proceeds to S1508, and the CPU 21 determines the location of one via arrangement in one target wiring pattern. A search is performed (see FIG. 4). Thereafter, the process proceeds to S1509.

  In step S1509, the CPU 21 determines whether there is a place where a via can be arranged. If a location where vias can be placed is found, the determination in S1509 is YES, and the process proceeds to S1510. The CPU 21 determines two more vias depending on the wiring pattern that connects the via and the test pad and the selected target wiring pattern. The route of the wiring pattern to be connected is determined. Thereafter, the process returns to S1502, and it is determined whether or not an unprocessed target wiring pattern exists. On the other hand, if the location where the via can be placed cannot be found, the determination in S1509 is NO and the process proceeds to S1511.

  The determination of NO in S1509 or the transition to S1511 due to the determination of NO in S1505 means that the selected target wiring pattern cannot be connected to the test pad. For this reason, in S1511 and subsequent steps, a series of processes for dealing with the situation is performed.

  In step S1511, the CPU 21 searches for a test pad that can be shared among the test pads whose arrangement locations have already been set. Next, as a result of the search, the CPU 21 determines whether there is a test pad that can be connected to the selected target wiring pattern (S1512). If there is a test pad that can be connected to the selected target wiring pattern among the test pads for which the placement location has already been set, the determination in S1512 is YES and the process moves to S1513. If there is no test pad that can be connected to the selected target wiring pattern among the test pads whose placement locations have already been set, the determination in S1512 is NO and the process proceeds to S1514 in FIG.

  In S1513, the CPU 21 extracts the optimum test pad from the test pads connectable to the selected target wiring pattern, searches for the position of the via used for connecting the extracted test pad and the target wiring pattern, and necessary wiring. Determine the path of the pattern. In determining the route of the wiring pattern, the shape and other wiring patterns whose routes have already been determined are changed as necessary. In this manner, after determining the connection path between the extracted test pad and the target wiring pattern, the process returns to S1502.

  The wiring board 30 according to the fifth embodiment shown in FIGS. 9 and 10 can be realized when S1511 to S1513 are executed at least twice and the test pad 93 is extracted each time. In the wiring board 30 according to the fifth embodiment, for example, a connection path between the target wiring pattern 91c and the test pad 93 is first determined. Thereafter, the connection path between the target wiring pattern 91b and the test pad 93 and the connection path between the target wiring pattern 91a and the test pad 93 are sequentially determined by executing S1510 to S1513 twice. Thereby, the wiring board 30 as in the fifth embodiment is designed.

  The wiring patterns 96a and 96b are arranged in the second layer and the third layer, respectively. This is because it is a rule that each wiring pattern 96 is connected to the test pad 93 through different vias 92. Thereby, in the wiring pattern 96b, the second-layer ground plane 41 is changed so as not to be connected to the via 92b, and the wiring pattern 96b can be arranged so that the third-layer power plane 42 is not connected to the via 92b. Will be changed. Similarly, in the wiring pattern 96a, the third-layer power plane 42 is changed so as not to be connected to the via 92a, and the wiring pattern 96a can be arranged so that the second-layer ground plane 41 is not connected to the via 92a. Will be changed as follows.

  The determination of whether or not there is a test pad that can be connected to the selected target wiring pattern in S1512 and whether or not there is a place where the test pad can be placed in S1505 are actually vias and wiring patterns. It is carried out in consideration of each arrangement. Thereby, each arrangement of the test pad, the via, and the wiring pattern is determined to be optimal.

  The transition to S1514 in FIG. 16 means that the connection path for connecting the selected target wiring pattern to the test pad cannot be automatically determined. Therefore, in S1514 and subsequent steps, a series of processes for responding to the situation is performed in accordance with the user's instruction.

  In S1514, for example, the CPU 21 displays an image (including a message) representing the current situation on the display device 3, and requests the user for an instruction via the input device 2. When the instruction is given by the user, the process proceeds to S1515, and the CPU 21 determines the content of the instruction.

  If the user instructs the end, in S1515, that is determined, and the process proceeds to S1516. In S1516, the CPU 21 stores the results up to the present time according to the user's instruction. Thereafter, the test pad placement / wiring process is completed.

  In the present embodiment, there are two types of end instructions: a storage end instruction for storing results up to the present time, and a discard end instruction for discarding results up to the present time. Thereby, only when the user selects a storage end instruction, the result is stored, that is, the manufacturing data 115m is generated.

  The image representing the current situation includes information related to the target wiring pattern that cannot be connected to the test pad and information related to the target wiring pattern that can be connected to the test pad. The information related to the target wiring pattern that cannot be connected to the test pad includes information related to the target wiring pattern that could not find the test pad to be connected. In this embodiment, the user can specify the location of the test pad to be connected to the target wiring pattern. Thereby, when the user designates the location designation, in S1515, the fact is determined, and the process proceeds to S1517.

  In step S1517, the CPU 21 inputs at least a place where a test pad is to be placed in accordance with a user operation on the input device 2, and determines a connection path for connecting the test pad placed at that place and the target wiring pattern. When the user designates a location where a via is to be arranged or a route of a wiring pattern, the designated location is reflected in the determination of the connection route. Thereafter, the process returns to S1502 in FIG.

  Thus, in this embodiment, the user can designate the test pad to be connected to the target wiring pattern and the connection path to be connected to the test pad. Thereby, the user can connect an arbitrary target wiring pattern to a test pad arranged at an arbitrary place.

  Test pad placement, via placement, and wiring pattern placement are all determined so as not to violate the design rules. The margin for arranging them increases as the design rules become stricter. As a result, the stricter the design rule, the higher the possibility that the target wiring pattern can be connected to the test pad. Thus, in this embodiment, the user can change the design rule. If the user has instructed to change the rule, in S1515, the fact is determined, and the process proceeds to S1518.

  In step S <b> 1518, the CPU 21 changes the design rule according to the user operation on the input device 2. Next, the CPU 21 reselects the target wiring pattern selected in the immediately preceding S1503 (S1519). Thereafter, the process returns to S1503 in FIG.

  There is a possibility that the test pad can be connected to another unprocessed target wiring pattern even if the test pad cannot be connected to the currently selected target wiring pattern. For this reason, in the present embodiment, the processing for the other unprocessed target wiring pattern can be continued by skipping the processing of the currently selected target wiring pattern. If the user has instructed that skip, in S1515, that is determined, and the process returns to S1502 in FIG. Accordingly, when another unprocessed target wiring pattern exists, the target wiring pattern selected from the target wiring patterns is processed.

  In this embodiment, the changed design rule is applied only to the unprocessed target wiring pattern. However, the processing of the target wiring pattern may be performed from the beginning in accordance with the change of the design rule. The user may be allowed to select whether or not to process the target wiring pattern from the beginning.

  In this embodiment, the test pad arrangement support program 252 is a subprogram of the design support program 251. However, the test pad arrangement support program 252 may be commercialized as one application.

DESCRIPTION OF SYMBOLS 1 Wiring board design support apparatus, data processing apparatus 2 Input device 3 Display apparatus 11 Storage part 12 Input control part 13 Output control part 14 Wiring board design support part 15 Main control part 21 CPU
22 RAM
23 ROM
24 Optical disk device 25 Hard disk device 27 GC
28 I / F card 30 Wiring board 31 IC
32 Connector 33, 33a to 33d, 61, 61a, 61b, 91, 91a to 91c Target wiring pattern 34, 34a to 34d, 62, 62a, 62b, 64, 64a, 64b, 92, 92a to 92c, 94 Via 35, 35a to 35d, 63, 63a, 63b, 93 Test pads 36, 36a to 36d, 66, 66a, 66b, 95, 96, 96a to 96c Wiring pattern 111 Library 112 Substrate data 113 Netlist 114 Observation target data 115 Manufacturing data 141 Circuit design support unit 142 Layout design support unit 145 Component placement / wiring unit 146 Test pad placement / wiring unit 250 Hard disk 251 Design support program 252 Test pad placement support program 1461 Test pad placement unit 1462 Via placement unit 1 63 via the wiring portion

JP-A-8-30647

Claims (11)

A multilayer wiring board,
A target wiring that is a wiring selected from the wirings formed on the wiring board;
A test pad for observing a signal transmitted on the target wiring;
A connection path including at least one via and electrically connecting the test pad and the target wiring;
A wiring board comprising:   The wiring board according to claim 1, wherein the via is in direct contact with the target wiring.   3. The device according to claim 1, wherein when there are a plurality of the target wirings, the connection paths of two or more target wirings are electrically connected to the same test pad. 4. Wiring board. A multilayer wiring board,
A target wiring that is a wiring selected from the wirings formed on the wiring board;
A test pad for observing a signal transmitted on the wiring;
A hole through one or more layers,
When the hole is assumed to be a conductor, a structure that allows the test pad and the target wiring to be electrically connected through the hole;
A wiring board comprising:   The wiring board according to claim 4, wherein the hole is directly electrically connected to the target wiring when the hole is assumed to be a conductor.   When there are a plurality of target wirings, the structure of two or more target wirings can electrically connect the two or more target wirings to the same test pad. The wiring board according to claim 4 or 5. A connection path that electrically connects one target wiring of the plurality of target wirings to the test pad when there are a plurality of the target wirings;
The structure of one or more target wirings excluding the one target wiring among the plurality of target wirings is electrically connected to the test pad electrically connected to the one target wiring. 6. The wiring board according to claim 4, wherein the wiring board is made possible. A wiring board design method for designing a multilayer wiring board,
Determining the placement of a test pad for observing a signal transmitted on a target wiring that is a wiring selected from among the wirings formed on the wiring board;
A wiring board design method comprising: determining an arrangement of a structure including at least one via as a connection path for electrically connecting the test pad and the target wiring. A wiring board design support device for supporting the design of a multilayer wiring board,
A storage unit for storing design data representing a layout design result of the wiring board;
A first placement unit that determines the placement of a test pad for observing a signal transmitted on a target wiring, which is a wiring selected from the wirings formed on the wiring board, with reference to the design data When,
A second placement portion that determines the placement of a structure including at least one via as a connection path for electrically connecting the test pad and the target wiring;
A wiring board design support apparatus comprising: The first placement unit has already been placed when there are a plurality of the target wirings, and an indefinite target wiring that is a target wiring for which the placement of the test pad cannot be determined occurs among the plurality of target wirings. Extract a test pad that can be shared from the determined test pads,
The second arrangement unit determines an arrangement of a structure that electrically connects the indeterminate target wiring to the shareable test pad when the shareable test pad is extracted. The wiring board design support apparatus according to claim 9. In a data processing apparatus that can be used as a wiring board design support apparatus for supporting the design of a multilayer wiring board,
Arrangement of a test pad for observing a signal transmitted on a target wiring which is a wiring selected from among wirings formed on the wiring board with reference to design data representing a layout design result of the wiring board To determine
As a connection path for electrically connecting the test pad and the target wiring, the arrangement of the structure including at least one via is determined.
A program characterized by that.