JPH0896012A - Support method for repair of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To decide in real time whether the repair of a semiconductor integrated circuit is possible or not by showing a logic diagram on a display and then designating the logical signal wiring to be changed. CONSTITUTION: The data are read out of a logical file and a logic diagram is shown on a display (302), and an instruction for the change of the logical information is given with a mouse, etc., to the connection information on the logic diagram (303). The signal name corresponding to the connection information on a changing subject is retrieved out of the logical file by an instruction, and the wiring information corresponding to the signal name is read out of a wiring information file based on the retrieved signal name and then displayed (304). A repair possibility rate is calculated to the change of the logical information based on the repair limit information on a repair library and the wiring information on the change and then displayed (305). When the possibility of repair is decided, the repair limit information and the wiring information used in the step 305 are compared with each other. Then the possibility of repair is decided if the repair limit cannot be applied to the wiring changing part (306), and the subsequent wiring changing processes are carried out (307 to 310).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a case where after manufacturing a chip of a semiconductor integrated circuit, a part of the wiring is corrected and processed on the chip by using FIB, laser CVD or the like to repair the logic change. , A semiconductor integrated circuit repair support method for supporting whether or not a logic change can be processed on an actual chip.

[0002]

2. Description of the Related Art After manufacturing a chip of a semiconductor integrated circuit, when a part of the wiring is modified and processed on the chip using FIB, laser CVD, etc., and the repair corresponding to the logic change is performed, the logic change actually occurs. As a repair support technology for determining whether processing is possible on a chip, logical information is changed as described in Japanese Patent Laid-Open No. 2-48775, a difference is detected from information before and after the change, and processing permission / inhibition is determined for the difference signal. Technology has been reported.

[0003]

The above-mentioned conventional technique is a technique for actually changing the logical file and determining whether or not the signal name of the difference information can be actually repaired. It is necessary to check, and as a result, if repair cannot be performed, there is a problem that the design work of returning the file to the original will be backtracked. Further, in a semiconductor integrated circuit which has been multi-layered and miniaturized in recent years, the possibility of repair has been reduced, and thus it was expected that such return work would occur frequently. Furthermore, when the logic designer considers the proposed logic change,
There is a need to think while looking at the logic diagram, but the logic diagram is generally printed on paper, and the time to input the information considered above into the computer again has occurred. . It is an object of the present invention to display a logic diagram on a display such as a workstation and specify a logic signal wiring to be changed on the logic diagram so that repairability can be determined in real time.

[0004]

In order to achieve the above-mentioned object, the present invention is to manufacture a semiconductor integrated circuit chip, and thereafter, to perform FIB (focused ion beam), laser CVD (chemical vapor deposition), etc. on the chip. Is used to modify a part of the existing wiring, or connect an unused gate for logic change that is not related to the prepared logic configuration to change the logic. It is a semiconductor integrated circuit repair support method that determines whether processing is possible on the chip,
The data is read from the logical file, the logical diagram is displayed on the display such as a workstation, the change information of the logical information is instructed by the mouse etc. for the connection information on the logical diagram, and the change target is based on the instruction. The signal name corresponding to the connection information of is searched from the logic file, the wiring information corresponding to the signal name is read from the wiring information file by the searched signal name, displayed on the display, and the repair possibility determination is instructed. At this time, the repair constraint information in the constraint library is compared with the wiring information related to the change, and if the repair constraint does not apply to the changed portion of the wiring, it is determined that the repair is possible,
The subsequent wiring change processing is performed. Also,
The wiring information corresponding to the signal name is read from the wiring information file by the searched signal name, displayed on the display, and then repaired for the change based on the repair constraint information of the constraint library and the wiring information related to the change. The possibility is calculated and displayed on the display. Further, when the wiring information is displayed on the display, the wiring is displayed by identifying the XY two-dimensional coordinate system and the wiring layer by color, and the display of the wiring determined to be repairable is differentiated by a high brightness display or the like. Are displayed.

[0005]

By the above means, the logic diagram which the logic designer has conventionally seen on the paper can be searched on the display such as a workstation, so that the search for the logic information can be performed manually on the paper. It will be easier than. Further, the designation of the signal name to be changed can be designated by a mouse or the like in the logical diagram, which has the effect of improving the designation operability and preventing mistakes. Also, since the information of the logic diagram and the wiring diagram is linked and held as a database on the workstation, the wiring diagram corresponding to the logic changed portion indicated on the logic diagram is displayed on the display in real time. This makes it possible to easily predict repairability. By displaying the repair possibility, it becomes possible to more easily predict the repair possibility. Furthermore, the repairability determination can be automatically obtained based on the repair library and the wiring information file.
In addition, the operability of the operator can be improved by the color coding of the wiring layer and the differential display of the repairable wiring.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the semiconductor integrated circuit, Japanese Unexamined Patent Publication No. 62-22995.
After the chip is manufactured as described in 6, the part of the existing wiring is modified by using FIB (Focused Ion Beam), laser CVD (Chemical Vapor Deposition), etc. on the chip, or the logical structure is formed. Repair is carried out by connecting unused unused gates for logic change to change the logic. Here, in repairing a semiconductor integrated circuit, not all logic changes are actually possible. This is due to the process accuracy of processing equipment such as FIB,
This is because there are some restrictions such as a restriction on the distance between adjacent wirings at the processing location, and other wirings that are obstacles in the sky above the processing location due to the process and the absence of terminals.
Conventionally, a method has been adopted in which a logic change is performed by ignoring such repairability determination, and at the stage of actually searching for a repair location on a wiring diagram, another logic is reconsidered because the location is not found. In the conventional semiconductor integrated circuit having a wiring structure of about three layers, most of the logic changes can be repaired by carrying out the wiring in consideration of repairing. I didn't. However, the number of repairable signals tends to decrease due to the multi-layered wiring of more than five layers in recent years, and the miniaturization of wirings and wiring intervals, and there is a risk of frequent backtracking of design work. Therefore, it is necessary to prevent this. .

FIG. 12 shows an example of a processing system to which the present invention is applied. What is shown in the figure is a WS (workstation) such as X-Windows, a logical file,
The wiring information file and various libraries exist in the hard disk on WS. The display is displayed on the WS CRT.

FIG. 1 shows an example of a repair processing constraint diagram. For example, when the wiring 101 of five layers is cut, it is possible to cut at the cutting point 102 when there is no other wiring at one pitch in the X direction and one pitch in the Y direction. This area 103
If there is a wire in, it means that cutting is not possible.
As shown in FIG. 2, such a restriction rule on processing is a work rule.
It is stored as constraint library information on the station. In this example, for the cutting of 5 layers, the wiring of 5 layers is X,
It means that it cannot exist in one lattice in the Y direction.

FIG. 3 shows an example of a flow chart of a process for determining whether or not a logic change and repair can be performed. When a logic change occurs (301), the logic diagram to be changed is displayed on the workstation (302), and the connection of the logic to be changed is clicked using the external instruction function such as a mouse (30).
3). An example of this processing is shown in FIG. The line 401 is the connection to be changed, and the line 402 is a mouse instruction. The logical diagram displayed on the screen displays the logical symbol and the connection information based on the connection information of the logical file. For example, when a logical file as shown in FIG. 8A exists, a logical diagram as shown in FIG. 8B is created and displayed based on the information.

The wiring diagram of the clicked connection is displayed as another window on the same WS screen (304). An example of this screen is shown in FIG. 501 corresponds to 401 in the logic diagram. The wiring diagram is displayed in the XY two-dimensional coordinate system. Further, the wiring layers may be identified by colors and displayed. The wiring diagram displayed on the screen displays the wiring information defined in the XY coordinate system on the screen, and the wiring information is stored in the wiring information file. FIG. 9A shows an example of the wiring information file, and FIG. 9B shows a wiring diagram displayed by the example. A process of displaying the corresponding wiring diagram in response to a click on the logical diagram will be described with reference to the screen example (a) and the flowchart (b) of FIG. Instruct the disconnection of the connection with the mouse in step, search the connection corresponding to the disconnection instruction in the logical file in step, display the signal name of the searched connection, and in step display the wiring information corresponding to the signal name. Read from file and display. 5 and 6, the signal name display window is not shown. Although only the corresponding wiring is displayed in the wiring diagram example of FIG. 5, it is possible to display other wiring or change the display area by an option. It is also possible to improve workability by displaying the corresponding wiring differently from the other wiring such as displaying it with high brightness.

Next, at the same time as displaying the wiring diagram, the repairable rate of the corresponding connection signal is displayed in another window (30).
5). An example of a window is shown in FIG. For the connection signal,
For example, the ratio of points that can be cut is displayed as the repairable rate. For example, if the connection has a wiring length of 9 grids as an actual wiring, there will be 10 cutting points, and if 8 points can be cut, the repairability rate will be 80%. An example of the process of obtaining the repairable rate will be described with reference to FIG. In this processing, the information of the wiring information file and the constraint library is used. The wiring SIGC of interest has a wiring length of 30 grids as shown in the figure, and it is read from the wiring information file that there is a wiring SIGX which is within 2 grids of the wiring SIGC as an adjacent wiring, and is read from the constraint library. Is the wiring SIG
A processing rule is read that there is an unprocessable area in the area on the path of C, and that processing is not possible when another wiring exists within two grids adjacent to the wiring. Then, the repairability rate is obtained based on the information read from these wiring information files and the information read from the constraint library. That is, in the wiring SIGC, the number of lattices existing in the unprocessable region is 9, and the number of lattices existing within 2 lattices with the adjacent wiring SIGX is 9,
The total number of these grids is 18, and 12 grids obtained by subtracting 18 grids from 30 grids are repairable grids, and the repairable rate is determined to be 40%.

When the operator refers to the screen display up to step 305 to determine whether the repair is possible or not, the operator determines whether the repair is actually possible or not. And so on. When this instruction is given, the constraint library information that defines the repair constraint described in FIG. 1 is compared with the actual wiring information, and if the repair constraint does not apply to the changed wiring portion, it is determined that repair is possible, and step 307 is performed. Go to step 310, and if yes, go to end step 310. When it is determined that repair is possible, the display of repairable wiring may be differentiated and displayed by high brightness display or the like. In the flowchart of FIG. 3, the repairability determination (306) is performed after the processing of step 305 for displaying the repairability rate, but the repairability determination (306) is performed after the processing of step 304 without incorporating the processing of step 305. You may do it. The actual wiring information may include already changed wiring information. With this function, it is possible to restrict the repaired parts due to interference with each other. If the result of this repairability determination is that repair is possible, first, the logic is changed on the logic diagram (307). The logic can be changed not only on the logic diagram but also on the file. Next, on the wiring diagram of FIG.
The actual wiring changes can be made (308). At this time, the wirings that can be changed are only the connection signals previously indicated in the logic diagram, and other wirings can be locked so that they cannot be changed. This can prevent accidentally changing other wiring. In addition, even during applicable wiring, points that cannot be repaired can be locked in point units, improving operability and making it possible to leave unchecked, for example, adjacency even when checking input data. Yes, you can speed up the check. When all changes have been completed, check the logical information and the wiring (wiring) information for inconsistency, check that the adjacency constraint is strictly adhered to, and perform necessary verification, and if there is no problem, create the repair information file. Then, based on this information, repair is performed by the actual repair device.

As another embodiment, in the method of instructing the logic change, only the connection is instructed by 402 in the logic diagram in FIG. 4, but in addition to this instruction, the processing information to be changed is combined and the menu is combined. It is also possible to provide a function of instructing with. FIG. 7 shows an example of the menu. For example, when it is desired to perform processing with a combination of connection, disconnection, and connection on the wiring, it is sufficient to click connection, disconnection, and connection in the menu in order, and finally click finish. In the repair availability check, it is possible to check whether or not this combination is possible at the same time, in addition to checking by events such as individual disconnection and connection. This is because when performing multiple processes on one wiring, there are cases where each repair point violates the adjacency constraint and cannot be realized as a combination, so this can be automatically checked. It is a means. This result is
In addition to the repairable rate, for example, as shown in the combination column of FIG. 6, if possible, OK is displayed, and if not possible, NG is displayed.

As described above, according to the present invention, repairability determination can be performed in real time by instructing a logical connection to be changed on the logical diagram, and at the same time, display as wiring information can be performed. Since it can be changed, time loss due to backtracking of work can be minimized, and repairability can be easily judged by displaying repairability rate. The active state has the effect of preventing correction mistakes and greatly improving workability. It is also possible to reduce the processing time of the check processing.

[0015]

According to the present invention, a logic diagram is displayed on a display such as a workstation, a logic signal wiring to be changed is designated, and the designated wiring diagram is displayed on the display. As a result, it becomes possible to judge repairability in real time while visually checking the wiring on the display.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a repair processing constraint diagram.

FIG. 2 is a diagram showing constraint rules corresponding to the example of FIG. 1 stored in a constraint library.

FIG. 3 is a diagram showing a flowchart of processing for determining whether or not logic change and repair are possible.

FIG. 4 is a diagram showing a display example in which a logical diagram desired to be changed is displayed on a workstation.

FIG. 5 is a diagram showing a display example in which a wiring diagram of a connection clicked on a logic diagram is displayed.

FIG. 6 is a diagram showing a display example in which a repairable rate of a connection signal is displayed.

FIG. 7 is a diagram showing an example of a display screen for instructing a combination of processing information to be changed by a menu.

FIG. 8 is a diagram showing an example of a logical file and a logical diagram based on the logical file.

FIG. 9 is a diagram showing an example of a wiring information file and a wiring diagram based on the wiring information file.

FIG. 10 is a diagram showing a screen example and a flowchart when displaying a corresponding wiring diagram based on a logic change in the logic diagram.

FIG. 11 is a diagram showing a wiring diagram for explaining calculation of a repairability rate.

FIG. 12 is a diagram showing an example of a processing system to which the present invention is applied.

Claims (3)

[Claims] 1. After manufacturing a chip of a semiconductor integrated circuit, a part of the existing wiring is modified by using FIB (focused ion beam), laser CVD (chemical vapor deposition) or the like on the chip, A semiconductor integrated circuit repair support method for deciding whether or not the modified logic can be actually processed on a chip in the case of repairing the logic by connecting unused gates for logic modification which are not related to the logic configuration prepared in advance The data is read from the logical file, the logical diagram is displayed on a display such as a workstation, and the instruction to change the logical information is given to the connection information on the logical diagram with a mouse or the like. The signal name corresponding to the connection information to be changed is searched from the logic file based on the above, and the wiring information corresponding to the signal name is read from the wiring information file by the searched signal name. When it is displayed on the display and the repair possibility judgment is instructed, the repair constraint information in the constraint library is compared with the wiring information related to the change, and if the repair constraint does not apply to the changed wiring part, the repair is possible. A method for supporting repair of a semiconductor integrated circuit, which comprises making a determination and performing subsequent wiring change processing. 2. The semiconductor integrated circuit repair support method according to claim 1, wherein the wiring information corresponding to the signal name is read from the wiring information file by the searched signal name, displayed on the display, and then the constraint is applied. A semiconductor integrated circuit repair support method, wherein a repair possibility rate for the change is obtained based on the repair constraint information of the library and the wiring information related to the change and displayed on the display. 3. The semiconductor integrated circuit repair support method according to claim 1, wherein when the wiring information is displayed on a display, the wiring is displayed by identifying an XY two-dimensional coordinate system and a wiring layer by color.
A method for assisting repair of a semiconductor integrated circuit, wherein the display of wiring determined to be repairable is differentiated and displayed by high brightness display or the like.