JP2017142311A - Liquid crystal display panel and liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display that can make viewing angle characteristics uniform.SOLUTION: A liquid crystal display panel (3) comprises: a plurality of pixels in which each includes a pixel electrode and that form a display area; a plurality of data signal lines (DL) that supply data signals to the plurality of pixels; a plurality of scanning signal lines (GL) that control writing of the data signals into the plurality of pixels; a capacitance wiring (CLj) that is supplied with a potential changing within one vertical period and forms a capacitance with the pixel electrodes; and an inside trunk wiring (Tc1) that is provided in the display area and connected to the capacitance wiring.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a liquid crystal display panel and a liquid crystal display device.

  According to Patent Document 1, a correction signal for correcting an inherent non-uniformity measured in advance in a liquid crystal display device is stored in a drive circuit, and the correction signal is added to display data input from the outside. Thus, a technique for driving a liquid crystal cell is disclosed.

  Patent Documents 2 and 3 disclose techniques for generating bright pixels and dark pixels by applying a periodically changing voltage to the auxiliary capacitance wiring of the liquid crystal display device. This improves the viewing angle characteristics of the liquid crystal display device.

Japanese Patent Laid-Open No. 9-318929 (released on December 12, 1997) International Publication WO2006 / 098449 (published September 21, 2006) International Publication WO2010 / 143348 (Released on December 16, 2010)

  However, as the display panel is increased in size, the auxiliary capacitance wiring becomes longer, and the delay and attenuation of the voltage change that propagates through the auxiliary capacitance wiring increases. Therefore, the difference in the voltage of the auxiliary capacitance wiring is large between a position close to the main wiring of the voltage supply source (to the left and right of the panel) and a position far from the center (panel center). Thereby, unevenness in viewing angle characteristics may occur in the display area.

  In the technique of Patent Document 1, a correction signal stored in advance is added to display data and written to a pixel. The technique of Patent Document 1 cannot improve the unevenness of viewing angle characteristics.

  The present invention has been made in view of the above-described problems, and an object thereof is to realize a liquid crystal display device capable of making viewing angle characteristics more uniform.

  A liquid crystal display panel according to one embodiment of the present invention includes a plurality of pixels forming a display region, a plurality of data signal lines for supplying a data signal to the plurality of pixels, and writing of the data signal to the plurality of pixels. A liquid crystal display panel including a plurality of scanning signal lines to be controlled, wherein each of the plurality of pixels has a first pixel electrode to which a data signal is written, and forms a capacitor with the first pixel electrode And a first inner trunk line provided in the display area and connected to the first capacitor line.

  According to one embodiment of the present invention, viewing angle characteristics of a liquid crystal display device can be made more uniform.

It is a schematic diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structure of a part of liquid crystal panel which concerns on one Embodiment of this invention. It is a timing chart which shows the example of a drive of the said liquid crystal display device in a certain vertical period. It is a schematic diagram which shows the display state of each pixel in a certain vertical period. It is a figure which shows typically the waveform of the capacity | capacitance signal supplied to an outer side trunk wiring from a data driver, and the waveform of this capacity | capacitance signal in the position of a pixel. It is a figure which shows typically the waveform of the capacity | capacitance signal supplied to an inner side trunk wiring from a data driver, and the waveform of the capacity | capacitance signal synthesize | combined in the pixel position. It is a figure which shows typically a 1st output waveform, a 1st propagation waveform, a 2nd output waveform, and a synthetic | combination waveform. It is a figure which shows typically a 1st output waveform, a 1st propagation waveform, a 2nd output waveform, and a synthetic | combination waveform. The change of the second output waveform shown in FIG. 8 is a step change. It is a figure which shows typically a 1st output waveform, a 1st propagation waveform, a 2nd output waveform, and a synthetic | combination waveform. It is a schematic diagram which shows the structure of the liquid crystal display device in a modification. It is a figure which shows typically the structure of a part of liquid crystal panel which concerns on other embodiment of this invention. It is a circuit diagram which shows the structure of a part of liquid crystal panel of further another embodiment of this invention. It is a timing chart which shows the example of a drive of the liquid crystal display of other embodiment of this invention. It is a top view which shows typically arrangement | positioning of the pixel of the liquid crystal panel in the liquid crystal display device of further another embodiment of this invention. It is a figure which shows the display state of a certain pixel in four continuous fields.

Embodiment 1
(Configuration of liquid crystal display device)
FIG. 1 is a schematic diagram showing the configuration of the liquid crystal display device 1 of the present embodiment. The liquid crystal display device 1 includes a liquid crystal panel 3 (liquid crystal display panel), a backlight 4, a gate driver 6, a data driver 7, and a display control circuit 9. The display control circuit 9 controls the backlight 4, the gate driver 6, and the data driver 7. The display control circuit 9 includes a timing controller (not shown) for generating various timing signals. The display control circuit 9 supplies a CS timing signal to the data driver 7. The data driver 7 is supplied with a plurality of reference potentials for generating a capacitance signal from a power source (not shown).

  The liquid crystal panel 3 includes a plurality of pixels, a plurality of scanning signal lines GLj, a plurality of data signal lines DLm, and a plurality of capacitance lines CLj. The subscript j represents the jth row, and the subscript m represents the mth column. Further, the liquid crystal panel 3 includes a plurality of outer trunk lines TL1 to TL4, TR1 to TR4, and a plurality of inner trunk lines Tb1 to Tb4, Tc1 to Tc4, Td1 to Td4. The liquid crystal panel 3 has a display area DA which is an area formed by a plurality of pixels and displaying an image. The plurality of outer trunk lines TL1 to TL4 and TR1 to TR4 are provided in an area outside the display area DA (non-display area). The plurality of outer trunk lines TL1 to TL4 are provided on the left side of the display area DA. The plurality of outer trunk lines TR1 to TR4 are provided on the right side of the display area DA. On the other hand, the plurality of inner trunk lines Tb1 to Tb4, Tc1 to Tc4, and Td1 to Td4 are provided in the display area DA (at least through the display area DA). Here, the inner trunk lines Tb1 to Tb4, the inner trunk lines Tc1 to Tc4, and the inner trunk lines Td1 to Td4 are arranged (distributed) evenly in the horizontal direction of the display area DA. The distribution of the inner trunk wiring may not be uniform. The plurality of inner trunk wires Tb1 to Tb4, Tc1 to Tc4, and Td1 to Td4 may be formed of metal or may be formed of a transparent conductor.

  Each capacitor line CLj is connected to two outer trunk lines and three inner trunk lines. The capacitor line CLj is connected to the outer trunk lines TL1, TR1 and the inner trunk lines Tb1, Tc1, Td1. The capacitor line CLj + 1 is connected to the outer trunk lines TL2 and TR2 and the inner trunk lines Tb2, Tc2, and Td2. The capacitive wiring CLj + 2 is connected to the outer trunk wirings TL3 and TR3 and the inner trunk wirings Tb3, Tc3 and Td3. The capacitive wiring CLj + 3 is connected to the outer trunk wirings TL4 and TR4 and the inner trunk wirings Tb4, Tc4 and Td4. Although not shown, the capacitor line CLj + 4 is connected to the outer trunk lines TL2, TR2 and the inner trunk lines Tb2, Tc2, Td2. The capacity line CLj + 5 is connected to the outer trunk lines TL1, TR1 and the inner trunk lines Tb1, Tc1, Td1. The capacitive wiring CLj + 6 is connected to the outer trunk wirings TL4, TR4 and the inner trunk wirings Tb4, Tc4, Td4. The capacitive wiring CLj + 7 is connected to the outer trunk wirings TL3 and TR3 and the inner trunk wirings Tb3, Tc3 and Td3. The arrangement (connection relationship) of these capacitor wirings CLj to CLj + 7 is repeated in the vertical direction (column direction).

  The gate driver 6 drives a plurality of scanning signal lines by supplying a scanning signal. The data driver 7 drives the plurality of data signal lines DLm, the plurality of outer trunk lines TL1 to TR4, and the plurality of inner trunk lines Tb1 to Td4. The data driver 7 includes a plurality of source drive circuits 7a to 7e. The source drive circuits 7a to 7e are connected to a plurality of data signal lines, respectively, and supply data signals to the corresponding data signal lines. Each of the source drive circuits 7a to 7e generates a capacitance signal based on the plurality of reference potentials and the CS timing signal. The source drive circuit 7a is connected to the plurality of outer trunk lines TL1 to TL4. The source drive circuit 7b is connected to a plurality of inner trunk lines Tb1 to Tb4. The source drive circuit 7c is connected to the plurality of inner trunk lines Tc1 to Tc4. The source drive circuit 7d is connected to a plurality of inner trunk lines Td1 to Td4. The source drive circuit 7e is connected to a plurality of outer trunk lines TR1 to TR4. Each of the source drive circuits 7a to 7e supplies a capacitance signal to the corresponding (connected) plural outer trunk lines or plural inner trunk lines. Note that a circuit for supplying a capacitance signal to the plurality of capacitance lines CLj and a circuit for supplying a data signal to the plurality of data signal lines DLm may be separated.

(Configuration of LCD panel)
FIG. 2 is a circuit diagram illustrating a partial configuration of the liquid crystal panel 3. In FIG. 2, pixels in the vicinity of the inner trunk line Tc1 (that is, the vicinity of the center in the horizontal direction of the display area) are shown. The pixel PXj is formed at the intersection of the scanning signal line GLj in the j-th row and the data signal line DLm in the m-th column. The capacitor wiring CLj extends along the pixel row so as to be adjacent to the upper side of the pixel PXj. Each pixel PXj includes a first pixel electrode PE1 and a second pixel electrode PE2. The first pixel electrode PE1 and the second pixel electrode PE2 are opposed to a counter electrode (common electrode: not shown) through a liquid crystal layer. The first pixel electrode PE1 forms a subpixel SP1, and the second pixel electrode PE2 forms a subpixel SP2.

  The pixel PXj will be described. The first pixel electrode PE1 is connected to the data signal line DLm through the transistor T1. The control terminal of the transistor T1 is connected to the scanning signal line GLj. An auxiliary capacitor C1 is formed between the first pixel electrode PE1 and the capacitor line CLj (first capacitor line). Similarly, the second pixel electrode PE2 is connected to the data signal line DLm via the transistor T2. The control terminal of the transistor T2 is connected to the scanning signal line GLj. The scanning signal line GLj controls writing of a data signal to the pixel by controlling conduction / non-conduction of the transistors T1 and T2 (switching elements). An auxiliary capacitor C2 is formed between the second pixel electrode PE2 and the capacitor line CLj + 1 (second capacitor line).

  The inner trunk lines Tc1 to Tc4 may be formed so as to overlap the data signal line DLm in plan view. By arranging the inner trunk lines Tc1 to Tc4 in this way, even when the metal inner trunk lines Tc1 to Tc4 are provided in the display area DA, a reduction in the opening area can be suppressed. Or when forming inner side trunk wiring Tc1-Tc4 with a transparent conductor, the reduction | decrease of opening area can be suppressed. However, regardless of the material of the inner trunk wires Tc1 to Tc4, it is preferable that the inner trunk wires Tc1 to Tc4 do not overlap the first pixel electrode PE1 and the second pixel electrode PE2 in plan view. This is to prevent a capacitance from being formed between the inner trunk lines Tc1 to Tc4 and the first pixel electrode PE1 and the second pixel electrode PE2.

  The inner trunk lines Tc1 to Tc4 may be arranged adjacent to one side of a column (pixel column) of pixels displaying a specific color component, for example, red or blue. Alternatively, the inner trunk lines Tc1 to Tc4 may be disposed adjacent to the pixel column of the color component having the largest opening area (pixel area). Thereby, the influence on the display quality by the reduction of the opening area by the inner trunk wirings Tc1 to Tc4 can be reduced. Here, each inner trunk wiring Tc1 to Tc4 extends so as to overlap the data signal line DLm corresponding to the pixel column displaying red. That is, three pixel columns (RGB: red, green, and blue) are arranged between the inner trunk lines Tc1 and Tc2 adjacent to each other. Each of the inner trunk lines Tc1 to Tc4 may extend so as to overlap with the data signal line DLm corresponding to the pixel column displaying another specific color component.

(Drive of liquid crystal display device)
Hereinafter, mainly regarding the pixel PXj, the scanning signal line GLj and the data signal line DLm connected to the pixel PXj, and the capacitance wiring CLj · CLj + 1 that forms a capacitance between the pixel PXj (subpixels SP1 and SP2). explain.

  FIG. 3 is a timing chart showing an example of driving the liquid crystal display device 1 in a certain vertical period. FIG. 3 shows the potential (data potential) of the data signal DSm supplied to the data signal line DLm and the potentials of the scanning signals GSj to GSJ + 3 respectively supplied to the scanning signal lines GLj to GLj + 3 with respect to time (horizontal axis). Gate potential), the potential (CS potential) of the capacitance signals CSj to CSj + 3 supplied to the capacitance lines CLj to CLj + 3, respectively, and the first pixel electrode PE1 in the pixels PXj to PXj + 2 of the jth row to j + 2th row of a certain pixel column. Potentials (pixel potentials) VAj to VAj + 2 and potentials VBj to VBj + 2 of the second pixel electrode PE2 are shown. In FIG. 3, with respect to the pixel potential (VAj to VAj + 2, VBj to VBj + 2) of each pixel electrode, the gate pulse becomes active (gate potential is High) in the vertical period, and the data signal is written to the pixel electrodes PE1 and PE2. Only changes since then. For the sake of simplicity, the influence of pixel potential pull-in due to gate parasitic capacitance is ignored here. FIG. 3 shows an example in which a data signal having the same gradation is written to each pixel as a two-dimensional image display. The horizontal broken line shown in FIG. 3 indicates the potential of the counter electrode.

  FIG. 4 is a schematic diagram showing a display state of each pixel in a certain vertical period. In FIG. 4, the polarity of the data signal written to each pixel electrode PE is indicated by + and −. In FIG. 4, the pixel electrode PE of a bright sub-pixel that performs bright display is shown in white, and the pixel electrode PE of a dark sub-pixel that performs dark display is indicated by dotted hatching.

  The polarity of the data potential is inverted every horizontal scanning period (1H). That is, a data potential having a reverse polarity is written to the pixels in the same column for each pixel row. The data potentials of two data signal lines adjacent to each other have opposite polarities. That is, a data potential having a different polarity for each pixel column is written to pixels in the same row.

  The gate potential sequentially becomes H (High) level in order to turn on the transistors T1 and T2 of each pixel (conductive state).

  The CS potential changes periodically in one vertical period. Here, the CS potential is inverted with respect to the reference potential (for example, the potential of the counter electrode) every two horizontal periods (2H). Note that the polarity of the potential CSj of the capacitor wiring CLj and the potential CSj + 1 of the lower capacitance wiring CLj + 1 are opposite to each other. The potential CSj of the capacitor wiring CLj and the potential CSj + 2 of the capacitor wiring CLj + 2 that is two lower than the potential CSj are out of phase by one horizontal period. The polarity of the potential CSj + 2 of the capacitor wiring CLj + 2 and the potential CSj + 3 of the lower capacitance wiring CLj + 3 are opposite to each other. Note that although not illustrated, the potential of the capacitor wiring CLj + 4 is the same as the potential CSj + 1 of the capacitor wiring CLj + 1. The potential of the capacitor wiring CLj + 5 is the same as the potential CSj of the capacitor wiring CLj. The potential of the capacitor wiring CLj + 6 is the same as the potential CSj + 3 of the capacitor wiring CLj + 3. The potential of the capacitor wiring CLj + 7 is the same as the potential CSj + 2 of the capacitor wiring CLj + 2.

  When the gate pulse becomes active, the two transistors T1 and T2 of the pixel PXj are simultaneously turned on. Therefore, the same data potential is written into the two subpixels SP1 and SP2 of the pixel PXj.

  After data is written to the pixel PXj (two subpixels) (after the gate pulse of the scanning signal GSj becomes inactive), the CS potentials CSj and CSj + 1 change (polarity inversion). As a result, the pixel potential of the pixel electrode PE1 connected to the capacitor line CLj through the auxiliary capacitor C1 also changes. Focusing on the pixel PXj, the pixel potential VAj and the pixel potential VBj of the two subpixels SP1 and SP2 are the same immediately after the data signal is written to the subpixels SP1 and SP2. Here, the sub-pixels SP1 and SP2 are connected to different capacitance lines CLj and CLj + 1 via auxiliary capacitors C1 and C2, respectively. After the transistor T1 is turned off (the gate potential is L (Low)), the CS potential CSj of the capacitor wiring CLj rises, so that the pixel potential VAj of the sub-pixel SP1 in which the positive polarity data is written rises. On the other hand, after the transistor T2 is turned off, the CS potential CSj + 1 of the capacitor wiring CLj + 1 falls, and thus the pixel potential VBj of the sub-pixel SP2 in which the positive data is written falls.

  As a result, the effective pixel voltage of the sub-pixel SP1 (average of pixel voltages in one frame period) increases, that is, the sub-pixel SP1 of the pixel PXj becomes a bright sub-pixel that is displayed brightly. On the other hand, the effective pixel voltage of the sub-pixel SP2 is small, that is, the sub-pixel SP2 of the pixel PXj is a dark sub-pixel that is displayed dark. Here, the pixel voltage is a difference between the potential of the counter electrode and the potential of the pixel electrode.

  For the subpixels SP1 and SP2 of the pixel PXj + 1 adjacent to the pixel PXj, the polarity of the data potential to be written is opposite (negative polarity). However, changes in the CS potentials CSj + 1 and CSj + 2 of the corresponding capacitor wiring are also reversed. Therefore, the sub-pixel SP1 of the pixel PXj + 1 is a bright sub-pixel displayed brightly, and the sub-pixel SP2 of the pixel PXj + 1 is a dark sub-pixel displayed dark. Further, since the polarity of the data potential is inverted for each pixel column, in the pixel column adjacent to the pixel PXj, the sub pixel SP1 is a dark sub pixel and the sub pixel SP2 is a bright sub pixel.

  In the next frame, the polarity of the data signal written to each pixel is inverted (dot inversion driving). However, the waveform of the CS potential of each capacitor line CLj is also shifted by a half period with respect to the gate pulse. For this reason, the positions of the bright sub-pixel and the dark sub-pixel do not change.

(Capacitance signal waveform)
The capacitance signal CSj is supplied from the data driver 7 to the capacitance line CLj via the outer trunk line TL1. Since the outer trunk wiring TL1 is provided in the non-display area (it does not affect the opening area), the width can be increased. On the other hand, since the capacitance line CLj is provided in the display area DA, the width is limited. For this reason, the capacitance signal CSj is delayed or the waveform thereof is dull at pixels far from the outer trunk wiring TL1.

  FIG. 5 is a diagram schematically showing the waveform of the capacitance signal CSj supplied from the data driver 7 to the outer trunk wiring TL1, and the waveform (first propagation waveform) of the capacitance signal CSj at the position of the pixel PXj. . In FIG. 5, the horizontal axis represents time, and the vertical axis represents potential. The pixel PXj will be described as a pixel adjacent to the inner trunk line Tc1, that is, a pixel near the center in the horizontal direction of the display area DA. A waveform of the capacitance signal CSj output from the data driver 7 to the outer trunk line TL1 is a first output waveform, and a waveform when the capacitance signal CSj propagates to the position of the pixel PXj is a first propagation waveform. The value on the vertical axis is normalized with the minimum value of the first output waveform being 0 and the maximum value being 1. In FIG. 5, the propagation waveform is schematically illustrated for simplification. The same applies to FIGS. 6 to 10 described later. The actual propagation waveform may change in a complicated manner due to the influence of various load capacities and surrounding wiring. However, the problem that the propagation waveform has the same period as the first output waveform, the phase is delayed, the waveform is blunt, and the amplitude is reduced by attenuation does not change. Therefore, the configuration of the present embodiment is effective even in an actual complicated situation.

  At the time of output from the data driver 7, the waveform of the capacitance signal CSj is the first output waveform. At the position of the pixel closest to the outer trunk line TL1, the capacitance signal CSj has a waveform close to the first output waveform. The capacitance signal CSj becomes the first propagation waveform because the phase is delayed and the amplitude is attenuated while being transmitted to the pixel PXj through the outer trunk wiring TL1 and the capacitance wiring CLj. The capacitance signal CSj having the first propagation waveform has an actual influence on the pixel PXj (changes the pixel voltage). Therefore, if the phase lag and the amplitude attenuation are large, the amount of change in pixel voltage (brightness difference between the bright subpixel and the dark subpixel) differs between the end of the display area DA and the vicinity of the center.

  Note that the capacitance signals output from the data driver 7 to the other outer trunk wires TL2 to TL4 and TR1 to TR4 are different in phase and phase from the first output waveform, and have the same amplitude and period.

  FIG. 6 is a diagram schematically showing the waveform of the capacitance signal supplied from the data driver 7 to the inner trunk wiring Tc1 and the waveform (synthesis waveform) of the synthesized capacitance signal at the position of the pixel PXj. In FIG. 6, the horizontal axis represents time, and the vertical axis represents potential. The value on the vertical axis is normalized with the minimum value of the first output waveform being 0 and the maximum value being 1. This figure also shows the first output waveform and the first propagation waveform of FIG. Let the waveform of the capacitance signal output from the data driver 7 to the inner trunk line Tc1 be the second output waveform.

  Here, the first output waveform of the capacitance signal supplied to the outer trunk wiring TL1 is the same as the second output waveform of the capacitance signal supplied to the inner trunk wiring Tc1. That is, the phase and potential of the capacitance signal supplied to the outer trunk wiring TL1 are the same as the phase and potential of the capacitance signal supplied to the inner trunk wiring Tc1, respectively. At the position of the pixel PXj, the first output waveform changes to the first propagation waveform. On the other hand, the second output waveform of the capacitance signal supplied to the inner trunk line Tc1 close to the pixel PXj remains almost the same as the original waveform even at the position of the pixel PXj. Therefore, at the position of the pixel PXj, the waveform of the capacitance signal is a waveform (synthesized waveform) obtained by combining the first propagation waveform and the second output waveform. The potential of the combined waveform is a value between the potential of the first propagation waveform and the potential of the second output waveform according to the position of the pixel PXj and the like. Here, the combined waveform is an average of the first propagation waveform and the second output waveform.

  The combined waveform is closer to the first output waveform than the first propagation waveform in which phase delay and amplitude attenuation occur at each time. Therefore, the pixel voltage of the pixel PXj changes according to a combined waveform close to the original waveform of the capacitance signal (first output waveform). Therefore, in the liquid crystal display device 1, the influence of the capacitance signal on the pixels far from the left and right ends (outer trunk lines) of the liquid crystal panel 3 can be made appropriate. Therefore, the brightness difference between the bright pixel and the dark pixel can be made uniform regardless of the position in the liquid crystal display device 1 for a certain gradation. Therefore, the viewing angle characteristics of the liquid crystal display device 1 can be made uniform.

  Here, for the sake of simplicity, the combined waveform of the capacitance signal of the outer trunk line TL1 and the inner trunk line Tc1 is shown, but the other inner trunk lines Tb1, Td1 and other outer trunks connected to the capacitor line CLj are shown. Similarly, the capacitance signal supplied to the wiring TR1 propagates through the capacitance wiring CLj and affects the pixel PXj. For this reason, the waveform of the capacitance signal at the actual position of the pixel PXj can be closer to the first output waveform than the combined waveform shown in FIG. For the pixels at other positions, the pixel voltage is changed by the combined capacitance signal according to the position of the pixel (distance to the outer trunk line and the inner trunk line). Note that when the pixel position is far from the inner trunk line, the capacitance signal supplied to the inner trunk line may also cause phase delay and amplitude attenuation while propagating to the pixel position.

  In the liquid crystal panel 3, the plurality of outer trunk lines TL1 to TR4 may not be provided. In this case, a capacity signal is supplied to each capacity line from the plurality of inner trunk lines Tb1 to Td4 provided in the display area DA. Capacitance signals having the first output waveform (= second output waveform) shown in FIG. 6 may be supplied to the inner trunk lines Tb1 to Td4. Since the outer trunk wiring does not hinder display, it can be arranged as a thicker wiring (that is, low resistance). For this reason, the outer trunk wiring has a greater influence than the inner trunk wiring. However, for the purpose of reducing the frame area (non-display area), it is conceivable to provide a plurality of inner trunk lines without providing the outer trunk lines. When the outer trunk wiring is not provided, there is no trunk wiring that dominantly determines the signal waveform of the capacitor wiring. Therefore, it is preferable to supply a capacitance signal having a basic output waveform to a plurality of inner trunk wires (for example, Tb1, Tc1, Td1). In this configuration, compared with the conventional configuration in which only the outer trunk wiring is provided, the waveform of the propagated capacitance signal can be made more uniform over the entire display region.

  In the above description, the case of dot inversion driving has been described, but other inversion driving methods may be used. For example, the present invention can also be applied to a liquid crystal display device of a driving method such as line inversion, 2 field inversion, block inversion, and 2H (2 horizontal periods) inversion. If the inversion driving method is different, the capacitance signal inversion timing and the appropriate capacitance signal waveform differ depending on the polarity arrangement of the pixel and the like. However, the use of a plurality of rectangular waves having the same period and amplitude and different phases from each other does not change from the problem that the rectangular waves are attenuated and deformed according to the distance from the main wiring. Therefore, the present invention can be applied to other inversion driving methods.

  Here, the principle of the present invention has been described by taking as an example a case where one pixel has two pixel electrodes (two subpixels). However, even when one pixel has only one pixel electrode, the principle of the present invention is similarly established. Therefore, each pixel of the liquid crystal panel may have a configuration having only one pixel electrode.

[Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, the amplitude of the supplied capacitance signal is different between the outer trunk line and the inner trunk line.

  A plurality (two) of reference potentials are supplied to the source drive circuits 7a and 7e that drive the outer trunk lines TL1 to TL4 and TR1 to TR4. A plurality of (two) reference potentials are supplied to the source drive circuits 7b to 7d that drive the inner trunk lines Tb1 to Td4. Each of the source drive circuits 7a to 7e generates a capacitance signal based on the supplied plurality of reference potentials and the CS timing signal.

  FIG. 7 is a diagram schematically illustrating a first output waveform, a first propagation waveform, a second output waveform, and a combined waveform. In FIG. 7, the horizontal axis represents time, and the vertical axis represents potential. The value on the vertical axis is normalized with the minimum value of the first output waveform being 0 and the maximum value being 1.

  In the present embodiment, the amplitude of the capacitance signal (the amplitude of the second output waveform) supplied from the source drive circuits 7b to 7d to the inner trunk lines Tb1 to Td4 is changed from the source drive circuits 7a and 7e to the outer trunk lines TL1 to TR4. It is larger than the amplitude of the supplied capacity signal (the amplitude of the first output waveform). The high potential side potential (highest potential) of the second output waveform is higher than the high potential side potential of the first output waveform, and the low potential side potential (lowest potential) of the second output waveform is the same as that of the first output waveform. Lower than the potential on the low potential side. The capacitance signal propagated to the pixel position near the center of the liquid crystal panel 3 via the outer trunk lines TL1 to TR4 is delayed and attenuated as in the first propagation waveform. In order to make the synthesized waveform resulting from the synthesis closer to the first output waveform, here, the amplitude of the capacitance signal supplied to the inner trunk wiring (the amplitude of the second output waveform) is larger than the amplitude of the first output waveform. It can be seen that the combined waveform (FIG. 7) obtained by combining the first propagation waveform and the second output waveform is closer to the first output waveform than the combined waveform shown in FIG. As described above, the amplitude of the capacitive signal supplied to the outer trunk lines TL1 to TR4 may be different from the amplitude of the capacitive signal supplied to the inner trunk lines Tb1 to Td4. Thereby, the influence by the capacitance signal can be made uniform, and the viewing angle characteristics of the liquid crystal display device 1 can be made uniform.

  For example, immediately before the potential of the first output waveform is inverted, the potential of the combined capacitance signal at the position of a certain pixel is supplied to each of the inner trunk lines Tb1 to Td4 so as to be the same as the potential of the first output waveform. The potential of the capacitance signal (the potential of the second output waveform) may be determined. Alternatively, at the timing when the corresponding gate pulse changes from active to inactive (the transistor is turned off), the potential of the combined capacitance signal at the position of a certain pixel is the same as the potential of the first output waveform. The potential of the capacitance signal (the potential of the second output waveform) supplied to the inner trunk lines Tb1 to Td4 may be determined.

  The high potential side potential of the second output waveform is lower than the high potential side potential of the first output waveform, and the low potential side potential of the second output waveform is lower than the low potential side potential of the first output waveform. It may be high.

[Embodiment 3]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, the potential on the high potential side and the potential on the low potential side of the capacitance signal supplied to the inner trunk line change stepwise or continuously.

  A plurality (two) of reference potentials are supplied to the source drive circuits 7a and 7e that drive the outer trunk lines TL1 to TL4 and TR1 to TR4. A plurality of (four or more) reference potentials are supplied to the source drive circuits 7b to 7d that drive the inner trunk lines Tb1 to Td4. Each of the source drive circuits 7a to 7e generates a capacitance signal based on the supplied plurality of reference potentials and the CS timing signal.

  FIG. 8 is a diagram schematically illustrating a first output waveform, a first propagation waveform, a second output waveform, and a combined waveform. In FIG. 8, the horizontal axis represents time, and the vertical axis represents potential. The value on the vertical axis is normalized with the minimum value of the first output waveform being 0 and the maximum value being 1.

  In the present embodiment, the potential of the capacitance signal (the potential of the second output waveform) supplied from the source drive circuits 7b to 7d to the inner trunk lines Tb1 to Td4 changes during the first period t0 to t2 which is a high potential. To do. Similarly, the potential of the second output waveform changes during the second period t2 to t4, which is a low potential. In FIG. 8, the potential of the second output waveform continuously decreases with time in the first period t0 to t2, and continuously increases with time in the second period t2 to t4. Actually, the decrease and increase of the potential are realized by a potential that changes stepwise by using a plurality of reference potentials.

  FIG. 9 is a stepwise change of the change in the second output waveform shown in FIG. The second output waveform changes in four steps in one cycle (four horizontal periods). In the period t0 to t1, the potential of the second output waveform is V1, in the period t1 to t2, the potential of the second output waveform is V2, and in the period t2 to t3, the potential of the second output waveform is V3. In the period t3 to t4, the potential of the second output waveform is V4. V1> V2> V4> V3. Here, the potential V2 is higher than the potential on the high potential side of the first output waveform, and the potential V4 is lower than the potential on the low potential side of the first output waveform, but is not limited thereto. The potential V2 may be the same as or lower than the potential on the high potential side of the first output waveform. The potential V4 may be the same as or higher than the potential on the low potential side of the first output waveform.

  The source drive circuits 7b to 7d may change the second output waveform with the number of steps larger than 4 in one cycle. If the number of steps is large, the second output waveform approaches the waveform that changes continuously as shown in FIG. Note that the potential of the second output waveform may be changed only in one of the first period and the second period.

  In this way, the composite waveform can be made closer to the first output waveform by changing the potential of the second output waveform in the first period or the second period. Thereby, the influence by the capacitance signal can be made uniform, and the viewing angle characteristics of the liquid crystal display device 1 can be made uniform.

  Note that when the capacitance signal is changed in multiple stages, a new timing signal for determining the timing of changing the potential may be required. In that case, the display control circuit 9 may supply an additional CS timing signal to the source drive circuits 7b to 7d that drive the inner trunk lines Tb1 to Td4.

[Embodiment 4]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, the phase of the supplied capacitance signal is different between the outer trunk line and the inner trunk line.

  The display control circuit 9 supplies a CS timing signal to the source drive circuits 7a and 7e that drive the outer trunk lines TL1 to TR4. The display control circuit 9 supplies another CS timing signal to the source drive circuits 7b to 7d that drive the inner trunk lines Tb1 to Td4. The other CS timing signal determines the timing of the potential change of the second output waveform. A plurality (two) of reference potentials are supplied to the source drive circuits 7a and 7e that drive the outer trunk lines TL1 to TL4 and TR1 to TR4. A plurality of (four or more) reference potentials are supplied to the source drive circuits 7b to 7d that drive the inner trunk lines Tb1 to Td4. Each of the source drive circuits 7a to 7e generates a capacitance signal based on the supplied plurality of reference potentials and the CS timing signal.

  FIG. 10 is a diagram schematically illustrating a first output waveform, a first propagation waveform, a second output waveform, and a combined waveform. In FIG. 10, the horizontal axis represents time, and the vertical axis represents potential. The value on the vertical axis is normalized with the minimum value of the first output waveform being 0 and the maximum value being 1.

  The waveform itself of the second output waveform of the present embodiment may be the same as that described in the third embodiment. The second output waveform changes stepwise or continuously in a high potential period or a low potential period.

  In the present embodiment, the phase of the second output waveform is ahead of the phase of the first output waveform. The phase advance is less than π, preferably less than π / 2. The time point when the potential changes from a low potential to a high potential is used as a phase reference. The time t0 ′ for changing from the low potential to the high potential in the second output waveform is ahead of the time t0 for changing from the low potential to the high potential in the first output waveform. In other words, the phase at the same time is more advanced in the second output waveform than in the first output waveform.

  The synthesized waveform can be advanced in phase from the phase of the first output waveform, but the waveform itself is close to the first output waveform. Note that, for example, the capacitance signal supplied to the inner trunk line also has a phase lag and an amplitude attenuation at the pixel position away from the inner trunk line. By causing the phase of the second output waveform to advance from the phase of the first output waveform, the influence of the capacitance signal of the entire liquid crystal panel 3 including the (middle) pixels away from both the outer trunk line and the inner trunk line is affected. It can be made uniform. Therefore, the viewing angle characteristics of the liquid crystal panel 3 can be made more uniform.

  Note that the phase of the first output waveform may be different from the phase of the second output waveform, and the phase of the first output waveform may be advanced from the phase of the second output waveform. Here, an example in which the phase and the amplitude are different has been described, but only the phase may be different between the first output waveform and the second output waveform.

[Embodiment 5]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, the number and arrangement of the inner trunk wires are different from those in the above-described embodiment. The configuration of the present embodiment is applicable to each of the above-described embodiments (capacitance signal forms).

  In the above-described embodiment, a case has been described in which there are four types of basic capacitance signals (that is, the number of outer trunk wires on one side is four). However, the present invention is not limited thereto, and at least two types (two phases) of capacitance signals are sufficient. For example, the capacity signal may be 6 types, 12 types, 24 types, or any other number.

  The plurality of capacitance signals have the same waveform but different phases. A capacitance signal having a first output waveform and a capacitance signal having a second output waveform as illustrated in FIGS. 5 to 10 are supplied to the outer trunk wiring and the corresponding inner trunk wiring, respectively. Similar to the outer trunk wires, the inner trunk wires are supplied with capacitance signals having a second output waveform that are out of phase with each other.

  When N types of capacitance signals are used, the liquid crystal panel is provided with one or more sets of N inner trunk wires connected to different capacitance wires corresponding to the N types of capacitance signals. The number of sets of N inner trunk lines is arbitrary. For example, 3 to 15 inner trunk wires may be evenly connected in the horizontal direction to each capacitor wire. When the number of the inner trunk wiring groups is large, the delay and attenuation of the capacitance signal is small. Therefore, even when the same capacitance signal is supplied to the inner trunk wiring and the outer trunk wiring, the synthesized waveform is close to the first output waveform.

  FIG. 11 is a schematic diagram illustrating a configuration of the liquid crystal display device 11 according to a modification. Thus, the liquid crystal panel 3 may include only one set of the four inner trunk lines Tc1 to Tc4 corresponding to the four types of capacitance signals.

  In addition, it is preferable that the plurality of inner trunk wirings are disposed in a display area of the liquid crystal panel that is moderately dispersed or evenly dispersed. It should be noted that a plurality of sets of inner trunk wirings may be arranged so as to be appropriately dispersed or evenly dispersed. This is because if the distribution of the plurality of inner trunk lines is non-uniform, the aperture ratio of the pixels becomes non-uniform in the display area. Further, if the distribution density of the inner trunk wiring is lowered, the number of defective products can be reduced also in the manufacturing process of the liquid crystal panel.

[Embodiment 6]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. This embodiment is different from the above-described embodiment in that a dummy trunk wiring is provided. Note that the configuration of the present embodiment is applicable to the above-described embodiments.

  FIG. 12 is a diagram schematically illustrating a partial configuration of the liquid crystal panel according to the present embodiment. In FIG. 12, pixels in the vicinity of the inner trunk wiring Tb1 are shown. Although not shown, the liquid crystal panel includes outer trunk lines TL1 to TR4 and other inner trunk lines Tb3, Tb4, Tc1 to Td4, as in the first embodiment. The connection relationship between the plurality of outer trunk wires and the plurality of inner trunk wires and the plurality of capacitor wires is the same as that in the first embodiment. Each pixel PXj includes a sub pixel SP1 and a sub pixel SP2. Detailed configurations of the sub-pixel SP1 and the sub-pixel SP2 are omitted. (R) shown in FIG. 12 indicates the color component (red) displayed by the pixels in the pixel column. For example, the data signal line DLm is connected to the pixels in the R pixel column. Similarly, (G) and (B) indicate the color components (green) (blue). One pixel typically represents any one color component of RGB, and one picture element includes three pixels corresponding to RGB.

  The plurality of inner trunk wirings Tb1 and Tb2 are provided so as to overlap the data signal lines DLm + 3 and DLm + 6 connected to pixels of a specific color component (here, R) in plan view. The inner trunk lines Tb1 and Tb2 and the data signal lines DLm + 3 and DLm + 6 do not have to overlap each other and may be adjacent to each other in plan view. In order to reduce the resistance of the inner trunk wiring (in order to suppress delay / attenuation of the capacitance signal), the inner trunk wiring is formed thick with metal. Therefore, there is a possibility that the pixel area adjacent to the inner trunk wiring has a narrow (limited) opening area for display. Therefore, particularly for pixel columns having the same color component, if there are columns in which the inner trunk wiring is disposed (adjacent) and columns in which the inner trunk wiring is not disposed, display characteristics may be non-uniform.

  In the present embodiment, among a plurality of pixel columns of a specific color component in the display region, a plurality of inner trunk lines are arranged in some of the plurality of pixel columns, and a plurality of other plurality of inner trunk lines are not arranged. A plurality of dummy trunk lines are arranged in the pixel column. For example, the dummy trunk line DT is provided so as to be adjacent to the R pixel column so as to overlap the data signal line DLm connected to the pixel column in plan view. The dummy trunk wiring DT preferably has the same shape as the inner trunk wirings Tb1 and Tb2. Unlike the inner trunk lines Tb1 and Tb2, the dummy trunk line DT is not connected to any capacitor line that changes the pixel voltage via the capacitor. The dummy trunk line DT is not connected to the data driver, and no capacitance signal is supplied to the dummy trunk line DT. A potential that is constant in one vertical period may be supplied from the data driver to the dummy trunk line DT. As a result, it is possible to prevent the dummy trunk wiring DT from becoming a floating capacity and the electric field of the surrounding pixels from being disturbed by the potential of the dummy trunk wiring DT being fluctuated depending on the surrounding electric field condition.

  The dummy trunk line DT may be connected to the data driver 7, and the data driver 7 may supply the same capacitance signal to the dummy trunk line DT that is supplied to the inner trunk line. However, the dummy trunk wiring DT is not connected to any capacitance wiring. When wirings overlap, some capacitance is formed between them. Thereby, the influence of the capacitance signal on the data signal lines DLm + 3 and DLm + 6 overlapping the inner trunk lines Tb1 and Tb2 and the influence of the capacitance signal on the data signal line DLm overlapping the dummy trunk line DT can be made the same. Therefore, it is possible to make the display characteristics of the location where the inner trunk wiring exists and the display characteristics of the location where the dummy trunk wiring exist uniform.

  Thus, by providing the inner trunk wiring and the dummy trunk wiring, the display characteristics of the display area can be made uniform. The trunk lines may be provided evenly in the display area of the liquid crystal panel, and the number of trunk lines necessary for supplying the capacitance signal (second output waveform) among the plurality of trunk lines may be connected to the data driver. In addition to the specific color component (R), the inner trunk wiring and the dummy trunk wiring may be provided in the pixel columns of other color components (G, B).

[Embodiment 7]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, a double source drive liquid crystal display device will be described.

  FIG. 13 is a circuit diagram illustrating a partial configuration of the liquid crystal panel of the present embodiment. In FIG. 13, pixels in the vicinity of the inner trunk wiring Tc1 are shown. In the present embodiment, two corresponding data signal lines are provided for each pixel column. The pixel PXj is connected to the data signal line DLm adjacent to the left side, and the pixel PXj + 1 below the pixel PXj is connected to the data signal line DL′m adjacent to the right side. The polarity of the data signal supplied from the data signal line DLm is different from the polarity of the data signal supplied from the data signal line DL'm. In the liquid crystal panel, six outer trunk lines are provided on one side from the display area, and six outer trunk lines are provided on the other side from the display area. Further, there are provided M sets (M ≧ 1) or more sets of six inner trunk lines in the display area. Each capacitance wiring is connected to two corresponding outer trunk wirings and corresponding M inner trunk wirings. Note that the outer trunk wiring and the inner trunk wiring corresponding to the outer trunk wiring are connected to each other through a capacitive wiring.

  In the present embodiment, the gate pulses of the two scanning signal lines GLj and GLj + 1 are simultaneously activated, and data signals are simultaneously written to the pixels PXj and PXj + 1 in the two rows.

  FIG. 14 is a timing chart showing an example of driving the liquid crystal display device of the present embodiment. FIG. 14 shows capacitance signals CS1 to CS28 supplied to the capacitance lines CL1 to CL28 and gate pulses G1 to G28 supplied to the scanning signal lines GL1 to GL28, respectively, with respect to time (horizontal axis). Yes. In FIG. 14, each gate pulse shows only a part of the rising period. 1H indicates one horizontal period.

  In the present embodiment, two adjacent scanning signal lines are simultaneously selected, and data is simultaneously written in each pixel of two adjacent pixel rows. For example, data signals are simultaneously written to the pixel row connected to the scanning signal line GL1 and the pixel row connected to the scanning signal line GL2. Next to the scanning signal lines GL1 and GL2, the scanning signal lines GL3 and GL4 are simultaneously selected. In this manner, two scanning signal lines are simultaneously selected in the order in which they are arranged in the scanning direction (column direction), and writing in one vertical period is performed.

  There are six types of capacitance signals. FIG. 14 shows the types of capacitance signals with circled numbers. Capacitance signals whose polarity with respect to a reference potential is inverted are supplied to each capacitance wiring every a plurality of horizontal periods. Thereby, the potential of each capacitor wiring is inverted at a constant period. Here, the capacitance signals supplied to the capacitance wiring CL1 and the capacitance wiring CL2 are inverted in phase, and always have a reverse polarity potential. The potential of each capacitor line is inverted every six horizontal periods, and the timing at which the potential changes is shifted by two horizontal periods for every four capacitor lines. Therefore, there are six types (six phases) of timing (phase) of the capacitance signal.

  The capacitance signal waveform in FIG. 14 represents the waveform (first output waveform) of the capacitance signal supplied to the outer trunk wiring. As in the example illustrated in FIG. 5, the capacitance signal having the same waveform may be supplied to the inner trunk wiring corresponding to the outer trunk wiring. Alternatively, as in the example illustrated in FIGS. 6 to 10, a capacitive signal having a phase or amplitude different from that of the capacitive signal supplied to the outer trunk wiring may be supplied to the corresponding inner trunk wiring. That is, the modification example of the capacitance signal supplied to the outer trunk wiring and the capacitance signal supplied to the corresponding inner trunk wiring shown in FIGS. Even if the period, amplitude, number of types, and timing change, it is applicable.

[Embodiment 8]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those described in the above embodiment are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, a liquid crystal display device including pixels of four types of color components RGBY (red green blue yellow) will be described.

  FIG. 15 is a plan view schematically showing the arrangement of pixels of the liquid crystal panel 12 in the liquid crystal display device of the present embodiment. The liquid crystal panel 12 includes a plurality of picture elements PEL in the display area. Each picture element PEL includes four pixels PX of R, G, B, and Y (red, green, blue, and yellow) arranged in the row direction. Here, in the picture element PEL, the pixels PX are arranged in the order of R, G, B, and Y from the left. Each pixel PX includes a sub-pixel SP1 disposed on the upper side and a sub-pixel SP2 disposed on the lower side. Similar to the above-described embodiment, the two subpixels SP1 and SP2 of one pixel PX are connected to one data signal line and one scanning signal line. Capacitance wiring is arranged between the pixels PX adjacent in the vertical direction.

  FIG. 15 shows the polarities of data signals written to pixels in a certain field for some pixels. In one picture element PEL, the polarity of the data signal is the same in the RBY pixel PX, and the polarity of the data signal is opposite to that of the RBY in the G pixel PX. Moreover, the polarity of the data signal of each pixel is reversed between the pixel elements PEL adjacent in the column direction or the row direction. In FIG. 15, white sub-pixels indicate bright sub-pixels in a certain field, and hatched sub-pixels indicate dark sub-pixels in the field.

  In the liquid crystal display device of the present embodiment, display data indicating one image (display data of one frame) is displayed divided into two fields. For example, when the frame rate of the display data is 60 fps, one field is 1/120 seconds.

  FIG. 16 is a diagram showing a display state of a certain pixel element PEL in four consecutive fields. FIG. 16A shows the display state of the picture element PEL, the scanning signal GSj, and the capacitance signals CSj and CSj + 1 in the first field. FIG. 16B shows the display state of the picture element PEL, the scanning signal GSj, and the capacitance signals CSj and CSj + 1 in the second field. FIG. 16C shows the display state of the picture element PEL, the scanning signal GSj, and the capacitance signals CSj and CSj + 1 in the third field. FIG. 16D shows the display state of the picture element PEL, the scanning signal GSj, and the capacitance signals CSj and CSj + 1 in the fourth field.

  In the first field, a positive data signal is written to the RBY pixel, and a negative data signal is written to the G pixel. In the first field, after the scanning signal GSj becomes Low (the gate pulse is inactive), the capacitance signal CSj of the capacitance line CLj rises and the capacitance signal CSj + 1 of the capacitance line CLj + 1 falls. Therefore, the pixel voltage of the sub-pixel SP1 to which the positive data signal is written increases, and the sub-pixel SP1 becomes a bright sub-pixel. On the other hand, the pixel voltage of the sub-pixel SP1 to which the negative data signal is written becomes small, and the sub-pixel SP1 becomes a dark sub-pixel. Further, the pixel voltage of the sub-pixel SP2 to which the positive data signal is written becomes small, and the sub-pixel SP2 becomes a dark sub-pixel. On the other hand, the pixel voltage of the sub-pixel SP2 to which the negative data signal is written increases, and the sub-pixel SP2 becomes a bright sub-pixel.

  In the second field, a positive data signal is written to the RBY pixel, and a negative data signal is written to the G pixel. In the second field, the relationship between the scanning signal and the capacitance signal is different from that in the first field. In the second field, after the scanning signal GSj becomes Low, the capacitance signal CSj of the capacitance wiring CLj falls and the capacitance signal CSj + 1 of the capacitance wiring CLj + 1 rises. Therefore, the relationship between the bright subpixel and the dark subpixel is inverted between the first field and the second field.

  In the third field, a negative data signal is written to the RBY pixel, and a positive data signal is written to the G pixel. In the third field, the relationship between the scanning signal and the capacitance signal is the same as in the second field. In the third field, after the scanning signal GSj becomes Low, the capacitance signal CSj of the capacitance line CLj falls and the capacitance signal CSj + 1 of the capacitance line CLj + 1 rises. Therefore, the relationship between the bright subpixel and the dark subpixel is the same in the first field and the third field.

  In the fourth field, a negative data signal is written to the RBY pixel, and a positive data signal is written to the G pixel. In the fourth field, the relationship between the scanning signal and the capacitance signal is the same as in the first field. In the fourth field, after the scanning signal GSj becomes Low, the capacitance signal CSj of the capacitance line CLj rises and the capacitance signal CSj + 1 of the capacitance line CLj + 1 falls. Therefore, the relationship between the bright subpixel and the dark subpixel is inverted between the first field and the fourth field.

  Here, in the first field and the second field, data signals having different gradations can be supplied to the R pixel PX. Further, by increasing the amplitudes of the capacitance signals CSj and CSj + 1, the dark sub-pixel can always be displayed in black (for example, 5% or less of the maximum luminance) regardless of the data signal. In this way, different images can be displayed in the first field and the second field. That is, in each pixel PX, different gradations can be displayed in the subpixel SP1 and the subpixel SP2. That is, an image can be displayed in the first field and the second field at a resolution twice as high as the resolution of the liquid crystal panel 12 in the vertical direction like interlace. For example, when the vertical resolution (the number of picture elements in the vertical direction) of the liquid crystal panel 12 is 1080, an image with a vertical resolution of 2160 can be displayed. The same applies to the third field and the fourth field.

  In the liquid crystal panel 12, in each of the plurality of pixels PX, the sub-pixel displaying the highest luminance color among the four types of sub-pixels (referred to as “first sub-pixel” for convenience) and the second luminance Sub-pixels that display a high color (referred to as “second sub-pixels” for convenience) are arranged so as not to be adjacent to each other (that is, to sandwich at least one sub-pixel). Here, the first sub-pixel is a G sub-pixel, and the second sub-pixel is a Y sub-pixel. In the example shown in FIG. 15, in each picture element PEL, four types of sub-pixels are arranged in the order of R sub-pixel, G sub-pixel, B sub-pixel, and Y sub-pixel from the left side to the right side. The G subpixel and the Y subpixel are not adjacent to each other. In one picture element PEL, RGB sub-pixels are used as one display unit representing achromatic luminance (white to black), and BY sub-pixels are used as another display representing achromatic luminance (white to black). Can be treated as a unit.

  In the liquid crystal display device of this embodiment, when the resolution of the input image data in the horizontal direction is higher than the resolution of the liquid crystal panel 12 (that is, when the number of picture elements of the input image data is larger than the number of picture elements of the liquid crystal panel 12), Each of the two display units can be displayed as a virtual picture element. Therefore, visual resolution can be improved in the lateral direction. Further, the liquid crystal panel 12 displays a color with the highest luminance (that is, the highest luminance at the highest gradation) and a color with the second highest luminance (that is, the luminance at the highest gradation is 2). The second sub-pixel is arranged so as not to be adjacent to each other in the picture element PEL. Therefore, the spatial frequency of the luminance distribution can be increased compared to the case where the first subpixel and the second subpixel are arranged adjacent to each other, and two adjacent virtual picture elements are merged and visually recognized. Can be prevented.

  The liquid crystal panel 12 includes one or more sets of N types of inner trunk lines corresponding to the N types of outer trunk lines, as in the above-described embodiment. Also in the liquid crystal display device of this embodiment, similarly to the above-described embodiment, the capacitance signal is supplied to the outer trunk line and the inner trunk line, respectively. Note that the waveform of the capacitance signal in FIG. 16 represents the waveform of the capacitance signal (first output waveform) supplied to the outer trunk wiring. As in the example illustrated in FIG. 5, the capacitance signal having the same waveform may be supplied to the inner trunk wiring corresponding to the outer trunk wiring. Alternatively, as in the example illustrated in FIGS. 6 to 10, a capacitive signal having a phase or amplitude different from that of the capacitive signal supplied to the outer trunk wiring may be supplied to the corresponding inner trunk wiring. That is, the modification example of the capacitance signal supplied to the outer trunk wiring and the capacitance signal supplied to the corresponding inner trunk wiring shown in FIGS. Even if the period, amplitude, number of types, and timing change, it is applicable.

  This embodiment has an effect of stabilizing the response time of the liquid crystal in addition to the above-described change in luminance and change in luminance difference. That is, in this embodiment, even when a still image video signal is input, the luminance of each sub-pixel varies for each field, but if the waveform of the capacitance signal varies depending on the position, the final liquid crystal alignment state of each field Can take a plurality of states for the same gradation signal. Since the liquid crystal continuously responds as an elastic body, the final liquid crystal alignment state affects the time until the liquid crystal state before the data signal application becomes the next state. In the present embodiment, this state can be stabilized and more appropriate moving image display can be realized. This is impossible with conventional unevenness correction, and is an important factor for realizing appropriate overdrive driving.

[Summary]
A liquid crystal display panel according to an aspect 1 of the present invention includes a plurality of pixels (PX) that form a display region, a plurality of data signal lines (DL) that supply data signals to the plurality of pixels, and the plurality of pixels. A liquid crystal display panel (liquid crystal panels 3 and 12) including a plurality of scanning signal lines (GL) for controlling writing of the data signal of the first pixel electrode to which the data signal is written. A first capacitance line (CLj) having (PE1) and forming a capacitance (auxiliary capacitance C1) with the first pixel electrode, and provided in the display region and connected to the first capacitance line First inner trunk wiring (Tb1, Tc1, Td1).

  According to the above configuration, a potential (capacitance signal) is supplied from the first inner trunk line provided in the display area to the first capacitor line. The capacitance signal is a signal whose potential changes in one vertical period. Therefore, it is possible to suppress the phase delay or the amplitude attenuation of the capacitive signal propagated to the pixel position, compared to the case where the main wiring is provided outside the display region. Further, even when the outer trunk wiring is provided outside the display area and the phase of the capacitance signal from the outer trunk wiring is delayed or the amplitude is attenuated, it can be compensated by the capacitance signal from the first inner trunk wiring. . Therefore, in the liquid crystal display panel, it is possible to make the influence of the capacitance signal appropriate for the pixels far from the edge of the display area. Therefore, the viewing angle characteristics of the liquid crystal display device can be made more uniform.

  The liquid crystal display panel according to aspect 2 of the present invention is the liquid crystal display panel according to aspect 1, in which each of the plurality of pixels has a second pixel electrode (PE2) to which a data signal is written, and between the second pixel electrode. A second capacitor line (CLj + 1) that forms a capacitor (auxiliary capacitor C2), and a second inner trunk line (Tb2, Tc2, Td2) provided in the display area and connected to the second capacitor line. It is good also as a structure provided with.

  The liquid crystal display panel according to aspect 3 of the present invention includes the three or more first inner trunk lines provided in the display area and connected to the first capacitor lines in the above aspect 1 or 2, The three or more first inner trunk lines may be arranged uniformly in the display area.

  According to said structure, the influence on the display by distribution of 1st inner side trunk wiring can be made uniform.

  The liquid crystal display panel according to Aspect 4 of the present invention is the liquid crystal display panel according to any one of Aspects 1 to 3, wherein the first inner trunk line is disposed adjacent to one side of a pixel column displaying a specific color component, The second inner trunk wiring may be arranged to be adjacent to the one side of another pixel column that displays the specific color component. The specific color component may be red or blue.

  The opening area of red or blue pixels may be larger than that of green pixels. According to said structure, the influence on the display by the reduction of the opening area by 1st inner side trunk wiring can be made small.

  A liquid crystal display panel according to an aspect 5 of the present invention is the liquid crystal display panel according to any one of the above aspects 1 to 4, wherein the first inner trunk line is disposed adjacent to a certain pixel column and disposed adjacent to another pixel column. The dummy trunk wiring is provided in the display area and is not connected to any capacitor wiring that changes the potential of the pixel through the capacitor. Also good.

  According to the above configuration, by arranging the dummy trunk lines in addition to the first inner trunk lines, it is possible to make the influence on the opening area of the pixels in the display region uniform.

  A liquid crystal display panel according to an aspect 6 of the present invention is the liquid crystal display panel according to any one of the aspects 1 to 5, provided outside the display area (DA) and connected to the first capacitor line (TL1, TR1), and the phase and potential of the first capacitance signal supplied to the outer trunk wiring and the phase and potential of the second capacitance signal supplied to the first inner trunk wiring may be the same. Good.

  According to the above configuration, the phase delay or the amplitude attenuation of the capacitive signal from the outer trunk line can be compensated by the capacitive signal from the first inner trunk line.

  A liquid crystal display panel according to Aspect 7 of the present invention is the liquid crystal display panel according to any one of Aspects 1 to 5, which is provided outside the display area (DA) and connected to the first capacitor wiring (TL1, TR1), and the phase of the first capacitance signal supplied to the outer trunk wiring and the phase of the second capacitance signal supplied to the first inner trunk wiring are the same as each other, The potential and the potential of the second capacitance signal may be different from each other.

  According to said structure, attenuation | damping of the amplitude of the capacity | capacitance signal from an outer side trunk wiring can be compensated more appropriately by the capacity | capacitance signal from a 1st inner side trunk wiring.

  A liquid crystal display panel according to an eighth aspect of the present invention is the liquid crystal display panel according to any of the first to fifth aspects, wherein the outer trunk wiring (TL1, TL1) provided outside the display area (DA) and connected to the first capacitor wiring is provided. TR1), and the phase of the first capacitance signal supplied to the outer trunk wiring may be different from the phase of the second capacitance signal supplied to the first inner trunk wiring.

  According to said structure, the delay of the phase of the capacity | capacitance signal from an outer side trunk wiring can be compensated more appropriately with the capacity | capacitance signal from a 1st inner side trunk wiring.

  The liquid crystal display panel according to aspect 9 of the present invention is the liquid crystal display panel according to aspect 7 or 8, wherein one cycle of the second capacitance signal includes a first period and a second period. The potential of the two-capacitance signal is higher than the potential of the second capacitance signal in the second period. In the first period, the potential of the second capacitance signal decreases with time. The potential of the two-capacitance signal may be increased with time.

  The liquid crystal display panel according to aspect 10 of the present invention is the liquid crystal display panel according to aspect 9, in which the potential of the second capacitance signal drops from the first potential to the second potential in the first period, and in the second period, The potential of the second capacitance signal may be increased from the third potential to the fourth potential.

  In the liquid crystal display panel according to an eleventh aspect of the present invention, in any one of the seventh to tenth aspects, the highest potential of the second capacitance signal is higher than the highest potential of the first capacitance signal, The lowest potential may be lower than the lowest potential of the first capacitance signal.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

1, 11 Liquid crystal display device 3, 12 Liquid crystal panel (liquid crystal display panel)
6 Gate driver 7 Data driver 7a-7e Source drive circuit 9 Display control circuit C1, C2 Auxiliary capacitor CL Capacitor line DT Dummy trunk line DL Data signal line GL Scan signal line PE1, PE2 Pixel electrode PX Pixel SP1, SP2 Subpixel Tb1 Tb4, Tc1 to Tc4, Td1 to Td4 Inner trunk wiring TL1 to TL4, TR1 to TR4 Outer trunk wiring

Claims (13)

A liquid crystal display comprising a plurality of pixels forming a display area, a plurality of data signal lines for supplying data signals to the plurality of pixels, and a plurality of scanning signal lines for controlling writing of the data signals to the plurality of pixels. A panel,
Each of the plurality of pixels has a first pixel electrode to which a data signal is written,
A first capacitor wiring that forms a capacitor with the first pixel electrode;
A liquid crystal display panel comprising: a first inner trunk line provided in the display region and connected to the first capacitor line. Each of the plurality of pixels has a second pixel electrode to which a data signal is written,
A second capacitor wiring forming a capacitor with the second pixel electrode;
The liquid crystal display panel according to claim 1, further comprising a second inner trunk line provided in the display region and connected to the second capacitor line. Three or more first inner trunk lines provided in the display area and connected to the first capacitor lines,
3. The liquid crystal display panel according to claim 1, wherein the three or more first inner trunk lines are evenly arranged in the display area. 4. The first inner trunk wiring is disposed adjacent to one side of a pixel column displaying a specific color component,
The liquid crystal display panel according to claim 2, wherein the second inner trunk line is disposed adjacent to the one side of another pixel column that displays the specific color component.   The liquid crystal display panel according to claim 4, wherein the specific color component is red or blue. The first inner trunk wiring is disposed adjacent to a certain pixel column,
Provided with dummy trunk lines arranged adjacent to other pixel columns,
6. The dummy trunk line is provided in the display area and is not connected to any capacitor line that changes a potential of a pixel through a capacitor. The liquid crystal display panel according to one item. Provided outside the display area, the outer trunk wiring connected to the first capacitance wiring,
2. The phase and potential of the first capacitance signal supplied to the outer trunk wiring and the phase and potential of the second capacitance signal supplied to the first inner trunk wiring are the same as each other. 7. A liquid crystal display panel according to any one of items 1 to 6. Provided outside the display area, the outer trunk wiring connected to the first capacitance wiring,
The phase of the first capacitance signal supplied to the outer trunk line and the phase of the second capacitor signal supplied to the first inner trunk line are the same as each other,
7. The liquid crystal display panel according to claim 1, wherein the potential of the first capacitance signal and the potential of the second capacitance signal are different from each other. Provided outside the display area, the outer trunk wiring connected to the first capacitance wiring,
The phase of the first capacitance signal supplied to the outer trunk line and the phase of the second capacitor signal supplied to the first inner trunk line are different from each other. A liquid crystal display panel according to item. One cycle of the second capacitance signal includes a first period and a second period,
The potential of the second capacitance signal in the first period is higher than the potential of the second capacitance signal in the second period,
In the first period, the potential of the second capacitance signal decreases with time,
10. The liquid crystal display panel according to claim 8, wherein the potential of the second capacitance signal rises with time in the second period. In the first period, the potential of the second capacitance signal drops from the first potential to the second potential,
11. The liquid crystal display panel according to claim 10, wherein the potential of the second capacitance signal rises from a third potential to a fourth potential in the second period. The highest potential of the second capacitance signal is higher than the highest potential of the first capacitance signal,
12. The liquid crystal display panel according to claim 8, wherein a minimum potential of the second capacitance signal is lower than a minimum potential of the first capacitance signal.   A liquid crystal display device comprising the liquid crystal display panel according to claim 1.

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