JP2017139291A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art to suppress flowing of load current in a sense element region by causing avalanche breakdown in a main element region preferentially.SOLUTION: A semiconductor device comprises: a main switching element SW1 having a drift region 13, which is formed on a semiconductor substrate 10 in a range corresponding to a main element region 10A; and a sense switching element SW2 having the drift region 13, which is formed on the semiconductor substrate 10 in a range corresponding to a sense element region 10B. A crystal defect concentration of the drift region 13 in a range where the sense switching element SW2 is formed is higher than a crystal defect concentration of the drift region 13 in a range where the main switching element SW1 is formed.SELECTED DRAWING: Figure 3

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device including a semiconductor substrate partitioned into a main element region and a sense element region. A main switching element is formed on a semiconductor substrate in a range corresponding to the main element region, and a sense switching element is formed on a semiconductor substrate in a range corresponding to the sense element region. The area of the main element region is larger than the area of the sense element region. The ratio of the current flowing through the main switching element and the current flowing through the sense switching element is substantially the same as the area ratio between the main element region and the sense element region. Therefore, the current flowing through the main switching element can be known by detecting the current flowing through the sense switching element.

JP 2012-253391 A

  A surge may be applied to such a semiconductor device due to a load short circuit or the like. When an avalanche breakdown occurs in the sense element region due to a surge, a load current flows in the sense element region. Since the area of the sense element region is small, current concentration occurs when a load current flows in the sense element region. In order to avoid such a situation, there is a demand for a technique for suppressing load current from flowing in the sense element region by preferentially causing avalanche breakdown in the main element region.

  One embodiment of a semiconductor device disclosed in this specification includes a semiconductor substrate that is partitioned into at least a main element region and a sense element region. In the semiconductor device of this embodiment, the area of the main element region is larger than the area of the sense element region. A main switching element having a first drift region is formed on a semiconductor substrate in a range corresponding to the main element region. A sense switching element having a second drift region is formed on a semiconductor substrate in a range corresponding to the sense element region. The crystal defect concentration in the second drift region in the range where the sense switching element is formed is higher than the crystal defect concentration in the first drift region in the range where the main switching element is formed. Here, each of the main switching element and the sense switching element is an element having a function of switching a current conduction state and a non-conduction state by a gate input, and includes an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (Metal Oxide Semiconductor Field Effect). Transistor) and the like.

  In the semiconductor device of the above embodiment, since the crystal defect concentration of the second drift region of the sense element region is adjusted to be high, the carrier density of the second drift region of the sense element region is low, and the depletion layer is the second drift region. Can spread to a high range. For this reason, in the semiconductor device of the above embodiment, the breakdown voltage of the sense element region is higher than the breakdown voltage of the main element region. As a result, even if a surge is applied to the semiconductor device due to a load short circuit or the like, avalanche breakdown occurs preferentially in the main element region. Since the area of the main element region is large, current concentration can be suppressed even when a load current flows through the main element region. As a result, the semiconductor device of the above embodiment can have a high tolerance for the load current.

1 schematically shows a circuit diagram of a semiconductor device. The top view of a semiconductor device is shown typically. FIG. 3 is a schematic cross-sectional view of a principal part of the semiconductor device, corresponding to a line III-III in FIG. 2.

  FIG. 1 is a schematic circuit diagram of a semiconductor device 1 according to the embodiment. The semiconductor device 1 includes an IGBT, a main emitter electrode 22, a sense emitter electrode 24, a collector electrode 28, and a gate pad 26 that constitute the main switching element SW1 and the sense switching element SW2. The main emitter electrode 22 is connected to the external electrode 44. The sense emitter electrode 24 is connected to the external electrode 44 via the sense resistor R1.

  As shown in FIG. 2, the semiconductor device 1 has a semiconductor substrate 10 made of silicon. A plurality of main emitter electrodes 22, sense emitter electrodes 24, and gate pads 26 are formed on the surface of the semiconductor substrate 10. A gate wiring (not shown) that is electrically connected to the gate pad 26 is disposed around the main emitter electrode 22 and between the adjacent main emitter electrodes 22. A collector electrode 28 is formed on the back surface of the semiconductor substrate 10. A range where the main emitter electrode 22 is formed corresponds to the main element region 10A, and a range where the sense emitter electrode 24 is formed corresponds to the sense element region 10B. Thus, the semiconductor substrate 10 is divided into the main element region 10A and the sense element region 10B, and the area of the main element region 10A is larger than the area of the sense element region 10B.

  As shown in FIG. 3, the main switching element SW1 is formed on the semiconductor substrate 10 in a range corresponding to the main element region 10A where the main emitter electrode 22 is formed, and the sense emitter electrode 24 is formed. Sense switching element SW2 is formed on semiconductor substrate 10 in a range corresponding to element region 10B. An isolation region 10C in which no switching element is formed exists between the main element region 10A and the sense element region 10B.

  The unit structure of the main switching element SW1 and the sense switching element SW2 is common. Therefore, in the following description, components common to the main switching element SW1 and the sense switching element SW2 are denoted by common reference numerals, and are described collectively.

  The semiconductor substrate 10 has a collector region 11, a buffer region 12, a drift region 13, a body region 14, a body contact region 15 and an emitter region 16. The collector region 11 is formed in the back layer portion of the semiconductor substrate 10, is exposed on the back surface of the semiconductor substrate 10, and is a p-type region having a high p-type impurity concentration. Each of the collector regions 11 of the main switching element SW1 and the sense switching element SW2 is commonly connected to the collector electrode 28 and is in ohmic contact with the collector electrode 28. The buffer region 12 is disposed between the collector region 11 and the drift region 13 and is an n-type region. The drift region 13 is an n-type region that is disposed between the buffer region 12 and the body region 14 and has a low n-type impurity concentration. The drift region 13 is a remaining part in which another semiconductor region is formed on the semiconductor substrate 10. The body region 14 is formed in the surface layer portion of the semiconductor substrate 10, is disposed between the drift region 13 and the emitter region 16, and is a p-type region. Body region 14 is separated by drift region 13 between main element region 10A and sense element region 10B. The body contact region 15 is formed in the surface layer portion of the semiconductor substrate 10, is exposed on the surface of the semiconductor substrate 10, is in contact with the body region 14, and is a p-type region having a high p-type impurity. The body contact region 15 of the main switching element SW1 is in ohmic contact with the main emitter electrode 22. The body contact region 15 of the sense switching element SW2 is in ohmic contact with the sense emitter electrode 24. The emitter region 16 is formed in the surface layer portion of the semiconductor substrate 10, is exposed on the surface of the semiconductor substrate 10, is in contact with the body region 14, and is an n-type region having a high n-type impurity concentration. A plurality of emitter regions 16 are formed in a range exposed on the surface of the semiconductor substrate 10. The emitter region 16 of the main switching element SW1 is in ohmic contact with the main emitter electrode 22. The emitter region 16 of the sense switching element SW2 is in ohmic contact with the sense emitter electrode 24.

  A plurality of trenches are formed in the surface layer portion of the semiconductor substrate 10. Each trench reaches the drift region 13 through the emitter region 16 and the body region 14. An insulating trench gate 30 having a gate insulating film 32 and a gate electrode 34 is formed in each trench. The gate insulating film 32 is formed so as to cover the inner surface of the trench. The gate electrode 34 is insulated from the semiconductor substrate 10 by the gate insulating film 32. The gate electrode 34 faces the emitter region 16, the body region 14, and the drift region 13 with the gate insulating film 32 interposed therebetween. An interlayer insulating film is formed on the gate electrode 34, the gate electrode 34 and the main emitter electrode 22 are insulated by the interlayer insulating film, and the gate electrode 34 and the sense emitter electrode 24 are also insulated by the interlayer insulating film. The gate electrode 34 is electrically connected to the gate pad 26 (see FIG. 2) by a gate wiring (not shown).

  As described above, the main switching element SW1 includes the collector electrode 28, the collector region 11, the buffer region 12, the drift region 13, the body region 14, the body contact region 15, the emitter region 16, the main emitter electrode 22, and the insulating trench gate 30. It is configured. The sense switching element SW2 includes a collector electrode 28, a collector region 11, a buffer region 12, a drift region 13, a body region 14, a body contact region 15, an emitter region 16, a sense emitter electrode 24, and an insulating trench gate 30. Yes. Thus, the unit structures of the main switching element SW1 and the sense switching element SW2 are common. The main switching element SW <b> 1 switches the current flowing between the collector electrode 28 and the main emitter electrode 22 based on the gate voltage applied to the gate electrode 34. The sense switching element SW <b> 2 switches the current flowing between the collector electrode 28 and the sense emitter electrode 24 based on the gate voltage applied to the gate electrode 34.

  The semiconductor device 1 is configured such that the crystal defect concentration in the drift region 13 in the range where the sense switching element SW2 is formed is higher than the crystal defect concentration in the drift region 13 in the range where the main switching element SW1 is formed. Has been. “X” in FIG. 3 indicates a crystal defect. In the semiconductor device 1, crystal defects are selectively formed in the sense element region 10B by the crystal defect formation step. For example, in the semiconductor device 1, crystal defects are selectively formed in the sense element region 10B by selectively performing He irradiation on the sense element region 10B. Thereby, the semiconductor device 1 is configured to have the above-described concentration relationship of crystal defects. Crystal defects may also be formed in the drift region 13 in the range where the main switching element SW1 is formed, but even in this case, the crystal defect concentration is adjusted so that the above relationship is established.

  Next, the operation of the semiconductor device 1 will be described. When the main switching element SW1 and the sense switching element SW2 are turned on simultaneously, a current flows from the collector electrode 28 toward the external electrode 44 (see FIG. 1). Most of the current flows through the main switching element SW1 (that is, the main emitter electrode 22). A part of the current flows through the sense switching element SW2 (that is, the sense emitter electrode 24). The current flowing through the sense switching element SW2 can be measured by the potential difference between both ends of the sense resistor R1. The ratio of the current flowing through the main switching element SW1 and the current flowing through the sense switching element SW2 is substantially equal to the ratio of the area of the main element region 10A and the area of the sense element region 10B. Therefore, the current of the main switching element SW1 can be detected by detecting the current of the sense switching element SW2.

  A surge may be applied to the semiconductor device 1 due to a load short circuit or the like. In the semiconductor device 1, since the crystal defect concentration of the drift region 13 in the sense element region 10 </ b> B is adjusted to be high, the carrier density in the drift region 13 in the sense element region 10 </ b> B is low, and the depletion layer is in the high range of the drift region 13. Can spread. For this reason, in the semiconductor device 1, the breakdown voltage of the sense element region 10B is higher than the breakdown voltage of the main element region 10A. Thereby, even if a surge is applied to the semiconductor device 1 due to a load short circuit or the like, avalanche breakdown preferentially occurs in the main element region 10A. Since the main element region 10A has a large area, current concentration can be suppressed even if a load current flows through the main element region 10A. As a result, the semiconductor device 1 can have a high tolerance for the load current.

  Japanese Patent Application Laid-Open No. 2012-253391 exemplified in the background art is an example in which the pitch of the insulating trench gate is narrower in the sense element region than in the main element region in order to cause avalanche breakdown preferentially in the main element region, An example in which the depth of the insulating trench gate is made deeper in the main element region than in the sense element region is disclosed. However, in order to improve the characteristics, the pitch of the insulating trench gate in the main element region is narrowed to the process limit, and it is difficult to make the pitch of the insulating trench gate in the sense element region narrower than that of the main element region. In other words, in order to make the pitch of the insulating trench gate narrower in the sense element region than in the main element region, it is necessary to increase the pitch of the insulating trench gate in the main element region. In this case, the characteristics of the main switching element SW1 are changed. You have to sacrifice. Further, in order to make the depth of the insulating trench gate deeper in the main element region than in the sense element region, the number of manufacturing steps must be greatly increased. On the other hand, in the semiconductor device 1 disclosed in this specification, the unit structures of the main switching element SW1 and the sense switching element SW2 are common. The characteristics of the main switching element SW1 are not sacrificed. The semiconductor device 1 disclosed in the present specification can preferentially generate avalanche breakdown in the main element region only by adding a step of forming crystal defects (for example, He irradiation).

  In the above, the example in which only the switching element SW1 is formed in the main element region 10A has been described. Instead of this example, a reflux diode may be formed in the main element region 10A in addition to the switching element SW1. In this case, a crystal defect may be formed in the drift region 13 in the range where the diode is formed in the main element region 10A. This crystal defect may be formed in the same process as the crystal defect formed in the sense element region 10B. Also in this case, the crystal defect concentration of the drift region 13 in the range in which the sense switching element SW2 is formed is larger than the crystal defect concentration in the drift region 13 in the range of the main element region 10A in which the main switching element SW1 is formed. If a surge is applied to the semiconductor device 1 due to a load short circuit or the like, the avalanche breakdown can be preferentially caused in the main element region 10A. It can have a high tolerance for load current.

  The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of them.

1: Semiconductor device 10: Semiconductor substrate 10A: Main element region 10B: Sense element region 10C: Isolation region 11: Collector region 12: Buffer region 13: Drift region 14: Body region 15: Body contact region 16: Emitter region 22: Main Emitter electrode 24: Sense emitter electrode 26: Gate pad 28: Collector electrode 30: Insulating trench gate 32: Gate insulating film 34: Gate electrode SW1: Main switching element SW2: Sense switching element External resistance: R1

Claims (1)

A semiconductor device comprising a semiconductor substrate divided into at least a main element region and a sense element region,
An area of the main element region is larger than an area of the sense element region;
A main switching element having a first drift region is formed on the semiconductor substrate in a range corresponding to the main element region;
A sense switching element having a second drift region is formed on the semiconductor substrate in a range corresponding to the sense element region;
The semiconductor device, wherein a crystal defect concentration of the second drift region in a range where the sense switching element is formed is higher than a crystal defect concentration of the first drift region in a range where the main switching element is formed.

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