JP2017134145A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device allowing a thinner bezel.SOLUTION: The display device comprise: a light-emitting element; a drive transistor connected to the light-emitting element; a first switching element connected to the drive transistor and a main power line; a second switching element connected to the drive transistor and a reset power source line; a third switching element connected to the drive transistor and a signal line; a fourth switching element connected to the third switching element and an initialization power source line; and a capacitive element connected to the drive transistor and the third switching element. An ON signal with two horizontal periods is supplied to respective gate terminals of the second switching element, the third switching element, and the fourth switching element.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a display device. In particular, the present invention relates to a circuit configuration of a display device.

  In recent years, there is an increasing demand for high definition and narrow frames in light emitting display devices for mobile use. As a display device for mobile use, a liquid crystal display device (LCD), a display device using an organic EL element (Organic Light-Emitting Diode; OLED), electronic paper, or the like is adopted. Yes.

  The display device using the organic EL element as described above does not require a backlight light source or a polarizing plate, which is necessary for a liquid crystal display device, and further has a low driving voltage for a light-emitting element that is a light source. It has attracted much attention as a thin light emitting display device. In addition, since a display device can be formed using only a thin film, a foldable (flexible) display device can be realized. Furthermore, since a glass substrate is not used, it is possible to realize a light and hard to break display device, which is attracting much attention.

  In the organic EL element, the light emission luminance changes depending on the current flowing through the element. The current flowing through the organic EL element is affected by the characteristics of the thin film transistor (TFT) element used in the active matrix panel. In the organic EL display device, since the drive transistor is connected in series between the power supply line and the organic EL element, the current does not flow through the organic EL element, and the current is affected by the threshold voltage (VTH) variation of the drive transistor. End up. If the current flowing through the organic EL element is different for each pixel, display unevenness is caused and the display quality is deteriorated.

  Therefore, in order to suppress the influence of the characteristic variation of the driving transistor on the display quality, a technique for suppressing the characteristic variation of the driving transistor by providing a constant current circuit for keeping the current flowing through the organic EL element constant, so-called VTH compensation A circuit has been developed.

  For example, as shown in Patent Document 1, the VTH compensation circuit can reduce the influence of the VTH variation of the drive transistor, so that the amount of current supplied to the organic EL element is accurately controlled by the input gradation data. be able to. Therefore, it is possible to effectively compensate for the VTH variation inherent to the drive transistor, and to greatly improve the display quality of the organic EL display device.

JP 2009-276744 A

  However, since the VTH compensation circuit needs to control a plurality of transistors, it is necessary to provide a control circuit for each of the plurality of transistors. This control circuit is arranged in the peripheral region of the display device. When signals supplied to a plurality of transistors provided in the VTH compensation circuit become complicated, the driver circuit becomes large, so that there is a problem that the peripheral region becomes wide and the frame becomes large.

  In view of the above circumstances, an object of the present invention is to provide a display device capable of realizing a narrow frame.

  A display device according to an embodiment of the present invention is a display device in which a plurality of pixels are arranged in a matrix direction, and each of the plurality of pixels includes a light emitting element and one of a source / drain terminal connected to the light emitting element. A first switching element in which one of the source and drain terminals is connected to the other of the source and drain terminals of the driving transistor, and the other of the source and drain terminals is connected to the main power supply line; A second switching element, one of which is connected to one of the source and drain terminals of the driving transistor and the other of the source and drain terminals is connected to the reset power supply line, and one of the source and drain terminals is connected to the gate terminal of the driving transistor. A third switching element having the other of the source / drain terminals connected to the signal line and one of the source / drain terminals Is connected to one of the source and drain terminals of the third switching element, the other of the source and drain terminals is connected to the initialization power supply line, and one electrode is one of the source and drain terminals of the driving transistor. Each of the gates of the second switching element, the third switching element, and the fourth switching element, and the other electrode is connected to one of the source / drain terminals of the third switching element. An ON signal for two horizontal periods is supplied to the terminal.

  A display device according to an embodiment of the present invention is a display device in which a plurality of pixels are arranged in a matrix direction, and each of the plurality of pixels includes a light emitting element and one of a source / drain terminal connected to the light emitting element. A first switching element in which one of the source and drain terminals is connected to the other of the source and drain terminals of the driving transistor, and one of the source and drain terminals is connected to the other of the source and drain terminals of the first switching element. A second switching element connected with the other of the source and drain terminals connected to the main power supply line, one of the source and drain terminals connected to the gate terminal of the drive transistor, and the other of the source and drain terminals connected to the signal line One of the third switching element and the source / drain terminal is one of the source / drain terminals of the third switching element. A fourth switching element having the other source / drain terminal connected to the initialization power supply line, one electrode connected to one of the source / drain terminals of the driving transistor, and the other electrode being the third switching element A capacitive element connected to one of the source / drain terminals of the first switching element, the other of the source / drain terminals of the first switching element and the one of the source / drain terminal of the second switching element via the fifth switching element. Are connected to the reset power supply line, and an ON signal for two horizontal periods is supplied to each gate terminal of the third switching element, the fourth switching element, and the fifth switching element.

It is the schematic which shows an example of the circuit structure of the display apparatus which concerns on one Embodiment of this invention. It is a circuit diagram showing an example of circuit composition of a pixel circuit concerning one embodiment of the present invention. It is a figure which shows the timing chart which shows the drive method of the pixel circuit which concerns on one Embodiment of this invention. It is a circuit diagram which shows an example of the circuit structure of the peripheral circuit which concerns on one Embodiment of this invention. It is a figure which shows the timing chart which shows the drive method of the pixel circuit of multiple rows concerning one Embodiment of this invention. It is a circuit diagram showing an example of circuit composition of a pixel circuit concerning one embodiment of the present invention. It is a figure which shows the timing chart which shows the drive method of the pixel circuit which concerns on one Embodiment of this invention. It is a circuit diagram which shows an example of the circuit structure of the peripheral circuit which concerns on one Embodiment of this invention. It is a figure which shows the timing chart which shows the drive method of the pixel circuit of multiple rows concerning one Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part in comparison with actual aspects for the sake of clarity of explanation, but are merely examples, and the interpretation of the present invention is not limited. It is not limited. In addition, in the present specification and each drawing, elements similar to those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description may be omitted as appropriate.

<Embodiment 1>
The outline | summary of the display apparatus which concerns on one Embodiment of this invention is demonstrated using FIGS. In Embodiment 1, an organic EL display device provided with a threshold compensation circuit for a driving transistor will be described.

[Configuration of Display Device 10]
FIG. 1 is a schematic diagram illustrating an example of a circuit configuration of a display device according to an embodiment of the present invention. As shown in FIG. 1, the display device 10 includes pixel circuits 100 arranged in a matrix of n rows and m columns, and each pixel circuit 100 is controlled by a row driver 110 and a column driver 120. Here, n = 1, 2, 3,..., M = 1, 2, 3,..., For example, if n = 3, the pixel circuit group arranged in the third row indicates m = 3 indicates a pixel circuit group arranged in the third column. Although FIG. 1 illustrates a pixel circuit group of 3 rows and 3 columns, the present invention is not limited to this form, and the numbers n and m can be arbitrarily determined.

  The row driver 110 is a drive circuit that selects a row in which data is written. As will be described later, the pixel circuit 100 includes a plurality of transistors, and the row driver 110 controls the plurality of transistors. In other words, a plurality of control signal lines 112 are connected to the row driver 110, and the plurality of control signal lines 112 are connected to the gate electrodes (or gate terminals) of the plurality of transistors arranged in the pixel circuit 100. It is connected. Although details will be described later, in the first embodiment, the plurality of control signal lines 112 include an output control signal line, a pixel control signal line, a reset control signal line, an initialization control signal line, and a reset power supply line. These control signal lines 112 are sequentially selected exclusively in a predetermined order for each row.

  The column driver 120 is a drive circuit that determines a gradation based on input image data and supplies a data voltage corresponding to the determined gradation to the pixel circuit 100. A plurality of data signal lines 122 are connected to the column driver 120, and the plurality of data signal lines 122 are part of source / drain electrodes (or source / drain terminals) of a plurality of transistors arranged in the pixel circuit 100. ). In other words, the image data is supplied to the pixel circuits 100 in each column via the data signal line 122. Although details will be described later, the first embodiment includes pixel data signal lines as the plurality of data signal lines 122. In addition, the main power supply line and the initialization power supply line extend in the same direction as the data signal line 122. Note that these power supply lines may be connected to the column driver 120 similarly to the data signal line 122. These data signal lines 122 supply image data or a predetermined potential to the pixel circuits 100 in the row selected by the control signal line 112.

  FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a pixel circuit according to an embodiment of the present invention. All the transistors included in the pixel circuit 100 illustrated in FIG. 2 are n-channel transistors. As shown in FIG. 2, the pixel circuit 100 includes a light emitting element D1, a drive transistor DRT, an output transistor BCT, a reset transistor RST, a pixel transistor SST, an initialization transistor IST, a storage capacitor Cs, and an auxiliary capacitor Cad. In the following description, one of the source and drain terminals of a transistor is referred to as a first terminal, and the other of the source and drain terminals is referred to as a second terminal. One terminal of the capacitor is referred to as a first terminal, and the other terminal of the capacitor is referred to as a second terminal.

  The first terminal 211 of the driving transistor DRT is connected to the anode terminal of the light emitting element D1, the first terminal 261 of the storage capacitor Cs, and the first terminal 271 of the auxiliary capacitor Cad, and the second terminal 212 is the first terminal of the output transistor BCT. 221 is connected. The second terminal 222 of the output transistor BCT is connected to the first main power supply line 130. The first terminal 231 of the reset transistor RST is connected to the first terminal 211 of the drive transistor DRT, the first terminal 261 of the storage capacitor Cs, the anode terminal of the light emitting element D1, and the first terminal 271 of the auxiliary capacitor Cad, and the reset transistor RST. The second terminal 232 is connected to the reset power line 142.

  The first terminal 241 of the pixel transistor SST is connected to the gate terminal 213 of the drive transistor DRT, the first terminal 251 of the initialization transistor IST, and the second terminal 262 of the storage capacitor Cs, and the second terminal 242 of the pixel transistor SST is an image. It is connected to the data signal line 144. The second terminal 252 of the initialization transistor IST is connected to the initialization power line 140. A second terminal 272 of the auxiliary capacitor Cad is connected to the initialization power line 140. Further, the cathode terminal of the light emitting element D1 is connected to the second main power supply line 132. Here, the first main power line 130 and the second terminal 272 of the auxiliary capacitor Cad may be connected, or the second main power line 132 and the second terminal 272 of the auxiliary capacitor Cad may be connected.

  Here, the first main power supply line 130 is supplied with the first main power supply voltage PVDD, and the second main power supply line 132 is supplied with the second main power supply voltage PVSS. The first main power supply voltage PVDD corresponds to a voltage based on the voltage applied to the anode, and the second main power supply voltage PVSS corresponds to the cathode voltage. The initialization power supply line 140 is supplied with the initialization power supply voltage Vini, the reset power supply line 142 is supplied with the reset power supply voltage Vrst, and the image data signal line 144 is supplied with the image data Vsig.

  Note that the gate terminal 223 of the output transistor BCT is connected to the output control signal line 150. The gate terminal 233 of the reset transistor RST is connected to the reset control signal line 152. A gate terminal 243 of the pixel transistor SST is connected to the pixel control signal line 154. The gate terminal 253 of the initialization transistor IST is connected to the initialization control signal line 156. Note that the output control signal BG is supplied to the output control signal line 150, the reset control signal RG is supplied to the reset control signal line 152, the pixel control signal SG is supplied to the pixel control signal line 154, and initialization control is performed. An initialization control signal IG is supplied to the signal line 156.

  In other words, the first terminal 261 of the storage capacitor Cs is connected to the first terminal 211 of the drive transistor DRT, and the second terminal 262 of the storage capacitor Cs is connected to the first terminal 241 of the pixel transistor SST. It can also be said. In the first embodiment, the configuration in which all the transistors included in the pixel circuit 100 are n-channel transistors is illustrated, but the present invention is not limited to this configuration. For example, all the transistors other than the driving transistor DRT constituting the pixel circuit 100 may be p-channel transistors, or both n-channel transistors and p-channel transistors may be used. The transistor may be any switching element that can be switched between an on state and an off state, and a switching element other than a transistor may be used.

  The output control signal line 150, the reset control signal line 152, the pixel control signal line 154, the initialization control signal line 156, and the reset power supply line 142 are included in the control signal line 112 in FIG. That is, these control signal lines and power supply lines extend in the row direction of the display device 10. Meanwhile, the first main power supply line 130, the initialization power supply line 140, and the image data signal line 144 are included in the data signal line 122 of FIG. That is, these control signal lines and power supply lines extend in the column direction of the display device 10. The second main power supply line 132 is disposed on the entire surface of the substrate.

[Driving Method of Display Device 10]
FIG. 3 is a timing chart showing the driving method of the pixel circuit according to the embodiment of the present invention. Note that this embodiment shows a case where all the transistors included in the pixel circuit are n-channel transistors. When a “low-level” control signal is supplied to the gate terminal of the transistor, the transistor is turned off (not turned on). Conductive state). On the other hand, when a “high level” control signal is supplied to the gate terminal of the transistor, the transistor is turned on (conductive state). Hereinafter, the driving method of the display device 10 will be described with reference to the circuit diagram of FIG. 2 and the timing chart of FIG. Here, an example in which image data is written to the pixel circuit group in the nth row will be described.

  As shown in FIG. 3, the display device 10 includes (a) a first reset period, (b) a second reset period, (c) a threshold compensation period, (d) a first write period, and (e) a second write. A period, and (f) a light emission period. Hereinafter, these periods will be described with reference to FIGS. The period delimited by the dotted line corresponds to one horizontal period (1H). One horizontal period means a period during which an image data signal is written to all the pixel circuits in a certain row.

(A) First reset period In the first reset period, the output control signal BG changes from the high level to the low level, and the output transistor BCT is turned off. Accordingly, the second terminal 212 of the driving transistor DRT is disconnected from the first main power supply line 130 by the output transistor BCT. Further, the reset control signal RG changes from the low level to the high level, and the reset transistor RST is turned on. Therefore, the reset power supply voltage Vrst is supplied to the first terminal 211 of the drive transistor DRT and the first terminal 261 of the storage capacitor Cs via the reset transistor RST. The initialization control signal IG and the pixel control signal SG are maintained at a low level, and the initialization transistor IST and the pixel transistor SST are maintained in an off state. That is, the gate terminal 213 of the driving transistor DRT and the second terminal 262 of the storage capacitor Cs are in a floating state.

  Here, a voltage lower than the second main power supply voltage PVSS is set as the reset power supply voltage Vrst. However, the reset power supply voltage Vrst does not necessarily need to be lower than the second main power supply voltage PVSS, and may be a voltage that does not allow the current to flow through the light emitting element D1 in the second reset period described later. Specifically, there is no problem as long as the reset power supply voltage Vrst is equal to or lower than the second main power supply voltage PVSS by the threshold voltage of the light emitting element D1. If the reset power supply voltage Vrst is the same as the second main power supply voltage PVSS, the number of necessary power supply voltages is reduced, which leads to a narrow frame and energy consumption reduction. Further, the voltage is set to be lower than the floating voltage of the gate terminal 213 of the drive transistor DRT (that is, the voltage that may be supplied to the gate terminal 213) so that the drive transistor DRT is not turned on. Also good. For example, −3V is supplied as the reset power supply voltage Vrst. With the above operation, the supply of current to the light emitting element D1 is stopped to make the light emitting state non-light emitting. Further, during this period, the auxiliary capacitor Cad is charged / discharged to stabilize the retained charge amount. In the first embodiment, since the second terminal 272 of the auxiliary capacitance Cad is connected to the initialization power supply line 140, the auxiliary capacitance Cad has a potential difference between the initialization power supply voltage Vini and the reset power supply voltage Vrst in the first reset period. The charge based on it is retained. On the other hand, since the second terminal 262 of the storage capacitor Cs is floating, charging / discharging of the storage capacitor Cs is not performed, and the potential of the second terminal 262 changes according to the change of the potential of the first terminal 261.

(B) Second reset period In the second reset period, the initialization control signal IG changes from the low level to the high level, and the initialization transistor IST is turned on. Therefore, the initialization power supply voltage Vini is supplied to the gate terminal 213 of the drive transistor DRT via the initialization transistor IST. The reset control signal RG is maintained at a high level, and the reset transistor RST is maintained in an on state. Further, the output control signal BG and the pixel control signal SG are maintained at a low level, and the output transistor BCT and the pixel transistor SST are maintained in an off state. That is, the reset power supply voltage Vrst is supplied to the first terminal 211 of the driving transistor DRT and the first terminal 261 of the holding capacitor Cs, and the initialization power supply is supplied to the gate terminal 213 of the driving transistor DRT and the second terminal 262 of the holding capacitor Cs. A voltage Vini is supplied.

  Here, as initialization power supply voltage Vini, a voltage higher than reset power supply voltage Vrst is set. For example, + 1V is supplied as the initialization power supply voltage Vini. Accordingly, in the driving transistor DRT, the potential (Vini) of the gate terminal 213 with respect to the potential (Vrst) of the first terminal 211 is at a high level, so that the driving transistor DRT is turned on. This is because a gate-source voltage that can sufficiently turn on the drive transistor DRT is applied to the drive transistor DRT even when the variation in the threshold voltage of the drive transistor DRT is taken into consideration. Further, during this period, the storage capacitor Cs holds charges based on the potential difference between the reset power supply voltage Vrst and the initialization power supply voltage Vini.

  As described above, charging / discharging of the auxiliary capacitor Cad is performed in the first reset period, and charging / discharging of the storage capacitor Cs is performed in the second reset period. That is, charging / discharging is performed on the auxiliary capacitor Cad and the holding capacitor Cs in different reset periods.

(C) Threshold Compensation Period During the threshold compensation period, the output control signal BG changes from the low level to the high level, and the output transistor BCT is turned on. Accordingly, the first main power supply voltage PVDD is supplied to the second terminal 212 of the drive transistor DRT via the output transistor BCT. Further, the reset control signal RG changes from the high level to the low level, and the reset transistor RST is turned off. Accordingly, the first terminal 211 of the driving transistor DRT is disconnected from the reset power supply line 142 by the reset transistor RST. The initialization control signal IG is maintained at a high level, and the initialization transistor IST is maintained in an on state. Further, the pixel control signal SG is maintained at a low level, and the pixel transistor SST is maintained in an off state.

  Here, since the driving transistor DRT is in the ON state during the second reset period, a current flows through the channel of the driving transistor DRT by the first main power supply voltage PVDD supplied to the second terminal 212 of the driving transistor DRT. The potential of the first terminal 211 increases. When the difference between the potential of the first terminal 211 and the potential of the gate terminal 213 reaches the threshold voltage (VTH) of the drive transistor DRT, the drive transistor DRT is turned off.

  Here, since Vini is supplied to the gate terminal 213, when the potential of the first terminal 211 reaches (Vini−VTH), the driving transistor DRT is turned off. At this time, since Vini is supplied to the second terminal 262 of the storage capacitor Cs and (Vini−VTH) is supplied to the first terminal 261, the storage capacitor Cs holds charges based on VTH. In other words, in the threshold compensation period, information based on VTH of the driving transistor DRT is stored in the storage capacitor Cs. Note that Vini is preferably set so that (Vini−VTH) −PVSS <the threshold voltage of the light emitting element, in order to suppress light emission of the light emitting element D1 during the threshold compensation period.

(D) First Write Period In the first write period, the output control signal BG and the initialization control signal IG are changed from the high level to the low level, and the output transistor BCT and the initialization transistor IST are turned off. Accordingly, the second terminal 212 of the drive transistor DRT is disconnected from the first main power supply line 130 by the output transistor BCT, and the gate terminal 213 of the drive transistor DRT is disconnected from the initialization power supply line 140 by the initialization transistor IST. Further, the pixel control signal SG changes from the low level to the high level, and the pixel transistor SST is turned on. The reset control signal RG is maintained at a low level, and the reset transistor RST is maintained in an off state. Thus, in the first writing period, the image data Vsig can be supplied to the gate terminal 213 of the drive transistor DRT. Here, in the first embodiment, in the first writing period, the image data signal line 144 is not supplied with the image data Vsig corresponding to the pixels 100 in the main row, and the image data Vsig corresponding to the pixels 100 in the previous row is basically used. Supplied.

(E) Second Writing Period In the second writing period, gradation data data (n) is supplied to the image data signal line 144 as the image data Vsig. Note that the levels (high level or low level) of the output control signal BG, the reset control signal RG, the initialization control signal IG, and the pixel control signal SG in the second writing period are the same as in the first writing period. In this way, the gradation data data (n) is supplied to the gate terminal 213 of the driving transistor DRT and the second terminal 262 of the storage capacitor Cs via the pixel transistor SST.

  Here, when the potential of the second terminal 262 of the storage capacitor Cs changes from Vini → Vsig, the potential of the first terminal 261 increases based on (Vsig−Vini). Specifically, since the storage capacitor Cs and the auxiliary capacitor Cad are connected in series, the potential (Vs) of the first terminal 261 located in the middle of these capacitors is expressed by the following formula (1).

  Therefore, the potential difference (Vgs) between the potential of the first terminal 211 and the potential of the gate terminal 213 is expressed by the following equation (2). That is, by supplying the image data Vsig to the gate terminal 213, the charge based on the VTH of the drive transistor DRT and the image data Vsig can be held in the storage capacitor Cs. In this way, the drive transistor DRT is turned on based on a potential difference obtained by adding VTH of the drive transistor DRT to the image data Vsig.

(F) Light emission period In the light emission period, the output control signal BG changes from the low level to the high level, and the output transistor BCT is turned on. Further, the pixel control signal SG changes from the high level to the low level, and the pixel transistor SST is turned off. The reset control signal RG and the initialization control signal IG are maintained at a low level, and the reset transistor RST and the initialization transistor IST are maintained in an off state. In this way, the driving transistor DRT provides the light emitting element D1 with a current based on the above formula (2) among the first main power supply voltage PVDD supplied to the second terminal 212.

  Here, the current (Id) flowing through the drive transistor DRT is expressed by the following equation (3). By substituting Equation (2) into Equation (3), the VTH component of the drive transistor DRT is eliminated from Equation (3), and Id is a current that does not depend on VTH as represented by Equation (4) below. It becomes.

  As described above, in the light emission period, the current from which the influence of VTH of the drive transistor DRT is eliminated can be supplied to the light emitting element D1. That is, a current in which VTH of the driving transistor DRT is compensated can be supplied to the light emitting element D1.

  As shown in FIG. 3, the display device 10 is supplied with a high level signal for one horizontal period in each of the first reset period and the second reset period. Further, since the first reset period and the second reset period are continuous, a high level signal for two horizontal periods is supplied to the reset control signal RG. That is, an on signal for two horizontal periods is supplied to the gate terminal 233 of the reset transistor RST. A high level signal for one horizontal period is supplied to each of the first writing period and the second writing period. Further, since the first writing period and the second writing period are continuous, a high level signal for two horizontal periods is supplied to the pixel control signal SG. That is, an ON signal for two horizontal periods is supplied to the gate terminal 243 of the pixel transistor SST.

  As will be described later, in the first writing period, image data is not written to the driving transistor DRT in the main row (n-th row), and the image data Vsig is written in the driving transistor DRT in the previous row (n-1 row). Write. In the first embodiment, the driving method for writing image data to the driving transistor DRT on the (n−1) th row in the first writing period is exemplified. However, the driving method is not limited to this driving method. Image data may be written. In the first embodiment, the image data signal line 144 is supplied with the image data Vsig of the (n−1) th row in the first writing period, and the gradation data data (n (n) is supplied as the image data Vsig of the nth row in the second writing period. However, the present invention is not limited to this driving method.

[Circuit Configuration of Peripheral Circuit of Display Device 10]
FIG. 4 is a circuit diagram showing an example of the circuit configuration of the peripheral circuit according to the embodiment of the present invention. FIG. 4 shows a part of the peripheral circuits from the nth row to the n + 3th row. As shown in FIG. 4, shift registers 310, 312, 314, and 316 are arranged in the peripheral circuits 300, 302, 304, and 306 in the nth to n + 3th rows, respectively. The peripheral circuit 300 in the n-th row includes an initialization control signal line 320, a reset control signal line 330, an OR circuit 340, an inverter 350, an output control signal line 360, and a pixel control signal line 370. The output control signal line 360 is connected to the reset control signal line 330 and the pixel control signal line 370 via the OR circuit 340 and the inverter 350.

  Similar to the peripheral circuit 300 in the nth row, the peripheral circuit 302 in the (n + 1) th row includes an initialization control signal line 322, a reset control signal line 332, an OR circuit 342, an inverter 352, an output control signal line 362, and a pixel control signal. It has a line 372. The peripheral circuit 304 in the (n + 2) th row includes an initialization control signal line 324, a reset control signal line 334, an OR circuit 344, an inverter 354, an output control signal line 364, and a pixel control signal line 374. The peripheral circuit 306 in the (n + 3) th row includes an initialization control signal line 326, a reset control signal line 336, an OR circuit 346, an inverter 356, an output control signal line 366, and a pixel control signal line 376.

  Of the four control signal lines in the peripheral circuit 300 in the n-th row, the pixel control signal line 370 is connected to the shift register 310. On the other hand, the initialization control signal line 320 and the reset control signal line 330 are connected to shift registers other than the nth row. The shift register 310 is connected to the initialization control signal line 324 in the (n + 2) th row and the reset control signal line 336 in the (n + 3) th row. That is, the pixel control signal SG (n) of the pixel control signal line 370, the initialization control signal IG (n + 2) of the initialization control signal line 324, and the reset control signal RG (n + 3) of the reset control signal line 336 have the same timing. A signal SR (n) is supplied.

  2 and 4, the n-th row shift register 310 controls the n-th row pixel transistor SST via the n-th row pixel control signal line 370. The n-th row shift register 310 controls the n + 2 row initialization transistor IST via the n + 2 row initialization control signal line 324. The n-th row shift register 310 controls the n + 3-th row reset transistor RST via the n + 3-th row reset control signal line 336.

  Here, a driving method of the display device 10 using the plurality of shift registers shown in FIG. 4 will be described with reference to FIG. FIG. 5 is a timing chart showing a method for driving a plurality of rows of pixel circuits according to an embodiment of the present invention. FIG. 5 shows timing signals supplied to the pixel circuits from the nth row to the n + 3th row. Referring to FIG. 4, the timing signal SR (n) supplied from the shift register 310 in the nth row is supplied as SG (n), IG (n + 2), and RG (n + 3). That is, as shown in FIG. 5, SG (n), IG (n + 2), and RG (n + 3) are supplied with the same timing signal (see A, B, and C in FIG. 5).

  Referring to FIG. 4, BG (n) is supplied with timing signals supplied as SG (n) and RG (n) through an OR circuit 340 and an inverter 350. That is, as shown in FIG. 5, a timing signal in which RG (n) and SG (n) are inverted is supplied to BG (n) (see A, D, and E in FIG. 5).

  As described above, the timing signals for two horizontal periods are all supplied to BG (n), RG (n), IG (n), and SG (n). Therefore, a shift register that supplies a timing signal for two horizontal periods may be provided in the peripheral circuit. That is, since it is not necessary to supply timing signals having a plurality of types of periods to one row, the pixel circuit can be driven by disposing one type of shift register for one row.

  Further, as shown in FIG. 5, for example, the first writing period (d) of the nth row (main row) overlaps with the second writing period (e ′) of the n−1th row of the preceding row. Therefore, gradation data data (n−1) of the (n−1) th row is supplied as Vsig. That is, in the first writing period (d) of the nth row, the gradation data data (n−1) is written to the pixel circuit of the n−1th row. Then, in the second writing period (e) of the nth row, the gradation data data (n) is written to the pixel circuit of the nth row. In this manner, writing can be performed in the pixel circuit in the previous row in the first writing period, and writing can be performed in the pixel circuit in the main row in the second writing period.

  As described above, according to the display device 10 according to the first embodiment, timing signals for two horizontal periods can be used as timing signals for driving the pixel circuits. Thus, the shift circuit for supplying the timing signal for two horizontal periods only needs to be arranged in the peripheral circuit, so that the area occupied by the peripheral circuit can be reduced. As a result, a display device capable of realizing a narrow frame can be provided.

  In addition, by charging / discharging each of the auxiliary capacitor Cad and the holding capacitor Cs in different reset periods, the load applied to the reset power supply line 142 connected between the auxiliary capacitor Cad and the holding capacitor Cs is reset. Can be distributed over time. Thereby, the light emission variation in the pixel circuit adjacent in the row direction can be reduced. Further, since the display device 10 has the first writing period and the second writing period, a sufficient time for writing can be secured, and more accurate signal writing can be performed. Further, since the signal voltage of the previous row is basically applied in the first writing period, the signal voltage applied in the second writing period varies only in the voltage width at which the gradation voltage varies from the previous row. Therefore, it is not necessary to apply an undesirably large potential difference.

<Embodiment 2>
An overview of a display device according to an embodiment of the present invention will be described with reference to FIGS. In Embodiment 2, an organic EL display device provided with a threshold compensation circuit for a driving transistor will be described.

[Configuration of Display Device 10A]
Since the overall circuit configuration of the display device 10A is the same as that of the display device 10 according to the first embodiment shown in FIG. 1, the description is omitted here and the description will be given with reference to FIG.

  FIG. 6 is a circuit diagram illustrating an example of a circuit configuration of a pixel circuit according to an embodiment of the present invention. All the transistors included in the pixel circuit 100A illustrated in FIG. 6 are n-channel transistors. As shown in FIG. 6, the pixel circuit 100A includes a light emitting element D1, a drive transistor DRT, a light emission control transistor CCT, an output transistor BCT, a pixel transistor SST, an initialization transistor IST, a storage capacitor Cs, and an auxiliary capacitor Cad. Further, for example, a reset transistor RST arranged outside the pixel circuit 100A such as a peripheral circuit is connected to the pixel circuit 100A. In the following description, one of the source and drain terminals of a transistor is referred to as a first terminal, and the other of the source and drain terminals is referred to as a second terminal. One terminal of the capacitor is referred to as a first terminal, and the other terminal of the capacitor is referred to as a second terminal.

  The first terminal 211A of the driving transistor DRT is connected to the anode terminal of the light emitting element D1, the first terminal 261A of the storage capacitor Cs, and the first terminal 271A of the auxiliary capacitor Cad, and the second terminal 212A is the first terminal of the light emission control transistor CCT. It is connected to the terminal 281A. The second terminal 282A of the light emission control transistor CCT is connected to the first terminal 221A of the output transistor BCT and the first terminal 231A of the reset transistor RST. The second terminal 222A of the output transistor BCT is connected to the first main power supply line 130A.

  The first terminal 241A of the pixel transistor SST is connected to the gate terminal 213A of the drive transistor DRT, the first terminal 251A of the initialization transistor IST, and the second terminal 262A of the storage capacitor Cs, and the second terminal 242A of the pixel transistor SST is an image. It is connected to the data signal line 144A. The second terminal 252A of the initialization transistor IST is connected to the initialization power supply line 140A. The second terminal 272A of the auxiliary capacitor Cad is connected to the initialization power line 140A. The cathode terminal of the light emitting element D1 is connected to the second main power supply line 132A.

  As described above, the first terminal 231A of the reset transistor RST disposed outside the pixel circuit 100A is connected to the second terminal 282A of the light emission control transistor CCT and the first terminal 221A of the output transistor BCT, and the second terminal 232A is a reset power source. Connected to line 142A.

  Here, the first main power supply line 130A is supplied with the first main power supply voltage PVDD, and the second main power supply line 132A is supplied with the second main power supply voltage PVSS. The first main power supply voltage PVDD corresponds to a voltage for creating an anode voltage, and the second main power supply voltage PVSS corresponds to a cathode voltage. The initialization power supply line 140A is supplied with the initialization power supply voltage Vini, the reset power supply line 142A is supplied with the reset power supply voltage Vrst, and the image data signal line 144A is supplied with the image data Vsig.

  Note that the gate terminal 283A of the light emission control transistor CCT is connected to the light emission control signal line 158A. The gate terminal 223A of the output transistor BCT is connected to the output control signal line 150A. The gate terminal 243A of the pixel transistor SST is connected to the pixel control signal line 154A. The gate terminal 253A of the initialization transistor IST is connected to the initialization control signal line 156A. The light emission control signal line 158A is supplied with the light emission control signal CG, the output control signal line 150A is supplied with the output control signal BG, the pixel control signal line 154A is supplied with the pixel control signal SG, and the initialization control is performed. An initialization control signal IG is supplied to the signal line 156A. The gate terminal 233A of the reset transistor RST is connected to the reset control signal line 152A, and the reset control signal RG is supplied to the reset control signal line 152A.

  In other words, the first terminal 261A of the storage capacitor Cs is connected to the first terminal 211A of the drive transistor DRT, and the second terminal 262A of the storage capacitor Cs is connected to the first terminal 241A of the pixel transistor SST. It can also be said. In the second embodiment, the configuration in which all the transistors included in the pixel circuit 100A are n-channel transistors is illustrated, but the present invention is not limited to this configuration. For example, all the transistors other than the driving transistor DRT constituting the pixel circuit 100A may be p-channel transistors, or both n-channel transistors and p-channel transistors may be used.

[Driving Method of Display Device 10A]
FIG. 7 is a timing chart showing the driving method of the pixel circuit according to the embodiment of the present invention. Note that this embodiment shows a case where all the transistors included in the pixel circuit are n-channel transistors. When a “low-level” control signal is supplied to the gate terminal of the transistor, the transistor is turned off (not turned on). Conductive state). On the other hand, when a “high level” control signal is supplied to the gate terminal of the transistor, the transistor is turned on (conductive state). Hereinafter, the driving method of the display device 10A will be described with reference to the circuit diagram of FIG. 6 and the timing chart of FIG. Here, an example in which image data is written to the pixel circuit group in the nth row will be described.

  As shown in FIG. 7, the display device 10A includes (a) a first reset period, (b) a second reset period, (c) a threshold compensation period, (d) a first write period, and (e) a second write. A period, and (f) a light emission period. Hereinafter, these periods will be described with reference to FIGS. The period delimited by the dotted line corresponds to one horizontal period (1H). One horizontal period means a period during which an image data signal is written to all the pixel circuits in a certain row. In addition, since the outline | summary of operation | movement in said each period is similar to Embodiment 1, detailed description is abbreviate | omitted.

(A) First reset period In the first reset period, the output control signal BG changes from high level to low level, and the reset control signal RG changes from low level to high level. The light emission control signal CG is maintained at a high level, and the initialization control signal IG and the pixel control signal SG are maintained at a low level. That is, the light emission control transistor CCT and the reset transistor RST are turned on, and the output transistor BCT, the pixel transistor SST, and the initialization transistor IST are turned off. As a result, the reset power supply voltage Vrst is supplied to the second terminal 212A of the driving transistor DRT. Note that the reset power supply voltage Vrst may be a voltage that allows the drive transistor DRT to be turned on in the first reset period. The reset power supply voltage Vrst may be a voltage obtained by adding the margin voltage to the threshold voltage VTH of the drive transistor DRT to the second main power supply voltage PVSS.

(B) Second reset period In the second reset period, the initialization control signal IG changes from low level to high level. The output control signal BG and the pixel control signal SG are maintained at a low level, and the reset control signal RG and the light emission control signal CG are maintained at a high level. That is, the reset transistor RST, the light emission control transistor CCT, and the initialization transistor IST are turned on, and the output transistor BCT and the pixel transistor SST are turned off. As a result, the reset power supply voltage Vrst is supplied to the second terminal 212A of the drive transistor DRT, and the initialization power supply voltage Vini is supplied to the gate terminal 213A of the drive transistor DRT and the second terminal 262A of the storage capacitor Cs.

  Here, as the reset power supply voltage Vrst and the initialization power supply voltage Vini, a voltage that turns on the driving transistor DRT is supplied. Therefore, the reset power supply voltage Vrst is supplied to the first terminal 211A and the first terminal 261A of the storage capacitor Cs via the drive transistor DRT.

(C) Threshold Compensation Period In the threshold compensation period, the output control signal BG changes from the low level to the high level, and the reset control signal RG changes from the high level to the low level. The light emission control signal CG and the initialization control signal IG are maintained at a high level, and the pixel control signal SG is maintained at a low level. That is, the output transistor BCT, the light emission control transistor CCT, and the initialization transistor IST are turned on, and the reset transistor RST and the pixel transistor SST are turned off.

  Here, since the driving transistor DRT is in an ON state during the second reset period, a current flows through the channel of the driving transistor DRT by the first main power supply voltage PVDD supplied to the second terminal 212A of the driving transistor DRT. The potential of the first terminal 211A increases. When the difference between the potential of the first terminal 211A and the potential of the gate terminal 213A reaches the threshold voltage (VTH) of the drive transistor DRT, the drive transistor DRT is turned off.

  Here, since Vini is supplied to the gate terminal 213A, when the potential of the first terminal 211A reaches (Vini−VTH), the driving transistor DRT is turned off. At this time, since Vini is supplied to the second terminal 262A of the storage capacitor Cs and (Vini−VTH) is supplied to the first terminal 261A, the storage capacitor Cs holds charges based on VTH. In other words, in the threshold compensation period, information based on VTH of the driving transistor DRT is stored in the storage capacitor Cs.

(D) First Write Period In the first write period, the output control signal BG, the light emission control signal CG, and the initialization control signal IG change from high level to low level, and the pixel control signal SG changes from low level to high level. . The reset control signal RG is maintained at a low level. That is, the pixel transistor SST is turned on, and the output transistor BCT, the reset transistor RST, the light emission control transistor CCT, and the initialization transistor IST are turned off. Thus, in the first writing period, the image data Vsig can be supplied to the gate terminal 213A of the driving transistor DRT. Here, in the second embodiment, in the first writing period, the image data signal line 144A is not supplied with the image data Vsig corresponding to the pixel 100A in the main row, and the image data Vsig corresponding to the pixel 100A in the previous row is basically used. Supplied.

(E) Second Writing Period In the second writing period, gradation data data (n) is supplied as image data Vsig to the image data signal line 144A. Note that the levels (high level or low level) of the output control signal BG, reset control signal RG, light emission control signal CG, initialization control signal IG, and pixel control signal SG in the second writing period are the same as in the first writing period. is there. In this way, the gradation data data (n) is supplied to the gate terminal 213A of the driving transistor DRT and the second terminal 262A of the storage capacitor Cs via the pixel transistor SST. At this time, the potential difference (Vgs) between the potential of the first terminal 211A of the driving transistor DRT and the potential of the gate terminal 213A is expressed by the above equation (2).

(F) Light emission period In the light emission period, the output control signal BG and the light emission control signal CG change from low level to high level, and the pixel control signal SG changes from high level to low level. The reset transistor RST and the initialization transistor IST are kept off. That is, the output transistor BCT and the light emission control transistor CCT are turned on, and the reset transistor RST, the initialization transistor IST, and the pixel transistor SST are turned off. In this way, the driving transistor DRT provides the light emitting element D1 with a current based on the above formula (2) among the first main power supply voltage PVDD supplied to the second terminal 212A.

  Here, the current (Id) flowing through the driving transistor DRT is expressed by the above equation (4). That is, Id is a current that does not depend on VTH.

  As described above, in the light emission period, the current from which the influence of VTH of the drive transistor DRT is eliminated can be supplied to the light emitting element D1. That is, a current in which VTH of the driving transistor DRT is compensated can be supplied to the light emitting element D1.

  As shown in FIG. 7, the display device 10A is supplied with a high level signal for one horizontal period in each of the first reset period and the second reset period. Further, since the first reset period and the second reset period are continuous, a high level signal for two horizontal periods is supplied to the reset control signal RG. That is, an ON signal for two horizontal periods is supplied to the gate terminal 233A of the reset transistor RST. A high level signal for one horizontal period is supplied to each of the first writing period and the second writing period. Further, since the first writing period and the second writing period are continuous, a high level signal for two horizontal periods is supplied to the pixel control signal SG. That is, an ON signal for two horizontal periods is supplied to the gate terminal 243A of the pixel transistor SST.

  As will be described later, in the first writing period, image data is not written to the driving transistor DRT in the main row (n-th row), and the image data Vsig is written in the driving transistor DRT in the previous row (n-1 row). Write. However, in the first writing period, the image data may be written to the driving transistors DRT other than the (n−1) th row.

[Circuit Configuration of Peripheral Circuit of Display Device 10A]
FIG. 8 is a circuit diagram showing an example of the circuit configuration of the peripheral circuit according to the embodiment of the present invention. FIG. 8 shows a part of the peripheral circuits from the nth row to the n + 3th row. As shown in FIG. 8, shift registers 310A, 312A, 314A, and 316A are arranged in the peripheral circuits 300A, 302A, 304A, and 306A in the nth to n + 3th rows, respectively. The peripheral circuit 300A in the n-th row includes an initialization control signal line 320A, a reset control signal line 330A, an OR circuit 340A, an inverter 350A, an output control signal line 360A, a pixel control signal line 370A, an inverter 380A, and a light emission control signal line 390A. have. The output control signal line 360A is connected to the reset control signal line 330A and the pixel control signal line 370A via the OR circuit 340A and the inverter 350A. The light emission control signal line 390A is connected to the pixel control signal line 370A via the inverter 380A.

  Similar to the peripheral circuit 300A in the nth row, the peripheral circuit 302A in the (n + 1) th row has an initialization control signal line 322A, a reset control signal line 332A, an OR circuit 342A, an inverter 352A, an output control signal line 362A, and a pixel control signal line. 372A, an inverter 382A, and a light emission control signal line 392A. The peripheral circuit 304A in the (n + 2) th row includes an initialization control signal line 324A, a reset control signal line 334A, an OR circuit 344A, an inverter 354A, an output control signal line 364A, a pixel control signal line 374A, an inverter 384A, and a light emission control signal. It has a line 394A. The peripheral circuit 306A in the (n + 3) th row includes an initialization control signal line 326A, a reset control signal line 336A, an OR circuit 346A, an inverter 356A, an output control signal line 366A, a pixel control signal line 376A, an inverter 386A, and a light emission control signal. It has line 396A.

  Of the five control signal lines in the n-th row peripheral circuit 300A, the pixel control signal line 370A and the light emission control signal line 390A are connected to the shift register 310A. On the other hand, the initialization control signal line 320A and the reset control signal line 330A are connected to shift registers other than the nth row. The shift register 310A is connected to the initialization control signal line 324A on the (n + 2) th row and the reset control signal line 336A on the (n + 3) th row. That is, the pixel control signal SG (n) of the pixel control signal line 370A, the initialization control signal IG (n + 2) of the initialization control signal line 324A, and the reset control signal RG (n + 3) of the reset control signal line 336A have the same timing. A signal SR (n) is supplied.

  6 and FIG. 8, the n-th row shift register 310A controls the n-th row pixel transistor SST via the n-th row pixel control signal line 370A. The n-th row shift register 310A controls the n + 2 row initialization transistor IST via the n + 2 row initialization control signal line 324A. The n-th row shift register 310A controls the n + 3-th row reset transistor RST via the n + 3-th row reset control signal line 336A.

  Here, a driving method of the display device 10A using the plurality of shift registers shown in FIG. 8 will be described with reference to FIG. FIG. 9 is a diagram illustrating a timing chart illustrating a method for driving a plurality of rows of pixel circuits according to an embodiment of the present invention. FIG. 9 shows timing signals supplied to the pixel circuits from the nth row to the n + 3th row. Referring to FIG. 8, the timing signal SR (n) supplied from the nth row shift register 310A is supplied as SG (n), IG (n + 2), and RG (n + 3). That is, as shown in FIG. 9, the same timing signal is supplied to SG (n), IG (n + 2), and RG (n + 3) (see F, G, and H in FIG. 9).

  Referring to FIG. 8, CG (n) is supplied with the timing signal supplied as SG (n) via an inverter 380A. That is, as shown in FIG. 9, a timing signal in which SG (n) is inverted is supplied to CG (n) (see F and I in FIG. 9). In addition, the timing signal supplied as SG (n) and RG (n) is supplied to BG (n) via the OR circuit 340A and the inverter 350A. That is, as shown in FIG. 9, a timing signal obtained by inverting RG (n) and SG (n) is supplied to BG (n) (see F, J, and K in FIG. 5).

  As described above, timing signals for two horizontal periods are supplied to BG (n), RG (n), CG (n), IG (n), and SG (n). Therefore, a shift register that supplies a timing signal for two horizontal periods may be provided in the peripheral circuit. That is, since it is not necessary to supply timing signals having a plurality of types of periods to one row, the pixel circuit can be driven by disposing one type of shift register for one row.

  Further, as shown in FIG. 9, for example, the first writing period (d) of the nth row (main row) overlaps with the second writing period (e ′) of the n−1th row of the preceding row. Therefore, gradation data data (n−1) of the (n−1) th row is supplied as Vsig. That is, in the first writing period (d) of the nth row, the gradation data data (n−1) is written to the pixel circuit of the n−1th row. Then, in the second writing period (e) of the nth row, the gradation data data (n) is written to the pixel circuit of the nth row. In this manner, writing can be performed in the pixel circuit in the previous row in the first writing period, and writing can be performed in the pixel circuit in the main row in the second writing period.

  As described above, according to the display device 10A according to the second embodiment, timing signals for two horizontal periods can be used as timing signals for driving the pixel circuits. Thus, the shift circuit for supplying the timing signal for two horizontal periods only needs to be arranged in the peripheral circuit, so that the area occupied by the peripheral circuit can be reduced. As a result, a display device capable of realizing a narrow frame can be provided.

  In addition, by charging / discharging each of the auxiliary capacitor Cad and the holding capacitor Cs in different reset periods, the load applied to the reset power supply line 142 connected between the auxiliary capacitor Cad and the holding capacitor Cs is reset. Can be distributed over time. Thereby, the light emission variation in the pixel circuit adjacent in the row direction can be reduced. Furthermore, since the display device 10A has the first writing period and the second writing period, a sufficient time for writing can be maintained, and more accurate signal writing can be performed. Further, since the signal voltage of the previous row is basically applied in the first writing period, the signal voltage applied in the second writing period varies only in the voltage width at which the gradation voltage varies from the previous row. Therefore, it is not necessary to apply an undesirably large potential difference.

  Note that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention.

10: Display device, 100: Pixel circuit, 110: Row driver, 112: Control signal line, 120: Column driver, 122: Data signal line, 130: First main power line, 132: Second main power line, 140: Initialization power supply line, 142: Reset power supply line, 144: Image data signal line, 150: Output control signal line, 152: Reset control signal line, 154: Pixel control signal line, 156: Initialization control signal line, 158: Light emission Control signal lines 211, 221, 231, 241, 251, 261, 271, 281: First terminal 212, 222, 232, 242, 252, 262, 272, 282: Second terminal, 213, 223, 233, 243, 253, 283: gate terminals, 300, 302, 304, 306: peripheral circuits, 310, 312, 314: shift register, 320, 322, 324, 326: initialization control signal line, 330, 332, 334, 336: reset control signal line, 340, 342, 344, 346: OR circuit, 350, 352 354, 356, 380, 382, 384, 386: inverter, 360, 362, 364, 366: output control signal line, 370, 372, 374, 376: pixel control signal line, 390, 392, 394, 396: light emission Control signal line, BCT: output transistor, CCT: light emission control transistor, Cad: auxiliary capacitor, Cs: holding capacitor, D1: light emitting element, DRT: drive transistor, IST: initialization transistor, RST: reset transistor, SST: pixel transistor

Claims (8)

It has a plurality of pixels arranged in a row direction and a column direction, and each of the plurality of pixels is
A light emitting element;
A drive transistor in which one of the source and drain terminals is connected to the light emitting element;
A first switching element in which one of the source and drain terminals is connected to the other of the source and drain terminals of the driving transistor, and the other of the source and drain terminals is connected to a main power supply line;
A second switching element in which one of the source and drain terminals is connected to one of the source and drain terminals of the drive transistor, and the other of the source and drain terminals is connected to a reset power supply line;
A third switching element in which one of the source / drain terminals is connected to the gate terminal of the driving transistor and the other of the source / drain terminals is connected to the signal line;
A fourth switching element in which one of the source and drain terminals is connected to one of the source and drain terminals of the third switching element, and the other of the source and drain terminals is connected to the initialization power supply line;
A capacitive element having one electrode connected to one of the source / drain terminals of the driving transistor and the other electrode connected to one of the source / drain terminals of the third switching element;
Have
A display device, wherein an ON signal for two horizontal periods is supplied to each gate terminal of the second switching element, the third switching element, and the fourth switching element. A plurality of shift registers provided for each row;
The shift register in the nth row is
the third switching element in the n-th row;
the fourth switching element in the (n + 2) th row;
the second switching element in the (n + 3) th row;
The display device according to claim 1, wherein the display device is controlled. A first reset period, a second reset period, a threshold compensation period, and a writing period;
In the first reset period, the first switching element is off, the second switching element is on, the third switching element is off, and the fourth switching element is off,
In the second reset period, the first switching element is off, the second switching element is on, the third switching element is off, and the fourth switching element is on,
In the threshold compensation period, the first switching element is on, the second switching element is off, the third switching element is off, and the fourth switching element is on,
The writing period is characterized in that the first switching element is off, the second switching element is off, the third switching element is on, and the fourth switching element is off. The display device according to 1. A first reset period for supplying a reset voltage supplied to the reset power supply line to one of the source / drain terminals of the drive transistor;
A second reset period for supplying an initialization voltage supplied to the initialization power supply line to the gate terminal of the drive transistor;
By cutting off the reset voltage supplied to one of the source / drain terminals of the driving transistor and supplying the main voltage supplied to the main power supply line to the other of the source / drain terminals of the driving transistor, A threshold compensation period for causing the capacitive element to retain charges based on the threshold voltage of the driving transistor;
The main voltage supplied to the other of the source and drain terminals of the driving transistor and the initialization voltage supplied to the gate terminal of the driving transistor are cut off and supplied to the signal line to the gate terminal of the driving transistor. A write period in which the capacitor element holds charges based on the threshold voltage and the signal voltage by supplying the signal voltage
The display device according to claim 1, comprising: It has a plurality of pixels arranged in a row direction and a column direction, and each of the plurality of pixels is
A light emitting element;
A drive transistor in which one of the source and drain terminals is connected to the light emitting element;
A first switching element in which one of the source and drain terminals is connected to the other of the source and drain terminals of the driving transistor;
A second switching element in which one of the source and drain terminals is connected to the other of the source and drain terminals of the first switching element, and the other of the source and drain terminals is connected to a main power supply line;
A third switching element in which one of the source / drain terminals is connected to the gate terminal of the driving transistor and the other of the source / drain terminals is connected to the signal line;
A fourth switching element in which one of the source and drain terminals is connected to one of the source and drain terminals of the third switching element, and the other of the source and drain terminals is connected to the initialization power supply line;
A capacitive element having one electrode connected to one of the source / drain terminals of the driving transistor and the other electrode connected to one of the source / drain terminals of the third switching element;
Have
The other of the source / drain terminals of the first switching element and one of the source / drain terminals of the second switching element are connected to a reset power line via a fifth switching element,
A display device, wherein an ON signal for two horizontal periods is supplied to each gate terminal of the third switching element, the fourth switching element, and the fifth switching element. A plurality of shift registers provided for each row;
The shift register in the nth row is
the third switching element in the n-th row;
the fourth switching element in the (n + 2) th row;
the fifth switching element in the (n + 3) th row;
The display device according to claim 5, wherein the display device is controlled. A first reset period, a second reset period, a threshold compensation period, and a writing period;
In the first reset period, the first switching element is on, the second switching element is off, the third switching element is off, the fourth switching element is off, and the fifth switching element is on State
In the second reset period, the first switching element is on, the second switching element is off, the third switching element is off, the fourth switching element is on, and the fifth switching element is on State
In the threshold compensation period, the first switching element is on, the second switching element is on, the third switching element is off, the fourth switching element is on, and the fifth switching element is on Is off,
In the writing period, the first switching element is off, the second switching element is off, the third switching element is on, the fourth switching element is off, and the fifth switching element is off The display device according to claim 5, wherein the display device is a display device. A first reset period for supplying a reset voltage supplied to the reset power supply line to the other of the source and drain terminals of the drive transistor;
A second reset period for supplying an initialization voltage supplied to the initialization power supply line to the gate terminal of the drive transistor;
Cutting off the reset voltage supplied to the other of the source / drain terminals of the driving transistor and supplying the main voltage supplied to the main power line to the other of the source / drain terminals of the driving transistor; A threshold compensation period for causing the capacitive element to retain charges based on the threshold voltage of the driving transistor;
The main voltage supplied to the other of the source and drain terminals of the driving transistor and the initialization voltage supplied to the gate terminal of the driving transistor are cut off and supplied to the signal line to the gate terminal of the driving transistor. A write period in which the capacitor element holds charges based on the threshold voltage and the signal voltage by supplying the signal voltage
The display device according to claim 5, further comprising:

Images