JP2017130579A - 半導体装置、電子部品、電子機器、および半導体装置の製造方法 - Google Patents
半導体装置、電子部品、電子機器、および半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】基板500と、前記基板500の上に設けられた第1導電型の第1コンタクト層100と、前記第1コンタクト層100の上に設けられたチャネル層300と、前記チャネル層300の側面に設けられ、前記チャネル層300の側面との間でバリア層310を挟持するゲート電極400と、前記チャネル層300の上に設けられた第1導電型の第2コンタクト層200と、前記第1コンタクト層100の上に設けられた第1電極110と、前記第2コンタクト層200の上に設けられた第2電極210と、を備える。
【選択図】図1
Description
0.本開示の技術的背景
1.第1の実施形態
1.1.半導体装置の構造
1.2.半導体装置の製造方法
2.第2の実施形態
3.第3の実施形態
4.第4の実施形態
5.第5の実施形態
6.第6の実施形態
6.1.第1の構造例
6.2.第2の構造例
6.3.第3の構造例
7.まとめ
まず、図17を参照して、本開示の技術的背景について説明する。図17は、比較例に係る半導体装置である化合物半導体トランジスタの積層構造を示す断面図である。
<1.1.半導体装置の構造>
まず、図1を参照して、本開示の第1の実施形態に係る半導体装置の積層構造について説明する。図1は、本実施形態に係る半導体装置1の積層構造を示す断面図である。
続いて、図3〜図9を参照して、本実施形態に係る半導体装置1の製造方法について説明する。図3〜図9は、図1で示した半導体装置1の製造工程を示す断面図である。
次に、図10を参照して、本開示の第2の実施形態に係る半導体装置2について説明する。図10は、本実施形態に係る半導体装置2の積層構造を示す断面図である。なお、図1と同一符号を付した構成は、実質的に図1で示した構成と同様であるため、ここでの説明は省略する。
次に、図11を参照して、本開示の第3の実施形態に係る半導体装置3について説明する。図11は、本実施形態に係る半導体装置3の積層構造を示す断面図である。なお、図1と同一符号を付した構成は、実質的に図1で示した構成と同様であるため、ここでの説明は省略する。
次に、図12を参照して、本開示の第4の実施形態に係る半導体装置4について説明する。図12は、本実施形態に係る半導体装置4の積層構造を示す断面図である。なお、図1と同一符号を付した構成は、実質的に図1で示した構成と同様であるため、ここでの説明は省略する。
次に、図13を参照して、本開示の第5の実施形態に係る半導体装置5について説明する。図13は、本実施形態に係る半導体装置5の積層構造を示す断面図である。なお、図1、図10および図12と同一符号を付した構成は、実質的に図1、図10および図12で示した構成と同様であるため、ここでの説明は省略する。
次に、図14〜図16を参照して、本開示の第6の実施形態に係る半導体装置について説明する。図14〜図16は、本実施形態に係る半導体装置の第1〜第3の構造例を示す断面図である。なお、図1と同一符号を付した構成は、実質的に図1で示した構成と同様であるため、ここでの説明は省略する。
まず、図14を参照して、第1の構造例について説明する。図14に示すように、第1の構造例に係る半導体装置6では、チャネル層300の下方の第1コンタクト層100に、容量低減領域として第1コンタクト層100よりも誘電率が低い低誘電率領域121が設けられる。
次に、図15を参照して、第2の構造例について説明する。図15に示すように、第2の構造例に係る半導体装置7では、チャネル層300の下方の第1コンタクト層100に、容量低減領域として第1コンタクト層100よりもキャリア密度が低い低キャリア領域122が設けられる。
次に、図16を参照して、第3の構造例について説明する。図16に示すように、第3の構造例に係る半導体装置8では、チャネル層300の下方の第1コンタクト層100に、容量低減領域として空乏層123が設けられる。
以上にて詳細に説明したように、本開示の一実施形態に係る半導体装置によれば、チャネル層300の膜厚がソース電極とドレイン電極との間の距離になるため、最先端の製造設備を用いなくともソース電極とドレイン電極との間の距離を縮小することができる。したがって、本開示の一実施形態に係る半導体装置によれば、チャネル抵抗を低下させ、オン抵抗を低下させることが可能である。
(1)
基板と、
前記基板の上に設けられた第1導電型の第1コンタクト層と、
前記第1コンタクト層の上に設けられたチャネル層と、
前記チャネル層の側面に設けられ、前記チャネル層の側面との間でバリア層を挟持するゲート電極と、
前記チャネル層の上に設けられた第1導電型の第2コンタクト層と、
前記第1コンタクト層の上に設けられた第1電極と、
前記第2コンタクト層の上に設けられた第2電極と、
を備える、半導体装置。
(2)
前記チャネル層の結晶のC軸方向は、前記チャネル層の側面に対して略垂直である、前記(1)に記載の半導体装置。
(3)
前記チャネル層は、平面視にて島状に設けられ、
前記第1電極は、平面視にて前記チャネル層を取り囲む位置に設けられる、前記(1)または(2)に記載の半導体装置。
(4)
前記ゲート電極と前記バリア層との間には、絶縁層が設けられる、前記(1)〜(3)のいずれか一項に記載の半導体装置。
(5)
前記ゲート電極と前記バリア層との間には、第2導電型の半導体層が設けられる、前記(1)〜(3)のいずれか一項に記載の半導体装置。
(6)
前記バリア層の前記ゲート電極と接する一部または全部は、第2導電型の半導体層である、前記(1)〜(3)のいずれか一項に記載の半導体装置。
(7)
チャネル層は、第2導電型の半導体層である、前記(1)〜(3)のいずれか一項に記載の半導体装置。
(8)
前記チャネル層の下方の前記第1コンタクト層には、容量低減領域が設けられる、前記(1)〜(7)のいずれか一項に記載の半導体装置。
(9)
前記容量低減領域は、前記第1コンタクト層よりも誘電率が低い低誘電率領域である、前記(8)に記載の半導体装置。
(10)
前記容量低減領域は、前記第1コンタクト層よりもキャリア密度が低い低キャリア領域である、前記(8)に記載の半導体装置。
(11)
前記容量低減領域は、空乏層であり、
前記空乏層は、前記第1コンタクト層の内部に設けられた第2導電型の空乏化領域によって形成される、前記(8)に記載の半導体装置。
(12)
基板と、
前記基板の上に設けられた第1導電型の第1コンタクト層と、
前記第1コンタクト層の上に設けられたチャネル層と、
前記チャネル層の側面に設けられ、前記チャネル層の側面との間でバリア層を挟持するゲート電極と、
前記チャネル層の上に設けられた第1導電型の第2コンタクト層と、
前記第1コンタクト層の上に設けられた第1電極と、
前記第2コンタクト層の上に設けられた第2電極と、
を備える半導体装置を含む、電子部品。
(13)
基板と、
前記基板の上に設けられた第1導電型の第1コンタクト層と、
前記第1コンタクト層の上に設けられたチャネル層と、
前記チャネル層の側面に設けられ、前記チャネル層の側面との間でバリア層を挟持するゲート電極と、
前記チャネル層の上に設けられた第1導電型の第2コンタクト層と、
前記第1コンタクト層の上に設けられた第1電極と、
前記第2コンタクト層の上に設けられた第2電極と、
を備える半導体装置を含む、電子機器。
(14)
基板の上に、第1導電型の第1コンタクト層をエピタキシャル成長させることと、
前記第1コンタクト層の上に、チャネル層をエピタキシャル成長させることと、
前記第1コンタクト層の上に、第1導電型の第2コンタクト層をエピタキシャル成長させることと、
前記チャネル層および前記第2コンタクト層を平面視にて島状にエッチングすることと、
前記第1コンタクト層および前記第2コンタクト層の上に、バリア層およびゲート電極材料層を順に形成することと、
前記ゲート電極材料層を異方性エッチングして、前記チャネル層の側面にゲート電極を形成することと、
前記第1コンタクト層および前記第2コンタクト層の上に、それぞれ第1電極および第2電極を形成することと、
を含む半導体装置の製造方法。
100 第1コンタクト層
110 第1電極
200 第2コンタクト層
210 第2電極
300 チャネル層
310 バリア層
320 二次元電子ガス層
400 ゲート電極
500 基板
510 バッファ層
520 絶縁層
Claims (14)
- 基板と、
前記基板の上に設けられた第1導電型の第1コンタクト層と、
前記第1コンタクト層の上に設けられたチャネル層と、
前記チャネル層の側面に設けられ、前記チャネル層の側面との間でバリア層を挟持するゲート電極と、
前記チャネル層の上に設けられた第1導電型の第2コンタクト層と、
前記第1コンタクト層の上に設けられた第1電極と、
前記第2コンタクト層の上に設けられた第2電極と、
を備える、半導体装置。 - 前記チャネル層の結晶のC軸方向は、前記チャネル層の側面に対して略垂直である、請求項1に記載の半導体装置。
- 前記チャネル層は、平面視にて島状に設けられ、
前記第1電極は、平面視にて前記チャネル層を取り囲む位置に設けられる、請求項1に記載の半導体装置。 - 前記ゲート電極と前記バリア層との間には、絶縁層が設けられる、請求項1に記載の半導体装置。
- 前記ゲート電極と前記バリア層との間には、第2導電型の半導体層が設けられる、請求項1に記載の半導体装置。
- 前記バリア層の前記ゲート電極と接する一部または全部は、第2導電型の半導体層である、請求項1に記載の半導体装置。
- チャネル層は、第2導電型の半導体層である、請求項1に記載の半導体装置。
- 前記チャネル層の下方の前記第1コンタクト層には、容量低減領域が設けられる、請求項1に記載の半導体装置。
- 前記容量低減領域は、前記第1コンタクト層よりも誘電率が低い低誘電率領域である、請求項8に記載の半導体装置。
- 前記容量低減領域は、前記第1コンタクト層よりもキャリア密度が低い低キャリア領域である、請求項8に記載の半導体装置。
- 前記容量低減領域は、空乏層であり、
前記空乏層は、前記第1コンタクト層の内部に設けられた第2導電型の空乏化領域によって形成される、請求項8に記載の半導体装置。 - 基板と、
前記基板の上に設けられた第1導電型の第1コンタクト層と、
前記第1コンタクト層の上に設けられたチャネル層と、
前記チャネル層の側面に設けられ、前記チャネル層の側面との間でバリア層を挟持するゲート電極と、
前記チャネル層の上に設けられた第1導電型の第2コンタクト層と、
前記第1コンタクト層の上に設けられた第1電極と、
前記第2コンタクト層の上に設けられた第2電極と、
を備える半導体装置を含む、電子部品。 - 基板と、
前記基板の上に設けられた第1導電型の第1コンタクト層と、
前記第1コンタクト層の上に設けられたチャネル層と、
前記チャネル層の側面に設けられ、前記チャネル層の側面との間でバリア層を挟持するゲート電極と、
前記チャネル層の上に設けられた第1導電型の第2コンタクト層と、
前記第1コンタクト層の上に設けられた第1電極と、
前記第2コンタクト層の上に設けられた第2電極と、
を備える半導体装置を含む、電子機器。 - 基板の上に、第1導電型の第1コンタクト層をエピタキシャル成長させることと、
前記第1コンタクト層の上に、チャネル層をエピタキシャル成長させることと、
前記第1コンタクト層の上に、第1導電型の第2コンタクト層をエピタキシャル成長させることと、
前記チャネル層および前記第2コンタクト層を平面視にて島状にエッチングすることと、
前記第1コンタクト層および前記第2コンタクト層の上に、バリア層およびゲート電極材料層を順に形成することと、
前記ゲート電極材料層を異方性エッチングして、前記チャネル層の側面にゲート電極を形成することと、
前記第1コンタクト層および前記第2コンタクト層の上に、それぞれ第1電極および第2電極を形成することと、
を含む半導体装置の製造方法。
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EP3405979A1 (en) | 2018-11-28 |
CN108352408B (zh) | 2021-09-17 |
JP6693142B2 (ja) | 2020-05-13 |
TWI732813B (zh) | 2021-07-11 |
WO2017126428A1 (en) | 2017-07-27 |
CN108352408A (zh) | 2018-07-31 |
TW201737354A (zh) | 2017-10-16 |
US20190035922A1 (en) | 2019-01-31 |
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