JP2017126810A - Amplifier and image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve highly accurate amplification with low power consumption.SOLUTION: An amplifier according to an embodiment of the present invention comprises a first capacitance, a second capacitance, a first switch, a current source, a second switch, a control voltage supply part, and a comparator. The first capacitance has one end connected with a first terminal supplied with a first power supply voltage. The second capacitance has one end connected with the other end of the first capacitance. The first switch connects a connection node between the first and second capacitances with a second terminal supplied with a second power supply voltage. The current source has one end connected with a third terminal supplied with a third power supply voltage. The second switch connects between the other end of the current source and the other end of the second capacitance. The output terminal is connected with the other end of the second capacitance. The control voltage supply part supplies a control voltage to the output terminal. The comparator controls the second switch depending on a difference between a voltage at the connection node and an input signal.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to an amplifier and an image sensor.

と表わされる。Ａはオペアンプの利得、Ｖｉｎはこの回路への入力電圧、Ｖｏｕｔは回路の出力電圧である。この式から分かるように、この回路の利得は、容量Ｃ_１とＣ_２の比によって決定され、またオペアンプの利得Ａに依存する。高精度で増幅する場合には、高い利得が必要になり、消費電力が高くなる問題がある。 Conventionally, operational amplifier-based amplifiers have been widely used. For example connect one capacitor C ₁ to the input terminal of the operational amplifier, the output of the operational amplifier, the circuit is negatively fed back via the capacitor C ₂ are known to the input terminal of the one. The other input terminal of the operational amplifier is connected to a power supply voltage such as a ground voltage. The input / output characteristics of this circuit are

It is expressed as A is the gain of the operational amplifier, Vin is the input voltage to this circuit, and Vout is the output voltage of the circuit. As can be seen from this equation, the gain of this circuit is determined by the ratio of the capacitors C ₁ and C ₂ and also depends on the gain A of the operational amplifier. In the case of amplifying with high accuracy, a high gain is required, and there is a problem that power consumption increases.

  As another amplifier mounting method, a comparator based switched capacitor (CBSC) amplifier is known. This CBSC amplifier also has a problem that it is difficult to amplify with high accuracy because the output voltage of the amplifier overshoots due to the delay characteristic of the comparator.

JP 2006-025246 A

J. K. Fiorenza, et al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies”, IEEE JSSC, vol. 41, no. 12, December 2006

  An object of the present invention is to realize high-precision amplification with low power consumption.

  An amplifier according to an embodiment of the present invention includes a first capacitor, a second capacitor, a first switch, a current source, a second switch, a control voltage supply unit, and a comparator. One end of the first capacitor is connected to a first terminal to which a first power supply voltage is applied. One end of the second capacitor is connected to the other end of the first capacitor. The first switch connects a connection node between the first and second capacitors to a second terminal to which a second power supply voltage is applied. One end of the current source is connected to a third terminal to which a third power supply voltage is applied. The second switch connects the other end of the current source and the other end of the second capacitor. The output terminal is connected to the other end of the second capacitor. The control voltage supply unit supplies a control voltage to the output terminal. The comparator controls the second switch according to a voltage of the connection node, an input signal, and a difference.

1 is a circuit diagram of an amplifier according to a first embodiment. 4 is a timing chart of the operation of the amplifier according to the first embodiment. The circuit diagram of the amplifier which concerns on 2nd Embodiment. 6 is a timing chart of the operation of the amplifier according to the second embodiment. The block diagram of the image sensor provided with the amplifier which concerns on 3rd Embodiment. The timing chart of the operation of the amplifier concerning a 3rd embodiment. The circuit diagram of the amplifier which concerns on 4th Embodiment. The circuit diagram of the amplifier which concerns on 5th Embodiment. Explanatory drawing of DC offset which concerns on 5th Embodiment. FIG. 10 is a circuit diagram of an amplifier according to a sixth embodiment. The block diagram of the image sensor provided with the amplifier which concerns on 7th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram of an amplifier according to the first embodiment. 1 includes a comparator (comparator) 100, a capacitor C _CP1 and a capacitor C _CP2 , switches 105 and 106, a current source 108, a control voltage supply circuit 110, a power supply terminal V _CM , a power supply terminal V _REF , and a power supply terminal GND. Is provided. The control voltage supply circuit 110 includes a control voltage generator 109 and a switch 107.

The comparator 100 has two input terminals 101 and 102. An input voltage V _PIX to be amplified is applied to the input terminal 101. As an example, this input voltage is a DC voltage. On the other hand, the input terminal 102 is connected to the connection node 104 between the capacitor C _CP1 and the capacitor C _CP2, and the V _FB voltage of the connection node 104 is applied. The comparator 100 controls the switch 107 by comparing the voltages input to the input terminals 101 and 102 and outputting a voltage corresponding to the difference. For example, when the voltage input to the input terminal 102 is larger than the voltage input to the input terminal 101, a high level (or low level) voltage is output, the switch 107 is turned on, and the input terminal 102 is turned on. When the input voltage is equal to or lower than the voltage input to the input terminal 101, a low level (or high level) voltage is output and the switch 107 is turned off. As an example of the comparator 100, an operational amplifier can be used. However, any element or circuit can be used as long as it is an element or circuit that compares two input voltages and outputs a voltage according to the difference between the two input voltages.

One end of the capacitor C _CP1 and one end of the capacitor C _CP2 are connected to each other, and this connection portion forms the connection node 104. Connection node 104 via a switch 105, a power supply terminal _{V CM,} is connected. The power supply terminal _{V CM,} the power supply voltage _{V CM} is given. Incidentally, the capacitance of the capacitor _{C CP1} and the capacitor _{C CP2,} represented by _{C CP1} and _{C CP2,} respectively.

One end of the switch 105 is connected to the connection node 104, the other end of the switch 105 is connected to a power supply terminal _{V CM.} The switch 105 can be composed of any switching element such as a MOS transistor or a bipolar transistor.

One end of the capacitor C _CP2 is connected to the connection node 104, and the other end of the capacitor C _CP2 is connected to the power supply terminal _VREF . A power supply voltage _VREF is applied to the power supply terminal _VREF . Supply voltage V _REF is _the same voltage as the power supply voltage V _CM, may be, for example, the voltage generated by the same voltage source.

One end of the capacitor C _CP1 is connected to the connection node 104, and the other end of the capacitor C _CP1 is connected to the output terminal V _SIG . The other end of the capacitor _CCP1 is connected to the switch 106 in parallel with the output terminal V _SIG . The voltage amplified by this amplifier is output from the output terminal V _SIG .

One end of the switch 106 is connected to the other end of the capacitor _{CP1, and} the other end of the switch 106 is connected to the current source 108. The switch 106 can be composed of any switching element such as a MOS transistor or a bipolar transistor.

  One end of the current source 108 is connected to the other end of the switch 106, and the other end of the current source 108 is connected to the power supply terminal GND. A predetermined power supply voltage GND (for example, ground voltage) is applied to the power supply terminal GND.

The output terminal V _SIG is connected to the control voltage supply circuit 110. The control voltage supply circuit 110 includes a control voltage generator 109 that generates a predetermined control voltage and a switch 107, and controls the switch 107 to control the supply of the control voltage to the output terminal V _SIG . One end of the switch 107 is connected to the output terminal V _SIG, and the other end of the switch 107 is connected to the control voltage generator 109. The switch 107 can be composed of any switching element such as a MOS transistor or a bipolar transistor. The switch 107 may be disposed inside the control voltage generator 109. The predetermined control voltage generated by the control voltage generator 109 is a voltage (V _CM + V _CTRL ) obtained by adding a predetermined voltage V _CTRL to the voltage V _CM of the power supply terminal V _CM .

  The switches 105 and 107 are turned on or off according to a control signal given from the outside. The control signal supplied from the outside has a high level or low level voltage, and the switches 105 and 107 are turned on and off depending on whether the control signal is high level or low level. It is turned on when it is high, turned off when it is low, or vice versa. The switch 106 is turned on or off according to the output of the comparator 100. For example, the output of the comparator 100 is turned on when the output is high, and turned off when the output is low. Alternatively, the reverse operation may be performed. Note that, similarly to the switches 105 and 107, the switch 106 may be controlled to be turned on / off according to a control signal given from the outside.

  Hereinafter, the outline of the operation of the present amplifier will be described, and then the detailed operation will be described using the timing chart of FIG.

As an operation of this amplifier, the fixed period P1 and the switches 105, 106, and 107 before the start of the amplification operation are turned on. At this time, the control voltage from the control voltage generator 109 _{(V CM +} V _CTRL) is, is given to the output terminal _{V SIG,} the voltage _{V SIG} output terminal _{V SIG is} a _{V CM +} V _CTRL. The voltage at the connection node 104, the connection node 104, from being connected to the power supply terminal _{V CM} via the switch _105, a _{V CM.} Therefore, the power supply voltage V _REF and the power supply voltage V _CM are applied to both ends of the capacitor C _CP2 , and the power supply voltage V _CM and the control voltage V _CM + V _CTRL are applied to both ends of the capacitor C _CP1 . Thereby, electric charge is charged in each capacitor.

The voltage V _FB of the connection node 104 is input to the input terminal 102 of the comparator 100. The voltage (DC voltage to be amplified) V _PIX input to the input terminal 101 is set in the range of the voltage V _CM or less. The comparator 100 turns on the switch 106 when the voltage V _FB input to the input terminal 102 is larger than the voltage V _PIX input to the input terminal 101 (V _CM > V _PIX ). When the input voltage V _{FB at the} input terminal 102 becomes equal to or lower than the input voltage V _{PIX at} one input terminal 101 (V _CM ≦ V _PIX ), the switch 106 is turned off. Here, since V _FB (= V _CM )> V _PIX , the switch 106 is on. As described above, the phase in which the switches 105, 106, and 107 are turned on and the capacitors are charged before the amplification operation is started is referred to as an initial phase.

By turning off the switches 105 and 107 at a certain time (time T1) by an external control signal, the phase shifts to the amplification phase. At this time, the current source I _CP forms a current path from the power supply voltage V _REF to the power supply voltage GND via the capacitors C _CP1 and C _CP2 . That is, the electric current is extracted from the capacitors C _CP1 and C _CP2 by the current source I _CP . Thus, the voltage _{V FB} at the connection node 104 is decreased at a certain inclination _{SR VFB} voltage _{V SIG} output terminal _{V SIG} also decreases at another certain inclination _{SR VSIG.} Such a graph of voltage decreasing at a certain slope is also called a ramp wave. The slope SR _VFB of the voltage V _FB of the connection node 104 and the slope SR _VSIG of the voltage V _SIG of the output terminal V _SIG are determined as follows according to the capacitance C _CP1 and the capacitance C _CP2 .

The slope SR _VSIG of the voltage V _SIG of the output terminal V _SIG is expressed by Expression (1).

Here, “C _CP1 // C _CP2 ” represents the combined capacitance of the capacitors C _CP1 and C _CP2 . Since the capacitors C _CP1 and C _CP2 are connected in series, the combined capacitance is (C _CP1 × C _CP2 ) / (C _CP1 + C _CP2 ).

The slope SRV _FB of the voltage V _FB of the connection node 104 is expressed by Expression (2) by capacity division.

となった段階で、スイッチ１０６がオフになる。スイッチ１０６がオフになったときの電圧Ｖ_ＳＩＧが、容量Ｃ_ＣＰ１、Ｃ_ＣＰ２によって保持され、この電圧が、出力端子Ｖ_ＳＩＧから増幅電圧として出力される。 When the voltage V _FB of the input terminal 102 becomes equal to or lower than the voltage V _PIX of the input terminal 101, the output of the comparator 100 is inverted, and at this time, the switch 106 is turned off. Specifically,

At this stage, the switch 106 is turned off. The voltage V _SIG when the switch 106 is turned off is held by the capacitors C _CP1 and C _CP2 , and this voltage is output as an amplified voltage from the output terminal V _SIG .

That is, the input voltage V _PIX is amplified by the amplification factor M and output from the output terminal V _SIG . It can be seen from the equations (3) and (4) that the amplification factor M of the comparator can be controlled based on the capacitances of the two capacitors C _CP1 and C _CP2 .

Here, consider the case where the comparator 100 is an ideal comparator with no delay. In an ideal comparator, when the input voltage V _PIX matches (or falls below) the voltage V _FB , the output of the comparator is inverted and the switch 106 is turned off.

However, there is a delay in the comparator from when the input voltage V _PIX and the voltage V _FB coincide and the magnitude relationship is reversed until it is actually reflected as the output of the comparator. Therefore, when this delay time is expressed as t _CMP , the output of the comparator 100 is actually inverted after the delay time t _{CMP has} elapsed from the time when the input voltage V _PIX matches the voltage V _FB (time T2). (For example, the output of the comparator changes from high level to low level). Because of this delay time _{t CMP,} the voltage _{V FB} at the input terminal 102, even after the match with the voltage _{V PIX,} only voltage _{V ofs,} which is also the voltage _{V PIX,} extra overshoot. As a result, the output voltage V _SIG also overshoots by a certain voltage (referred to as overshoot voltage V _OS ) as compared with an ideal comparator.

The overshoot voltage V _{OS with} respect to the output voltage V _SIG described above is expressed by the following equation (5).

From equation (5), the overshoot voltage V _{OS with} respect to the output voltage V _SIG increases as SR _VSIG (V _SIG slew rate) or SR _VFB (V _FB slew rate) increases and the delay time t _CMP increases. ,growing. In the present embodiment, the overshoot voltage V _OS with respect to the output voltage V _SIG is devised to cancel by adjusting the control voltage generated by the control voltage generator 109.

More specifically, in the present embodiment, the output voltage V _SIG after the output inversion of the comparator 100 (after the switch 106 is turned off) is expressed by Expression (6) in consideration of the delay of the comparator 100. In Expression (6), V _ofs represents a voltage corresponding to the voltage V _FB at the input terminal 102 that is excessively lower than the voltage V _PIX (the amount of overshoot) as described above. As described above, V _CTRL is a voltage that is added to V _CM in the control voltage V _CM + V _CTRL generated by the control voltage generator 109.

Therefore, the overshoot voltage with respect to the output voltage V _SIG can be arbitrarily controlled by controlling the control voltage (V _CM + V _CTRL ) given to the output terminal V _SIG .

となり、出力電圧Ｖ_ＳＩＧに対するオーバーシュート電圧が、キャンセルされる。よって、制御電圧生成器１０９により、Ｖ_ＣＴＲＬ ＝ Ｍ・Ｖ_ｏｆｓとなるように調整した制御電圧（Ｖ_ＣＭ＋Ｖ_ＣＴＲＬ）を生成することで、遅延時間を考慮しつつ、入力電圧Ｖ_ＰＩＸを高精度に増幅できる。なお、増幅率Ｍの値は任意でよく、１以上の値でもよいし、１未満の値でもよい。 From the equation (6), if the control voltage (V _CM + V _CTRL ) is adjusted so that V _CTRL = M · V _ofs ,

Thus, the overshoot voltage with respect to the output voltage V _SIG is canceled. Therefore, the control voltage generator 109 generates the control voltage (V _CM + V _CTRL ) adjusted so as to satisfy V _CTRL = M · V _ofs, and thus the input voltage V _PIX is highly accurate while considering the delay time. Can be amplified. Note that the value of the amplification factor M is arbitrary and may be 1 or more, or may be a value less than 1.

FIG. 2 is a timing chart of the operation of the amplifier of FIG. The horizontal direction along the paper corresponds to the time axis. A graph of each voltage V _FB , V _CM , V _SIG , V _PIX is shown. Note that these graphs, as the reference voltage V _CM, depicted in a position corresponding to the distance (difference) from the voltage.

In the following description, with the amplification factor M = 2, a voltage (2 × V _PIX ) that is twice the input voltage V _PIX is obtained as the output voltage V _SIG (more precisely, the difference from V _CM is V _PIX Is obtained).

W1 is a graph of the voltage _{V FB} at the connection node 104 (the voltage _{V FB} inputted to the input terminal 102), W2 represents a graph of the voltage at the output terminal _{V SIG.} In the first initial phase, the switches 105, 106, and 107 are on, the voltage V _{FB at} the input terminal 102 matches V _CM , and the voltage at the output terminal V _SIG matches V _CM + V _CTRL . Also, V _CTRL = M · V _ofs is set. An input voltage V _PIX to be amplified is applied to the input terminal 101 of the comparator 100.

At time T1, when the switches 105 and 107 are turned off by an external control signal, the phase shifts to the amplification phase. At this time, as shown in the graph W1, the voltage V _FB decreases with the above-described slope SRV _FB , and the input voltage V _PIX and the voltage V _FB of the input terminal 102 match at time T2. Due to the delay of the comparator 100, the output of the comparator 100 is not inverted at this time, and at time T3 after the delay time t _CMP , the output of the comparator 100 is inverted and the switch 106 is turned off. At this time, the voltage V _{FB at the} input terminal 102 overshoots the input voltage V _PIX by the voltage V _ofs .

Next, the graph W2 will be described. During the initial phase, the voltage at the output terminal V _SIG is V _CM + V _CTRL . When the switches 105 and 107 are turned off at time T1, the output voltage V _SIG decreases with the slope SR _VSIG . The output of the comparator 100 is inverted at time T3 after the delay time t _CMP after the input voltage V _PIX and the voltage V _FB of the input terminal 102 match at time T2. As a result, the switch 106 is turned off, and the output voltage V _SIG is held by the charges of the capacitors C _CP1 and C _CP2 at this time. The value of the output voltage _{V SIG} is from equation _{(6) M (V PIX +} V ofs) -V CTRL, since _{the V CTRL} is set to be _{V CTRL = M · V ofs,} 2 × V _PIX . Therefore, a voltage obtained by amplifying the input voltage with a desired amplification factor M (= 2) can be obtained regardless of the overshoot for the voltage V _ofs in the voltage V _FB of the input terminal 102.

Here, the output terminal of the comparison between the present embodiment, when the control voltage generated by the control voltage generator 109, and the same power supply voltage V _CM and the power supply terminal V _CM (i.e. case of a V _{CTRL = 0)} Is shown as a graph W3. In this case, during the initial phase, the voltage of V _SIG at the output terminal matches the power supply voltage V _CM . When the switches 105 and 107 are turned off at time T1, the output voltage V _SIG decreases with the slope SR _VSIG . At time T2, after the input voltage V _PIX and the voltage V _FB of the input terminal 102 coincide with each other, at time T3 after the delay time t _CMP , the output of the comparator 100 is inverted, whereby the switch 106 is turned off. . At this time, the output voltage V _SIG is higher than the voltage (2 × V _PIX ) obtained by amplifying the input voltage V _PIX with a desired amplification factor M (= 2) by an overshoot voltage Vos (= M · V _ofs ). Shoot. The graph W2 of the present embodiment described above is V _CTRL = M · V _ofs , which is the same as the graph W3 for comparison raised by V _CTRL . That is, in this embodiment, the output terminal V _SIG, to provide a voltage obtained by adding the voltage of the overshoot voltage Vos min to V _CM during the initial phase, it is possible to cancel the overshoot of the output voltage V _SIG.

As described above, according to the present embodiment, the overshoot voltage generated due to the delay of the comparator 100 can be prevented by controlling the voltage applied to the output terminal V _SIG in the initial phase. Therefore, it is possible to amplify the input voltage with high accuracy and low power consumption in consideration of the delay time of the comparator.

(Second Embodiment)
FIG. 3 is a circuit diagram of an amplifier according to the second embodiment. The difference from the amplifier of the first embodiment shown in FIG. 1 is that the control voltage supply circuit 110 (the control voltage generator 109 and the switch 107) is removed, and the control voltage supply circuit 210 having a different configuration from this is The switch 111 is added. The output terminal _{V SIG} is connected to one end of the switch 105 is connected to the power supply terminal _{V CM} via the switch 105. The control voltage supply circuit 210 includes switches 201, 202, 203, and 204. Note that the switch 106 of FIG. 1 is shown here as an example embodied as an NMOS transistor 206. The switches 201, 202, 203, and 204 can be composed of arbitrary switching elements such as MOS transistors and bipolar transistors. The switch 111 operates in response to an external control signal and operates in synchronization with the switch 105 so that the switch 111 is on when the switch 105 is on and off when the switch 105 is off.

The switches 201, 202, 203, and 204 have a role of switching the connection relationship between both ends of the capacitor _CP1 , the connection node 104, and the output terminal V _SIG . The switches 201, 202, 203, and 204 are turned on or off according to a control signal given from the outside. When the switches 201 and 202 are on and the switches 203 and 204 are off, one end of the capacitor _CCP1 is connected to the connection node 104 and the other end is connected to the output terminal V _SIG . On the other hand, when the switches 201 and 202 are off and the switches 203 and 204 are on, one end of the capacitor _CP1 is connected to the output terminal V _SIG and the other end is connected to the connection node 104. These switches 201, 202, 203, 204 invert the polarity of the capacitor C _CP1 by reversing the connection relationship between both ends of the capacitor C _CP1 and the connection node 104 and the output terminal V _SIG. Can be applied to the output terminal V _SIG as a control voltage.

In the first embodiment, the output terminal _{V SIG} during the initial phase, the control voltage applied to _{(V CM + V CTRL),} this _time, by adjusting the _{V CTRL} such that V CTRL = M _{· V ofs,} over Canceled the shoot voltage. In the present embodiment, the voltage applied to the output terminal V _SIG at the initial phase is V _CM, and a part of the overshoot voltage is canceled by inverting the polarity of the capacitor CC ₁ at the start of the amplification operation.

FIG. 4 is a timing chart of the operation of the amplifier of FIG. The horizontal direction along the paper corresponds to the time axis. A graph of each voltage V _FB , V _CM , V _SIG , V _PIX is shown.

First, in the initial phase, the switches 105 and 206 and the switches 201 and 202 are turned on and the switches 203 and 204 are turned off by an external control signal. An initial voltage V _ini is applied to the input terminal 101 of the comparator 100. This initial voltage to match the voltage _{V CM.}

Under this state, at time T11, the switch 105 (and the switch 111) is turned off to shift to the overshoot voltage extraction phase. After the transition to the extraction phase, the voltage _{V SIG} of the voltage _{V FB} and output terminal _{V SIG} of the connection node 104, according to the capacity _{C CP1} and the capacitor _{C CP2,} respectively, decreased in a certain inclination, from the time T11 of the comparator 100 At time T12 after the delay time has elapsed, the output of the comparator 100 is inverted and the switch 206 is turned off. Note that a control signal for turning off the switch 206 may be given after the delay time of the comparator 100 has elapsed from time T11. Since the initial voltage V _ini that matches V _CM is applied to the input terminal 101, the overshoot voltage V _OS can be extracted as the charges accumulated in the capacitors C _CP1 and C _CP2 . The voltage of the output terminal V _SIG at the time T12 is decreased by the overshoot voltage V _OS from the time T11, and the voltage V _FB of the connection node 104 is decreased by V _ofs (= V _OS / M).

At time T13 after a certain time from time T12, the switches 201 and 202 are turned off and the switches 203 and 204 are turned on, thereby inverting the polarity of the capacitor _CC1 . As a result, the voltage of the output terminal V _SIG is increased by the voltage across the capacitor _CCP1 . Thereafter, a desired input voltage _VPIX to be amplified is applied to the input terminal 101 of the comparator 100, and at time T14, the switch 206 is turned on by an external control signal.

The voltage of the connection node (the voltage of the input terminal 102) V _FB and the voltage V _SIG of the output terminal V _SIG decrease with a certain slope according to the capacitance C _CP1 and the capacitance C _CP2 , respectively. At time T15, after the input voltage V _PIX and the voltage V _FB of the input terminal 102 coincide with each other, at time T16 after the delay time t _CMP , the output of the comparator 100 is inverted and the switch 206 is turned off. At this time, the electric charge held in the capacitor _{C CP1} and the capacitor _{C CP2,} the voltage _{V SIG} output terminal _{V SIG} is fixed.

となる。よって、出力端子Ｖ_ＳＩＧに対するオーバーシュート電圧Ｖｏｓを、Ｖｏｓ／Ｍに抑制することができる。つまり、オーバーシュート電圧抽出フェーズで抽出したオーバーシュート電圧Ｖ_ＯＳの一部を、容量Ｃ_ＣＰ１の反転により、キャンセルすることができる。オフセット第１実施形態の図２のグラフＷ２の場合に比べて、Ｖｏｓ／Ｍだけ、オーバーシュートするが、比較例のグラフＷ３に比べれば、その１／Ｍに抑えることができる。 The value of the output voltage V _SIG at this time is

It becomes. Therefore, the overshoot voltage Vos with respect to the output terminal V _SIG can be suppressed to Vos / M. That is, a part of the overshoot voltage V _OS extracted in the overshoot voltage extraction phase can be canceled by inversion of the capacitor _CCP1 . Compared to the case of the graph W2 of FIG. 2 of the first embodiment of the offset, the overshoot is by Vos / M, but can be suppressed to 1 / M compared to the graph W3 of the comparative example.

(Third embodiment)
FIG. 5 shows a block diagram of a CMOS image sensor according to the third embodiment.

  A light receiving unit 301, an input control circuit 302, an amplifier (programmable gain amplifier) 303, an analog / digital (AD) converter 304, and a digital circuit 305 are provided. The amplifier 303 is an amplifier according to the first or second embodiment.

The light receiving unit 301 accumulates an amount of charge corresponding to the intensity of the received light, and outputs a voltage _VPIX corresponding to the accumulated amount of charge. The input control circuit 302 selects one of the output voltage of the light receiving unit 301 and a reset signal having a predetermined voltage according to a control signal supplied from the outside, and inputs the selected signal to the amplifier 303. Reset signal is the same voltage V _CM and the initial voltage of the second embodiment. This voltage corresponds to, for example, a signal representing black (a signal when no light is received by the light receiving unit). The input control circuit 302 may be provided inside the amplifier 303 and configured as a switch that selects any one of the above voltages.

The amplifier 303 amplifies the voltage input from the input control circuit 302 and outputs the amplified voltage to the AD converter 304. The AD converter 304 digitizes the voltage amplified by the amplifier 303 as digital data by AD conversion. The digital circuit 305 performs CDS (Correlated Double Sampling) processing that takes the difference between the digital data of the signal with the amplified voltage V _PIX and the digital data of the signal with the amplified reset signal. Thereby, the overshoot voltage generated in the amplifier 303 is more reliably reduced. In addition, the digital circuit 305 may perform arbitrary image processing such as color correction and noise cut on the digital data obtained by the CDS processing.

In a general CMOS image sensor, both a reset signal and an actual signal (input signal V _PIX ) are amplified by an amplifier, A / D converted, and the difference is obtained by CDS processing. Since the overshoot voltage generated in the amplifier hardly changes between the reset signal and the input signal, the overshoot voltage is canceled by performing the CDS process.

  However, particularly when the amplification factor in the amplifier is set high, the overshoot voltage becomes very large. As a result, the demand for the dynamic range of the AD converter connected to the subsequent stage of the amplifier becomes very high. In addition, the overdrive voltage of the current source in the amplifier cannot be secured, which causes analog distortion.

  As described in the first embodiment, the amplifier 303 according to this embodiment has a configuration that cancels the overshoot voltage. However, the overshoot voltage remains due to the effects of element matching and parasitic capacitance. There is also a possibility to do. Therefore, in this embodiment, after both the reset signal and the actual input signal are amplified by the amplifier 303, A / D conversion is performed by the AD converter 304, and further, the CDS processing is performed by the digital circuit 305 in the subsequent stage. Calculate and output the difference. Thereby, the overdrive voltage remaining in the amplifier 303 is surely canceled.

FIG. 6 shows a timing chart of the operation according to the present embodiment. The horizontal direction along the paper corresponds to the time axis. A graph of each voltage V _FB , V _CM , V _SIG , V _PIX is shown.

First, a reset sampling (RST sampling) phase is performed. In this phase, a reset signal (voltage V _CM ) is applied to the input terminal 101 of the comparator 100 in the amplifier 303, and the switches 105 and 107 are turned off at time T21. Thereafter, the same operation as in the first embodiment is performed. The amplified signal is a residual overshoot voltage Vos (ideally 0), which is digitized by a subsequent AD converter and input to the digital circuit 305.

Next, the process proceeds to a set sampling (SET sampling) phase. In this phase, first, at time T22, the switches 105, 106, and 107 are turned on to charge the capacitor C _CP1 and the capacitor C _CP2 . At time T23, the input signal voltage V _PIX is applied to the input terminal 101, and the switches 105 and 107 are turned off. Thereafter, the same operation as in the first embodiment is performed. The amplified signal is a voltage (M · V _PIX + Vos) obtained by adding the M · V _PIX obtained by amplifying the input voltage V _PIX and the residual overshoot voltage Vos. This voltage is digitized by a subsequent AD converter 304, and digital data is input to the digital circuit 305.

The digital circuit 305 cancels the overdrive voltage by subtracting the digital data input in the reset sampling phase from the digital data input in the SET sampling phase. That is, (M · V _PIX + Vos) −Vos = M · V _PIX is obtained, and voltage data obtained by amplifying the actual input signal V _PIX with a desired amplification factor M is obtained.

(Fourth embodiment)
FIG. 7 shows a block diagram of an amplifier according to the fourth embodiment. Unlike the first embodiment, the capacitances of the capacitors C _CP1 and C _CP2 are variable. Further, the current (bias current) I _{CP of the} current source 108 is variable. A gain control circuit 401 is added, and the gain control circuit 401 controls the capacitances of the capacitors C _CP1 and C _CP2 and the current I _CP of the current source 108 in accordance with an instruction signal supplied from the terminal 402. The instruction signal may be, for example, a signal that specifies the amplification factor M of the amplifier, or a signal that specifies the capacitances of the capacitors C _CP1 and C _CP2 and the value of the current I _CP of the current source 108. When the amplification factor M is designated, the capacitances of the capacitors C _CP1 and C _CP2 and the current I _CP of the current source 108 are controlled according to the amplification factor M. For example the amplification factor _M, and C _{CP1, C CP2,} according to the table associates the _{I CP,} may be controlled these values, the value of the amplification factor _M, and C _CP1, C _{CP2, I CP} You may control based on the function to calculate, respectively.

By controlling C _CP1 , C _CP2 , and I _CP in this manner, the amount of overshoot can be suppressed regardless of the amplification factor (gain). This will be described in detail below.

となる。オーバーシュート電圧は、バイアス電流と，各容量のキャパシタンスの両方によって決定される。一方、増幅率Ｍは、第１の実施形態の式（４）に示したように、

で表わされ、容量Ｃ_ＣＰ１とＣ_ＣＰ２を調整することで、利得Ｍを調整できる。 As shown in the equations (1) and (5) of the first embodiment, the overshoot voltage when the comparator is used is the bias current I _CP , the capacitors C _CP1 , C _CP2 , and the delay time t of the comparator. _{Using CMP} ,

It becomes. The overshoot voltage is determined by both the bias current and the capacitance of each capacitor. On the other hand, the amplification factor M, as shown in the equation (4) of the first embodiment,

The gain M can be adjusted by adjusting the capacitors C _CP1 and C _CP2 .

In this case, the value of the combined capacitance C _CP1 // C _CP2 changes according to the setting of the gain M, and the overshoot voltage also changes. For example, even if the overshoot voltage becomes a certain value (for example, 0) under a certain gain, if the capacitance of each capacitor is changed in order to change the amplification factor (gain), the overshoot voltage is also the value. The value deviates from. Therefore, in the present embodiment, at the time of gain adjustment, not only C _CP1 and C _CP2 but also I _CP is adjusted to suppress fluctuations in the overshoot voltage. For example, control is performed so that I _CP increases as the combined capacity C _CP1 // C _CP2 increases. As a result, the overshoot voltage can be suppressed to some extent regardless of the gain value.

(Fifth embodiment)
FIG. 8 shows a block diagram of an amplifier according to the fifth embodiment. A capacitor C _DCOC and a switch 501 are added to the amplifier of the first embodiment (see FIG. 1). One end of the switch 501 is connected to the output of the comparator 100, and the other end is connected to the input terminal 102 of the comparator 100. In addition, one end of the capacitor _CDOC is connected to the input terminal 102, and the other end is connected to the connection node 104. This amplifier extracts and corrects a comparator input conversion DC (Direct Current) offset at the input terminal 102 of the comparator 100 before starting the operation of the first embodiment, and thereafter, similarly to the first embodiment. Perform the operation.

と表わされる。よって、増幅器の出力は、ＤＣオフセット電圧Ｖｏｆｓの影響を受ける。これは、特に増幅率が高い時に顕著となる。そこで、本実施形態は、第１の実施形態の動作の開始前に、コンパレータのＤＣオフセットの抽出およびキャンセルを行うことで、この問題を解決する。 The amplifier as shown in the first embodiment is easily affected by the comparator input conversion DC offset. For example, when the DC offset of Vofs is input to the input terminal 102 of the comparator, the output signal V _SIG is

It is expressed as Therefore, the output of the amplifier is affected by the DC offset voltage Vofs. This is particularly noticeable when the amplification factor is high. Therefore, this embodiment solves this problem by extracting and canceling the DC offset of the comparator before the operation of the first embodiment is started.

In the extraction of the DC offset, the switch 501 is turned on to connect the output of the comparator 100 and the input terminal 102, and charges corresponding to the DC offset voltage are accumulated in the capacitor _CDOCC . This is called a DC offset extraction phase. An operation image of this phase is shown in FIG. At this time, the voltage of the input terminal 101 and _{V CM,} switches 105, 106 and 107 while turning on, performs DC offset extraction. Thereafter, the process proceeds to the DC offset correction phase. In this phase, the DC offset is corrected (cancelled) by the electric charge accumulated in the capacitor _CDOC by turning off the switch 501. FIG. 10B shows an operation image of the offset correction phase. Thereafter, the same operation as in the first embodiment (see FIG. 2) is performed.

  Hereinafter, the principle of DC offset extraction and cancellation according to this embodiment will be described in more detail.

となる。ＶｉＰはコンパレータのプラス端子（ここでは入力端子１０１）の電圧を表す。 As shown in FIG. 9A, a DC offset / cancellation capacitor 505 (corresponding to the capacitor _CDOC ) is connected in front of the input terminal 102 of the comparator. First, in the DC offset extraction phase, the input terminal 102 of the comparator (such as an operational amplifier) and the output are short-circuited. At this time, since the output Vo of the comparator and the voltage of the input terminal 102 match, in the case of an ideal comparator having no offset,

It becomes. ViP represents the voltage of the plus terminal (here, input terminal 101) of the comparator.

となる。このため、ＤＣオフセットを抽出できる。上記のオフセットの抽出のとき、容量５０５の両端にはＶｏｆｓが蓄積されるため、コンパレータ（オペアンプ等）の入力端子１０２と出力間の短絡を解放することで、ＤＣオフセットをキャンセルした状態で動作させることができる。 On the other hand, if there is an offset Vofs,

It becomes. For this reason, DC offset can be extracted. Since Vofs is accumulated at both ends of the capacitor 505 at the time of the above-described offset extraction, the circuit is operated in a state where the DC offset is canceled by releasing the short circuit between the input terminal 102 and the output of the comparator (operational amplifier or the like). be able to.

(Sixth embodiment)
In the fifth embodiment, a new capacitor _CDOC is added to add a DC offset / cancellation function. However, in this embodiment, DC offset / cancellation is executed with a different configuration.

FIG. 10 shows a block diagram of an amplifier according to the sixth embodiment. A capacitor C _DCOC for DC offset cancellation shown in FIG. 8 is included in the capacitor C _CP2 . That is, in the present embodiment, the DC offset / cancellation capacitor _DCCOC in FIG. 8 is removed, one end of the switch 501 is connected to the output of the comparator 100, and the other end is connected to the connection node 104 and the input terminal 102. Yes.

When DC offset extraction phase turns on the switch 105,106,107,501, by inputting a power supply voltage _{V CM} as the input voltage _{V PIX,} storing the offset voltage _{V ofs} the capacitance _{C CP2.} With the voltage held, the switches 105, 107, and 501 are turned off to perform the same operation as in the first embodiment. As a result, it is possible to operate with the DC offset canceled.

According to this embodiment, an increase in area can be suppressed as compared with the fifth embodiment. _Further, it is possible to suppress a change in the gain of the amplifier due to the capacitance division due to the parasitic capacitance generated in the capacitor _CDOC .
(Seventh embodiment)
FIG. 11 is a block diagram illustrating an image sensor according to the seventh embodiment. This image sensor is a CMOS image sensor, and includes a pixel array 601, a row selection circuit 602, a readout circuit 603, and a control signal generation circuit 604. As described above, the image sensor may be configured to further include the digital circuit 305 shown in FIG.

The pixel array 601 includes a plurality of light receiving units 611 arranged in an array. The row selection circuit 602 selects a row of the light receiving unit 1 from which the voltage _VPIX is read. The readout circuit 603 amplifies the voltage _PIX output from each light receiving unit 1, converts the amplified signal into a digital signal, and outputs the digital signal. The readout circuit 603 includes a plurality of amplifiers 612 and a plurality of AD converters 613 provided for each column of the light receiving units 1. The amplifier 612 may be any of the embodiments described above. The control signal generation circuit 604 generates various control signals used by the amplifier 2 and the AD converter 3 and inputs them to the reading circuit 603. For example, the control signal generation circuit 604 has the function of the control voltage generator 109 in FIG. 1, the input control circuit 302 in FIG. 5, or the gain control circuit in FIG. The control signal generation circuit 604 generates a switch control signal shown in each embodiment.

In this image sensor, when the pixel array 601 is irradiated with light, the row selection circuit 602 selects a row of the pixel array 101, and the voltage V _PIX is output from the light receiving unit 1 of the selected row. The voltage V _PIX is input to the amplifier 612 provided in each column corresponding to the light receiving unit 611. The amplifier 612 outputs a voltage V _SIG obtained by amplifying the voltage V _PIX . The voltage V _SIG is input to an AD converter 613 provided in each column corresponding to the light receiving unit 611 and is digitally converted.

  Although the embodiment of the CMOS image sensor has been described above, the CCD image sensor can be similarly implemented using the amplifier of each embodiment.

  As described above, the amplifier 612 can perform high-accuracy amplification with low power consumption. Therefore, this image sensor can be realized as having a low power consumption and a highly accurate detection function.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

Claims (13)

A first capacitor having one end connected to a first terminal to which a first power supply voltage is applied;
A second capacitor having one end connected to the other end of the first capacitor;
A first switch connecting a connection node between the first and second capacitors to a second terminal to which a second power supply voltage is applied;
A current source having one end connected to a third terminal to which a third power supply voltage is applied;
A second switch connecting the other end of the current source and the other end of the second capacitor;
An output terminal connected to the other end of the second capacitor;
A control voltage supply unit for supplying a control voltage to the output terminal;
A comparator that controls the second switch according to a difference between an input signal and a voltage of the connection node;
With amplifier. The control voltage supply unit includes a control voltage generator that generates the control voltage and a third switch, and supplies the control voltage by switching on and off of the third switch. The amplifier described in 1. The amplifier according to claim 2, wherein the control voltage is a voltage determined based on the first power supply voltage and a voltage corresponding to an operation delay time of the comparator. An initial phase for supplying the control voltage to the output terminal in a state where the first switch is on and the second switch is on, and after the initial phase, the first switch is turned off and connected to the output terminal. The amplifier according to claim 2, further comprising: an amplification phase that performs amplification by stopping supply of the control voltage. The output terminal is connected to the second terminal via the first switch;
The control voltage supply unit includes a fourth switch, a fifth switch, a sixth switch, and a seventh switch,
One end of the fourth switch is connected to the other end of the first capacitor to form the connection node, and the other end of the fourth switch is connected to one end of the second capacitor,
One end of the fifth switch is connected to the other end of the second capacitor, and the other end of the fifth switch is connected to the second switch and the output terminal,
One end of the sixth switch is connected to the connection node, the other end of the sixth switch is connected to the other end of the second capacitor,
The amplifier according to claim 1, wherein one end of the seventh switch is connected to one end of the second capacitor, and the other end of the seventh switch is connected to the second switch and the output terminal. . The control voltage supply unit is configured to turn off the fourth switch and the fifth switch and turn on the sixth switch and the seventh switch while the first switch is off, so that the output The amplifier according to claim 5, wherein a voltage of the connection node is supplied to a terminal as the control voltage. The amplifier includes a first phase that receives an input of a predetermined voltage signal different from the input signal and operates based on the predetermined voltage signal; and a first phase that operates based on the input signal; The amplifier according to any one of claims 1 to 6, wherein the first phase and the second phase are executed in this order or in the reverse order. The amplifier according to claim 7, wherein the predetermined voltage signal has the same voltage as the first power supply voltage. A terminal for receiving a gain adjustment signal for the amplifier, and a gain control circuit for controlling the first capacitor, the second capacitor, and the current source according to a gain control signal received at the terminal. Item 9. The amplifier according to any one of Items 1 to 8. A third capacitor and an eighth switch;
The comparator has a first input terminal that receives the input signal, and a second input terminal that receives the voltage of the connection node;
One end of the third capacitor is connected to the connection node, the other end of the third capacitor is connected to the second input terminal;
The amplifier according to any one of claims 1 to 9, wherein one end of the eighth switch is connected to the second input terminal, and the other end of the eighth switch is connected to an output of the comparator. . A ninth switch,
The comparator has a first input terminal that receives the input signal, and a second input terminal that receives the voltage of the connection node;
The one end of the ninth switch is connected to the second input terminal, and the other end of the ninth switch is connected to the output of the comparator. amplifier. A light receiving unit that outputs a signal corresponding to the received light;
The amplifier according to any one of claims 1 to 11, which receives an output signal of the light receiving unit as the input signal and amplifies the output signal;
An image sensor comprising: an analog / digital converter that performs analog / digital conversion on the signal amplified by the amplifier. A digital circuit for processing the digital signal converted by the analog-digital converter;
An amplifier according to claim 7,
The image sensor according to claim 12, wherein the digital circuit calculates a difference between a digital signal output from the amplifier in the first phase and a digital signal output from the amplifier in the second phase. .

Images