JP2017123893A - Transmission circuit for ultrasonic wave - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission circuit for an ultrasonic wave which suppresses excessive potential.SOLUTION: A transmission circuit 100 outputs a transmission signal with its amplitude changed step-wise. A plurality of output circuits (11P, 12P, 11N, 12N) controls a plurality of output timings of charges mutually different that correspond to the step-wise amplitude. The transmission circuit 100 is provided with a plurality of suppression circuits (21P, 22P, 21N, 22N) corresponding to the respective plurality of output circuits. The respective suppression circuits form a path of charges suppressing excessive potential of the output circuits between the respective output circuits corresponding to the suppression circuits and power supplies corresponding to the output circuits. Thus, the excessive potential beyond a target value of the potential can be suppressed each potential.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an ultrasonic transmission circuit, and more particularly to a transmission circuit that outputs a transmission signal whose amplitude is changed stepwise.

  An apparatus for transmitting an ultrasonic wave, for example, an ultrasonic diagnostic apparatus or an ultrasonic therapy apparatus, includes an ultrasonic transmission circuit. Conventionally, various ultrasonic transmission circuits have been proposed.

  For example, Patent Document 1 includes a pair of a P-channel MOSFET (MOS-type FET) and an N-channel MOSFET, and transmits a voltage output pulse having both upward and downward convex polarity to drive an ultrasonic transducer. A circuit is described.

  Further, by connecting a plurality of pairs of P-channel MOSFETs and N-channel MOSFETs, it is possible to form a waveform whose amplitude is changed stepwise. For example, Non-Patent Document 1 proposes a transmission circuit that outputs a transmission signal whose amplitude is changed stepwise by connecting two pairs of a P-channel MOSFET and an N-channel MOSFET. The transmission circuit described in Non-Patent Document 1 can be used for transmission of HIFU (High-Intensity Focused Ultrasound).

Japanese Patent No. 4946572

Keisuke Takada, Jumpei Okada, Kotaro Nakamura, Shin Yoshizawa, and Shin-ichiro Uemura, `` High Voltage Staircase Drive Circuit for Triggered High-Intensity Focused Ultrasound Treatment '', Japanese Journal of Applied Physics 51 (2012) 07GF23

  When a waveform whose amplitude is changed stepwise is formed by a switching circuit using a MOSFET or the like, for example, as described in FIG. 3 (FIG. 3) of Non-Patent Document 1, for example, at a change timing of a potential that becomes an amplitude. A spike-like excess potential is generated. The excessive potential destroys the waveform of the transmission signal, and further causes a rise in temperature of the MOSFET constituting the switching circuit and avalanche breakdown.

  The present invention has been made in view of such background circumstances, and an object thereof is to provide an ultrasonic transmission circuit that suppresses an excessive potential.

  An ultrasonic transmission circuit suitable for the above-described object is an ultrasonic transmission circuit that outputs a transmission signal whose amplitude is changed stepwise, and outputs a plurality of different potentials corresponding to the stepwise amplitude. An output control unit that controls timing and a potential suppression unit that suppresses an excess potential that exceeds a target value of each potential for each potential output from the output control unit.

  According to the above configuration, it is possible to suppress the excess potential for each potential for a plurality of different potentials corresponding to the stepped amplitude. Thereby, the waveform of the transmission signal whose amplitude is changed stepwise is arranged. Further, for example, when a transmission signal whose amplitude is changed stepwise is formed by a switching circuit using a MOSFET or the like, it is possible to suppress a temperature rise or avalanche breakdown of the MOSFET constituting the switching circuit.

  Incidentally, the transmission circuit can be used as a transmission circuit of a general ultrasonic diagnostic apparatus suitable for diagnosis by an ultrasonic image, and more powerful therapeutic ultrasonic waves than a general ultrasonic diagnostic apparatus, For example, it is also suitable as a transmission circuit of an ultrasonic therapy apparatus or an ultrasonic therapy system that transmits high intensity focused ultrasound (HIFU). If the transmission circuit is used in an ultrasonic medical apparatus including an ultrasonic diagnostic apparatus, an ultrasonic therapy apparatus, an ultrasonic therapy system, etc., the temperature rise of the vibration element as a load can be suppressed by the waveform of the transmission signal close to a sine wave. . As a result, for example, the energy efficiency for transmission is improved, and the amount of transmission energy input to the vibration element is increased.

  In a preferred embodiment, the output control unit controls the output timing of the plurality of potentials obtained from a power source, and the potential suppression unit is a charge that suppresses the excess potential between the output control unit and the power source. And the excess potential is suppressed.

  In a preferred embodiment, the output control unit includes 2N output circuits corresponding to 2N different potentials composed of N (N is a natural number) positive potentials and N negative potentials, and the potential suppression unit Comprises 2N suppression circuits corresponding to each of the 2N output circuits, each output circuit controls the output timing of each potential corresponding to each output circuit, and each suppression circuit includes The excess potential of each potential output from each output circuit corresponding to each suppression circuit is suppressed.

  In a preferred embodiment, each output circuit controls the output timing of each potential obtained from a power supply corresponding to each output circuit, and each suppression circuit includes each output circuit corresponding to each suppression circuit. A charge path that suppresses the excess potential of each output circuit is formed between the power supply corresponding to each output circuit.

  In addition, a preferable ultrasonic medical apparatus having the transmission circuit includes the 2N output circuits so that the output circuits that form a through current path between power supplies and the suppression circuits are not in a conductive state at the same time. It further has a control part which controls the operation timing of the 2N suppression circuits.

  According to the present invention, an ultrasonic transmission circuit for suppressing an excessive potential is provided. For example, according to a preferred aspect of the present invention, an excess potential can be suppressed for each potential with respect to a plurality of different potentials corresponding to stepped amplitudes.

1 is an overall configuration diagram of an ultrasonic transmission circuit suitable for implementing the present invention. FIG. It is a figure which shows the specific example of the positive electric potential side circuit with which the transmission circuit of FIG. 1 is provided. It is a figure which shows the specific example of the ground circuit with which the transmission circuit of FIG. 1 is provided. It is a figure which shows the specific example of the negative potential side circuit with which the transmission circuit of FIG. 1 is provided. It is a figure which shows the specific example of operation | movement of the transmission circuit of FIG. It is a figure which shows the specific example of an excess potential. It is a figure which shows the comparative example of the transmission signal which does not utilize a suppression circuit. It is a figure which shows the specific example of the transmission signal using a suppression circuit. It is a figure which shows the modification of a transmission circuit. It is a figure which shows the specific example of the positive electric potential side circuit with which the transmission circuit 100 of FIG. 9 is provided. It is a figure which shows the specific example of the negative potential side circuit with which the transmission circuit 100 of FIG. 9 is provided. It is a figure for demonstrating the relationship between the stage number N of a transmission power supply, and power consumption.

  FIG. 1 is an overall configuration diagram of an ultrasonic transmission circuit suitable for implementing the present invention. The ultrasonic transmission circuit 100 shown in FIG. 1 includes four output circuits, four suppression circuits, and two ground circuits. The transmission circuit 100 is connected to a power source that generates a plurality of different potentials, and uses each potential obtained from the power source to output an ultrasonic transmission signal whose amplitude is changed stepwise. The transmission circuit 100 outputs a transmission signal from the output terminal OP to drive the ultrasonic vibration element 30. When there are a plurality of vibration elements 30, the number of transmission circuits 100 is also plural. For example, one vibration element 30 is driven by one transmission circuit 100.

  FIG. 2 is a diagram illustrating a specific example of a positive potential side circuit included in the transmission circuit 100 (FIG. 1). FIG. 2 illustrates a specific circuit configuration example of the output circuit 12P, the suppression circuit 22N, the output circuit 11P, and the suppression circuit 21N.

  The output circuit 12P controls the timing at which the second positive potential obtained from the power supply is output to the output terminal OP (FIG. 1). The power supply generates a second positive potential of the target value + HV2, and the output timing is controlled according to a signal input from the input terminal 12P. The output circuit 12P includes a P-channel MOS FET (PMOS), an output separation diode D, a Zener diode (ZD) provided for protecting the gate of the PMOS, and a resistor R.

  The PMOS of the output circuit 12P is controlled according to a signal input from the input terminal 12P, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the PMOS of the output circuit 12P is turned off when the potential of the signal inputted from the input terminal 12P is + HV2, and turned on when + HV2-Vgs. Vgs is the gate-source potential of the PMOS of the output circuit 12P.

  Then, when the source and drain of the PMOS of the output circuit 12P is in the ON state, electric charges are supplied to the output terminal OP via the PMOS and the diode D from the power source that generates the second positive potential of the target value + HV2. As a result, the output terminal OP becomes the second positive potential, and the second positive potential is applied to the vibration element 30 (FIG. 1).

  The suppression circuit 22N suppresses an excessive potential (described in detail later) exceeding the target value + HV2 of the second positive potential output from the output circuit 12P. The suppression circuit 22N includes an N-channel MOS type FET (NMOS), an output separation diode D, a Zener diode (ZD) provided for NMOS gate protection, and a resistor R.

  The NMOS of the suppression circuit 22N is controlled according to a signal input from the input terminal 22N, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the NMOS of the suppression circuit 22N is turned on when the potential of the signal input from the input terminal 22N is + HV2 + Vgs, and is turned off when the potential is + HV2. Vgs is an NMOS gate-source potential of the suppression circuit 22N.

  When the source and drain of the NMOS of the suppression circuit 22N are in the ON state, the charge that causes an excessive potential output from the output circuit 12P to the output terminal OP (FIG. 1) is transmitted via the diode D and the NMOS of the suppression circuit 22N. Then, it is drawn into the power source that generates the second positive potential of the target value + HV2. As a result, the second positive potential output from the output circuit 12P is controlled to maintain the target value + HV2.

  The output circuit 11P controls the timing at which the first positive potential obtained from the power supply is output to the output terminal OP (FIG. 1). The power supply generates a first positive potential of the target value + HV1, and the output timing is controlled according to a signal input from the input terminal 11P. The output circuit 11P has the same circuit configuration as that of the output circuit 12P, and the PMOS of the output circuit 11P is controlled according to a signal input from the input terminal 11P, and an on state (conduction) and an off state between the source and drain are controlled. (Non-conduction) is changed. For example, the PMOS of the output circuit 11P is turned off when the potential of the signal input from the input terminal 11P is + HV1, and turned on when + HV1-Vgs. Vgs is the gate-source potential of the PMOS of the output circuit 11P.

  Then, when the source and drain of the PMOS of the output circuit 11P are in the ON state, electric charges are supplied to the output terminal OP from the power source that generates the first positive potential of the target value + HV1 through the PMOS and the diode D. As a result, the output terminal OP becomes the first positive potential, and the first positive potential is applied to the vibration element 30 (FIG. 1).

  The suppression circuit 21N suppresses an excessive potential (described in detail later) that exceeds the target value + HV1 of the first positive potential output from the output circuit 11P. The suppression circuit 21N has the same circuit configuration as the suppression circuit 22N, is controlled according to a signal input from the input terminal 21N, and changes an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the NMOS of the suppression circuit 21N is turned on when the potential of the signal input from the input terminal 21N is + HV1 + Vgs, and is turned off when + HV1. Vgs is the gate-source potential of the NMOS of the suppression circuit 21N.

  Then, when the source-drain of the NMOS of the suppression circuit 21N is in the ON state, the charge that causes an excessive potential output from the output circuit 11P to the output terminal OP (FIG. 1) is transmitted via the diode D and the NMOS of the suppression circuit 21N. Then, it is drawn into the power source that generates the first positive potential of the target value + HV1. Accordingly, the first positive potential output from the output circuit 11P is controlled to maintain the target value + HV1.

  FIG. 3 is a diagram illustrating a specific example of a ground circuit included in the transmission circuit 100 (FIG. 1). FIG. 3 shows a specific circuit configuration example of the two ground circuits GP and GN. The two ground circuits GP and GN, for example, fix (stabilize) the potential of the output terminal OP of the transmission circuit 100 to 0 V (zero volt) when no transmission signal is output from the transmission circuit 100 (FIG. 1). Also, unnecessary transmission signals can be reduced and preferably removed by the two ground circuits GP and GN.

  The ground circuit GP includes a P-channel MOS FET (PMOS), an output separating diode D, a Zener diode (ZD) provided for protecting the gate of the PMOS, and a resistor R. The PMOS of the ground circuit GP is controlled according to a signal input from the input terminal GP, and changes between an on state (conduction) and an off state (non-conduction) between the source and drain. For example, the PMOS of the ground circuit GP is turned off when the potential of the signal input from the input terminal GP is GND (grounded), and turned on when the potential of the ground circuit GP is GND-Vgs. Vgs is the gate-source potential of the PMOS of the ground circuit GP.

  Then, when the source and drain of the PMOS of the ground circuit GP is in an ON state, electric charges are supplied from the ground (GND) to the output terminal OP via the PMOS and the diode D. As a result, the output terminal OP is controlled so as not to have a negative potential.

  On the other hand, the ground circuit GN includes an N channel MOS type FET (NMOS), an output separating diode D, a Zener diode (ZD) provided for NMOS gate protection, and a resistor R. The NMOS of the ground circuit GN is controlled according to a signal input from the input terminal GN, and changes between an on state (conduction) and an off state (non-conduction) between the source and drain. For example, the NMOS of the ground circuit GN is turned on when the potential of the signal input from the input terminal GN is GND + Vgs, and is turned off when GND. Vgs is an NMOS gate-source potential of the ground circuit GN.

  When the source and drain of the NMOS of the ground circuit GN are in the ON state, the charge that causes the positive potential of the output terminal OP is drawn to the ground (GND) via the diode D and the NMOS of the ground circuit GN. Thereby, the output terminal OP is controlled so as not to become a positive potential.

  FIG. 4 is a diagram illustrating a specific example of a negative potential side circuit included in the transmission circuit 100 (FIG. 1). FIG. 4 shows a specific circuit configuration example of the output circuit 12N, the suppression circuit 22P, the output circuit 11N, and the suppression circuit 21P.

  The output circuit 12N controls the timing at which the second negative potential obtained from the power supply is output to the output terminal OP (FIG. 1). The power supply generates a second negative potential of the target value −HV2, and the output timing is controlled according to a signal input from the input terminal 12N. The output circuit 12N includes an N-channel MOS type FET (NMOS), an output separation diode D, a Zener diode (ZD) provided for NMOS gate protection, and a resistor R.

  The NMOS of the output circuit 12N is controlled according to a signal input from the input terminal 12N, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the NMOS of the output circuit 12N is turned on when the potential of the signal input from the input terminal 12N is −HV2 + Vgs, and is turned off when the potential is −HV2. Vgs is an NMOS gate-source potential of the output circuit 12N.

  Then, when the source and drain of the NMOS of the output circuit 12N are in the ON state, the charge at the output terminal OP is drawn to the power source that generates the second negative potential of the target value −HV2 via the diode D and the NMOS. As a result, the output terminal OP becomes the second negative potential, and the second negative potential is applied to the vibration element 30 (FIG. 1).

  The suppression circuit 22P suppresses an excessive potential (detailed later) that exceeds the absolute value of the target value −HV2 of the second negative potential output from the output circuit 12N. The suppression circuit 22P includes a P-channel MOS FET (PMOS), a diode D for output separation, a Zener diode (ZD) provided for protecting the gate of the PMOS, and a resistor R.

  The PMOS of the suppression circuit 22P is controlled according to a signal input from the input terminal 22P, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the PMOS of the suppression circuit 22P is turned off when the potential of the signal input from the input terminal 22P is -HV2, and is turned on when -HV2-Vgs. Vgs is a gate-source potential of the PMOS of the suppression circuit 22P.

  Then, when the source and drain of the PMOS of the suppression circuit 22P is in the ON state, electric power is supplied from the power source that generates the second negative potential of the target value −HV2 to the output terminal OP (FIG. 1) via the PMOS and the diode D. Is done. As a result, the second negative potential output from the output circuit 12N is controlled so as to maintain the target value -HV2.

  The output circuit 11N controls the timing at which the first negative potential obtained from the power supply is output to the output terminal OP (FIG. 1). The power supply generates a first negative potential of the target value -HV1, and the output timing is controlled according to a signal input from the input terminal 11N. The output circuit 11N has the same circuit configuration as that of the output circuit 12N, and the NMOS of the output circuit 11N is controlled according to a signal input from the input terminal 11N, and an on state (conduction) and an off state between the source and drain are controlled. (Non-conduction) is changed. For example, the NMOS of the output circuit 11N is turned on when the potential of the signal input from the input terminal 11N is −HV1 + Vgs, and turned off when the potential is −HV1. Vgs is an NMOS gate-source potential of the output circuit 11N.

  Then, when the source and drain of the NMOS of the output circuit 11N is in the ON state, the charge at the output terminal OP is drawn to the power source that generates the first negative potential of the target value −HV1 via the diode D and the NMOS. As a result, the output terminal OP becomes the first negative potential, and the first negative potential is applied to the vibration element 30 (FIG. 1).

  The suppression circuit 21P suppresses an excessive potential (detailed later) that exceeds the absolute value of the target value −HV1 of the first negative potential output from the output circuit 11N. The suppression circuit 21P has the same circuit configuration as that of the suppression circuit 22P, and is controlled according to a signal input from the input terminal 21P to change an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the PMOS of the suppression circuit 21P is turned off when the potential of the signal input from the input terminal 21P is -HV1, and is turned on when -HV1-Vgs. Vgs is the gate-source potential of the PMOS of the suppression circuit 21P.

  Then, when the source and drain of the PMOS of the suppression circuit 21P is in the ON state, electric power is supplied from the power source that generates the first negative potential of the target value −HV1 to the output terminal OP (FIG. 1) via the PMOS and the diode D. Is done. Thus, the first negative potential output from the output circuit 11N is controlled to maintain the target value -HV1.

  FIG. 5 is a diagram illustrating a specific example of the operation of the transmission circuit 100 (FIG. 1). FIG. 5 shows the drive timing of each circuit (FIGS. 2 to 4) constituting the transmission circuit 100, that is, the ON state (ON) and the OFF state (OFF) of the MOS FET (PMOS or NMOS) included in each circuit. A specific example of the control timing is shown. In the specific example shown in FIG. 5, the transmission circuit 100 outputs a transmission signal having a staircase transmission waveform that simulates an ideal sine wave (ideal sine wave) (transmission signal with amplitude changed in a staircase pattern).

  First, the drive timing of the four output circuits (11P, 12P, 11N, 12N) will be described. At time t0, all four output circuits are in the OFF state, and the amplitude of the stepped transmission waveform is GND (ground).

  At time t1, the output circuit 11P is turned on, the first positive potential (target value + HV1) is output from the output circuit 11P, and the amplitude of the stepped transmission waveform becomes the first positive potential (target value + HV1). Further, at time t2, the output circuit 12P is turned on, the second positive potential (target value + HV2) is output from the output circuit 12P, and the amplitude of the stepped transmission waveform becomes the second positive potential (target value + HV2).

  The output circuit 12P is turned on from time t2 to time t3. Thereby, in the period from the time t2 to the time t3, the amplitude of the stepped transmission waveform becomes the second positive potential. The output circuit 11P is turned on from time t1 to time t4. As a result, the amplitude of the stepped transmission waveform becomes the first positive potential in the period from time t1 to time t2 and in the period from time t3 to time t4. Note that since the second positive potential is output from the output circuit 12P during the period from the time t2 to the time t3, the output circuit 11P may be turned off.

  When the output circuit 11P is switched from the on-state to the off-state at time t4, the output circuit 11N is turned on immediately after time t5, and the first negative potential (target value −HV1) is output from the output circuit 11N. The amplitude of the stepped transmission waveform is the first negative potential (target value -HV1). Time t4 and time t5 are preferably determined so that the period between time t4 and time t5 is as short as possible so that output circuit 11P and output circuit 11N are not turned on simultaneously.

  Then, at time t6, the output circuit 12N is turned on, the second negative potential (target value -HV2) is output from the output circuit 12N, and the amplitude of the stepped transmission waveform becomes the second negative potential (target value -HV2). Become.

  The output circuit 12N is turned on from time t6 to time t7. Thereby, in the period from the time t6 to the time t7, the amplitude of the stepped transmission waveform becomes the second negative potential. Further, the output circuit 11N is turned on from time t5 to time t8. Thereby, in the period from time t5 to time t6 and the period from time t7 to time t8, the amplitude of the stepped transmission waveform becomes the first negative potential. Note that, during the period from time t6 to time t7, the output circuit 11N may be turned off because the second negative value is output from the output circuit 12N.

  When the output circuit 11N is switched from the on state to the off state at time t8, the output circuit 11P is turned on at time t9 immediately after that, and the first positive potential (target value + HV1) is output from the output circuit 11P, and the staircase The amplitude of the waveform transmission waveform becomes the first positive potential (target value + HV1). Time t8 and time t9 are preferably determined so that the period between time t8 and time t9 is as short as possible so that output circuit 11N and output circuit 11P are not turned on simultaneously.

  Then, in the period from time t9 to time t10, the same control as in the period from time t1 to time t8 is executed. After time t10, all four output circuits are turned off, and the amplitude of the stepped transmission waveform is GND ( Ground). As a result, in the specific example shown in FIG. 5, a transmission signal having a stepped transmission waveform corresponding to two periods of ideal sine waves is output.

  Although the driving timing of the four output circuits (11P, 12P, 11N, 12N) has been described, only the four output circuits are driven in the transmission circuit 100 (FIG. 1), and the four suppression circuits (21N, 22N, 21P, 22P) are driven. ) Is not driven, an excess potential exceeding the target potential value may be generated from each output circuit.

  FIG. 6 is a diagram illustrating a specific example of excess potential. FIG. 6 shows a transmission signal waveform in which the horizontal axis indicates time and the vertical axis indicates amplitude (potential). The waveform in FIG. 6 is a specific example when the four suppression circuits are not driven (when the four suppression circuits are not provided). It is a waveform illustrated in 3 (b).

  For example, a spike-like noise voltage (spike noise voltage) is output from each output circuit by a switching operation for switching between an off state (OFF) and an on state (ON) of a MOS FET (PMOS or NMOS) included in each output circuit. The Note that the noise voltage when transitioning from the on state to the off state may be referred to as a flyback voltage. If these noise voltages are output as they are from each output circuit, for example, as shown by an ellipse frame in FIG. 6, a transmission signal on which a noise voltage (spike noise voltage or flyback voltage) is superimposed is obtained. These noise voltages destroy the shape of the transmission signal waveform, and further cause a temperature rise and avalanche breakdown of the MOS type FET provided in each output circuit.

  Therefore, the four suppression circuits (21N, 22N, 21P, 22P) included in the transmission circuit 100 of FIG. 1 are excessive potentials (for example, spike noise voltages) output from the four output circuits (11P, 12P, 11N, 12N). Suppress.

  Returning to FIG. 5, the drive timing of the four suppression circuits (21N, 22N, 21P, 22P) will be described. The suppression circuit 22N suppresses an excess potential (for example, spike noise voltage) exceeding the target value + HV2 of the second positive potential output from the output circuit 12P. Therefore, the suppression circuit 22N is turned on during a period including the timing (for example, time t2 and time t3) when the output circuit 12P switches between the on state and the off state. In the specific example shown in FIG. 5, the suppression circuit 22N is turned on in the entire period from time t0.

  If the suppression circuit 22N is always turned on, the cathode terminal of the output separation diode D (see FIG. 2) included in the suppression circuit 22N is directly used as the power source of the second positive potential (target value + HV2). A connecting modified circuit configuration may be employed.

  The suppression circuit 21N suppresses an excess potential (for example, spike noise voltage) exceeding the target value + HV1 of the first positive potential output from the output circuit 11P. Therefore, the suppression circuit 21N is turned on in a period including the timing (for example, time t1 and time t4) when the output circuit 11P switches between the on state and the off state.

  However, the suppression circuit 21N is controlled so as not to be turned on simultaneously with the output circuit 12P. For example, as in the specific example shown in FIG. 5, the suppression circuit 21N is turned on from time t0, and is turned off immediately before time t2 when the output circuit 12P is turned on. The suppression circuit 21N is turned on immediately after time t3 when the output circuit 12P is turned off. As a result, control is achieved that does not cause a through current between the power supplies that flows from the second positive potential (target value + HV2) to the first positive potential (target value + HV1) through the output circuit 12P and the suppression circuit 21N.

  The suppression circuit 22P suppresses an excess potential (for example, spike noise voltage) exceeding the absolute value of the target value −HV2 of the second negative potential output from the output circuit 12N. Therefore, the suppression circuit 22P is turned on in a period including the timing (for example, time t6 and time t7) when the output circuit 12N switches between the on state and the off state. In the specific example shown in FIG. 5, the suppression circuit 22P is turned on in the entire period from time t0.

  If the suppression circuit 22P is always turned on, the anode terminal of the output separation diode D (see FIG. 4) included in the suppression circuit 22P is directly connected to the power source of the second negative potential (target value −HV2). A modified circuit configuration that connects to may be employed.

  The suppression circuit 21P suppresses an excess potential (for example, spike noise voltage) exceeding the absolute value of the target value −HV1 of the first negative potential output from the output circuit 11N. Therefore, the suppression circuit 21P is turned on during a period including the timing (for example, time t5 and time t8) when the output circuit 11N switches between the on state and the off state.

  However, the suppression circuit 21P is controlled so as not to be turned on simultaneously with the output circuit 12N. For example, as in the specific example shown in FIG. 5, the suppression circuit 21P is turned on from time t0, and is turned off immediately before time t6 when the output circuit 12N is turned on. Then, immediately after time t7 when the output circuit 12N is turned off, the suppression circuit 21P is turned on. As a result, control is achieved that does not cause a through current between the power supplies that flows from the first negative potential (target value −HV1) to the second negative potential (target value −HV2) through the suppression circuit 21P and the output circuit 12N.

  The two ground circuits GP and GN are turned on when no transmission signal having a stepped transmission waveform is output from the transmission circuit 100 (FIG. 1), and the amplitude of the transmission signal is stabilized to GND (ground). . Therefore, for example, as in the specific example shown in FIG. 5, the ground circuit GP and the ground circuit GN are turned on from time t0, and are turned off immediately before time t1 when the stepped transmission waveform is output. In addition, immediately after time t10 when the stepped transmission waveform ends, the ground circuit GP and the ground circuit GN are turned on.

  FIG. 7 is a diagram illustrating a comparative example of transmission signals that do not use the suppression circuit. FIG. 7 shows a specific example of a transmission signal obtained when the four suppression circuits are not driven in the transmission circuit 100 (FIG. 1) (when four suppression circuits are not provided).

  FIGS. 7A and 7B show waveforms of transmission signals having frequencies of 250 KHz (kilohertz) and 1 MHz (megahertz), respectively. In the comparative example of FIG. 7, the second positive potential target value + HV2 is + 20V (volts), the second negative potential target value -HV2 is -20V, the first positive potential target value + HV1 is + 7.9V, The target value -HV1 of 1 negative potential is -7.9V.

  In the comparative example of FIG. 7, the excess potential (for example, spike noise voltage) is not suppressed by the four suppression circuits. Therefore, in particular, in the transmission signal having the frequency of 250 KHz, the second positive potential target value + 20V and the second A high potential output (within the ellipse frame) exceeding −20 V, which is the target value of the negative potential, appears remarkably. In the comparative example of FIG. 7, the maximum temperature rise when the frequency was 1 MHz was +30.9 degrees Celsius, and the power consumption was 3.22 W.

  FIG. 8 is a diagram illustrating a specific example of a transmission signal using a suppression circuit. FIG. 8 shows a specific example of a transmission signal obtained when four suppression circuits are driven in the transmission circuit 100 (FIG. 1).

  FIGS. 8A and 8B show waveforms of transmission signals having frequencies of 250 KHz (kilohertz) and 1 MHz (megahertz), respectively. Also in the specific example of FIG. 8 as in the comparative example of FIG. 7, the second positive potential target value + HV2 is +20 V (volts), the second negative potential target value −HV2 is −20 V, and the first positive potential target. The value + HV1 is + 7.9V, and the target value -HV1 of the first negative potential is -7.9V.

  In the specific example of FIG. 8, the excess potential (for example, spike noise voltage) is suppressed by the four control circuits. Therefore, in particular, the target value of the second positive potential is +20 V and the target value of the second negative potential is − Almost no high potential output exceeding 20V is generated. Further, compared with the waveform of FIG. 7, the waveform of the specific example of FIG. 8 is shaped as a whole.

  In the specific example of FIG. 8, when the frequency is 1 MHz, the maximum temperature rise was +16.4 degrees Celsius and the power consumption was 2.36 W. Compared to the comparative example of FIG. 7, the maximum temperature rise in the specific example of FIG. 8 was 14.5 degrees Celsius lower (-14.5 degrees) and the power consumption was 73.3 percent.

  FIG. 9 is a diagram illustrating a modification of the transmission circuit 100. The transmission circuit 100 in FIG. 9 is connected to a power source that generates a plurality of different potentials, and uses each potential obtained from the power source to output an ultrasonic transmission signal with the amplitude changed stepwise. The transmission circuit 100 outputs a transmission signal from the output terminal OP to drive the ultrasonic vibration element 30. When there are a plurality of vibration elements 30, the number of transmission circuits 100 is also plural. For example, one vibration element 30 is driven by one transmission circuit 100.

  9, the second positive potential is output from the output circuit 12P, the first positive potential is output from the output circuit 11P, the second negative potential is output from the output circuit 12N, and the first negative potential is output from the output circuit 11N. Negative potential is output. In the transmission circuit 100 of FIG. 9, the second positive potential is larger than the first positive potential and the second negative potential is smaller than the first negative potential (the absolute value of the second negative potential is larger than the absolute value of the first negative potential). Is also used).

  FIG. 10 is a diagram illustrating a specific example of a positive potential side circuit included in the transmission circuit 100 (FIG. 9). FIG. 10 illustrates a specific circuit configuration example of the output circuit 12P, the output circuit 11P, and the suppression circuit 21N.

  The output circuit 12P controls the timing at which the second positive potential obtained from the power supply is output to the output terminal OP (FIG. 9). The power supply generates a second positive potential of the target value + HV2, and the output timing is controlled according to a signal input from the input terminal 12P. The output circuit 12P includes a P-channel MOS type FET (PMOS), a Zener diode (ZD) provided for protecting the gate of the PMOS, and a resistor R.

  The PMOS of the output circuit 12P is controlled according to a signal input from the input terminal 12P, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the PMOS of the output circuit 12P is turned off when the potential of the signal inputted from the input terminal 12P is + HV2, and turned on when + HV2-Vgs. Vgs is the gate-source potential of the PMOS of the output circuit 12P.

  Then, when the source and drain of the PMOS of the output circuit 12P are in the ON state, electric charges are supplied from the power source that generates the second positive potential of the target value + HV2 to the output terminal OP via the PMOS. As a result, the output terminal OP becomes the second positive potential, and the second positive potential is applied to the vibration element 30 (FIG. 9).

  The PMOS of the output circuit 12P in FIG. 10 includes a body diode (also referred to as a parasitic diode) between the drain terminal and the source terminal, and current flows from the drain terminal side to the source terminal side via the body diode. Then, the charge that causes the excessive potential output from the output circuit 12P to the output terminal OP is drawn into the power source that generates the second positive potential of the target value + HV2 through the body diode. As a result, the second positive potential output from the output circuit 12P is controlled to maintain the target value + HV2. That is, the body diode functions as the suppression circuit 22N (FIGS. 1 and 2). The body diode may be provided outside the PMOS.

  The output circuit 11P and the suppression circuit 21N in FIG. 10 have the same circuit configuration and the same function as the output circuit 11P and the suppression circuit 21N in FIG. That is, the output circuit 11P in FIG. 10 controls the timing at which the first positive potential obtained from the power supply is output to the output terminal OP (FIG. 9). The power supply generates a first positive potential of the target value + HV1, and the output timing is controlled according to a signal input from the input terminal 11P. Further, the suppression circuit 21N of FIG. 10 suppresses an excessive potential exceeding the target value + HV1 of the first positive potential output from the output circuit 11P. The suppression circuit 21N is controlled in accordance with a signal input from the input terminal 21N and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. Then, when the source and drain of the NMOS of the suppression circuit 21N are in the ON state, the charge that causes an excessive potential output from the output circuit 11P to the output terminal OP is set to the target value + HV1 via the diode D and the NMOS of the suppression circuit 21N. Of the first positive potential. Accordingly, the first positive potential output from the output circuit 11P is controlled to maintain the target value + HV1.

  FIG. 11 is a diagram illustrating a specific example of a negative potential side circuit included in the transmission circuit 100 (FIG. 9). FIG. 11 illustrates a specific circuit configuration example of the output circuit 12N, the output circuit 11N, and the suppression circuit 21P.

  The output circuit 12N controls the timing at which the second negative potential obtained from the power supply is output to the output terminal OP (FIG. 9). The power supply generates a second negative potential of the target value −HV2, and the output timing is controlled according to a signal input from the input terminal 12N. The output circuit 12N includes an N-channel MOS type FET (NMOS), a Zener diode (ZD) provided for protecting the gate of the NMOS, and a resistor R.

  The NMOS of the output circuit 12N is controlled according to a signal input from the input terminal 12N, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. For example, the NMOS of the output circuit 12N is turned on when the potential of the signal input from the input terminal 12N is −HV2 + Vgs, and is turned off when the potential is −HV2. Vgs is an NMOS gate-source potential of the output circuit 12N.

  Then, when the source and drain of the NMOS of the output circuit 12N is in the ON state, the charge at the output terminal OP is drawn into the power source that generates the second negative potential of the target value −HV2 through the NMOS. As a result, the output terminal OP becomes the second negative potential, and the second negative potential is applied to the vibration element 30 (FIG. 9).

  The NMOS of the output circuit 12N in FIG. 11 includes a body diode (also called a parasitic diode) between the source terminal and the drain terminal, and current flows from the source terminal side to the drain terminal side via the body diode. Therefore, charge can be supplied from the power supply that generates the second negative potential of the target value −HV2 to the output terminal OP via the body diode. As a result, the second negative potential output from the output circuit 12N is controlled so as to maintain the target value -HV2. That is, the body diode functions as the suppression circuit 22P (FIGS. 1 and 4). The body diode may be provided outside the NMOS.

  The output circuit 11N and the suppression circuit 21P in FIG. 11 have the same configuration and the same function as the output circuit 11N and the suppression circuit 21P in FIG. That is, the output circuit 11N of FIG. 11 controls the timing of outputting the first negative potential obtained from the power supply to the output terminal OP (FIG. 9). The power supply generates a first negative potential of the target value -HV1, and the output timing is controlled according to a signal input from the input terminal 11N. Further, the suppression circuit 21P of FIG. 11 suppresses an excessive potential exceeding the absolute value of the target value −HV1 of the first negative potential output from the output circuit 11N. The suppression circuit 21P is controlled according to a signal input from the input terminal 21P, and changes between an on state (conduction) and an off state (nonconduction) between the source and drain. Then, when the source and drain of the PMOS of the suppression circuit 21P is in the ON state, electric power is supplied from the power source that generates the first negative potential of the target value −HV1 to the output terminal OP via the PMOS and the diode D. Thus, the first negative potential output from the output circuit 11N is controlled to maintain the target value -HV1.

  The specific example (FIG. 10) of the positive potential side circuit included in the transmission circuit 100 of FIG. 9 and the specific example (FIG. 11) of the negative potential side circuit are as described above. A specific circuit configuration example of the two ground circuits GP and GN included in the transmission circuit 100 of FIG. 9 is the same as the specific example of FIG.

  9 operates according to the specific example of FIG. However, in the transmission circuit 100 of FIG. 9, the body diode (see FIG. 10) included in the PMOS of the output circuit 12P functions as the suppression circuit 22N, and the body diode (see FIG. 11) included in the NMOS of the output circuit 12N is the suppression circuit 22P. Function as. Therefore, in order to realize the operation of the transmission circuit 100 of FIG. 9 with the specific example of FIG. 5, the timing chart of the suppression circuit 22N and the suppression circuit 22P in FIG.

  The transmission circuit 100 (FIG. 1 or FIG. 9) detailed above can be used as a transmission circuit of a general ultrasonic diagnostic apparatus that forms a diagnostic ultrasonic image, for example. Further, the transmission circuit 100 may be provided in a device that transmits therapeutic ultrasonic waves stronger than a general ultrasonic diagnostic apparatus. For example, the transmission circuit 100 may be used in an ultrasonic therapy apparatus or an ultrasonic therapy system that transmits high intensity focused ultrasound (HIFU). In this case, it is desirable that the ultrasonic treatment apparatus and the ultrasonic treatment system include a transmission control unit that controls the transmission circuit 100 according to a specific example of the operation illustrated in FIG.

  When the transmission circuit 100 outputs a transmission signal of intense focused ultrasound (HIFU), for example, the second positive potential target value + HV2 is set to +125 to +250 V (volts), and the second negative potential target value is set. -HV2 is set to -125 to -250V, the first positive potential target value + HV1 is set to +50 to + 80V, and the first negative potential target value -HV1 is set to -50 to -80V. In the circuit configuration of the transmission circuit 100 described with reference to FIGS. 1 to 4, the target value of the potential can be set to + HV1> + HV2, −HV1 <−HV2. In the case of intense focused ultrasound (HIFU), for example, a continuous transmission signal having several tens to several hundreds of cycles is output.

  In the above description, the circuit configuration of two positive potentials (first positive potential and second positive potential) and two negative potentials (first negative potential and second negative potential) is shown. The number N of potentials (N is a natural number) is not limited to N = 2. For example, N = 3, 4, 5,... And the number N of positive and negative potentials (the number N of transmission power supply stages) can be set as appropriate. The stage number N of the transmission power supply can be set to an optimum stage number in consideration of, for example, the waveform of the transmission signal, the circuit scale of the transmission circuit, the power consumption of the transmission circuit, and the like.

  FIG. 12 is a diagram for explaining the relationship between the number N of transmission power supplies and the power consumption. FIG. 12 shows an example of actual measurement of power consumption, where the horizontal axis is the number N of transmission power supplies and the vertical axis is the power consumption W.

  FIG. 12 shows power consumption (1) generated when the transmission circuit changes the potential of the transmission signal, and power consumption (2) when the MOS FET (PMOS or NMOS) constituting the transmission circuit is in the OFF state. ) And power consumption (1) and total power consumption (3) are shown.

  The power consumption (1) decreases as the number N of transmission power supplies (N positive potentials and N negative potentials) increases. This is because the potential difference between the stages becomes smaller as the stage number N increases. On the other hand, the power consumption (2) increases as the number N of transmission power supplies (N positive potentials and N negative potentials) increases.

  As a result, in the measurement example shown in FIG. 12, the total power consumption (3) is the smallest when the number of stages N is 3 or 4. Therefore, in the actual measurement example of FIG. 12, if it is desired to minimize the total power consumption, it is desirable to set N = 3 or N = 4. For example, when N = 3, a configuration including three positive potentials, three negative potentials, and GND is an example of an optimal circuit configuration.

  As mentioned above, although preferred embodiment of this invention was described, embodiment mentioned above is only a mere illustration in all the points, and does not limit the scope of the present invention. The present invention includes various modifications without departing from the essence thereof.

  11, 12 Output circuit, 21, 22 Suppression circuit, 30 Vibration element, 100 Transmission circuit.

Claims (6)

An ultrasonic transmission circuit that outputs a transmission signal whose amplitude is changed stepwise,
An output control unit for controlling the output timing of a plurality of different potentials corresponding to the stepped amplitude;
For each potential output from the output control unit, a potential suppression unit that suppresses excess potential exceeding the target value of each potential,
Having
An ultrasonic transmission circuit. The transmission circuit according to claim 1,
The output control unit controls the output timing of the plurality of potentials obtained from a power source,
The potential suppression unit suppresses the excess potential by forming a charge path that suppresses the excess potential between the output control unit and the power source.
An ultrasonic transmission circuit. The transmission circuit according to claim 1 or 2,
The output control unit includes 2N output circuits corresponding to 2N different potentials composed of N (N is a natural number) positive potentials and N negative potentials,
The potential suppression unit includes 2N suppression circuits corresponding to each of the 2N output circuits,
Each output circuit controls the output timing of each potential corresponding to each output circuit,
Each suppression circuit suppresses the excess potential of each potential output from each output circuit corresponding to each suppression circuit.
An ultrasonic transmission circuit. The transmission circuit according to claim 3, wherein
Each output circuit controls the output timing of each potential obtained from a power supply corresponding to each output circuit,
Each suppression circuit forms a charge path that suppresses the excess potential of each output circuit between each output circuit corresponding to each suppression circuit and the power supply corresponding to each output circuit.
An ultrasonic transmission circuit. The transmission circuit according to claim 3 or 4,
The output control unit includes 2N output circuits corresponding to 2N different potentials (N is 3 or 4) composed of N positive potentials and N negative potentials,
The potential suppression unit includes 2N suppression circuits equal in number to 2N output circuits.
An ultrasonic transmission circuit. An ultrasonic medical device comprising the transmission circuit according to any one of claims 3 to 5,
A control unit for controlling operation timings of the 2N output circuits and the 2N suppression circuits so that the output circuits and the suppression circuits that form a through current path between power supplies are not in a conductive state at the same time; In addition,
An ultrasonic medical device.