JP2017118139A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of maintaining high breakdown voltage and high in reliability, and a method for manufacturing the semiconductor device.SOLUTION: A ptype base area 12 serves as an inner end part in a breakdown voltage structure 102 surrounding an active area 101. A ptype area 3b is provided in contact with the ptype base area 12 on the outer peripheral side of the ptype base area 12 and surrounds the periphery of the ptype base area 12. A first ptype area 5a is provided away from the p- type area 3b on the outer peripheral side of the ptype area 3b and surrounds the periphery of the ptype area 3b. A second ptype area 5b is provided in contact with the first ptype area 5a on the outer peripheral side of the first ptype area 5a and surrounds the periphery of the first ptype area 5a. The first ptype area 5a and the second ptype area 5b constitute a termination structure.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In a high withstand voltage semiconductor device, a high voltage is applied not only to the active region where the element structure is formed but also to the withstand voltage structure portion provided around the active region to hold the withstand voltage, and the electric field is concentrated on the withstand voltage structure portion. To do. The breakdown voltage of the high breakdown voltage semiconductor device is determined by the impurity concentration, thickness, and electric field strength of the semiconductor (see, for example, Non-Patent Document 1 below). Thus, the breakdown tolerance determined by the characteristic features of the semiconductor is from the active region. Equal across the pressure resistant structure. For this reason, depending on the design of the withstand voltage structure part, the electric field concentrates on the withstand voltage structure part, and an electric load exceeding the breakdown resistance may be applied to the withstand voltage structure part, which may lead to destruction.

  As a device that improves the withstand voltage of the entire high withstand voltage semiconductor device by relaxing or dispersing the electric field of the withstand voltage structure portion, a junction termination extension (JTE) structure or a field limiting ring (FLR) structure is provided. A semiconductor device in which a termination structure such as the above is formed in a breakdown voltage structure is known. Also known is a semiconductor device in which a floating metal electrode in contact with the FLR is arranged as a field plate (FP) and the charge generated in the breakdown voltage structure is released to improve the reliability (for example, (See the following Patent Documents 1 to 3.)

JP 2010-50147 A JP 2006-165225 A JP 2012-195519 A

Edited by Kazuo Arai and Sadafumi Yoshida, Basics and Applications of SiC Devices, Ohmsha, 2003, p. 100

  However, the above-described termination structure such as the JTE structure or the FLR structure is a structure for improving the breakdown voltage as an initial characteristic that is a specification of the semiconductor device, and the breakdown voltage during operation varies greatly depending on the environment in which the semiconductor device is used. However, the reliability of the semiconductor device may be reduced. For example, when a high voltage is applied, depending on the design conditions, the electric field concentrates at the end of the breakdown voltage structure (the end opposite to the active region side, that is, the chip end), and breakdown voltage breakdown occurs. In this case, it is reliable that the characteristics deteriorate due to a large current flowing in the interface between the semiconductor substrate (chip) and the oxide film provided thereon (hereinafter referred to as oxide film / semiconductor interface) in the breakdown voltage structure. Cause a decline in sex.

  In Patent Document 2, the breakdown voltage is maintained by forming a JTE structure that can be designed to be several μm or more on a silicon carbide (SiC) semiconductor substrate having a high impurity concentration. However, a SiC semiconductor requires a high temperature of 1500 ° C. or higher for heat treatment (annealing) for activating the impurities, and it is difficult to activate the impurities at a uniform temperature in a large-diameter wafer. For this reason, the impurity concentration of the semiconductor region constituting the JTE structure varies. Although the adverse effect on the initial characteristics of the semiconductor device due to the variation in the impurity concentration is small enough not to cause a problem, the concentration of the donor (acceptor) in the semiconductor region constituting the JTE structure varies due to the difference in activation rate.

  When variations occur in the donor (acceptor) concentration in the semiconductor region constituting the JTE structure, breakdown voltage breakdown occurs at the end portion (chip end portion) of the breakdown voltage structure portion, and a large current flows through the oxide film / SiC interface. As a result, the breakdown voltage of the breakdown voltage structure portion is lowered, and there is a problem that the reliability of the semiconductor device is lowered. Similarly, even when the FLR surrounding the periphery of the JTE structure is arranged on the outer periphery of the JTE structure as in Patent Document 3, the width of the JTE structure (the width in the direction from the active region toward the chip end) is the same. Due to the long length, depending on the design conditions, a structure in which a large current flows in the JTE structure is adversely affected on the oxide film / SiC interface.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of maintaining a high breakdown voltage and improving reliability in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A first conductive type semiconductor substrate made of a semiconductor having a wider band gap than silicon; a first conductive type semiconductor substrate having a wider band gap than silicon provided on the front surface of the first conductive type semiconductor substrate; A first conductive type semiconductor deposited layer having an impurity concentration lower than that of the conductive type semiconductor substrate; an active region having at least a metal film in contact with the second conductive type semiconductor deposited layer provided on the first conductive type semiconductor deposited layer; A first second conductivity type semiconductor region selectively provided on a surface layer of the first conductivity type semiconductor deposition layer opposite to the first conductivity type semiconductor substrate; and the first second From the first second conductivity type semiconductor region, which is provided on the outer peripheral side of the conductivity type semiconductor region in contact with the first second conductivity type semiconductor region and surrounds the first second conductivity type semiconductor region Even the low impurity concentration A second conductive type semiconductor region and an outer peripheral side of the second second conductive type semiconductor region, separated from the second second conductive type semiconductor region, and the second conductive type semiconductor region A third second-conductivity-type semiconductor region having a lower impurity concentration than the first second-conductivity-type semiconductor region surrounding the periphery, and the third second-conductivity-type semiconductor region on the outer peripheral side of the third second-conductivity-type semiconductor region A fourth second-conductivity-type semiconductor having a lower impurity concentration than the third second-conductivity-type semiconductor region, provided in contact with the second-conductivity-type semiconductor region and surrounding the third second-conductivity-type semiconductor region; A region, and an interlayer insulating film covering the third second conductivity type semiconductor region and the fourth second conductivity type semiconductor region. The active region is selectively provided on the first conductivity type semiconductor deposition layer and has an impurity concentration lower than that of the first second conductivity type semiconductor region covering the first second conductivity type semiconductor region. And the second conductivity type semiconductor deposition layer made of a semiconductor having a wider bandgap than silicon, the first conductivity type source region selectively provided inside the second conductivity type semiconductor deposition layer, and the second Excluding the first conductivity type well region that penetrates the conductivity type semiconductor deposition layer in the depth direction and reaches the first conductivity type semiconductor deposition layer, and the first conductivity type well region of the second conductivity type semiconductor deposition layer A second conductivity type contact region having a higher impurity concentration than the second conductivity type semiconductor deposition layer, and the first conductivity type source region and the first conductivity type of the second conductivity type semiconductor deposition layer. Of the part sandwiched between the well region A gate electrode provided on a surface via a gate insulating film; a source electrode made of the metal film in contact with the first conductive type source region and the second conductive type contact region; and the first conductive semiconductor substrate A drain electrode provided on the back surface of the metal film, and an ohmic junction between the metal film and the second conductivity type contact region is a metal-semiconductor junction.

  In the semiconductor device according to the present invention as set forth in the invention described above, the metal film is provided from a bonding surface forming the metal-semiconductor junction to the interlayer insulating film, and the third insulating film is interposed through the interlayer insulating film. It covers at least part of the second conductivity type semiconductor region.

  In the semiconductor device according to the present invention, the end portion of the metal film terminates at a boundary between the third second conductivity type semiconductor region and the fourth second conductivity type semiconductor region. It is characterized by.

  In the semiconductor device according to the present invention, the end of the metal film is terminated above the fourth second-conductivity-type semiconductor region via the interlayer insulating film in the above-described invention. And

  In the semiconductor device according to the present invention, the impurity concentration of the fourth second conductivity type semiconductor region is 0.4 times or more of the impurity concentration of the third second conductivity type semiconductor region. .7 or less.

  In the semiconductor device according to the present invention, in the above-described invention, the metal film includes a group IVa metal, a group Va metal, a group VIa metal, carbon, silicon, or two or three elements of these metals. It is a composite film.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor having a wider band gap than silicon is silicon carbide.

  In the semiconductor device according to the present invention, the crystallographic plane index of the surface of the first conductivity type semiconductor substrate on which the first conductivity type semiconductor deposition layer is provided is (000-1). It is a plane parallel to the plane or a plane tilted within 10 degrees.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. A first conductivity type semiconductor made of a semiconductor having a wider band gap than silicon and having an impurity concentration lower than that of the first conductivity type semiconductor substrate on a surface of the first conductivity type semiconductor substrate made of a semiconductor having a wider band gap than silicon. Depositing a deposition layer; selectively forming a first second conductivity type semiconductor region on a surface layer of the first conductivity type semiconductor deposition layer; and on the first conductivity type semiconductor deposition layer, A second conductivity type semiconductor deposition layer made of a semiconductor having an impurity concentration lower than that of the first second conductivity type semiconductor region and having a wider band gap than silicon is selected to cover the first second conductivity type semiconductor region. Forming the first conductivity type well region, penetrating the second conductivity type semiconductor deposition layer in the depth direction and reaching the first conductivity type semiconductor deposition layer, and the second conductivity type. Half A step of selectively forming a first conductivity type source region in the body deposition layer, and a surface layer of the first conductivity type semiconductor deposition layer on the outer peripheral side of the first second conductivity type semiconductor region. , Having a lower impurity concentration than the first second conductivity type semiconductor region so as to be in contact with the first second conductivity type semiconductor region and surround the first second conductivity type semiconductor region. A step of selectively forming a second conductive type semiconductor region, and a surface layer of the first conductive type semiconductor deposition layer on the outer peripheral side of the second conductive type semiconductor region. A third second conductivity having an impurity concentration lower than that of the first second conductivity type semiconductor region so as to be separated from the second conductivity type semiconductor region and surround the periphery of the second second conductivity type semiconductor region. A step of selectively forming a type semiconductor region, and the first conductive type semiconductor deposition layer, The surface layer on the outer peripheral side of the second conductivity type semiconductor region is in contact with the third second conductivity type semiconductor region and surrounds the periphery of the third second conductivity type semiconductor region. A step of selectively forming a fourth second conductivity type semiconductor region having an impurity concentration lower than that of the second second conductivity type semiconductor region, and a surface of the first conductivity type semiconductor deposition layer on the surface of the first conductivity type semiconductor deposition layer. A step of forming an interlayer insulating film covering the conductive type semiconductor region and the fourth second conductive type semiconductor region; a region of the second conductive type semiconductor deposited layer excluding the first conductive type well region; and Forming a second conductivity type contact region having an impurity concentration higher than that of the second conductivity type semiconductor deposition layer, and on a surface of a portion sandwiched between the first conductivity type source region and the first conductivity type well region; Forming a gate electrode through a gate insulating film And forming a source electrode made of a metal film in contact with the first conductivity type source region and the second conductivity type contact region and forming a metal-semiconductor junction with the second conductivity type semiconductor deposition layer. And

  According to the above-described invention, the second second-conductivity-type semiconductor region surrounding the element structure around the active region and the third second-conductivity-type semiconductor region constituting the termination structure in the breakdown voltage structure portion are arranged apart from each other. By doing so, the electric field can be concentrated most in the vicinity of the boundary between the active region and the breakdown voltage structure portion, so that a large current can be avoided from flowing through the oxide film / semiconductor interface in the breakdown voltage structure portion. Hereinafter, a structure in which a termination structure is arranged apart from the second second conductivity type semiconductor region provided in the vicinity of the boundary between the active region and the breakdown voltage structure portion is referred to as a separation termination (STE) structure. Thereby, it can be set as the structure which raise | generates a pressure | voltage resistant breakdown in the vicinity of the boundary of an active region and a pressure | voltage resistant structure part instead of the edge part (chip edge part) of a pressure | voltage resistant structure part, and can improve the withstand amount of a pressure | voltage resistant structure part. . Thereby, the tolerance of the entire semiconductor device can be improved. In addition, according to the above-described invention, a double-zone STE structure in which an STE structure is configured by two second conductivity type semiconductor regions having different impurity concentrations makes it possible to use a wide-bandgap semiconductor as a semiconductor material and a high breakdown voltage semiconductor. Even when a device is manufactured, a highly reliable semiconductor device can be manufactured.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, there is an effect that a high breakdown voltage can be maintained. In addition, according to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, there is an effect that the reliability of the semiconductor device can be improved.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device concerning the reference example 1. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning the reference example 1. FIG. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning the reference example 1. FIG. It is sectional drawing which shows typically the state in the middle of manufacture of the silicon carbide semiconductor device concerning the reference example 1. FIG. 12 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to Reference Example 2. FIG. 1 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment. FIG. 5 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a second embodiment. It is sectional drawing which shows the structure of the pressure | voltage resistant structure part of the silicon carbide semiconductor device concerning an Example. It is sectional drawing which shows the structure of the pressure | voltage resistant structure part of the silicon carbide semiconductor device of a comparative example. It is a characteristic view which shows the pressure | voltage resistant characteristic of the silicon carbide semiconductor device concerning an Example. It is a characteristic view which shows electric field distribution of the silicon carbide semiconductor device concerning an Example. It is a characteristic view which shows electric field distribution of the silicon carbide semiconductor device of a comparative example.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Further, in this specification, in the notation of Miller index (crystallographic plane index), “−” means a bar attached to the index immediately after that, and “−” is added before the index to make it negative. It represents an index.

(Reference Example 1)
The semiconductor device according to the present invention is configured using, for example, a semiconductor having a wider band gap than silicon (Si) (hereinafter referred to as a wide band gap semiconductor). In Reference Example 1, a silicon carbide semiconductor device manufactured (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described using a diode having a junction barrier Schottky (JBS) structure as an example. To do. 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to Reference Example 1. FIG. As shown in FIG. 1, a silicon carbide semiconductor device according to Reference Example 1 includes, for example, an n-type silicon carbide epitaxial layer (first conductivity type) on a main surface of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1. An epitaxial substrate on which a semiconductor deposition layer 2 is deposited is provided.

The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N). N-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer formed by doping, for example, nitrogen with an impurity concentration lower than that of n ⁺ -type silicon carbide substrate 1. Hereinafter, the n ⁺ -type silicon carbide substrate 1 alone or the n ⁺ -type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2 are combined to form a silicon carbide semiconductor substrate (semiconductor chip). Surface layer of n type silicon carbide epitaxial layer 2 opposite to the n ⁺ type silicon carbide substrate 1 side (front side of the silicon carbide semiconductor substrate) (hereinafter referred to as the surface layer of n type silicon carbide epitaxial layer 2) The p ⁺ type region (first second conductivity type semiconductor region) 3a, the p ⁻ type region (second second conductivity type semiconductor region) 3b, and the p ⁺ type region (first type) constituting the JBS structure. 5 second conductive type semiconductor region) 4, first p ⁻ type region (third second conductive type semiconductor region) 5 a and second p ⁻ type region (fourth second type) constituting the termination structure. A conductive semiconductor region) 5b is selectively provided.

The p ⁺ -type region 3a is provided from the breakdown voltage structure portion 102 surrounding the active region 101 where the element structure of the diode is formed, to the active region 101. A portion provided in the active region 101 of the p ⁺ -type region 3a is in contact with a Schottky electrode 9 described later. p ^- type region 3b is, p ⁺ than -type region 3a is provided in contact with the p ⁺ -type region 3a to the tip outer peripheral side of the silicon carbide semiconductor substrate, surrounding the said p ⁺ -type region 3a. The active region 101 is a region through which current flows when in the on state. The breakdown voltage structure 102 is a region that relaxes the electric field on the substrate front surface side of the n-type drift layer and maintains the breakdown voltage.

The p ⁺ type region 3a has a higher impurity concentration than the p ⁻ type region 3b, the first p ⁻ type region 5a, and the second p ⁻ type region 5b, and is doped with, for example, aluminum (Al). The impurity concentration of the p ⁺ -type region 3a is preferably about 1.0 × 10 ¹⁸ / cm ³ or more and about 1.0 × 10 ²⁰ / cm ³ or less, and the impurity concentration of the p ⁻ -type region 3b is, for example, 1.0. It is preferable that it is about 10 × 10 ¹⁷ / cm ³ or more and 1.0 × 10 ¹⁸ / cm ³ or less. The reason is that the effect of the present invention is remarkably exhibited. P ⁺ type region 3 a and p ⁻ type region 3 b have a function of avoiding electric field concentration at the junction end between n type silicon carbide epitaxial layer 2 and Schottky electrode 9. That is, p ⁺ type region 3 a and p ⁻ type region 3 b have a structure that relaxes the electric field applied to the junction end portion between n type silicon carbide epitaxial layer 2 and Schottky electrode 9. The p ⁻ type region 3b has a function of relaxing the electric field applied to the p ⁺ type region 3a.

A plurality of p ⁺ -type regions 4 are provided in the active region 101 in the n-type silicon carbide epitaxial layer 2 at a predetermined interval to form a JBS structure (element structure portion) (part indicated by a two-dot chain line). The impurity concentration of the p ⁺ type region 4 may be equal to the impurity concentration of the p ⁺ type region 3a. The first p ⁻ -type region 5a and the second p ⁻ -type region 5b constitute a double zone isolation termination (STE) structure. The STE structure is a structure in which a termination structure is disposed apart from the p-type regions (p ⁺ -type region 3a and p ⁻ -type region 3b) constituting the electric field relaxation structure. In the double zone STE structure, two p-type regions (first p ^- type region 5a and second p ^- type region 5b) having different impurity concentrations constituting the termination structure are arranged in parallel so as to be in contact with each other. It is a STE structure of composition.

Specifically, first p ^- type region 5a is, p ^- the chip outer circumferential side than the type region 3b p ^- provided apart from the type region 3b, the p ^- surround type region 3b. That is, n type silicon carbide epitaxial layer 2 is interposed between first p ⁻ type region 5a and p ⁻ type region 3b so as to be exposed on the front surface of the silicon carbide semiconductor substrate. The impurity concentration of the first p ⁻ type region 5a may be equal to the impurity concentration of the p ⁻ type region 3b. The second p ^- type region 5b, the first p ^- surrounding -type region 5a ^- provided in contact with the mold region 5a, the first p ^- first p the chip outer circumferential side than the type region 5a Enclose. That is, in the breakdown voltage structure 102, from the active region 101 side toward the chip outer peripheral side, the p ⁺ type region 3a, the p ⁻ type region 3b, a part of the n type silicon carbide epitaxial layer 2, the first p ⁻ type. Region 5a and second p ^- type region 5b are arranged in parallel in this order.

The p ⁺ type region 4, the first p ⁻ type region 5a, and the second p ⁻ type region 5b are each doped with, for example, aluminum. The impurity concentration of the first p − type region 5 a is preferably, for example, about 1.0 × 10 ¹⁷ / cm ³ or more and 1.0 × 10 ¹⁸ / cm ³ or less. The reason is that a desired breakdown voltage can be easily obtained and the effects of the present invention are remarkably exhibited. The impurity concentration of the second p ⁻ -type region 5b is lower than the impurity concentration of the first p ⁻ -type region 5a. Preferably, the second p ^- impurity concentration type region 5b is, for example a first p ^- is good is the order 0.4 times 0.7 times the impurity concentration in the type region 5a. The reason is that the effect of the present invention is remarkably exhibited. The first p ⁻ type region 5 a and the second p ⁻ type region 5 b have a function of further dispersing the electric field in the vicinity of the boundary between the active region 101 and the breakdown voltage structure portion 102.

Pressure-resistant structure 102, p p ⁺ -type region 3a ^- -type region 3b side portion of the, p ^- type region 3b, the n-type silicon carbide epitaxial layer 2, p ^- type region 3b and the first p ^- type region Interlayer insulating film 6 is provided to cover the portion sandwiched between 5a and the surfaces of first and second p ⁻ type regions 5a and 5b. The first p ⁻ -type region 5 a and the second p ⁻ -type region 5 b are electrically insulated from the element structure portion of the active region 101 by the interlayer insulating film 6 covering the STE structure. On the surface of n-type silicon carbide epitaxial layer 2 (the front surface of the silicon carbide semiconductor substrate), Schottky electrode 9 is provided through a contact hole penetrating interlayer insulating film 6. The Schottky electrode 9 is provided from the active region 101 to a part of the breakdown voltage structure 102.

Specifically, Schottky electrode 9 covers the entire surface of n type silicon carbide epitaxial layer 2 exposed in the contact hole of interlayer insulating film 6 in active region 101, and is provided in active region 101 of p ⁺ type region 3a. It touches the part. Further, the Schottky electrode 9 is provided from the active region 101 to the breakdown voltage structure portion 102 and extends over the interlayer insulating film 6. The end of the Schottky electrode 9 terminates, for example, above the p ⁺ type region 3a (on the portion of the interlayer insulating film 6 covering the p ⁺ type region 3a). Schottky electrode 9 forms a Schottky junction with n-type silicon carbide epitaxial layer 2 and constitutes an anode electrode.

  The Schottky electrode 9 is preferably made of the following material. The reason is that the effect of the present invention is remarkably exhibited. The Schottky electrode 9 is preferably made of, for example, a group IVa metal, a group Va metal, a group VIa metal, carbon, or silicon. Alternatively, the Schottky electrode 9 is preferably made of a composite film containing two or three elements of Group IVa metal, Group Va metal, Group VIa metal, carbon, and silicon. In particular, the Schottky electrode 9 is preferably made of titanium (Ti), carbon or silicon, or a composite film containing two or three elements of titanium, carbon and silicon. More preferably, in Schottky electrode 9, the portion forming Schottky junction with n-type silicon carbide epitaxial layer 2 is made of, for example, titanium. The Schottky barrier height between Schottky electrode 9 and n-type silicon carbide epitaxial layer 2 is preferably 1 eV or more, for example, when the silicon carbide semiconductor device according to Reference Example 1 is used as a high breakdown voltage semiconductor device. . In addition, when the silicon carbide semiconductor device according to Reference Example 1 is used as a power supply device, the Schottky barrier height of Schottky electrode 9 is preferably not less than 0.5 eV and less than 1 eV, for example.

On the Schottky electrode 9, an electrode pad 10 made of, for example, aluminum is provided. The electrode pad 10 is provided from the active region 101 to the breakdown voltage structure 102. The end of the electrode pad 10 may terminate on the Schottky electrode 9. On the STE structure, a protective film 11 such as a passivation film made of polyimide is provided so as to cover each end of the Schottky electrode 9 and the electrode pad 10. The protective film 11 has a function of preventing discharge. On the surface opposite to the n-type silicon carbide epitaxial layer 2 side of n ⁺ -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate), a back electrode that forms ohmic junction 8 with n ⁺ -type silicon carbide substrate 1 (Ohmic electrode) 7 is provided. The back electrode 7 constitutes a cathode electrode.

Next, a method for manufacturing a silicon carbide semiconductor device according to Reference Example 1 will be described by taking as an example a case where a high breakdown voltage diode having a JBS structure having a breakdown voltage class of 600 V or higher is manufactured. 2 to 4 are cross-sectional views schematically showing a state during the manufacture of the silicon carbide semiconductor device according to Reference Example 1. FIG. First, as shown in FIG. 2, an n ⁺ type silicon carbide substrate 1 having a thickness of, for example, about 300 μm doped with nitrogen at an impurity concentration of 1 × 10 ¹⁸ / cm ³ is prepared. The main surface of n ⁺ type silicon carbide substrate 1 may be, for example, a (0001) plane. Next, an n-type silicon carbide epitaxial layer 2 having a thickness of, for example, about 10 μm and doped with nitrogen at an impurity concentration of 1.0 × 10 ¹⁶ / cm ³ is grown on the main surface of the n ⁺ -type silicon carbide substrate 1. .

Next, as shown in FIG. 3, by photolithography and the first ion implantation, the surface layer of the n-type silicon carbide epitaxial layer 2, the p ⁺ -type constituting the p ⁺ -type region 3a and the JBS structure constituting the end structures Region 4 is selectively formed. The p ⁺ -type regions 3a and 4 are first ion-implanted with a p-type impurity such as aluminum, and are about 0.5 μm from the surface of the n-type silicon carbide epitaxial layer 2 (front surface of the silicon carbide semiconductor substrate), for example. It is formed so that the impurity concentration of the box profile up to the depth is about 3 × 10 ¹⁹ / cm ³ .

The first ion implantation for forming the p ⁺ -type regions 3a and 4 may be multi-stage ion implantation performed by changing acceleration energy and doping concentration in, for example, five stages. In this case, for example, the acceleration energy and doping concentration of the first to fifth stage ion implantations are 300 keV and 5 × 10 ¹⁴ ions / cm ² , 200 keV and 3 × 10 ¹⁴ ions / cm ² , 150 keV and 3 ×, respectively. It may be 10 ¹⁴ pieces / cm ² , 100 keV and 2 × 10 ¹⁴ pieces / cm ² , 50 keV and 3 × 10 ¹⁴ pieces / cm ² .

Next, as shown in FIG. 4, p ⁻ type region 3b constituting the electric field relaxation structure is selectively formed on the surface layer of n type silicon carbide epitaxial layer 2 by photolithography and second ion implantation. By photolithography and third ion implantation, first p ⁻ type region 5a constituting the STE structure is selectively formed in the surface layer of n type silicon carbide epitaxial layer 2. By photolithography and fourth ion implantation, the surface layer of the n-type silicon carbide epitaxial layer 2, a second p constituting the STE structure ^- selectively -type region 5b. In the second, third, and fourth ion implantations, the respective ion implantations for forming the p ⁻ type region 3b, the first p ⁻ type region 5a, and the second p ⁻ type region 5b are sequentially performed. The order of these ion implantations can be variously changed. The dopant and dopant concentration of each ion implantation for forming the p ⁻ type region 3b, the first p ⁻ type region 5a, and the second p ⁻ type region 5b have the following values, for example.

A p-type impurity such as aluminum is implanted at a dopant concentration of 3 × 10 ¹⁷ / cm ³ into portions corresponding to the formation regions of the p ⁻ -type region 3b and the first p ⁻ -type region 5a. A p-type impurity such as aluminum is implanted at a dopant concentration of 1.5 × 10 ¹⁷ / cm ³ into the portion corresponding to the formation region of the second p ⁻ type region 5b. After these ion implantations, for example, heat treatment (annealing) for activating the impurities is performed at a temperature of 1650 ° C. in an argon (Ar) atmosphere for 240 seconds, and the p-type impurities implanted into the n-type silicon carbide epitaxial layer 2 are removed. Activate.

Next, an oxide film having a thickness of, for example, 0.5 μm is formed as interlayer insulating film 6 on the entire surface of n-type silicon carbide epitaxial layer 2 (the front surface of the silicon carbide semiconductor substrate). Next, the interlayer insulating film 6 is patterned and selectively removed to form a contact hole penetrating the interlayer insulating film 6, and the activation of the n-type silicon carbide epitaxial layer 2 and the p ⁺ -type region 3a in the active region 101 The region 101 side is exposed. Thus, p p ⁺ -type region 3a ^- part of the mold region 3b side, p ^- -type region 3b, the n-type silicon carbide epitaxial layer 2, p ^- -type region 3b and the first p ^- sandwiched between -type region 5a Interlayer insulating film 6 is formed so as to cover the surface of the formed portion, first p ⁻ type region 5a and second p ⁻ type region 5b.

Next, a nickel (Ni) film, for example, is formed (formed) with a thickness of, for example, 50 nm as the back electrode 7 on the surface of the n ⁺ -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate). Next, for example, heat treatment is performed at a temperature of 1100 ° C. for 2 minutes in an argon atmosphere. By this heat treatment, ohmic junction 8 between n ⁺ -type silicon carbide substrate 1 and back electrode 7 is formed. Next, for example, a titanium film having a thickness of 100 nm is formed as the Schottky electrode 9 so as to bury a contact hole penetrating the interlayer insulating film 6 on the entire front surface side of the silicon carbide semiconductor substrate. Next, the Schottky electrode 9 on the breakdown voltage structure 102 is selectively removed so that the end of the Schottky electrode 9 terminates above the p ⁺ -type region 3a.

  Next, heat treatment is performed for 5 minutes at a temperature of 500 ° C. in an argon atmosphere. By this heat treatment, a Schottky junction between n-type silicon carbide epitaxial layer 2 and Schottky electrode 9 is formed. Next, an aluminum film, for example, with a thickness of 5 μm is deposited as an electrode pad 10 on the entire front surface of the silicon carbide semiconductor substrate so as to cover the Schottky electrode 9. Next, the electrode pad 10 is selectively removed so that the end of the electrode pad 10 terminates on the Schottky electrode 9. Thereafter, a protective film 11 made of polyimide for preventing discharge is formed on the electrode pad 10 to a thickness of, for example, 8 μm, thereby completing the JBS structure diode shown in FIG.

  As described above, according to Reference Example 1, the p-type region constituting the electric field relaxation structure in the vicinity of the boundary between the active region and the withstand voltage structure portion and the p-type region constituting the termination structure in the withstand voltage structure portion are provided. By adopting the STE structure arranged separately, the electric field can be concentrated most in the vicinity of the boundary between the active region and the breakdown voltage structure. For this reason, it can be avoided that a large current flows through the interface (oxide film / SiC interface) between the interlayer insulating film and the silicon carbide semiconductor substrate in the breakdown voltage structure. Thereby, it can be set as the structure which raise | generates a pressure | voltage resistant breakdown in the vicinity of the boundary of an active region and a pressure | voltage resistant structure part instead of the edge part (chip edge part) of a pressure | voltage resistant structure part, and can improve the withstand amount of a pressure | voltage resistant structure part. . As a result, the tolerance of the entire device can be improved, and the reliability of the semiconductor device can be improved. In addition, according to Reference Example 1, a high-voltage semiconductor device with high reliability can be obtained even when a high-voltage semiconductor device is manufactured using a wide band gap semiconductor as a semiconductor material by adopting a double zone STE structure. Can be produced.

(Reference Example 2)
Next, the structure of the silicon carbide semiconductor device concerning the reference example 2 is demonstrated. FIG. 5 is a cross-sectional view showing a configuration of the silicon carbide semiconductor device according to Reference Example 2. The silicon carbide semiconductor device according to the reference example 2 is different from the silicon carbide semiconductor device according to the reference example 1 in that the Schottky electrode 9 extends over the interlayer insulating film 6 covering the STE structure. In FIG. 5, the end of the Schottky electrode 9 is located above the first p ⁻ type region 5a constituting the STE structure (on the portion of the interlayer insulating film 6 covering the first p ⁻ type region 5a). The case of termination is illustrated.

Schottky electrode 9, a first p via the interlayer insulating film 6 ^- it is sufficient to cover at least a portion of the mold region 5a, a first p via the interlayer insulating film 6 ^- the entire type region 5a It may be covered. That is, the end of Schottky electrode 9 extends to the boundary between first p ⁻ type region 5a and second p ⁻ type region 5b (on the outer periphery of first p ⁻ type region 5a). it may be, second p ^- may extend to the upper mold region 5b. The configuration other than the arrangement of the end portion of the Schottky electrode 9 of the silicon carbide semiconductor device according to Reference Example 2 is the same as that of Reference Example 1.

  As described above, according to the reference example 2, the same effect as the reference example 1 can be obtained. Further, according to the reference example 2, the portion of the Schottky electrode protruding on the interlayer insulating film can function as a field plate. For this reason, the electric field generated in the breakdown voltage structure portion during the operation of the semiconductor device can be dispersed by the portion of the Schottky electrode protruding on the interlayer insulating film, and the withstand capability can be further improved. Further, according to the reference example 2, the portion of the Schottky electrode protruding on the interlayer insulating film can discharge the charge generated in the breakdown voltage structure portion during the operation of the semiconductor device to the outside. For this reason, it can suppress that a proof pressure fluctuates at the time of operation of a semiconductor device, and can further improve the reliability of a semiconductor device.

(Embodiment 1)
Next, the structure of the silicon carbide semiconductor device concerning Embodiment 1 is demonstrated. FIG. 6 is a cross-sectional view showing a configuration of the silicon carbide semiconductor device according to the first embodiment. The silicon carbide semiconductor device according to the first embodiment is different from the silicon carbide semiconductor device according to the reference example 1 in that an insulated gate field effect transistor (MOSFET: Metal Oxide Field Effect Transistor) is used instead of the element structure of the diode. This is the point where an element structure is formed. In the first embodiment, a MOSFET having a vertical planar gate structure will be described as an example. In addition, n ⁺ -type silicon carbide substrate 1, n-type silicon carbide epitaxial layer 2 and p-type silicon carbide epitaxial layer 13 described later are collectively used as a silicon carbide semiconductor substrate.

As shown in FIG. 6, in the silicon carbide semiconductor device according to the first embodiment, n-type silicon carbide epitaxial layer 2 is deposited on the main surface of n ⁺ -type silicon carbide substrate 1 serving as a drain region. N ⁺ type silicon carbide substrate 1 and n type silicon carbide epitaxial layer 2 are the same as the n ⁺ type silicon carbide substrate and n type silicon carbide epitaxial layer of Reference Example 1. On the surface opposite to the n-type silicon carbide epitaxial layer 2 side of the n ⁺ -type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate), a back electrode 7 is provided in the same manner as in Reference Example 1. The back electrode 7 constitutes a drain electrode.

In active region 101, a MOS (insulated gate made of metal-oxide film-semiconductor) structure (element structure portion) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, in the active region 101, the surface layer on the opposite side of the n-type silicon carbide epitaxial layer 2 to the n ⁺ -type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate) has p ^{A +} -type region (hereinafter referred to as a first p ⁺ -type base region (first second conductivity type semiconductor region)) 12 is selectively provided. The first p ⁺ type base region 12 is doped with, for example, aluminum.

A p-type silicon carbide epitaxial layer is formed on the surface of first p ⁺ -type base region 12 and on the surface of n-type silicon carbide epitaxial layer 2 between the adjacent first p ⁺ -type base regions 12. (Second conductivity type semiconductor deposition layer) 13 is selectively deposited. P-type silicon carbide epitaxial layer 13 is deposited only in active region 101. The impurity concentration of p type silicon carbide epitaxial layer 13 is lower than the impurity concentration of first p ⁺ type base region 12. The p-type silicon carbide epitaxial layer 13 is doped with, for example, aluminum.

An n ⁺ type source region 14 and a p ⁺ type contact region 15 are provided on the portion of p type silicon carbide epitaxial layer 13 on first p ⁺ type base region 12. The n ⁺ type source region 14 and the p ⁺ type contact region 15 are in contact with each other. The p ⁺ type contact region 15 is arranged closer to the breakdown voltage structure 102 than the n ⁺ type source region 14. In addition, p ⁺ type contact region 15 penetrates p type silicon carbide epitaxial layer 13 in the depth direction and reaches first p ⁺ type base region 12.

In the portion of p-type silicon carbide epitaxial layer 13 on n-type silicon carbide epitaxial layer 2, an n-type well region 16 that penetrates p-type silicon carbide epitaxial layer 13 in the depth direction and reaches n-type silicon carbide epitaxial layer 2. Is provided. N type well region 16 functions as a drift region together with n type silicon carbide epitaxial layer 2. The region of the p-type silicon carbide epitaxial layer 13 excluding the n-type well region 16 (hereinafter referred to as a second p-type base region (second conductivity type base region) 13) is the first p ⁺ -type base region. 12 functions as a base region.

On the surface of the second p-type base region 13 between the n ⁺ -type source region 14 and the n-type well region 16, a gate electrode 18 is provided via a gate insulating film 17. The gate electrode 18 may be provided on the surface of the n-type well region 16 via the gate insulating film 17. Interlayer insulating film 20 is provided on the entire front surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 18. Source electrode 19 is in contact with n ⁺ type source region 14 and p ⁺ type contact region 15 through a contact hole penetrating interlayer insulating film 20, and forms an ohmic junction with the silicon carbide semiconductor substrate.

The source electrode 19 is electrically insulated from the gate electrode 18 by the interlayer insulating film 20. An end portion of the source electrode 19 extends on the interlayer insulating film 20 and is located above the first p ⁺ type base region 12 (a portion of the interlayer insulating film 20 that covers the first p ⁺ type base region 12). It is terminated with (above). An electrode pad 21 is provided on the source electrode 19. The end of the electrode pad 21 terminates on the source electrode 19. A protective film 22 such as a passivation film made of polyimide is provided on the breakdown voltage structure 102 so as to cover the end portions of the source electrode 19 and the electrode pad 21. The protective film 22 has a function of preventing discharge.

Pressure-resistant structure 102, a first p ⁺ -type base region 12 first p ⁺ -type base region 12 in contact with the outer periphery of the chip side of and surrounding the first p ⁺ -type base region 12 p ^- A mold region 3b is provided. As in Reference Example 1, a first p ⁻ type region 5a and a second p ⁻ type region 5b are provided on the outer peripheral side of the p ⁻ type region 3b. That is, in the first embodiment, the first p ⁺ type base region 12, the p ⁻ type region 3 b, and the n type silicon carbide epitaxial layer 2 are formed on the breakdown voltage structure 102 from the active region 101 side toward the chip outer peripheral side. , A first p ⁻ type region 5a and a second p ⁻ type region 5b are sequentially arranged in parallel.

The impurity concentration of the p ⁻ type region 3 b is lower than the impurity concentration of the first p ⁺ type base region 12. The impurity concentration of the first p ⁻ type region 5 a is lower than the impurity concentration of the first p ⁺ type base region 12. The first p ⁻ type region 5a and the second p ⁻ type region 5b constituting the STE structure are covered with an interlayer insulating film 20, and are electrically connected to the element structure portion of the active region by the interlayer insulating film 20. Insulated. Although FIG. 6 shows only one MOS structure in the active region 101, a plurality of MOS structures may be arranged in parallel in the active region 101.

Next, the method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described by taking as an example the case of creating a MOSFET having a breakdown voltage class of 1200 V, for example. First, an n ⁺ type silicon carbide substrate 1 doped with nitrogen at an impurity concentration of about 2 × 10 ¹⁹ / cm ³ is prepared. N ⁺ -type silicon carbide substrate 1 may have a (000-1) plane whose main surface has an off angle of about 4 degrees in the <11-20> direction, for example. Next, an n-type silicon carbide epitaxial layer 2 having a thickness of 10 μm and doped with nitrogen at an impurity concentration of 1.0 × 10 ¹⁶ / cm ³ is grown on the main surface of n ⁺ -type silicon carbide substrate 1.

Next, first p ⁺ -type base region 12 is selectively formed on the surface layer of n-type silicon carbide epitaxial layer 2 by photolithography and first ion implantation. In this first ion implantation, for example, aluminum may be used as a dopant, and the dose may be set so that the impurity concentration of the first p ⁺ -type base region 12 is about 1.0 × 10 ¹⁸ / cm ³ . The width and depth of the first p ⁺ -type base region 12 may be 13 μm and 0.5 μm, respectively. The distance between adjacent first p ⁺ -type base regions 12 may be 2 μm, for example.

Next, a p-type silicon carbide epitaxial layer to be the second p-type base region 13 is grown on the surface of the n-type silicon carbide epitaxial layer 2 to a thickness of 0.5 μm, for example. At this time, for example, a p-type silicon carbide epitaxial layer doped with aluminum may be grown so that the impurity concentration of the second p-type base region 13 is 1.0 × 10 ¹⁶ / cm ³ .

Next, the conductivity type of the portion of the second p-type base region 13 on the n-type silicon carbide epitaxial layer 2 is inverted by photolithography and second ion implantation to selectively form the n-type well region 16. . In the second ion implantation, for example, the conductivity type of the n-type silicon carbide epitaxial layer 2 is inverted by using an n-type impurity such as nitrogen as a dopant. The dose amount of the second ion implantation may be set so that, for example, the impurity concentration of the n-type well region 16 is 5.0 × 10 ¹⁶ / cm ³ . The width and depth of the n-type well region 16 may be 2.0 μm and 0.6 μm, respectively.

Next, an n ⁺ type source region 14 is selectively formed on the surface layer of the second p type base region 13 on the first p ⁺ type base region 12 by photolithography and third ion implantation. . Next, a p ⁺ -type contact region 15 is selectively formed on the surface layer of the second p-type base region 13 on the first p ⁺ -type base region 12 by photolithography and fourth ion implantation. . Next, the portion of the second p-type base region 13 on the breakdown voltage structure 102 is removed by etching, for example, with a surface layer of the n-type silicon carbide epitaxial layer 2 at a depth of 0.7 μm. N type silicon carbide epitaxial layer 2 in portion 102 is exposed.

Next, the p ⁻ type region 3b and the first p ⁻ type region 5a are selected as the surface layer of the exposed portion of the n-type silicon carbide epitaxial layer 2 etched in the breakdown voltage structure 102 by photolithography and fifth ion implantation. Form. In the fifth ion implantation, for example, aluminum may be used as a dopant, and the dose may be set to 2.0 × 10 ¹³ / cm ² . Next, the photolithography and the sixth ion implantation, the surface layer of the exposed portion by etching of the n-type silicon carbide epitaxial layer 2 in the pressure-resistant structure portion 102, a second p ^- selectively -type region 5b . In the sixth ion implantation, for example, aluminum may be used as a dopant, and the dose may be set to 1.0 × 10 ¹³ / cm ² .

Next, impurities implanted to form the n ⁺ -type source region 14, the p ⁺ -type contact region 15, the n-type well region 16, the first p ⁻ -type region 5a, and the second p ⁻ -type region 5b are added. Heat treatment (annealing) for activation is performed. At this time, the heat treatment temperature and the heat treatment time may be, for example, 1620 ° C. and 2 minutes, respectively. The order of forming the n ⁺ type source region 14, the p ⁺ type contact region 15, the n type well region 16, the first p ⁻ type region 5a, and the second p ⁻ type region 5b can be variously changed.

  Next, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 17 having a thickness of, for example, 100 nm. This thermal oxidation may be performed, for example, by heat treatment at a temperature of about 1000 ° C. in an oxygen atmosphere. Thereby, each region formed in the surface layer of second p-type base region 13 and n-type silicon carbide epitaxial layer 2 from active region 101 to breakdown voltage structure portion 102 is covered with gate insulating film 17. Next, a polycrystalline silicon layer doped with, for example, phosphorus (P) is formed on the gate insulating film 17 as the gate electrode 18.

Next, the polycrystalline silicon layer is selectively removed by patterning, and polycrystalline silicon is formed on the portion of the second p-type base region 13 sandwiched between the n ⁺ -type source region 14 and the n-type well region 16. Leave a layer. At this time, a polycrystalline silicon layer may be left on the n-type well region 16. Next, for example, phosphorous glass (PSG: Phospho Silicate Glass) is formed (formed) to a thickness of 1.0 μm as the interlayer insulating film 20 so as to cover the gate insulating film 17. Next, the interlayer insulating film 20 and the gate insulating film 17 are patterned and selectively removed to form a contact hole that penetrates the interlayer insulating film 20 and the gate insulating film 17, and the n ⁺ -type source region 14 and the p ⁺ The mold contact region 15 is exposed. Next, heat treatment (reflow) for planarizing the interlayer insulating film 20 is performed.

Next, the source electrode 19 is formed on the surface of the interlayer insulating film 20. At this time, the source electrode 19 is buried in the contact hole of the interlayer insulating film 20, and the n ⁺ type source region 14 and the p ⁺ type contact region 15 and the source electrode 19 are brought into contact with each other. Next, the source electrode 19 on the breakdown voltage structure 102 is selectively removed so that the end of the source electrode 19 terminates above the first p ⁺ -type base region 12. Next, for example, a nickel film is formed as the back electrode 7 on the surface of the n ⁺ type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate). Next, for example, heat treatment is performed at a temperature of 970 ° C., and ohmic junction 8 between n ⁺ -type silicon carbide substrate 1 and back electrode 7 is formed.

  Next, an electrode pad 21 is deposited so as to cover the source electrode 19 over the entire front surface of the silicon carbide semiconductor substrate, for example, by sputtering. The thickness of the portion of the electrode pad 21 on the interlayer insulating film 20 may be 5 μm, for example. The electrode pad 21 may be formed of, for example, aluminum (Al—Si) containing silicon at a rate of 1%. Next, the electrode pad 21 is selectively removed so that the end of the electrode pad 21 terminates on the source electrode 19. Next, protective film 22 is formed on the front surface side of the silicon carbide semiconductor substrate so as to cover each end of source electrode 19 and electrode pad 21. Then, for example, titanium, nickel, and gold (Au) are deposited in this order as the back electrode 7 on the surface of the nickel film, thereby completing the MOSFET shown in FIG.

  As described above, according to the first embodiment, the same effect as that of the reference example 1 can be obtained even when the element configuration of the MOSFET is formed.

(Embodiment 2)
Next, the structure of the silicon carbide semiconductor device concerning Embodiment 2 is demonstrated. FIG. 7 is a cross-sectional view showing a configuration of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that the source electrode 19 extends over the interlayer insulating film 20 covering the STE structure. Specifically, the end portion of the source electrode 19 is terminated above the first p ⁻ type region 5a constituting the STE structure (on the portion of the interlayer insulating film 20 covering the first p ⁻ type region 5a). doing.

The source electrode 19, a first p via the interlayer insulating film 20 ^- cover the entire -type region 5a ^- it is sufficient to cover at least a portion of the mold region 5a, the first through the interlayer insulating film 20 p It may be. That is, the end of source electrode 19 extends to the boundary between first p ⁻ type region 5a and second p ⁻ type region 5b (on the outer periphery of first p ⁻ type region 5a). Alternatively, it may extend to above the second p ^- type region 5b. The end portion of the electrode pad 21 may extend to the same position as the end portion of the source electrode 19. The configuration of the silicon carbide semiconductor device according to the second embodiment is similar to that of the first embodiment except for the arrangement of the end portions of source electrode 19 and electrode pad 21.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, according to the second embodiment, the portion of the source electrode and the electrode pad that protrudes from the interlayer insulating film can function as a field plate. For this reason, the electric field generated in the breakdown voltage structure portion during the operation of the semiconductor device can be dispersed by the portion of the source electrode and the electrode pad that protrudes over the interlayer insulating film, and the resistance can be further improved. Further, according to the second embodiment, charges generated in the breakdown voltage structure portion during the operation of the semiconductor device can be discharged to the outside by the portion of the source electrode and the electrode pad that protrudes from the interlayer insulating film. For this reason, it can suppress that a proof pressure fluctuates at the time of operation of a semiconductor device, and can further improve the reliability of a semiconductor device.

(Example)
Next, the breakdown voltage characteristics of the silicon carbide semiconductor device according to the present invention were verified. FIG. 8A is a cross-sectional view showing the configuration of the breakdown voltage structure portion of the silicon carbide semiconductor device according to the example. FIG. 8B is a cross sectional view showing a configuration of the breakdown voltage structure portion of the silicon carbide semiconductor device of the comparative example. 8A and 8B, an electrode pad and a protective film are not shown. First, according to Reference Example 2, a diode having a JBS structure made of a silicon carbide semiconductor (hereinafter referred to as an example) was manufactured. Specifically, as shown in FIG. 8A, in the embodiment, the p ⁻ -type region 3b on the breakdown voltage structure 102 side that forms the electric field relaxation structure near the boundary between the active region 101 and the breakdown voltage structure 102, The structure portion 102 has an STE structure in which the first p ⁻ -type region 5 a on the active region 101 side constituting the termination structure is separated by a part of the n-type silicon carbide epitaxial layer 2. Further, the Schottky electrode 9 was projected on the interlayer insulating film 6 of the breakdown voltage structure portion 102, and the portion of the Schottky electrode 9 on the interlayer insulating film 6 was used as a field plate (portion indicated by symbol A).

As a comparison, as shown in FIG 8B, an electric field relaxation structure constituted of only the p ⁺ -type region 3a, so as to contact the p ⁺ -type region 3a, the first p active region 101 constituting the termination structure ^- A conventional diode having a JBS structure provided with a mold region 5a (hereinafter referred to as a comparative example) was produced. In the comparative example, the Schottky electrode 9 is not projected on the interlayer insulating film 6 of the breakdown voltage structure portion 102 (portion indicated by reference numeral B). The configuration of the comparative example other than the arrangement of the end of the Schottky electrode 9 and the arrangement of the first p ⁻ -type region 5a is the same as that of the example. For this reason, in FIG. 8B, the same code | symbol is attached | subjected to the structure similar to an Example. In both the examples and the comparative examples, the thickness of the interlayer insulating film 6 was set to 0.5 μm. The impurity concentration of n-type silicon carbide epitaxial layer 2 was 1 × 10 ¹⁶ / cm ³ and the thickness thereof was 10 μm. Both the first p ⁻ type region 5a and the second p ⁻ type region 5b were 30 μm and 0.5 μm in width and depth, respectively.

For these examples and comparative examples, the simulation results of the withstand voltage characteristics when the impurity concentration of the first p ⁻ type region 5a is changed in the range of 2 × 10 ¹⁷ / cm ^{3 to} 7 × 10 ¹⁷ / cm ³ are shown. 9 shows. FIG. 9 is a characteristic diagram showing a breakdown voltage characteristic of the silicon carbide semiconductor device according to the example. FIG. 9 shows the impurity concentration of the first p ⁻ -type region 5a on the horizontal axis and the breakdown voltage on the vertical axis. The second p ^- impurity concentration type region 5b is first the p ^- as the impurity concentration of the half of the impurity concentration in the type region 5a. In the embodiment, the width and depth of the p ⁻ type region 3b are 4 μm and 0.5 μm, respectively, and the distance between the p ⁻ type region 3b and the first p ⁻ type region 5a is 3 μm. From the results shown in FIG. 9, it was confirmed that the pressure resistance characteristics equivalent to or higher than those of the comparative example were obtained in the example. That is, even when the STE structure in which the electric field relaxation structure and the termination structure are arranged apart from each other as in the present invention, the breakdown voltage characteristic is equal to or higher than that of the conventional structure in which the electric field relaxation structure and the termination structure are in contact. It was confirmed that it was obtained.

Next, the simulation results of the electric field distribution in the voltage withstanding structure 102 of the above-described example and comparative example are shown in FIGS. 10A and 10B, respectively. FIG. 10A is a characteristic diagram illustrating an electric field distribution of the silicon carbide semiconductor device according to the example. FIG. 10B is a characteristic diagram showing an electric field distribution of the silicon carbide semiconductor device of the comparative example. 10A and 10B show the electric field strength of the pn junction portion having a depth of 0.5 μm from the interface (oxide film / SiC interface) between the interlayer insulating film 6 where the electric field is concentrated and the silicon carbide semiconductor substrate. ^- shown for each impurity concentration type region 5a. The pn junction portion is a pn junction between the p-type region constituting the electric field relaxation structure and the termination structure and the n-type silicon carbide epitaxial layer 2. 10A and 10B show the boundary between the active region 101 and the breakdown voltage structure 102, that is, the position of the end of the interlayer insulating film 6 on the active region 101 side (hereinafter referred to as the origin X = 0 μm). An electric field distribution at a predetermined distance toward the 102 side (outer peripheral side) is shown.

From the result shown in FIG. 10B, in the comparative example, the boundary b1 between the p ⁺ type region 3a and the first p ⁻ type region 5a located 3 μm away from the origin X on the outer peripheral side, and 33 μm away from the origin X on the outer peripheral side. A boundary b2 between the first p ⁻ type region 5a and the second p ⁻ type region 5b at a certain position, and a second p ⁻ type region 5b located 63 μm away from the origin X on the outer peripheral side. It was confirmed that electric field concentration occurred at the end b3 on the outer peripheral side. Further, when the impurity concentration of the first p ⁻ type region 5a is 3.0 × 10 ¹⁷ / cm ³ or less, the electric field concentration at the boundary b1 between the p ⁺ type region 3a and the first p ⁻ type region 5a. Was the maximum, and a large current did not flow at the oxide film / SiC interface. However, when the impurity concentration of the first p ⁻ type region 5a is 4.0 × 10 ¹⁷ / cm ³ or more, the electric field concentration at the boundary b2 between the first p ⁻ type region 5a and the second p ⁻ type region 5b. When the impurity concentration of the first p ⁻ type region 5a is 6.0 × 10 ¹⁷ / cm ³ or more, the electric field concentration at the outer end b3 of the second p ⁻ type region 5b is maximum. As a result, it was confirmed that a large current flows at the oxide film / SiC interface, and the reliability of the device is lowered.

On the other hand, as shown in FIG. 10A, in the embodiment, the boundary a1 between the p ⁻ type region 3b and the n-type silicon carbide epitaxial layer 2 located 4 μm away from the origin X toward the outer periphery, and from the origin X to the outer periphery. An end a2 of the Schottky electrode 9 located 20 μm away, a boundary a3 between the first p ⁻ type region 5a and the second p ⁻ type region 5b located 34 μm away from the origin X on the outer peripheral side, and It was confirmed that the electric field concentration occurred at the end a4 on the outer peripheral side of the second p ⁻ -type region 5b located 64 μm away from the origin X on the outer peripheral side. Further, the p ⁻ type region 3b and the n type silicon carbide epitaxial layer are used in the entire impurity concentration range of 1.0 × 10 ¹⁷ / cm ^{3 to} 7.0 × 10 ¹⁷ / cm ³ in the first p ⁻ type region 5a. The electric field concentration at the boundary a1 with the layer 2 was maximized. It was confirmed that a large current flows directly from the Schottky electrode 9 to the silicon carbide semiconductor substrate and does not flow to the oxide film / SiC interface. For this reason, in the embodiment, even if the activation rate or the like is uneven in the p-type region constituting the termination structure (STE structure) in the breakdown voltage structure 102, a structure in which a large current does not flow at the oxide film / SiC interface. It has been confirmed that a device including the highly reliable pressure-resistant structure 102 can be provided.

Further, as disclosed in Non-Patent Document 1, the activation rate depends on the temperature, and a difference of nearly 90% occurs with a temperature fluctuation of 100 ° C. For this reason, in the conventional structure in which the electric field relaxation structure and the termination structure are in contact as in the comparative example, the impurity concentration of the first p ⁻ -type region 5a is set to 2 × 10 ¹⁷ / cm ³ to reduce the impurity concentration. Even if the type impurities are implanted, the activation rate decreases due to the temperature difference of the heat treatment for activation, and the withstand voltage becomes 1400 V or less. Further, even if the impurity concentration of the first p ⁻ type region 5a is increased in order to improve the breakdown voltage, breakdown breakdown occurs in the vicinity of the first p ⁻ type region 5a, and the reliability of the semiconductor device is lowered. On the other hand, in the example, when the ratio of the impurity concentration of the first p ⁻ type region 5a and the second p ⁻ type region 5b is 1: 0.5, the result shown in FIG. In order to maintain the withstand voltage of 1400 V or higher, it is understood that the impurity concentration of the first p ⁻ -type region 5a should be in the range of, for example, about 2 × 10 ¹⁷ / cm ^{3 to} 7 × 10 ¹⁷ / cm ³ . Further, from the result shown in FIG. 10A, in order to concentrate the electric field near the boundary between the active region 101 and the breakdown voltage structure 102, the impurity concentration of the first p ⁻ -type region 5a is, for example, 1.0 × 10 ¹⁷ / It can be seen that a range of cm ³ or more and 7.0 × 10 ¹⁷ / cm ³ or less is preferable.

Although not shown in the drawings, when the portion of the Schottky electrode 9 overhanging the interlayer insulating film is short as in Reference Example 1 and the effect as a field plate is low, or active as in the first and fourth embodiments. Even when a MOSFET element structure is formed in region 101, an STE structure in which p ⁻ type region 3b and first p ⁻ type region 5a are separated by part of n type silicon carbide epitaxial layer 2 in the same manner as in the embodiment. Therefore, the same effect as the embodiment can be obtained.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-described embodiments, a JBS structure diode or vertical MOSFET is described as an example. However, the present invention is applied to semiconductor devices having various structures including a breakdown voltage structure portion surrounding an active region. Is possible. Therefore, the junction between each region constituting the element structure of the active region and the wide band gap semiconductor substrate is a configuration provided with a metal-semiconductor junction, a configuration provided with an insulator-semiconductor junction, or a configuration provided with both. It may be. The element structure having only the metal-semiconductor junction is, for example, an element structure of a diode. The element structure including the metal-semiconductor junction and the insulator-semiconductor junction is, for example, a MOSFET element structure.

  In the above-described embodiment, titanium is described as an example of a metal material that forms a Schottky junction with a silicon carbide semiconductor substrate, but it is sufficient that a Schottky junction with a silicon carbide semiconductor substrate can be formed. The Schottky electrode may be formed using other materials. Further, although the double zone STE structure has been described as a configuration example of the STE structure, a multi-zone STE structure having a configuration in which three or more p-type regions having different impurity concentrations are arranged in parallel so as to be in contact with each other may be used. . In the above-described embodiment, the case where an STE structure termination structure is provided in the breakdown voltage structure is described as an example. However, a plurality of p-type regions are arranged at predetermined intervals as in the FLR structure. The STE structure may be a configuration.

  In the above-described embodiment, the case where the main surface is the (0001) surface of the silicon carbide substrate made of silicon carbide has been described as an example. Various wide band gap semiconductor materials can be changed. For example, the substrate main surface may be a (000-1) plane, or a semiconductor substrate made of a wide band gap semiconductor such as gallium nitride (GaN) may be used. In the above-described embodiment, the field plate is formed using the front surface electrode such as the Schottky electrode or the source electrode. However, an electrode pad, a gate electrode, or another metal electrode is newly provided. The field plate may be formed using an electrode other than the front surface electrode. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a high voltage semiconductor device used for a power conversion device and a power supply device such as various industrial machines.

1 n ⁺ type silicon carbide substrate 2 n type silicon carbide epitaxial layer 3a p ⁺ type region constituting electric field relaxation structure 3b p ⁻ type region constituting electric field relaxation structure 4 p ⁺ type region constituting JBS structure 5a STE structure 1st p ⁻ type region 5b 2nd p ⁻ type region constituting STE structure 6 Interlayer insulating film 7 Back surface electrode 8 Ohmic junction 9 Schottky electrode 10 Electrode pad 11 Protective film 12 1st p ⁺ type base region 13 second p-type base region 14 n ⁺ -type source region 15 p ⁺ -type contact region 16 n-type well region 17 gate insulating film 18 gate electrode 19 source electrode 20 interlayer insulating film 21 electrode pad 22 protective film 101 active region 102 withstand voltage structure

Claims (9)

A first conductivity type semiconductor substrate made of a semiconductor having a wider band gap than silicon;
A first conductive type semiconductor deposited layer formed on a front surface of the first conductive type semiconductor substrate and made of a semiconductor having a wider band gap than silicon and having a lower impurity concentration than the first conductive type semiconductor substrate; ,
An active region having at least a metal film in contact with the second conductive type semiconductor deposited layer provided on the first conductive type semiconductor deposited layer;
A first second conductivity type semiconductor region selectively provided on a surface layer opposite to the first conductivity type semiconductor substrate side of the first conductivity type semiconductor deposition layer;
The first second conductivity type semiconductor region is provided on the outer peripheral side of the first second conductivity type semiconductor region so as to be in contact with the first second conductivity type semiconductor region, and surrounds the first second conductivity type semiconductor region. A second second conductivity type semiconductor region having a lower impurity concentration than the two conductivity type semiconductor region;
The first second conductivity type semiconductor region is provided on the outer peripheral side of the second second conductivity type semiconductor region, separated from the second second conductivity type semiconductor region, and surrounding the second second conductivity type semiconductor region. A third second conductivity type semiconductor region having an impurity concentration lower than that of the two conductivity type semiconductor region;
The third second conductivity type semiconductor region is provided on the outer peripheral side of the third second conductivity type semiconductor region so as to be in contact with the third second conductivity type semiconductor region and surrounds the periphery of the third second conductivity type semiconductor region. A fourth second conductivity type semiconductor region having an impurity concentration lower than that of the two conductivity type semiconductor region;
An interlayer insulating film covering the third second conductivity type semiconductor region and the fourth second conductivity type semiconductor region;
With
The active region is
An impurity concentration lower than that of the first second conductivity type semiconductor region, which is selectively provided on the first conductivity type semiconductor deposition layer and covers the first second conductivity type semiconductor region, and is lower than that of silicon. The second conductivity type semiconductor deposition layer made of a semiconductor having a wide band gap;
A first conductivity type source region selectively provided inside the second conductivity type semiconductor deposition layer;
A first conductivity type well region that penetrates the second conductivity type semiconductor deposition layer in a depth direction and reaches the first conductivity type semiconductor deposition layer;
A second conductivity type contact region of the second conductivity type semiconductor deposition layer excluding the first conductivity type well region and having a higher impurity concentration than the second conductivity type semiconductor deposition layer;
A gate electrode provided on a surface of a portion of the second conductivity type semiconductor deposition layer sandwiched between the first conductivity type source region and the first conductivity type well region via a gate insulating film;
A source electrode made of the metal film in contact with the first conductivity type source region and the second conductivity type contact region;
A drain electrode provided on the back surface of the first conductivity type semiconductor substrate,
An ohmic junction between the metal film and the second conductivity type contact region is a metal-semiconductor junction.   The metal film is provided from the junction surface forming the metal-semiconductor junction to the interlayer insulating film, and covers at least a part of the third second conductivity type semiconductor region through the interlayer insulating film. The semiconductor device according to claim 1.   3. The end of the metal film terminates at a boundary between the third second-conductivity-type semiconductor region and the fourth second-conductivity-type semiconductor region. 4. Semiconductor device.   3. The semiconductor device according to claim 1, wherein an end portion of the metal film is terminated above the fourth second-conductivity-type semiconductor region through the interlayer insulating film.   The impurity concentration of the fourth second conductivity type semiconductor region is 0.4 to 0.7 times the impurity concentration of the third second conductivity type semiconductor region. 5. The semiconductor device according to any one of 4.   6. The metal film according to claim 1, wherein the metal film is a group IVa metal, a group Va metal, a group VIa metal, carbon or silicon, or a composite film containing two or three elements of these metals. The semiconductor device according to any one of the above.   The semiconductor device according to claim 1, wherein the semiconductor having a wider band gap than silicon is silicon carbide.   The crystallographic plane index of the surface of the first conductive type semiconductor substrate on which the first conductive type semiconductor deposition layer is provided is a plane parallel to (000-1) or a plane tilted within 10 degrees. The semiconductor device according to claim 1, wherein the semiconductor device is provided. A first conductivity type semiconductor made of a semiconductor having a wider band gap than silicon and having an impurity concentration lower than that of the first conductivity type semiconductor substrate on a surface of the first conductivity type semiconductor substrate made of a semiconductor having a wider band gap than silicon. Depositing a deposition layer;
Selectively forming a first second conductivity type semiconductor region on a surface layer of the first conductivity type semiconductor deposition layer;
A semiconductor having an impurity concentration lower than that of the first second conductivity type semiconductor region and a band gap wider than that of silicon covering the first second conductivity type semiconductor region on the first conductivity type semiconductor deposition layer. Selectively forming a second conductivity type semiconductor deposition layer comprising:
Forming a first conductivity type well region that penetrates the second conductivity type semiconductor deposition layer in a depth direction and reaches the first conductivity type semiconductor deposition layer;
Selectively forming a first conductivity type source region in the second conductivity type semiconductor deposition layer;
The first conductivity type semiconductor deposition layer is in contact with the first second conductivity type semiconductor region on a surface layer on the outer peripheral side of the first second conductivity type semiconductor region, and the first second conductivity type semiconductor region. Selectively forming a second second conductivity type semiconductor region having an impurity concentration lower than that of the first second conductivity type semiconductor region so as to surround the periphery of the conductivity type semiconductor region;
In the surface layer of the first conductivity type semiconductor deposition layer on the outer peripheral side of the second second conductivity type semiconductor region, the second second conductivity type semiconductor region is separated from the second second conductivity type semiconductor region. Selectively forming a third second conductivity type semiconductor region having an impurity concentration lower than that of the first second conductivity type semiconductor region so as to surround the periphery of the conductivity type semiconductor region;
The surface layer of the first conductivity type semiconductor deposition layer on the outer peripheral side of the third second conductivity type semiconductor region is in contact with the third second conductivity type semiconductor region and the third second type. Selectively forming a fourth second conductivity type semiconductor region having an impurity concentration lower than that of the third second conductivity type semiconductor region so as to surround the periphery of the conductivity type semiconductor region;
Forming an interlayer insulating film covering the third second conductivity type semiconductor region and the fourth second conductivity type semiconductor region on the surface of the first conductivity type semiconductor deposition layer;
Forming a second conductivity type contact region of the second conductivity type semiconductor deposition layer excluding the first conductivity type well region and having a higher impurity concentration than the second conductivity type semiconductor deposition layer;
Forming a gate electrode on a surface of a portion sandwiched between the first conductivity type source region and the first conductivity type well region via a gate insulating film;
Forming a source electrode made of a metal film in contact with the first conductivity type source region and the second conductivity type contact region and forming a metal-semiconductor junction with the second conductivity type semiconductor deposition layer;
A method for manufacturing a semiconductor device, comprising:

Images