JP2017112294A - Semiconductor device and motor driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small chip semiconductor device excellent in characteristics, while arranging a plurality of H bridge circuits, and to provide a motor diver.SOLUTION: A semiconductor device 10 includes a plurality of H bridge circuits HBR1, HBR2 formed on the same semiconductor substrate. The H bridge circuits HBR1, HBR2 are placed, respectively, along the opposite sides of the semiconductor substrate. Even when the H bridge circuits HBR1, HBR2 are operated asynchronously, malfunction due to mutual interference via a parasitic transistor, and interference due to thermal noise caused by a large current or noise caused by PWM operation can be minimized.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a motor driver.

A forward / reverse control circuit using a semiconductor device is used in place of a conventional mechanical switch (relay switch) to control a motor capable of normal rotation and reverse rotation that operates a power window and a door lock of an automobile. It is becoming.
For example, Patent Document 1 discloses an H bridge circuit for realizing forward / reverse control by a semiconductor device.

JP 2014-093373 A

In a semiconductor device according to the background art, a motor is controlled by a two-chip solution using two chips each having one H-bridge circuit.
However, there has been a demand for a one-chip solution that uses only one chip in which two H-bridge circuits are formed.

Therefore, there has been a demand for a semiconductor device and a motor driver that are small in size and excellent in characteristics while arranging a plurality of H bridge circuits.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

According to one embodiment, in the semiconductor device, a plurality of H bridge circuits are formed on a semiconductor substrate, and the H bridge circuits are respectively disposed along opposing sides of the substrate.
Note that a device in which the device of the above-described embodiment is replaced with a system (for example, a motor driver), an automobile including the device, and the like are also effective as an aspect of the present invention.

  According to the one embodiment, it is possible to provide a semiconductor device and a motor driver that are small in size and excellent in characteristics while arranging a plurality of H bridge circuits.

1 is a schematic arrangement diagram of circuit elements of a semiconductor device 1 according to a first embodiment. FIG. 6 is a schematic layout diagram of circuit elements of a semiconductor device 10 according to a second embodiment. FIG. 10 is a schematic layout diagram of circuit elements of another semiconductor device 20 according to the second embodiment. 6 is a diagram for explaining VDD monitors 51 and 52 of a semiconductor device according to a third embodiment; FIG. 7 is a diagram showing an arrangement of pads 71 of a semiconductor device 30 according to a fourth embodiment. FIG.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Moreover, in each drawing, the same code | symbol is attached | subjected to the same element and duplication description is abbreviate | omitted as needed.

(Embodiment 1)
In the semiconductor device according to the first embodiment, when two or more independent H bridge circuits are formed or arranged on a semiconductor substrate, a reference voltage generation circuit, a logic circuit, etc. are arranged one by one as a common circuit, The two H-bridge circuits share a common circuit so as to reduce the size of the semiconductor device.

FIG. 1 is a schematic layout of circuit elements of a semiconductor device 1 according to the first embodiment.
The semiconductor device 1 includes a pre-driver circuit Pre1, Pre2, a logic circuit Logic, a reference that drives a first H-bridge circuit HBR1, a second H-bridge circuit HBR2, an H-bridge circuit HBR1, and an HBR2 disposed on a semiconductor substrate. A voltage generation circuit BGR (Band Gap Reference), an operation current generation circuit Ibias, other circuits Other 1 and 2 are provided.

  The H bridge circuits HBR1 and HBR2 are circuits having the same configuration including a high side driver HS1 and a high side driver HS2 which are P channel power MOS transistors, and a low side driver LS1 and a low side driver LS2 which are N channel power MOS transistors, respectively. The specific configuration of the H-bridge circuits HBR1 and HBR2 may be the same as that described in Patent Document 1, for example. Further, the high side driver HS can also be constituted by an N channel power MOS transistor and a charge pump. The H bridge circuits HBR1 and HBR2 operate asynchronously in response to individual PWM (Pulse Width Modulation) signals.

  In the semiconductor device 1 according to the first embodiment, as shown in FIG. 1, the H bridge circuits HBR1 and HBR2 are provided along one long side of the semiconductor substrate (or on the outer peripheral portion on one long side). Arranged so that it occupies almost half of the semiconductor substrate, the logic circuit Logic, the reference voltage generation circuit BGR, the operation current generation circuit Ibias, etc., which are common circuits, are arranged in the central part on the other long side of the semiconductor substrate, Pre-driver circuits Pre1 and Pre2 for the H-bridge circuit HBR1 or H-bridge circuit HBR2 and other circuits Other1 and Other2 are arranged at respective end portions on the other long side.

  With such a configuration, the logic circuit Logic, the reference voltage generation circuit BGR, the operation current generation circuit Ibias, etc. that have been provided for each H bridge circuit until now are provided one by one as a common circuit for the H bridge circuits HBR1 and HBR2. The semiconductor device 1 can be reduced in size. Further, by using a single logic circuit Logic, that is, a control circuit, the degree of freedom in controlling the H bridge circuit HBR and the pre-driver circuit Pre can be increased.

  In the semiconductor device 1 according to the first embodiment, the reference voltage generation circuit BGR requiring high accuracy is arranged along the other long side farthest from the H bridge circuits HBR1 and HBR2. As a result, the influence of noise generated by the switching operation of each driver HS, LS can be minimized, and erroneous detection by a detection circuit using the reference voltage VBGR as a detection reference can be reduced.

(Embodiment 2)
In the semiconductor device 1 according to the first embodiment, the H bridge circuits HBR1 and HBR2 are arranged along one long side of the semiconductor substrate. However, in the semiconductor device according to the second embodiment, along the opposite sides of the semiconductor substrate. Each H bridge circuit HBR is arranged, and a common circuit such as a reference voltage generating circuit BGR is arranged at a substantially central portion of the semiconductor substrate between the H bridge circuits to further reduce the size and improve the characteristics of the semiconductor device. is there.

FIG. 2 is a schematic layout diagram of circuit elements of the semiconductor device 10 according to the second embodiment.
The semiconductor device 10 also includes a first H bridge circuit HBR11, a second H bridge circuit HBR12, a logic circuit Logic, pre-driver circuits Pre11 and Pre12, a reference voltage generation circuit BGR, other circuits Other11 and Other12, and the like.

  In the semiconductor device 10 according to the second embodiment, as shown in FIG. 2, an H bridge circuit HBR11 is arranged along one short side of the semiconductor substrate, and an H bridge circuit is arranged along the other short side of the semiconductor substrate. HBR12 is arranged, and logic circuit Logic and reference voltage generation circuit BGR that are common circuits are arranged between H bridge circuits HBR11 and HBR12, that is, at a position farthest from H bridge circuits HBR11 and HBR12, in a substantially central portion of the semiconductor substrate. doing. The H-bridge circuits HBR11 and HBR12 can be arranged, for example, in a point-symmetric or line-symmetric state with respect to the center of the semiconductor substrate. In that case, a large current (10 A or more) is equally applied to each driver HS and LS. It will be able to flow.

  The other circuit Other11 for the H bridge circuit HBR11 and the other circuit Other12 for the H bridge circuit HBR12 are respectively arranged between the H bridge circuits HBR11 and HBR12 and the common circuit. The other circuits Other11 and Other12 may include circuits and elements that function as a common circuit.

  Further, in the semiconductor device 10, the pre-driver circuits Pre11 and Pre12 are arranged between the half bridges constituting the H bridge circuits HBR11 and HBR12, respectively.

  With such a configuration, the influence of negative potential parasitics and noise between the H-bridge circuits HBR11 and HBR12 can be minimized, and the influence on the common circuit, in particular, the reference voltage generation circuit BGR can be minimized. Can be.

  In addition, the wiring between the pre-driver circuits Pre11 and Pre12 and the drivers HS and LS can be minimized, and the wiring between the H-bridge circuits HBR11 and HBR12 and the common circuit can be shortened. For example, the semiconductor device 10 can be reduced in size by efficient wiring.

  In the semiconductor device according to the second embodiment, the high side drivers HS1 and HS2 constituting the H bridge circuit HBR are arranged along the opposite sides of the semiconductor device, that is, the high side drivers HS1 and HS2 are arranged. It can also be arranged on the outer peripheral side of the semiconductor device.

FIG. 3 is a schematic layout of circuit elements of another semiconductor device 20 according to the second embodiment.
As shown in FIG. 3, high-side drivers HS <b> 1 and HS <b> 2 are arranged along the short side of the semiconductor device 20. With such a configuration, it is possible to minimize the influence of the substrate current ISub on the high-side drivers HS1 and HS2 which are P-channel power MOS transistors.

  When the two H-bridge circuits HBR11 and HBR12 that drive a large current are arranged on a single semiconductor substrate, they may interfere with each other via parasitic transistors and cause malfunctions, especially when they are operated asynchronously. In addition, there may be interference due to thermal noise caused by a large current or noise caused by PWM operation. In the semiconductor devices 10 and 20 according to the second embodiment, these possibilities can be reduced. it can.

  In the semiconductor devices 10 and 20 according to the second embodiment, the two H bridge circuits HBR1 and HBR2 are arranged along the opposing short sides of the semiconductor substrate, respectively, but the two H bridge circuits HBR1 and HBR2 are arranged. It can also be arranged along the opposing long sides of the semiconductor substrate.

  In the semiconductor devices 10 and 20 according to the second embodiment, the two H-bridge circuits HBR1 and HBR2 are arranged along the opposing sides of the semiconductor substrate, but three or more H-bridge circuits are provided on the semiconductor substrate. Even when the HBR is arranged, the effect according to the second embodiment can be enjoyed by arranging the H bridge circuits HBR along the opposite side or the adjacent side.

  As described above, in the semiconductor devices 10 and 20 according to the second embodiment, the plurality of H bridge circuits HBR are formed on the semiconductor substrate, and the H bridge circuits HBR are respectively along the opposing sides of the semiconductor substrate. It is arranged.

Further, in the semiconductor devices 10 and 20 according to the second embodiment, it is preferable that the opposing sides are short sides of the semiconductor substrate.
Further, in the semiconductor devices 10 and 20 according to the second embodiment, the pre-driver circuit Pre that drives the H-bridge circuit HBR is further formed on the semiconductor substrate, and the pre-driver circuit Pre forms a half-bridge that constitutes the H-bridge circuit HBR. It is preferable to arrange | position between.

  In the semiconductor devices 10 and 20 according to the second embodiment, a common circuit shared by the plurality of H bridge circuits HBR is formed on a semiconductor substrate, and the common circuit is interposed between the plurality of H bridge circuits HBR. It is preferable that they are arranged.

  Further, in the semiconductor devices 10 and 20 according to the second embodiment, the common circuit includes the reference voltage generation circuit BGR, and the reference voltage generation circuit BGR is located at the position where the distance is the longest from each of the plurality of H bridge circuits HBR. It is preferable that they are arranged.

  In the semiconductor device 20 according to the second embodiment, it is preferable that the high-side driver HS that constitutes the H-bridge circuit HBR is disposed along the opposing sides of the semiconductor substrate.

  In addition, the motor driver according to the second embodiment includes a plurality of H bridge circuits HBR, a pre-driver circuit Pre that drives the H bridge circuit HBR, a plurality of H bridge circuits HBR, and a pre-driver. A control circuit Logic that controls the driver circuit Pre and a reference voltage generation circuit BGR that supplies a reference voltage VBGR are provided, and an H-bridge circuit HBR is arranged along the opposing sides of the semiconductor substrate.

(Embodiment 3)
In the semiconductor device according to the first and second embodiments, a common circuit is provided to reduce the size of the semiconductor device when two H-bridge circuits are arranged on the semiconductor substrate. However, in the semiconductor device according to the third embodiment, a reference is provided. Even when the voltage generation circuit BGR is a common circuit, a plurality of voltage conversion circuits are provided so that an appropriate power supply voltage can be supplied to each H bridge circuit.

FIG. 4 is a diagram for explaining the VDD monitors 51 and 52 of the semiconductor device according to the third embodiment.
The VDD monitor (power supply voltage monitoring circuit) 51 is included in, for example, the other circuit Other1 of the semiconductor device, and the VDD monitor 52 is included in the other circuit Other2, and the potential level of the power supply voltage VDD appearing on the power supply wiring is set. This is a circuit to be monitored.

  In general, the reference voltage generation circuit BGR is a circuit that occupies a large area in the semiconductor device. In the semiconductor devices according to the first and second embodiments, the reference voltage generation circuit BGR is integrated as one common circuit.

  However, in the case where the GND reference power supply voltage VDD set for each H bridge circuit is used as in some in-vehicle semiconductor devices, a reference voltage generation circuit BGR is provided for each H bridge circuit. Don't be.

  However, in the semiconductor device according to the third embodiment, the reference voltage VBGR created by the reference voltage generation circuit BGR using the common GND is level-shifted by the level shift circuits (reference voltage conversion circuits) 61 and 62 in the VDD monitors 51 and 52. The VDD monitor 51 generates a GNDA reference voltage VBGRA for the first H bridge circuit HBR1, and the VDD monitor 52 generates a GNDB reference voltage VBGRB for the second H bridge circuit HBR2. Monitor the voltage VDD.

  With such a configuration, it is necessary to configure the VDD monitors 51 and 52 with simple and small circuit elements such as a level shift circuit, a comparator, a resistance voltage divider, and a current mirror, respectively, and to provide two reference voltage generation circuits BGR. There is no. For this reason, the semiconductor device can be reduced in size and excellent in characteristics.

  As described above, in the semiconductor device according to the third embodiment, a plurality of monitoring circuits 51 and 52 for monitoring the power supply voltage VDD supplied to the plurality of H bridge circuits HBR are further formed on the substrate. 51 and 52 preferably include reference voltage conversion circuits 61 and 62 for converting the reference voltage VBGR supplied from the reference voltage generation circuit BGR into GND reference voltages VBGRA and VBGRB set for each H bridge circuit HBR. .

(Embodiment 4)
In the semiconductor devices 10 and 20 according to the second embodiment, the H-bridge circuit HBR is arranged along the opposite sides of the semiconductor substrate. However, the semiconductor device according to the fourth embodiment is a circuit as in the second embodiment. When the elements are arranged, a terminal through which a large current flows is constituted by a plurality of pads to reduce the size of the semiconductor device.

  FIG. 5 is a diagram showing the arrangement of the pads 71 of the semiconductor device 30 according to the fourth embodiment. Only the characteristic pads 71 are extracted and shown for the semiconductor device 30 having the same arrangement as the circuit elements shown in FIG. 2 (that is, the description of the non-characteristic pads is omitted). Further, the semiconductor device 10 shown in FIG. 2 and the semiconductor device 30 shown in FIG. 5 have the same orientation (top and bottom) for comparison.

These pads 71 are all formed on a copper (Cu) rewiring (not shown). For the terminals that allow a large current to be connected to the power supply, ground (GND), or motor, five pads (shown by the same hatching) are provided, and these five pads are bonded to the same lead of the lead frame. I am doing so.
The five pads located substantially symmetrical with respect to the center of the semiconductor device 10 function as the same kind of terminals of the two H bridge circuits HBR.

  By providing such a configuration, that is, by providing five or more pads on the same terminal, for example, when a package such as SSOP (Shrink Small Outline Package) is used, wire bonding can be performed efficiently. Further, the bonding wire can be stabilized by minimizing the wire diameter of the bonding wire to 40 μm or less, for example.

Further, even if one or two bonding wires are disconnected, the influence can be reduced.
In addition, the area of each driver HS, LS can be minimized by minimizing connection resistance and wire resistance.

  As described above, in the semiconductor device 30 according to the fourth embodiment, the H bridge circuit HBR has the high side driver HS and the low side driver LS, and the terminals connected to the high side driver HS or the low side driver LS are provided. It is preferable to provide a plurality of pads 71 which constitute each.

  As mentioned above, the invention made by the present inventor has been specifically described based on each embodiment. However, the present invention is not limited to each embodiment described above, and various modifications can be made without departing from the scope of the invention. It goes without saying that changes are possible.

1, 10, 20, 30 Semiconductor devices 51, 52 VDD monitor (power supply voltage monitoring circuit)
61, 62 Level shift circuit (reference voltage conversion circuit)
71 Pad HBR H Bridge Circuit HS High Side Driver LS Low Side Driver Pre Predriver Circuit BGR Reference Voltage Generation Circuit Logic Logic Circuit (Control Circuit)
Other Other circuit Ibias Operating current generation circuit

Claims (9)

A semiconductor device in which a plurality of H-bridge circuits are formed on a semiconductor substrate,
A semiconductor device in which the H-bridge circuit is disposed along opposite sides of the substrate. The semiconductor device according to claim 1, wherein the opposing sides are short sides of the substrate. A pre-driver circuit for driving the H-bridge circuit is further formed on the substrate;
The semiconductor device according to claim 1, wherein the pre-driver circuit is disposed between half bridges constituting the H-bridge circuit. A common circuit shared by the plurality of H bridge circuits is further formed on the substrate,
The semiconductor device according to claim 1, wherein the common circuit is disposed between the plurality of H bridge circuits. The common circuit includes a reference voltage generation circuit,
The semiconductor device according to claim 4, wherein the reference voltage generation circuit is arranged at a position where the distance from each of the plurality of H bridge circuits is the largest. The semiconductor device according to claim 1, wherein high-side drivers constituting the H-bridge circuit are arranged along the opposing sides. A plurality of monitoring circuits for monitoring power supply voltages supplied to the plurality of H bridge circuits are further formed on the substrate.
The semiconductor device according to claim 1, wherein the monitoring circuit includes a reference voltage conversion circuit that converts a reference voltage supplied from the reference voltage generation circuit into a GND reference voltage set for each of the H bridge circuits. The H bridge circuit has a high side driver and a low side driver,
The semiconductor device according to claim 1, further comprising a plurality of pads that respectively constitute terminals connected to the high-side driver or the low-side driver. Formed on a semiconductor substrate,
A plurality of H-bridge circuits;
A pre-driver circuit for driving the H-bridge circuit;
A control circuit that controls the plurality of H-bridge circuits and the pre-driver circuit; and a reference voltage generation circuit that supplies a reference voltage.
A motor driver in which the H-bridge circuit is disposed along opposite sides of the substrate.

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