JP2017103544A - Image pick-up device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read out pixel data without using a PLL circuit.SOLUTION: According to one embodiment, an image pick-up device includes a pixel array in which a plurality of pixels is disposed in an array state. The pixel array can be divided into a plurality of sub arrays individually including the plurality of pixels. The plurality of sub arrays generates pixel data of a multiple value corresponding to incident light intensity in the sub arrays. The pixel includes a photodetector generating a pixel voltage corresponding to the incident light intensity. The photodetector is connected to a comparator comparing the pixel voltage with a reference voltage and generating binary information indicating a comparison result. The pixel data of the multiple value depend on a total number of "0" or "1" included in the binary information generated by the comparator connected to the plurality of photodetectors in the sub arrays corresponding thereto.SELECTED DRAWING: Figure 1

Description

  Embodiments relate to an image sensor.

  In a conventional image sensor, each pixel converts the incident light intensity (incident light amount) at the pixel into time information using pulse width modulation. Since the pulse signal having this time information can be expressed by a binary voltage, it has excellent noise resistance and can use a low power supply voltage, which contributes to low power consumption of the image sensor.

  A TDC (Time to Digital Converter) arranged for each column of the pixel array converts this pulse signal into a multi-value digital signal (pixel data). The TDC corresponds to a counter circuit that operates using a reference clock signal. Therefore, reading out pixel data requires a PLL (Phase Locked Loop) circuit for generating the reference clock signal.

  The PLL circuit can be shared by the entire pixel array. For this reason, one PLL circuit is normally arranged for one image sensor IC (Integrated Circuit). If other conditions are ignored, the power consumption by the pixel array and TDC (counter circuit) increases as the number of pixels of the image sensor IC increases. Therefore, when the resolution of the image sensor IC is high, the power consumption by the PLL circuit occupies only a small proportion of the power consumption of the entire image sensor IC, so that it does not matter much. On the other hand, when the resolution of the image sensor IC is low, the power consumption by the PLL circuit accounts for a large proportion of the power consumption of the entire image sensor IC, which hinders low power consumption.

JP 58-179068 A Japanese Patent No. 2879670

Skiler Weaver, Benjamin Hershberg, Peter Kurahashi, Daniel Knierim, Un-Ku Moon, “Stochastic Flash Analog-to-Digital Cons. 57, no. 11, Nov. 2010, pp. 2825-2833.

  The embodiment is intended to read pixel data without using a PLL circuit.

  According to the embodiment, the imaging device includes a pixel array in which a plurality of pixels are arranged in an array. The pixel array can be divided into a plurality of subarrays each including a plurality of pixels. The subarray generates multivalued pixel data corresponding to the incident light intensity in the subarray. The pixel includes a photodetector that generates a pixel voltage corresponding to the incident light intensity. The photodetector is connected to a comparator that compares the pixel voltage with a reference voltage and generates binary information indicating the comparison result. Multi-value pixel data depends on the total number of “0” or “1” included in the binary information generated by the comparators connected to the plurality of photodetectors in the corresponding subarray.

FIG. 3 is a block diagram illustrating a subarray included in the image sensor according to the first embodiment. The graph which illustrates distribution of the offset voltage of a comparator. The graph which illustrates the relationship between the difference voltage between a pixel voltage and a reference voltage, and the total number of the comparators which output "1". 1 is a block diagram illustrating an image sensor according to a first embodiment. FIG. 6 illustrates a circuit configuration of a pixel. 6 is a timing chart illustrating the operation of the pixel in FIG. 5. FIG. 6 illustrates a circuit configuration of a pixel. 8 is a timing chart illustrating the operation of the pixel in FIG. FIG. 6 illustrates a circuit configuration of a pixel. The figure which illustrates the pixel contained in the image sensor concerning a 2nd embodiment. 11 is a timing chart illustrating the operation of the pixel in FIGS. 9 and 10. The block diagram which illustrates the image sensor concerning a 3rd embodiment. FIG. 3 is a block diagram illustrating an adder circuit included in the image sensor according to the first embodiment. 14 is a timing chart illustrating the operation of the addition circuit in FIG. 13. The block diagram which illustrates the addition circuit contained in the image sensor concerning a 3rd embodiment. FIG. 16 is a timing chart illustrating the operation of the addition circuit in FIG. 15; FIG. The block diagram which illustrates the image sensor concerning a 4th embodiment. The block diagram which illustrates the image sensor concerning a 5th embodiment. The graph which illustrates the relationship between the difference voltage between a pixel voltage and a reference voltage, and the total number of the comparators which output "1" when exposure time is too short. The graph which illustrates the relationship between the difference voltage between a pixel voltage and a reference voltage, and the total number of the comparators which output "1" when exposure time is appropriate. The graph which illustrates the relationship between the difference voltage between a pixel voltage and a reference voltage, and the total number of the comparators which output "1" when exposure time is too long. The block diagram which illustrates the image sensor concerning a 6th embodiment. The graph which illustrates the relationship between the difference voltage between a pixel voltage and a reference voltage in case the average value of the offset voltage of a comparator is 0, and the total number of the comparators which output "1". The graph which illustrates the relationship between the difference voltage in case the average value of the offset voltage of a comparator is larger than 0, and the total number of the comparators which output "1". 6 is a graph illustrating the relationship between the differential voltage and the total number of comparators that output “1” when the reference voltage is adjusted to cancel the average value of the offset voltage of the comparator. FIG. 10 is a block diagram illustrating an image sensor according to a seventh embodiment. 6 is a graph illustrating a probability density function centered on a plurality of different reference voltages. 28 is a graph illustrating a probability density function obtained by combining a plurality of probability density functions in FIG. The graph which illustrates the relationship between the difference voltage between pixel voltage and a reference voltage, and pixel data at the time of using the probability density function of FIG. Explanatory drawing of the 1st subarray division | segmentation method. Explanatory drawing of the 2nd subarray division | segmentation method. Explanatory drawing of the 3rd subarray division | segmentation method. Explanatory drawing of the 4th subarray division | segmentation method. FIG. 20 is a block diagram illustrating an adder circuit included in an image sensor according to an eighth embodiment. The figure which illustrates SSADC which shares the pixel contained in the image sensor which concerns on 9th Embodiment, and the said pixel and a comparator.

  Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the same or similar elements as those already described are denoted by the same or similar reference numerals, and redundant description is basically omitted. For example, when there are a plurality of identical or similar elements, a common reference may be used to explain each element without distinction, and the common reference may be used to distinguish each element. In addition, branch numbers may be used.

(First embodiment)
A general image sensor generates multivalued pixel data corresponding to the incident light intensity in each pixel. On the other hand, as illustrated in FIG. 4, the imaging device according to the first embodiment includes one or more subarrays 310 including a plurality of pixels 100, and each subarray 310 corresponds to the incident light intensity in the subarray 310. Multi-value pixel data is generated.

  4 includes a pixel array 300 in which a plurality of pixels 100 are arranged in an array, a plurality of addition circuits 200, a reference voltage generation circuit 320, a vertical selection register 330, and a horizontal transfer register 340. .

The pixel array 300 can be divided into a plurality of subarrays 310. That is, the subarray 310 corresponds to a subset of the pixel array 300. In the following description, the sub-array 310 is assumed to be N ² pixels 100 arranged in a square shape of N rows × N columns (N is an integer of 2 or more), but is not limited thereto.

  The reference voltage generation circuit 320 generates a reference voltage and applies it to each pixel 100. The vertical selection register 330 sequentially selects rows to be read from the pixel array 300. The plurality of pixels 100 arranged in the row selected by the vertical selection register 330 outputs binary information to the addition circuit 200. The horizontal transfer register 340 obtains multivalued pixel data for each subarray 310 by sequentially reading the multivalued pixel data output from the adder circuit 200.

Each pixel 100 includes a photodiode 110 and a comparator 120, as illustrated in FIG. The photodiode 110 may be another type of photodetector that can detect light. The photodiode 110 detects light and applies a pixel voltage (V _PD ) corresponding to the incident light intensity to the comparator 120. The comparator 120 compares the pixel voltage (V _PD ) with the reference voltage (V _REF ) from the reference voltage generation circuit 320 and generates binary information (COUT) according to the comparison result. Then, the image pickup device performs calculation by combining binary information (COUT) generated in the plurality of pixels 100 included in the subarray 310 for each subarray 310, so that one multivalue can be obtained for the entire subarray 310. Pixel data (D _OUT ) is generated.

Strictly speaking, the incident light intensity in the plurality of pixels 100 included in the sub-array 310 is not necessarily completely uniform. However, in the following description, it is assumed that these incident light intensities are uniform. In other words, the photodiodes 110 included in a plurality of (usually all) pixels 100 included in the sub-array 310 supply pixel voltages (V _PD ) having the same magnitude to the comparator 120.

If the characteristics of the comparator 120 and the reference voltage (V _REF ) are completely the same among the plurality of pixels 100 included in the sub-array 310, binary information (COUT) output from the comparators 120 is used. ) Will be all "1" or all "0". However, the actual comparator 120 has a random offset voltage (V _{OS_CMP} ) due to element variations. And it is very rare that these offset voltages (V _{OS_CMP} ) match each other. Therefore, the binary information (COUT) output by each comparator 120 includes a differential voltage (V _PD −V _REF ) and an offset voltage (V _{OS_CMP} ) between the pixel voltage (V _PD ) and the reference voltage (V _REF ). Depending on the magnitude relationship between and, it will vary as illustrated in FIG.

The offset voltage (V _{OS_CMP} ) of the comparator 120 is generally distributed according to a normal distribution with an average value = 0, for example. Therefore, if the total number of comparators 120 used by the subarray 310 (ie, the number of pixels included in the subarray 310) is sufficiently large, the offset voltage (V _{OS_CMP} ) is distributed as illustrated in FIG. Then, the comparator 120 (indicated by the hatched portion in FIG. 2) having an offset voltage (V _{OS_CMP} ) lower than the differential voltage (V _PD −V _REF ) outputs “1”, and the differential voltage (V _PD −V Comparator 120 having an offset voltage (V _{OS_CMP} ) higher than _REF ) outputs “0”.

Therefore, the total number of comparators 120 that output “1” is integrated from −∞ to V _PD −V _{REF in} the distribution of FIG. 2 (normal distribution of mean value 0) as shown in the following formula (1). It can be calculated by

Here, N ₁ represents the total number of comparators 120 that output “1”, N represents the number of pixels in the horizontal and vertical directions of the subarray 310, N ² represents the number of pixels in the subarray 310, and σ represents the comparison Represents the standard deviation of the offset voltage (V _{OS — CMP} ) of the device 120.

When the total number (N ₁ ) of the comparators 120 that output “1” is the vertical axis and the differential voltage (V _PD −V _REF ) is the horizontal axis, the graph illustrated in FIG. 3 can be drawn. It can be seen from FIG. 3 that N ₁ monotonically increases with respect to V _PD −V _REF . Therefore, by utilizing such a relationship, the total number (N ₁ ) of the comparators 120 that output “1” can be handled as multi-value pixel data corresponding to the pixel voltage (V _PD ).

Specifically, as illustrated in FIG. 1, the binary information (COUT) generated by the comparator 120 of each pixel 100 is supplied to the adding circuit 200, and the adding circuit 200 outputs the binary information (COUT). ) To calculate the total number (N ₁ ) of the comparators 120 that output “1”. The adder circuit 200 outputs the sum (N ₁ ) as multi-value pixel data (D _OUT ). The adding circuit 200 may calculate the total number of comparators 120 that output “0” instead of “1”. Furthermore, the addition circuit 200 may be replaced with a calculation circuit that performs other calculations.

  A specific example of the adding circuit 200 is shown in FIG. The adder circuit 200 is shared by a plurality of subarrays 310 arranged in the same column of the pixel array 300. Accordingly, the subarray 310 occupying the first column to the Nth column of the pixel array 300 is connected to the adding circuit 200-1, the subarray 310 occupying the N + 1th column to the second Nth column is connected to the adding circuit 200-2, and the Mth The subarray 310 occupying the Mth column from the (N + 1) th column is connected to the adding circuit 200-M / N. Note that M represents the number of pixels in the horizontal direction of the pixel array 300.

  Each adder circuit 200 includes a multiplexer 210, an AND gate 220, and a counter 230. Further, the addition circuits 200-1, 200-2,..., 200-M / N can share the control circuit 240, the oscillation circuit 250, and the counter 260.

  The control circuit 240 resets the counter 230 and the counter 260 with the reset signal RST1 and the reset signal RST2, respectively, and controls the operation / non-operation by supplying the enable signal EN to the oscillation circuit 250.

  The oscillation circuit 250 oscillates in response to the enable signal EN from the control circuit 240 and generates a clock signal CLK. Oscillation circuit 250 outputs clock signal CLK to AND gate 220 and counter 260.

  The counter 260 receives the clock signal CLK from the oscillation circuit 250 and counts up by one according to the clock signal CLK. The counter 260 outputs a selection control signal SEL indicating the count value to the multiplexer 210 of each adder circuit 200 and feeds it back to the control circuit 240.

The multiplexer 210-1 receives the selection control signal SEL from the counter 260. Further, the multiplexer 210-1 outputs binary information COUT ₁ , COUT ₂ ..., COUT _N from N pixels 100 arranged in the row selected by the vertical selection register 330 among the pixels 100 belonging to the sub-array 310. Receive. The multiplexer 210-1 selects _{one of} the binary information COUT ₁ , COUT ₂ ..., COUT _N according to the selection control signal SEL, and guides the selection signal MOUT _N to the AND gate 220-1.

The AND gate 220-1 receives the selection signal MOUT _N from the multiplexer 210-1 and receives the clock signal CLK from the oscillation circuit 250. AND gate 220-1 performs a logical AND operation of the selection signal MOUT _N and the clock signal CLK, and obtain the calculation result signal. The AND gate 220-1 outputs an operation result signal to the counter 230-1. The counter 230-1 counts up by one according to the calculation result signal.

When the selection signal MOUT _N is “1”, the operation result signal matches the clock signal CLK, and the counter 230-1 counts up. On the other hand, when the selection signal MOUT _N is "0", the calculation result signal also remains "0", the counter 230-1 does not count up. Since the value indicated by the selection control signal SEL is incremented by _one , all of the binary information COUT ₁ , COUT ₂ ..., COUT _N are sequentially selected as the selection signal MOUT _N.

Accordingly, the counter 230-1 is included in the binary information COUT ₁ , COUT ₂ ..., COUT _N generated by the pixels 100 for one row of the subarray 310 in the operation of one cycle illustrated in FIG. The total number of “1” can be counted. Then, by repeating the same operation for the remaining N−1 rows of pixels 100 over N−1 cycles, the counter 230-1 can generate binary information generated by all the pixels 100 of the sub-array 310. Can be obtained as a sum signal DOUT _N indicating the total number of “1” s included in.

  Hereinafter, specific examples of the circuit configuration of the pixel 100 will be described with reference to FIGS. 5, 6, 7, 8, and 9.

The pixel 100 in FIG. 5 includes one photodiode 110 and three NMOS (N-type Metal-Oxide-Semiconductor) transistors M _TX , M _RST, and M _SF . The pixel 100 in FIG. 5 corresponds to a general pixel circuit that outputs a pixel voltage corresponding to the incident light intensity. In the circuit configuration in FIG. 5, the number of transistors arranged in one pixel 100 is smaller than that in the circuit configurations in FIGS. 7 and 9. It is useful for improving the ratio of the occupied area.

As illustrated in FIG. 6, the operation cycle of the pixel 100 in FIG. 5 is roughly divided into a reset phase, a charge accumulation phase, and a 0/1 conversion phase. In the reset phase, the NMOS transistors _MTX and _MRST are first turned on. Then, the gate potential _{(V FD)} and the cathode terminal of the photodiode 110 potential of the NMOS transistor _{M SF (V PD)} is reset.

Specifically, when the power supply voltage (V _DD ) is applied to the gates of the NMOS transistors M _TX and M _RST , the gate potential (V _FD ) of the NMOS transistor M _SF starts to rise. Then, when the gate potential of the NMOS transistor _{M SF (V FD)} reaches _V DD _-V THN (threshold voltage of the NMOS transistor _{M TX} and _{M RST),} NMOS transistors _{M TX} and _{M RST} is turned off. Therefore, the gate potential of the NMOS transistor _{M SF (V FD) is} reset to V _{DD -V THN.} If the gate potential (V _FD ) of the NMOS transistor M _SF needs to be reset to V _DD , the voltage applied to the gates of the NMOS transistors M _TX and M _RST during the reset phase is adjusted to V _DD + V _THN do it.

In the charge accumulation phase following the reset phase, the NMOS transistors _MTX and _MRST are turned off. Then, by accumulating charges generated in the photodiode 110, the cathode potential (V _PD ) of the photodiode 110 decreases with time. When the incident light intensity is high (bright), the cathode potential (V _PD ) of the photodiode 110 decreases greatly, and when the incident light intensity is low (dark), the cathode potential (V _PD ) does not decrease so much. When a predetermined time elapses from the start of the charge accumulation phase, the reference voltage (V _REF ) is applied to the gate of the NMOS transistor M _TX and the 0/1 conversion phase starts.

The cathode potential (V _PD ) of the photodiode 110 at the start of the 0/1 conversion phase is compared with the reference voltage (V _REF ). _{Specifically,} in the case of _V REF _{-V PD} ≧ V _THN is, the NMOS transistor _{M TX} is turned on, the charge of the photodiode PD110 is passing through the channel of the NMOS transistor _{M TX,} the gate potential of the NMOS transistor _{M SF} (V _FD ) decreases. On the other _hand, V _REF -V PD _<in the case of _{V THN} is, the NMOS transistor _{M TX} will remain off, the charge of the photodiode PD110 is blocked by the NMOS transistor _{M TX,} the gate potential of the NMOS transistor _{M SF (V FD} ) Does not change.

By using the presence or absence of change in the gate potential (V _FD) of such NMOS transistors M _SF, as described later, the binary information of 0/1 can be read via the signal read line BL.

Specifically, when the decrease width of V _FD when the NMOS transistor M _TX is turned on is ΔV _FD , V _FD in this case is V _DD −V _THN −ΔV _FD . On the other hand, V _FD when NMOS transistor M _TX remains off is V _DD −V _THN . The 0/1 middle NMOS transistor _{M PRE} of the conversion phase is turned on, the signal read line BL is charged to _{V DD -2 × V THN -ΔV A} . Here, ΔV _A is a value used for adjusting the charging potential of the signal readout line BL, and is set to an appropriate range (for example, ΔV _A <ΔV _FD ).

The NMOS transistor M _PRE is then turned off again. If V _FD is _V DD _{-V THN,} the gate of the NMOS transistor _{M SF} - since source potential becomes _{V THN} + [Delta] V _A, charging the NMOS transistor _{M SF} is the signal read line BL turned on. Therefore, the potential of the signal read line BL rises to V _DD -V _THN . On the other _hand, if _{V FD} is _V DD _{-V THN -ΔV FD,} the gate of the NMOS transistor _{M SF} - source potential becomes _{V THN} + _{ΔV A -ΔV FD.} Here, if ΔV _A <ΔV _FD , V _THN + ΔVa−ΔV _FD <V _THN , that is, the NMOS transistor M _SF is turned off, so that the potential of the signal read line BL is V _DD −2 × V _THN −ΔV _A Will remain.

The signal readout line BL is connected to a shaping circuit such as an inverter circuit. The shaping circuit outputs "1" when the potential of the signal read line BL is _V DD _{-V THN,} when the potential of _V DD -2 × _{V THN -ΔV A} output to "0" To do. The adder circuit 200 collects output signals (binary information (COUT)) of each shaping circuit and outputs the sum of these as multi-valued pixel data (DOUT).

In the example of FIGS. 5 and 6, the NMOS transistor M _TX functions as the comparator 120, and the variation in the threshold voltage (V _THN ) of the NMOS transistor M _TX is the variation in the offset voltage (V _{OS_CMP} ) of the comparator 120. Give rise to

In the pixel 100 of FIG. 7, the NMOS transistor _MCMPN and the PMOS (P-type MOS) transistor _MCMPP function as a single-ended comparator 120. As illustrated in FIG. 8, the operation cycle of the pixel 100 of FIG. 7 is also roughly divided into a reset phase, a charge accumulation phase, and a 0/1 conversion phase.

In the reset phase, the NMOS transistor _MRST is first turned on. Then, the gate potential of the NMOS transistor _{M SF (V FD)} is reset. In the charge accumulation phase following the reset phase, the NMOS transistor _MRST is turned off. Then, by accumulating charges generated in the photodiode 110, the cathode potential (V _PD ) of the photodiode 110 decreases with time. When a predetermined time elapses from the start of the charge accumulation phase, the NMOS transistor _MTX is turned on regardless of the incident light intensity, and the 0/1 conversion phase starts. That is, regardless of the incident light intensity, the charge of the photodiode PD110 reduces the gate potential _{(V FD)} of the NMOS transistor _{M SF} through the channel of the NMOS transistor _{M TX.} The gate potential of the NMOS transistor _{M SF (V FD)} is significantly reduced as the incident light intensity is high.

Drain current _{I CMPN} of the NMOS transistor _{M CMPN} forming part of the comparator 120 included in the pixel 100 in FIG. 7, assuming the output resistance of the NMOS transistor _{M CMPN} is sufficiently high, the NMOS transistor _{M SF} It depends on the gate potential (V _FD ). On the other hand, the drain current I _CMPP of the PMOS transistor _MCMPP , which also forms part of the comparator 120 included in the pixel 100 of FIG. 7, is assumed to have the gate resistance _if the output resistance of the PMOS transistor _MCMPP is sufficiently high. It is determined by the reference voltage (V _REF ) applied to.

When I _CMPP > I _CMPN , the output voltage of the comparator 120 increases, and when I _CMPP <I _CMPN , the output voltage of the comparator 120 decreases. Assuming that the output resistance of the comparator 120 is sufficiently high, the output voltage of the comparator 120 is V _DD or 0. The potential of the signal readout line BL is reset to 0 in advance (for example, during the reset phase) by discharging through the PMOS transistor _MPRE . Therefore, when the output voltage of the comparator 120 is V _DD , the potential of the signal readout line BL is V _DD −V _THN , and when the output voltage of the comparator 120 is 0, the potential of the signal readout line BL remains 0. Become.

The signal readout line BL is connected to a shaping circuit such as an inverter circuit. This shaping circuit outputs “1” when the potential of the signal readout line BL is V _DD −V _THN , and outputs “0” when the potential is 0. The adder circuit 200 collects output signals (binary information (COUT)) of each shaping circuit and outputs the sum of these as multi-valued pixel data (DOUT).

As described above, in the example of FIGS. 7 and 8, the NMOS transistor M _CMPN and the PMOS transistor _MCMPP function as the single-ended comparator 120, and the threshold _values of the NMOS transistor _MCMPN and the PMOS transistor _MCMPP are as _follows . The variation in voltage causes a variation in the offset voltage (V _{OS_CMP} ) of the comparator 120.

  In the circuit configuration in FIG. 7, the number of transistors arranged in one pixel 100 is larger than that in the circuit configuration in FIG. 5, but the amplitude of the output voltage of the comparator 120 and the potential of the signal readout line BL is large. Therefore, for example, variations and noise in the shaping circuit are less likely to be a problem.

  In the pixel 100 of FIG. 9, a total of four NMOS transistors, one NMOS transistor included in each pixel 100 and one NMOS transistor and two PMOS transistors shared between the other pixels 100 arranged in the same column. These transistors function as a differential amplifier type comparator 120. As illustrated in FIG. 11, the operation cycle of the pixel 100 in FIG. 9 is also roughly divided into a reset phase, a charge accumulation phase, and a 0/1 conversion phase.

In the reset phase, the NMOS transistor _MRST is first turned on. Then, the gate potential of the NMOS transistor _{M SF (V FD)} is reset. Thus, when V _FD > V _REF , the output signal (binary information (COUT)) of the shaping circuit is inverted from “0” to “1”. In the charge accumulation phase following the reset phase, the NMOS transistor _MRST is turned off. Then, by accumulating charges generated in the photodiode 110, the cathode potential (V _PD ) of the photodiode 110 decreases with time. When a predetermined time elapses from the start of the charge accumulation phase, the NMOS transistor _MTX is turned on regardless of the incident light intensity, and the 0/1 conversion phase starts. That is, regardless of the incident light intensity, the charge of the photodiode PD110 reduces the gate potential _{(V FD)} of the NMOS transistor _{M SF} through the channel of the NMOS transistor _{M TX.} The gate potential of the NMOS transistor _{M SF (V FD)} is significantly reduced as the incident light intensity is high.

If the gate potential of the NMOS transistor _{M SF (V FD)} falls below the reference voltage _{(V REF),} the output signal of the shaping circuit (binary information (COUT)) returns to "0" from "1". On the other hand, if less than the gate potential _{(V FD)} is the reference voltage of the NMOS transistor _{M SF (V REF),} the output signal of the shaping circuit (binary information (COUT)) remains "1". The adder circuit 200 collects output signals (binary information (COUT)) of each shaping circuit and outputs the sum of these as multi-valued pixel data (DOUT).

  In the circuit configuration in FIG. 9, the number of transistors arranged in one pixel 100 is the same as that in the circuit configuration in FIG. 5, but the amplitude of the output voltage of the comparator 120 and the potential of the signal readout line is large. Therefore, for example, variations and noise in the shaping circuit are less likely to be a problem.

  On the other hand, the circuit configuration in FIG. 9 has more signal readout lines than the circuit configuration in FIG. In general, in a front-illuminated imaging device that irradiates light from the surface on the wiring layer side, it is better that the number of signal readout lines is small because a part of incident light is blocked by the wiring. On the other hand, in the backside illuminating type imaging device that irradiates light from the surface opposite to the wiring layer, the influence of the wiring on the incident light is small.

  As described above, the image sensor according to the first embodiment generates multivalued pixel data for each subarray including a plurality of pixels. Specifically, the comparator compares the pixel voltage and the reference voltage for each pixel, but the comparison result varies due to the influence of the offset voltage of the comparator. Therefore, according to this imaging device, by counting the total number of comparators that output “1” for each subarray, it is possible to calculate multivalued pixel data corresponding to the incident light intensity in the subarray.

  Note that the count of the total number of comparators that output “1” can be realized by using, for example, an adder circuit, so that a highly accurate reference clock is not required. Therefore, this image sensor can reduce power consumption by omitting the PLL circuit. Furthermore, since the signal processing subsequent to the comparator can be realized by a digital circuit (that is, without an analog circuit), the power consumption can be reduced by using a low power supply voltage.

(Second Embodiment)
In the first embodiment described above, each pixel incorporates one comparator. However, a plurality of pixels arranged in the same column in the pixel array may share one comparator.

  A specific example of the pixel 100 included in the image sensor according to the second embodiment is shown in FIG. In the example of FIG. 10, pixel voltages generated by a plurality of pixels 100 arranged in the same column in the pixel array 300 are sequentially read out via the signal read line SIG and applied to the comparator 120.

  For example, when the subarray 310 corresponds to 256 pixels 100 of 16 rows × 16 columns, the total number of comparators 120 required for the subarray 310 is also 256 according to the first embodiment. According to the second embodiment, the number is 16.

  If all of the 16 pixels 100 arranged in the same column apply the same pixel voltage to the comparator 120, the 16 binary information output by the comparator 120 is the same. End up. However, in actuality, the pixel voltage is output via a source follower amplifier built in the pixel 100, and an offset voltage of the source follower amplifier is added. The 16 pieces of binary information output from the comparator 120 vary due to the influence of the offset voltage. Accordingly, the subarray 310 can generate pixel data having a maximum value of 256 as in the first embodiment.

  As described above, in the imaging device according to the second embodiment, a plurality of pixels arranged in the same column in the pixel array share one comparator. Therefore, according to this image sensor, the total number of comparators is reduced compared to the case where a comparator is prepared for each pixel, so that the circuit area can be suppressed.

(Third embodiment)
In the first embodiment described above, the adder circuit is shared by a plurality of subarrays arranged in the same column of the pixel array. In other words, one adder circuit is arranged for each column of the subarray. However, one adder circuit can be shared by the entire pixel array.

  An imaging device according to the third embodiment is illustrated in FIG. 12 includes a pixel array 300, a reference voltage generation circuit 320, a vertical selection register 330, a horizontal transfer register 440, and an addition circuit 500.

  The horizontal transfer register 440 sequentially reads the binary information generated by each subarray 310 and transfers it to the adder circuit 500. A specific example of the adding circuit 500 is shown in FIG.

  15 includes a control circuit 510, an oscillation circuit 520, a 1 / N frequency dividing circuit 530, a counter 540, a demultiplexer 550, counters 560-1, 560-2,. -M / N and AND gate 570 are included.

  The control circuit 510 operates by applying the reset signal RST2 to the 1 / N frequency dividing circuit 530 and the counter 540, resetting the counter 560 by applying the reset signal RST1, or providing the enable signal EN to the oscillation circuit 520. / Control non-operation.

  The oscillation circuit 520 oscillates in response to the enable signal EN from the control circuit 510 and generates a clock signal CLK. The oscillation circuit 520 outputs the clock signal CLK to the horizontal transfer register 440, the 1 / N frequency dividing circuit 530, and the AND gate 570.

  The 1 / N frequency dividing circuit 530 receives the clock signal CLK from the oscillation circuit 520 and multiplies the frequency by 1 / N. The 1 / N divider circuit 530 outputs the divided clock signal to the counter 540.

  The counter 540 receives the divided clock signal from the 1 / N frequency dividing circuit 530, and counts up by one according to the divided clock signal. Counter 540 outputs selection control signal SEL indicating the count value to demultiplexer 550.

The horizontal transfer register 440 receives binary information COUT ₁ , COUT ₂ ,..., COUT _M from the M pixels 100 arranged in the row selected by the vertical selection register 330 and holds them. Then, the horizontal transfer register 440 sequentially transfers the binary information COUT ₁ , COUT ₂ ,..., COUT _M from the oscillation circuit 520 to the AND gate 570 in synchronization with the clock signal CLK.

  The AND gate 570 receives the transfer signal MOUT from the horizontal transfer register 440 and the clock signal CLK from the oscillation circuit 520. The AND gate 570 performs an AND operation on the transfer signal MOUT and the clock signal CLK to obtain an operation result signal. AND gate 570 outputs the operation result signal to demultiplexer 550.

  The demultiplexer 550 receives the selection control signal SEL from the counter 540 and the operation result signal from the AND gate 570. The demultiplexer 550 selects any of the counters 560-1, 560-2,..., 560 -M / N according to the selection control signal SEL, and outputs an operation result signal to the selected counter 560. The counter 560 counts up by one according to the calculation result signal.

  When the transfer signal MOUT is “1”, the operation result signal coincides with the clock signal CLK, so that the selected counter 560 counts up. On the other hand, when the transfer signal MOUT is “0”, the calculation result signal also remains “0”, so the selected counter 560 does not count up. Since the value indicated by the selection control signal SEL is incremented by one, all the counters 560-1, 560-2,..., 560-M / N sequentially correspond to one row of the subarray 310. An operation result signal based on the binary information of the minute is given.

Therefore, the counters 560-1, 560-2,..., 560 -M / N are generated by the pixels 100 corresponding to one row of the corresponding subarray 310 in the operation of one cycle illustrated in FIG. The total number of “1” included in the binary information can be counted. Then, by repeating the same operation for the remaining N-1 rows of pixels 100 over N-1 cycles, the counters 560-1, 560-2,. A sum signal DOUT _N , DOUT _2N ,..., DOUT _M indicating the total number of “1” included in the binary information generated by all the pixels 100 of the corresponding subarray 310 can be obtained.

  As described above, the image sensor according to the third embodiment shares one adder circuit in the entire pixel array. Therefore, according to this imaging device, an adder circuit can be realized using one demultiplexer regardless of the number of columns of the pixel array, so that the circuit area can be suppressed.

(Fourth embodiment)
As described above, the offset voltage of the comparator 120 follows a normal distribution of, for example, average value = 0, and therefore if the total number of comparators 120 used is sufficiently large, the total number of comparators 120 that output “1”. (N ₁ ) can be handled as multi-value pixel data. However, the relationship between the total number of comparator 120 to output a pixel voltage and a "1" (N _1), as can be seen from the above equation (1) and 3, perfectly particular upper limit and the lower limit of N ₁ not linear It is distorted in the vicinity.

  Therefore, the image sensor according to the fourth embodiment corrects the total number of comparators 120 that output “1” in the subarray 310 by using the inverse function of the function obtained by integrating the normal distribution. To be linear. Alternatively, a function obtained by integrating the normal distribution can be approximated by a line function, and correction can be performed using this line function. The latter correction has a larger error than the former correction, but the calculation is simplified. Such correction processing can be performed by, for example, a correction circuit 650 disposed at the subsequent stage of the addition circuit 200 as shown in FIG.

  As described above, the image sensor according to the fourth embodiment calculates the total number of comparators that output “1” in the subarray by using the inverse function of the function obtained by integrating the normal distribution or the line function approximating the function. Use to correct. Therefore, according to this imaging device, the relationship between the pixel voltage and the multivalued pixel data can be made substantially linear.

(Fifth embodiment)
In general, the range of the pixel voltage output from a photodiode depends on the length of exposure time for accumulating charges generated in the photodiode. For example, even if the incident light intensity is the same, the pixel voltage increases because more charge is accumulated in the photodiode if the exposure time is longer.

  The allowable range of the pixel voltage in the image sensor according to each embodiment has a width determined by the standard deviation of the offset voltage of the comparator 120 with the reference voltage as the center. For example, if the exposure time is too long, the pixel voltage may exceed the upper limit of the allowable range and the pixel data may be saturated, as shown in FIG. On the other hand, if the exposure time is too short, as illustrated in FIG. 19, the pixel voltage changes in a small part of the allowable range, so that the dynamic range of the pixel data becomes narrow.

  Therefore, the imaging device according to the fifth embodiment secures a large dynamic range while avoiding saturation of pixel data as illustrated in FIG. 20 by controlling the exposure time to an appropriate length. In other words, this imaging device brings the range in which the pixel voltage changes closer to the allowable range.

  As illustrated in FIG. 18, the imaging device according to the fifth embodiment includes a pixel array 300, a reference voltage generation circuit 320, a vertical selection register 330, a horizontal transfer register 340, a column circuit 760, and exposure. A time control circuit 770 and a timing control circuit 780 are included.

  The column circuit 760 can include, for example, the above-described comparator 120, addition circuit 200, correction circuit 650, and the like.

  The exposure time control circuit 770 inspects the pixel data of each subarray 310 output from the horizontal transfer register 340. When the pixel data of any of the subarrays 310 is saturated, the exposure time control circuit 770 shortens the exposure time, and the image sensor in FIG. 18 performs imaging again. For example, the exposure time is set to the maximum length in the initial setting, and the exposure time control circuit 770 reduces the exposure time to an appropriate length (until the pixel data of all the subarrays 310 are not saturated). The operation may be repeated.

  The timing control circuit 780 performs, for example, control on the adder circuit 200, control on the horizontal transfer register 340 that serially transfers the output of the adder circuit 200 using a shift register, etc., and selection control on the readout row of the pixel array 300.

  As described above, the image sensor according to the fifth embodiment controls the exposure time to an appropriate length. Therefore, according to this imaging device, a large dynamic range can be secured while avoiding saturation of pixel data.

(Sixth embodiment)
As described above, the offset voltage of the comparator 120 follows, for example, a normal distribution with an average value = 0, and uses the above formula (1) to calculate the pixel voltage and the total number (N ₁ ) of the comparators 120 that output “1”. Can describe the relationship.

  However, in practice, the average value of the offset voltage of the comparator 120 depends on the circuit configuration of the comparator 120 and is not necessarily zero. For example, the average value of the offset voltage of the differential amplifier type comparator 120 illustrated in FIG. However, the offset voltage of the comparator 120 including one transistor as shown in FIG. 5 and the single-ended comparator 120 as shown in FIG. 7 is affected by the average value of the threshold voltages of the transistors. Therefore, the average value of the offset voltage of these comparators 120 varies due to process variations.

  When the average value of the offset voltage is expressed by μ, the above formula (1) can be rewritten as the following formula (2).

FIG. 23 illustrates the relationship between the differential voltage (V _PD −V _REF ) and the total number (N ₁ ) of the comparators 120 that output “1” when μ = 0. In the graph of FIG. 23, the above relationship is substantially linear from the minimum value V _{PD_Min} of the pixel voltage to the maximum value V _{PD_MAX} . On the other hand, FIG. 24 illustrates the relationship between the differential voltage (V _PD −V _REF ) and the total number (N ₁ ) of the comparators 120 that output “1” when μ> 0. Compared with the graph of FIG. 23, the graph of FIG. 24 has a large distortion near the minimum value V _{PD_Min} of the pixel voltage, and the range in which the above relationship is linear is narrow.

  Therefore, the image sensor according to the sixth embodiment adjusts the magnitude of the reference voltage so as to cancel μ. In other words, the imaging device adjusts the reference voltage so that the sum of the reference voltage and the average value of the offset voltage approaches the intermediate value (average value of the maximum value and the minimum value) of the pixel voltage. Therefore, according to this image sensor, as illustrated in FIG. 25, a range in which the above relationship is linear can be ensured to the same extent as when μ = 0, regardless of the size of μ.

  As illustrated in FIG. 22, the imaging device according to the sixth embodiment includes a pixel array 300, a reference voltage generation circuit 820, a vertical selection register 330, a horizontal transfer register 340, a column circuit 760, and a timing. And a control circuit 880.

  If the average value of the offset voltage is known, the reference voltage generation circuit 820 may set the magnitude of the reference voltage to, for example, a value obtained by subtracting the average value from the intermediate value of the pixel voltage. Alternatively, the reference voltage generation circuit 820 may perform negative feedback control on the magnitude of the reference voltage based on the pixel data of each subarray 310 output from the horizontal transfer register 340. That is, when the pixel data of any of the sub-arrays 310 is saturated, the reference voltage generation circuit 820 increases (if the pixel data is saturated at the upper limit) or decreases (the pixel data is saturated at the lower limit). 22), the image pickup device in FIG. 22 picks up an image again. For example, in the initial setting, the reference voltage is set to a predetermined magnitude (for example, the same as the intermediate value of the pixel voltage), and the reference voltage generation circuit 820 adjusts the reference voltage to an appropriate magnitude (all The operation may be repeated (until the pixel data of the subarray 310 is no longer saturated).

  As described above, the image sensor according to the sixth embodiment controls the reference voltage to an appropriate magnitude. Therefore, according to this imaging device, even when the average value of the offset voltage of the comparator is not 0, the range in which the relationship between the pixel voltage and the total number of comparators 120 that output “1” is linear is described above. It can be ensured to the same extent as when the average value is zero.

(Seventh embodiment)
As described above, the allowable range of the pixel voltage in the image sensor according to each embodiment has a width determined by the standard deviation of the offset voltage of the comparator with the reference voltage as the center. Within this allowable range, the total number of comparators that output “1” increases or decreases according to the change in pixel voltage. On the other hand, outside this tolerance, the total number of comparators that output “1” saturates and does not change regardless of the change in pixel voltage.

  Specifically, the allowable range of the pixel voltage is about ± 2 to 3 times the standard deviation of the offset voltage of the comparator with the reference voltage as the center. Here, since the standard deviation of the comparator offset voltage depends on the circuit configuration of the comparator, it is not easy to extend the width of the allowable range itself. On the other hand, the center of the allowable range can be shifted by changing the magnitude of the reference voltage. As an example, a pixel voltage that exceeds an upper limit of an allowable range centered on the first reference voltage can be included in an allowable range centered on a second reference voltage that is higher than the first reference voltage. .

  Therefore, the imaging device according to the seventh embodiment prepares a plurality of reference voltages having different sizes, and each comparator 120 compares the plurality of reference voltages with the pixel voltage. The image sensor calculates the total number of comparators 120 that output “1” for each reference voltage, and averages the total number to obtain pixel data. The use of a plurality of reference voltages can be realized by switching a reference voltage generation circuit 921 and a reference voltage generation circuit 922 that generate reference voltages having different magnitudes using a switch 923 as illustrated in FIG. is there. According to this imaging device, as will be described below, a plurality of probability density distributions centered on each of the plurality of reference voltages are combined, so that the allowable range of the pixel voltage can be substantially expanded. .

  First, the above formula (1) can be rewritten into the following formula (3).

Here, for simplification, the following formula (4) is obtained by substituting N ² = 1 and σ = 1 into the probability density function integrated in the formula (3).

The probability density function in the case of V _REF = 0, ± 1, ± 3 is illustrated in FIG.

For example, when two reference voltages of V _REF = ± 1 are prepared and two probability density functions centered on each of these reference voltages are synthesized (averaged), the following formula (5) is obtained.

  Further, when four reference voltages VREF = ± 1 and ± 3 are prepared and four probability density functions centered on each of these reference voltages are synthesized (averaged), the following formula (6) is obtained.

  These synthesized probability density functions f2 (x) and f3 (x) are plotted in FIG. 28 for comparison with the probability density function f1 (x, 0).

Pixel data h1 (V _PD ), h2 (V _PD ), and h3 (V _PD ) when the probability density functions f1 (x, 0), f2 (x), and f3 (x) plotted in FIG. 28 are used. Can be calculated by the following equation (7).

The pixel data h1 (V _PD ), h2 (V _PD ), and h3 (V _PD ) are plotted in FIG. 29, respectively. As shown in FIG. 29, the allowable range of the pixel voltage can be expanded by using more reference voltages. It should be noted that the allowable range of the pixel voltage can be further expanded by using more reference voltages than described here.

  As described above, the image sensor according to the seventh embodiment compares a pixel voltage with a plurality of reference voltages, and calculates the total number of comparators that output “1” for each reference voltage. Then, pixel data is calculated by averaging these total numbers. Therefore, according to this image sensor, a plurality of probability density distributions centered on each of the plurality of reference voltages are combined, so that the allowable range of the pixel voltage can be substantially expanded.

(Eighth embodiment)
The image sensor according to each of the above-described embodiments generates multivalued pixel data for each subarray including a plurality of pixels. Therefore, the resolution of the output image read from the image sensor is lower than the total number of pixels in the pixel array. For example, if the pixel array is vertical 3840 pixels × horizontal 5120 pixels and the sub-array is 16 pixels × 16 pixels, the resolution of the output image read from the image sensor is vertical 240 pixels × horizontal 320 pixels. These relationships can be generalized by the following mathematical formula (8).

In Equation (8), N _image represents the total number of pixels of the output image that can be read from the image sensor, H and V represent the number of pixels in the horizontal and vertical directions of the pixel array, and N ² represents the total number of sub-arrays. Represents the number of pixels.

  According to Equation (8), the total number of pixels of the output image that can be read from the image sensor can be improved by reducing the total number of pixels in the subarray. However, when the total number of pixels in the subarray is reduced, the total number of comparators used by the subarray is also reduced, so that the gradation of pixel data becomes coarse. Further, as the total number of comparators decreases, the offset voltage distribution of the comparators deviates from the normal distribution, so that the linearity of the relationship between the pixel voltage and the pixel data is likely to be impaired.

With reference to the non-patent document 1, the following equation (9) is established between the total number n _c of the comparator to be used by the effective resolution ENOB and subarray.

Here, since n _c = N ² , the following formula (10) can be derived from the above formula (8) and formula (9).

According to Equation (10), the higher the effective resolution ENOB, the smaller the total number of pixels N _image of the output image that can be read from the image sensor. For example, in order to realize an effective resolution of 5.5 bits, 4096 comparators are used by each subarray according to Equation (9) above. That is, the sub-array needs to include 4096 pixels, for example, vertical 64 pixels × horizontal 64 pixels. When this subarray is used, when the pixel array is vertical 3840 pixels × horizontal 5120 pixels, the resolution of the output image read from the image sensor is 60 vertical pixels × 80 horizontal pixels.

  Therefore, the image sensor according to the eighth embodiment allows the pixel array to be divided using a plurality of subarray division methods. For example, as shown in FIGS. 30A, 30B, 30C, and 30D, if the pixel array is divided by using four types of subarray division methods, the subarray is compared with the case where a single subarray division method is employed. Therefore, the resolution of the output image read from the image sensor is also improved by a factor of four.

  In the first subarray division method illustrated in FIG. 30A, the pixel array is divided into N pixels vertically and horizontally from the left end and the upper end, respectively. In the second sub-array division method illustrated in FIG. 30B, the vertical division position of the pixel array is shifted by N / 2 pixels to the right as compared to FIG. 30A. In the third sub-array division method illustrated in FIG. 30C, the horizontal division position of the pixel array is shifted by N / 2 pixels downward as compared to FIG. 30A. In the fourth sub-array division method illustrated in FIG. 30D, the vertical and horizontal division positions of the pixel array are shifted by N / 2 pixels to the right and N / 2 pixels downward, respectively.

  When the four types of subarray division methods as exemplified in FIGS. 30A, 30B, 30C, and 30D are adopted, the adder circuit in FIG. 13 is modified to the adder circuit exemplified in FIG. Can do.

  In FIG. 31, in order to calculate the sum of binary information from subarrays (FIGS. 30B and 30D) that differ from the subarray obtained by the first subarray division method in the vertical division position, an adder circuit 200-1.5 , 200-2.5, ... are added. That is, the subarray occupying the N / 2 + 1th column to the third N / 2th column of the pixel array 300 is connected to the adder circuit 200-1.5, and the subarray occupying the third N / 2 + 1th column to the fifth N / 2th column is the adder circuit 200. Connected to -2.5.

  For the subarrays (FIGS. 30C and 30D) that differ from the subarray obtained by the first subarray division method in the horizontal division position, the operation timing of the vertical selection register 330 and the operation timing of the adder circuit 200 in FIG. By appropriately modifying, the total sum of the binary information can be calculated appropriately.

  As described above, the imaging device according to the eighth embodiment divides a pixel array using a plurality of different subarray division methods, and the number of subarrays that can be used in the pixel array without reducing the subarray. Is substantially increased. Therefore, according to this image sensor, the resolution of the output image can be improved without sacrificing the effective resolution.

(Ninth embodiment)
The imaging device according to the eighth embodiment described above achieves an improvement in the resolution of the output image by using a plurality of different subarray division methods. However, the resolution of the output image in the case of generating pixel data for each subarray is still lower than the method of generating multivalued pixel data for each pixel.

  Therefore, in addition to the image sensors according to the first to eighth embodiments, the image sensor according to the ninth embodiment performs additional reading for generating multivalued pixel data for each pixel. Provide a circuit. That is, this image sensor can provide a low power consumption shooting mode and a high resolution shooting mode in a selectable manner. Therefore, the user selects a shooting mode for generating pixel data for each sub-array when reduction of power consumption is desired rather than improvement of resolution, and for each pixel when improvement of resolution is desired rather than reduction of power consumption. A photographing mode for generating pixel data may be selected.

  The additional readout circuit may include, for example, an analog / digital converter (ADC) that generates pixel data for each pixel by performing analog / digital conversion of the pixel voltage, and time information corresponding to the pixel voltage is obtained. A time digital converter (TDC) that generates pixel data for each pixel by time / digital conversion may be included.

  Note that specific types of ADCs and TDCs use a comparator to achieve conversion. When the additional readout circuit includes such a converter, the converter 120 and the photodiode 110 included in the pixel 100 may share the comparator 120 as illustrated in FIG. Since the converter and the photodiode 110 share the comparator 120, the circuit area can be reduced.

  In the example of FIG. 32, the additional readout circuit includes a single slope ADC (SSADC). However, the additional readout circuit is not limited to the SSADC, and may include other types of ADCs using a comparator (for example, successive approximation ADCs, cyclic ADCs, etc.).

  As described above, the image sensor according to the ninth embodiment is provided for each pixel in addition to the imaging mode for generating pixel data for each subarray as in the first to eighth embodiments. A shooting mode for generating pixel data is provided. Therefore, according to this imaging device, it is possible to perform photographing that matches the user's request. Further, when an additional readout circuit that realizes a photographing mode for generating pixel data for each pixel includes an ADC or TDC using a comparator, the ADC or TDC and the photodiode included in the pixel share the comparator. To do. By sharing the comparator, the circuit area can be reduced.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 100 ... Pixel 110 ... Photodiode 120 ... Comparator 200, 500 ... Adder circuit 210 ... Multiplexer 220, 570, 1110 ... AND gate 230, 260, 540, 560, 1120 ..Counter 240,510 ... Control circuit 250,520 ... Oscillator circuit 300 ... Pixel array 310 ... Subarray 320,820,921,922 ... Reference voltage generation circuit 330 ... Vertical selection Registers 340, 440 ... Horizontal transfer register 530 ... 1 / N frequency divider 550 ... Demultiplexer 650 ... Correction circuit 760 ... Column circuit 770 ... Exposure time control circuit 780, 880, 980 ... Timing control circuit 923 ... Switch

Claims (11)

Comprising a pixel array in which a plurality of pixels are arranged in an array;
The pixel array can be divided into a plurality of subarrays each including a plurality of pixels,
The subarray generates multi-value pixel data corresponding to the incident light intensity in the subarray,
The pixel includes a photodetector that generates a pixel voltage corresponding to incident light intensity;
The photodetector is connected to a comparator that compares the pixel voltage with a reference voltage and generates binary information indicating a comparison result;
The multi-value pixel data depends on the total number of “0” or “1” included in the binary information generated by the comparators connected to the plurality of photodetectors in the corresponding subarray.
Image sensor.   The image sensor according to claim 1, wherein the total number of “0” or “1” depends on the pixel voltage, the reference voltage, and a probability density distribution of the offset voltage of the comparator.   The imaging device according to claim 1, wherein the pixel includes a comparator connected to a photodetector included in the pixel.   The imaging device according to claim 1, wherein photodetectors included in a plurality of pixels arranged in the same column in the pixel array are connected to a common comparator.   The imaging device according to claim 1, further comprising a calculation circuit that calculates a total number of the “0” or “1”.   6. The correction circuit according to claim 1, further comprising a correction circuit that corrects the total number of the “0” or “1” so that a relationship between the pixel voltage and the multi-value pixel data is substantially linear. The imaging device according to claim 1.   The imaging device according to claim 1, further comprising a control circuit that shortens an exposure time of the photodetector when the multi-value pixel data is saturated. A generator circuit for generating the reference voltage;
The generation circuit adjusts the reference voltage so as to approach a value obtained by subtracting an average value of the offset voltage of the comparator from an intermediate value of the pixel voltage.
The image sensor according to any one of claims 1 to 7.   The multi-value pixel data is “0” or “1” included in binary information generated when a first reference voltage is applied to a comparator connected to a plurality of photodetectors in a corresponding sub-array. ”And the second number of“ 0 ”or“ 1 ”included in the binary information generated when a second reference voltage different from the first reference voltage is applied to the comparator. The imaging device according to claim 1, wherein the imaging device depends on the total number of the imaging elements. The pixel array is divided into a plurality of first sub-arrays using a first division method, and a second division method that differs from the first division method at at least one division position in the vertical direction and the horizontal direction. Is divided into a plurality of second sub-arrays using
The first subarray generates multi-value pixel data corresponding to the incident light intensity in the first subarray,
The second subarray generates multivalued pixel data corresponding to the incident light intensity in the second subarray.
The image sensor according to any one of claims 1 to 9. A converter that converts the pixel voltage or time information corresponding to the pixel voltage into multi-value pixel data corresponding to incident light intensity in the pixel;
The comparator is shared by the photodetector and the converter;
The image sensor according to any one of claims 1 to 10.