JP2017103489A - Damascene-type magnetic tunnel junction structure comprising horizontal and vertical portions and method of forming the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which MTJ photo and etch processes may cause an undesired slope, corner rounding and undesired film loss, and such damage can impact a contact resistance of the MTJ structure and potentially even expose or damage the MTJ junction.SOLUTION: A method of fabricating a semiconductor device is disclosed that includes forming a metal layer over a device substrate, forming a via in contact with the metal layer, and adding a dielectric layer above the via. The method further includes etching a portion of the dielectric layer to form a trench area, and depositing a perpendicular magnetic tunnel junction (MTJ) structure within the trench area.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates generally to magnetic tunnel junction (MTJ) structures.

  In general, the widespread adoption of portable computing devices and wireless communication devices has increased the demand for high density and low power non-volatile memory. As process technology has improved, it has become possible to manufacture magnetoresistive random access memories (MRAM) based on magnetic tunnel junction (MTJ) devices. Conventional spin torque tunnel (STT) junction devices are typically formed as flat stacked structures. Such devices typically have a two-dimensional magnetic tunnel junction (MTJ) cell with a single magnetic domain. An MTJ cell typically has a bottom electrode, a reference layer formed of a diamagnetic material, a fixed or pinned layer having a magnetic moment fixed or pinned by the reference layer, a tunnel barrier layer (ie, a tunnel oxide layer). , Including a free layer (ie, a ferromagnetic layer having a magnetic moment with a changeable direction), a cap layer, and a top electrode. The direction of the magnetic moment of the free layer relative to the direction of the fixed magnetic moment of the fixed layer determines the data value represented by the MTJ cell.

  Typically, a magnetic tunnel junction (MTJ) cell is formed by depositing multiple layers of material, defining a pattern on the layer, and selectively removing portions of the layer according to the pattern. A conventional STT MTJ cell is an in-plane magnetic moment and is formed to maintain a length to width aspect ratio greater than 1 in order to maintain a magnetic isotropic effect. Conventionally, the aspect ratio of the MTJ cell is maintained by controlling the accuracy of the MTJ pattern and performing the MTJ photo process and etching process. In one particular example, a hard mask may be used to accurately shift and define the MTJ pattern. However, MTJ cell structures can be subject to erosion, which can lead to undesired slopes, rounded corners, and undesired film loss. Such damage can affect the contact resistance of the MTJ structure and can further expose or damage the MTJ junction.

  In certain exemplary embodiments, a method for manufacturing a semiconductor device is disclosed. The method includes forming a metal layer over the device substrate. The method further includes forming a via in contact with the metal layer and adding a dielectric layer over the via. The method also includes etching a portion of the dielectric layer to form a trench region. The method further includes depositing a perpendicular magnetic tunnel junction (MTJ) structure in the trench region.

  In another particular embodiment, a semiconductor device is disclosed that includes a perpendicular magnetic tunnel junction (MTJ) structure disposed in a trench region of the semiconductor device.

  One particular advantage provided by at least some of the disclosed embodiments is that oxidation, erosion is achieved by using trenches to define the dimensions of the vertical MTJ structure without photo / etching the vertical MTJ structure. , And rounding of corners can be reduced. The trench can be formed in an oxide-based substrate that is easier to photoetch than a vertical MTJ metal film. Furthermore, oxide-based substrates are easier to photoetch accurately than metal layers. Reverse trench photoetching and chemical mechanical polishing (CMP) processes are used to remove excess material without causing erosion, corner rounding, or other problems that can affect the performance of the vertical MTJ structure. Can be.

  Another specific advantage is that the process window for the formation of the vertical MTJ structure is improved, i.e. widened, and the overall reliability of the vertical MTJ process and the resulting vertical MTJ structure is also improved.

  Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections, including a brief description of the drawings, a mode for carrying out the invention, and the claims. Let's go.

FIG. 6 is a cross-sectional view illustrating the formation of a trench in a device and illustrating an exemplary embodiment of a perpendicular magnetic tunnel junction (MTJ) disposed in the trench. 1 is a top view of a particular exemplary embodiment of a circuit device including a perpendicular magnetic tunnel junction (MTJ) cell having a substantially rectangular shape. FIG. 3 is a cross-sectional view of the circuit device of FIG. 2 taken along line 3-3 of FIG. FIG. 3 is a top view of a second particular exemplary embodiment of a circuit device including a perpendicular magnetic tunnel junction (MTJ) having a substantially elliptical shape. FIG. 6 is a top view of a third particular exemplary embodiment of a circuit device including a perpendicular magnetic tunnel junction (MTJ). FIG. 6 is a cross-sectional view of the circuit device of FIG. 5 taken along line 6-6 of FIG. 1 is a top view of a particular exemplary embodiment of a storage device including a substrate having a perpendicular magnetic tunnel junction cell adapted to store a plurality of bits. FIG. FIG. 8 is a cross-sectional view of the circuit device of FIG. 7 taken along line 8-8 of FIG. FIG. 9 is a cross-sectional view of the circuit device of FIG. 7 taken along line 9-9 of FIG. FIG. 6 is a top view of another particular exemplary embodiment of a storage device including a substrate having a perpendicular magnetic tunnel junction (MTJ) adapted to store a plurality of bits. FIG. 11 is a cross-sectional view of the storage device of FIG. 10 taken along line 11-11 of FIG. 12 is a cross-sectional view of the storage device of FIG. 10 taken along line 12-12 of FIG. FIG. 4 is a cross-sectional view of a circuit board after deposition of a cap thin film layer and via photo / etching, photoresist stripping, via filling, and via chemical mechanical polishing (CMP) processes. After intermetal dielectric layer (IMD) deposition, cap thin film deposition, trench photo / etch process, bottom electrode deposition, magnetic tunnel junction (MTJ) thin film deposition, top electrode deposition, and reverse photo / etch process FIG. 14 is a cross-sectional view of the circuit board of FIG. 13 showing multiple trenches and multiple vertical MTJ structures. FIG. 15 is a cross-sectional view of the circuit board of FIG. 14 after reverse photoresist stripping and an MTJ CMP process that stops at the cap film layer. 15 is a cross-sectional view of the circuit board of FIG. 15 taken along line 16-16 of FIG. 15 after spin coating a photoresist and photoetching to remove the sidewalls of the vertical MTJ stack and providing a process opening. It is. FIG. 17 is a cross-sectional view of the circuit board of FIG. 16 after filling a process opening with IMD oxide material and a CMP process stopping at the cap layer. FIG. 18 is a cross-sectional view of the circuit board of FIG. 17 taken along line 18-18 of FIG. 17 after first IMD layer deposition, via process, metal film deposition, and surface wiring patterning. 3 is a flow diagram of a particular exemplary embodiment of a method of forming a perpendicular magnetic tunnel junction (MTJ) cell. 2 is a flow diagram of a second particular exemplary embodiment of a method of forming a perpendicular magnetic tunnel junction (MTJ) cell. 2 is a flow diagram of a second particular exemplary embodiment of a method of forming a perpendicular magnetic tunnel junction (MTJ) cell. 1 is a block diagram of an exemplary wireless communication device including a storage device having multiple vertical MTJ cells. 2 is a data flow diagram of a particular exemplary embodiment of a manufacturing process for manufacturing an electronic device including a vertical MTJ cell.

  FIG. 1 is a cross-sectional view illustrating the formation of a trench in a device and an exemplary embodiment of a perpendicular magnetic tunnel junction (MTJ) cell disposed in the trench. Referring to FIG. 1, a cross-sectional view of a particular embodiment of a circuit board is shown after a first stage 192, a second stage 194, and a third stage 196 of the process. The circuit board 100 includes a device substrate 105, a first intermetal dielectric layer (IMD) 101, a wiring 103, and a second intermetal dielectric layer disposed over the first intermetal dielectric layer (IMD) 101. (IMD) 102 is included. In certain embodiments, a photoresist layer can be applied by spin coating the photoresist over the second IMD 102. A photo etch process may be applied to define a trench pattern in the second intermetal dielectric layer 102. The photoresist layer is stripped after etching to expose openings or vias through the second intermetal dielectric layer 102. A conductive material or via filling material 108 is deposited in the openings and a polishing process, such as a CMP process, can be performed to polish the circuit board 100. The trench 114 is defined in the second intermetal dielectric layer 102, for example, by performing a trench photo-etching and cleaning process.

  After the first stage 192, a perpendicular magnetic tunnel junction (MTJ) cell 150 is deposited in the trench 114. The vertical MTJ cell 150 includes a lower electrode 176 coupled to the lower via filling material 108, a vertical MTJ stack 152 coupled to the lower electrode 176, and an upper electrode 170 coupled to the vertical MTJ stack 152. A photoresist layer may be patterned on the upper electrode 170. A reverse MTJ photoetch process is applied to the photoresist layer, top electrode 170, vertical MTJ stack 152, and bottom electrode 176 to remove excess material that is not in or over the trench 114.

  In this particular example, trench 114 is defined to have a trench depth (d). The thickness of the bottom electrode 176 is defined to have an associated vertical MTJ cell depth (c). In one particular example, the vertical MTJ cell depth (c) is approximately equal to the trench depth (d) minus the thickness of the bottom electrode 176.

  In general, by making vertical MTJ cell 150 in trench 114, the dimensions of trench 114 define the dimensions of vertical MTJ cell 150. In addition, because the trench 114 defines the dimensions of the vertical MTJ cell 150, the vertical MTJ cell 150 can be formed without performing a critical and expensive photo-etching process on the vertical MTJ cell 150. Reduce the problems associated with 150 related to oxidation, rounding of corners, and other erosion.

  In certain embodiments, the vertical MTJ cell 150 includes a vertical MTJ stack 152 that includes a free layer 154, a tunnel barrier layer 156, and a pinned layer 158. The free layer 154 of the vertical MTJ stack 152 is coupled to the upper electrode 170 via the cap layer 180. In this example, the pinned layer 158 of the vertical MTJ stack 152 is coupled to the lower electrode 176 via the reference layer 178. In certain embodiments, the reference layer 178 can include platinum.

  Reference layer 178 and pinned layer 158 have respective magnetic domains 107 and 109 oriented in the same direction. The free layer 154 includes magnetic domains 111 that are programmable via a write current (not shown). From this particular point of view, the magnetic domains 107, 109, and 111 are oriented vertically. In other embodiments, additional layers may be included such as one or more seed layers, buffer layers, stray field balance layers, connection layers, performance improvement layers, such as an integrated pinned layer, An integrated free (SyF) layer, a dual spin filter (DSF), or any combination thereof. In certain embodiments, the vertical MTJ cell 150 may include iron / platinum. In another specific embodiment, the vertical MTJ cell can include cobalt / platinum. In yet another specific embodiment, the vertical MTJ cell can include cobalt / nickel.

  After the bottom electrode 176, vertical MTJ stack 152, and top electrode 170 are formed in the trench 114, in a third stage 196, a chemical mechanical polishing (CMP) process is applied to remove the substantially flat surface 112. Form. A third cap layer and a fourth intermetal dielectric layer may be deposited. A photo etch process is applied to define the via 160. The via 160 is filled with a conductive material, and a polishing process such as a via chemical mechanical polishing process may be applied.

  In certain embodiments, the vertical MTJ stack can be in the form of a trench 114. For example, in the particular embodiment shown in FIG. 2, the vertical MTJ stack may have a substantially rectangular shape and the trench region may have a substantially rectangular shape. In another particular embodiment shown in FIG. 3, the vertical MTJ stack may have a substantially U-shaped cross section and the trench region may have a substantially U-shaped cross section. In yet another specific embodiment, as shown in FIG. 8, the vertical MTJ stack may have a substantially L-shaped cross section, and the trench region has a substantially L-shaped cross section. Also good. In yet another specific embodiment, as shown in FIG. 4, at least a portion of the trench may have a substantially curved shape. In certain embodiments, the shape of the vertical MTJ stack can be defined by a trench without etching the MTJ stack.

  A vertical STT MTJ formed in a trench can provide advantages over a planar STT MTJ. For example, a planar STT MTJ has a high attenuation coefficient that increases the switching current. The MTJ switching current also correlates with the MTJ energy barrier and coercive field, which limits the reduction of the MTJ bit cell switching current. As a result, the reduction in the size of planar MRAM bit cells is also limited. However, in the vertical STT MTJ, the energy barrier switching current is substantially uncorrelated with the coercive field and reduces attenuation. Therefore, the energy barrier switching current can be estimated without considering the coercive field. The aspect ratio and isotropic requirements of the shape of the vertical STT MTJ are also relaxed when compared to the planar STT MTJ. As a result, the size of the MRAM bit cell can be reduced. For example, deleterious effects on performance that can limit the sizing of a vertical MTJ due to erosion or corner rounding can be reduced or avoided by forming the vertical MTJ in a trench.

  FIG. 2 is a top view of a particular exemplary embodiment of a circuit device 200 that includes a perpendicular magnetic tunnel junction (MTJ) cell 204 having a substantially rectangular shape. The circuit device 200 includes a substrate 202 having vertical MTJ cells 204. The vertical MTJ cell 204 includes a lower electrode 206, a vertical MTJ stack 208, a center electrode 210, and a via 212. The vertical MTJ cell 204 has a first sidewall 214, a second sidewall 216, a third sidewall 218, and a fourth sidewall 220. The second sidewall 216 includes a second magnetic domain 222 that represents the first data value, and the fourth sidewall 220 includes a fourth magnetic domain 224 that represents the second data value. The bottom wall (not shown) may include a lower magnetic domain 346 (see FIG. 3) that represents another data value. The first side wall 214 and the third side wall 218 may also have magnetic domains depending on the specific implementation.

  The vertical MTJ cell 204 has a length (a) and a width (b). The length (a) corresponds to the length of the second side wall 216 and the fourth side wall 220. The width (b) corresponds to the length of the first side wall 214 and the third side wall 218. In this particular example, the length (a) of the vertical MTJ cell 204 is longer than the width (b). Alternatively, the length (a) of the vertical MTJ cell 204 may be equal to the width (b).

  FIG. 3 is a cross-sectional view 300 of the circuit device 200 of FIG. 2 taken along line 3-3 of FIG. The cross-sectional view 300 includes a substrate 202 shown in cross-section that includes a vertical MTJ cell 204, a via 212, an upper electrode 210, a vertical MTJ stack 208, and a lower electrode 206. The substrate 202 includes a first intermetal dielectric layer 332, a first cap layer 334, a second intermetal dielectric layer 336, a second cap layer 338, a third cap layer 340, and a third intermetal dielectric. Layer 342 is included.

  A trench is formed in the second cap layer 338 and the second intermetal dielectric layer 336 and receives the lower electrode 206, the vertical MTJ stack 208, and the upper electrode 210. The trench has a trench depth (d), and the vertical MTJ stack 208 has a depth (c) approximately equal to the trench depth (d) minus the thickness of the lower electrode 206. Lower via 344 extends through first cap layer 334 and first intermetal dielectric layer 332 and is coupled to lower electrode 206. Via 212 extends from surface 330 of substrate 202 through third intermetal dielectric layer 342 and third cap layer 340 and is coupled to upper electrode 210. The surface 330 may be a substantially flat surface.

  FIG. 4 is a top view of a second particular exemplary embodiment of a circuit device 400 that includes a perpendicular magnetic tunnel junction (MTJ) cell 404 having a substantially elliptical shape. Alternatively, the vertical MTJ cell may have a circular shape. The circuit device 400 includes a substrate 402 having vertical MTJ cells 404. The vertical MTJ cell 404 includes a lower electrode 406, a vertical MTJ stack 408, an upper electrode 410, and vias 412 that extend from a surface (eg, surface 330 shown in FIG. 3) to the upper electrode 410. The vertical MTJ cell 404 includes a first sidewall 416 and a second sidewall 418 that are adapted to have independent magnetic domains 422 and 424, respectively. Each direction of each of the independent magnetic domains 422 and 424 may represent a respective data value. In addition, the vertical MTJ cell 404 may include a bottom wall adapted to have another independent magnetic domain, such as the lower magnetic domain 346 of FIG. 3, which may represent another data value.

  The vertical MTJ cell 404 includes a length (a) and a width (b), and the length (a) is longer than the width (b). Alternatively, the length (a) may be equal to the width (b). In certain embodiments, the cross-sectional view of FIG. 3 may also represent a cross-section taken along line 3-3 of FIG. In this example, as shown in FIG. 3, the vertical MTJ cell 404 can be formed in a trench having a depth (d) so that the vertical MTJ cell 404 has a depth (c). In this particular example, the vertical MTJ cell 404 has a length (a) greater than the width (b) and a width (b) greater than the trench depth (d) or the vertical MTJ cell depth (c). Can be formed. Alternatively, as shown in FIGS. 5 and 6, the MTJ cell 404 has a trench depth (d) that is longer than the vertical MTJ cell depth (c), and the vertical MTJ cell depth (c) is long. The vertical MTJ cell 404 can be formed to be longer than (a).

  FIG. 5 is a top view of a third particular exemplary embodiment of a circuit device 500 that includes a perpendicular magnetic tunnel junction (MTJ) cell 504. The circuit device 500 includes a substrate 502 having vertical MTJ cells 504. The vertical MTJ cell 504 includes a lower electrode 506, a vertical MTJ stack 508, a center electrode 510, and a via 512. Vertical MTJ cell 504 has a first sidewall 514, a second sidewall 516, a third sidewall 518, and a fourth sidewall 520. The second sidewall 516 includes a second magnetic domain 522 that is adapted to represent a first data value, and the fourth sidewall 520 includes a fourth magnetic domain 524 that is adapted to represent a second data value. Including. As shown in FIG. 6, the bottom wall 670 can include a lower magnetic domain 672. The first side wall 514 and the third side wall 518 may also have magnetic domains depending on the specific implementation.

  The vertical MTJ cell 504 has a length (a) and a width (b). The length (a) corresponds to the length of the second side wall 516 and the fourth side wall 520. The width (b) corresponds to the length of the first side wall 514 and the third side wall 518. In this particular example, the length (a) of the vertical MTJ cell 504 is longer than the width (b). Alternatively, the length (a) of the vertical MTJ cell 504 may be equal to the width (b).

  6 is a cross-sectional view of the circuit device of FIG. 5 taken along line 6-6 of FIG. Cross-sectional view 600 includes a substrate 502, shown in cross-section including vertical MTJ cell 504, via 512, top electrode 510, vertical MTJ stack 508, and bottom electrode 506. The substrate 502 includes a first intermetal dielectric layer 632, a first cap layer 634, a second intermetal dielectric layer 636, a second cap layer 638, a third cap layer 640, and a third intermetal dielectric. Layer 642 is included.

  A trench is formed in the second cap layer 638 and the second intermetal dielectric layer 636 and receives the lower electrode 506, the vertical MTJ stack 508, and the upper electrode 510. The trench has a trench depth (d), and the vertical MTJ stack 508 has a depth (c) approximately equal to the trench depth (d) minus the thickness of the lower electrode 506. Lower via 644 extends from bottom surface 690 through first cap layer 634 and first intermetal dielectric layer 632 and is coupled to lower electrode 506. Via 512 extends from top surface 680 of substrate 502 through third intermetal dielectric layer 642 and third cap layer 640 and is coupled to upper electrode 510. The top surface 680 may be a substantially flat surface.

  In certain embodiments, the trench depth (d) is greater than the vertical MTJ cell depth (c), and both the trench depth (d) and the vertical MTJ cell depth (c) are the length of the vertical MTJ cell 504. It is longer than (a). In this particular example, the magnetic domains 522 and 524 are in a direction substantially parallel to the top surface 680 of the substrate 502 and perpendicular to the sidewall (ie, not perpendicular to the direction of the sidewall depth (d)). Extend.

  FIG. 7 is a top view of a particular exemplary embodiment of a storage device 700 including a substrate 702 having a perpendicular magnetic tunnel junction (MTJ) cell 704 that can be configured to store a plurality of data bits. A perpendicular magnetic tunnel junction (MTJ) cell 704 includes a lower electrode 706, a vertical MTJ stack 708, and a center electrode 710. The vertical MTJ cell 704 has a length (a) and a width (b), and the length (a) is equal to or greater than the width (b). The substrate 702 includes an upper via 736 that is coupled to the center electrode 710 and a lower via 732 that is coupled to the lower electrode 706. The substrate 702 also includes a first wiring 734 coupled to the upper via 736 and a second wiring 730 coupled to the lower via 732. The substrate 702 includes a process opening 738. Process opening 738 is an optional step for removing one sidewall of the MTJ.

  The vertical MTJ stack 708 includes a pinned (fixed) magnetic layer having a fixed magnetic domain with a fixed direction, a tunnel barrier layer, and a free magnetic layer having a magnetic domain that can be changed or programmed via a write current. The vertical MTJ stack 708 may also include a reference layer for pinning the pinned magnetic layer. In certain embodiments, the pinned magnetic layer of the perpendicular MTJ stack 708 may include one or more layers. In addition, the vertical MTJ stack 708 can include other layers. The vertical MTJ cell 704 includes a first sidewall 712 having a first magnetic domain 722, a second sidewall 714 having a second magnetic domain 724, and a third sidewall 716 having a third magnetic domain 726. The vertical MTJ cell 704 also includes a bottom wall 870 having a fourth magnetic domain 872 (see FIG. 8). The first magnetic domain 722, the second magnetic domain 724, the third magnetic domain 726, and the fourth magnetic domain 872 are independent. In certain embodiments, the first magnetic domain 722, the second magnetic domain 724, the third magnetic domain 726, and the fourth magnetic domain 872 are configured to represent respective data values. In general, the orientation of magnetic domains 722, 724, 726, and 872 is determined by the stored data value. For example, the value “0” may be represented by a first direction and the value “1” may be represented by a second direction.

  8 is a cross-sectional view 800 of the circuit device 700 of FIG. 7 taken along line 8-8 of FIG. FIG. 800 illustrates a first intermetal dielectric layer 850, a second intermetal dielectric layer 852, a first cap layer 854, a third intermetal dielectric layer 856, a second cap layer 858, and a third cap layer. 860, a fourth intermetal dielectric layer 862, and a fifth intermetal dielectric layer 864 is included. The substrate 702 has a first surface 880 and a second surface 890. The substrate 702 also includes a vertical MTJ structure 704 that includes a vertical MTJ stack 708. The lower electrode 706, the vertical MTJ stack 708, and the upper electrode 710 are disposed in the trench of the substrate 702. The trench has a depth (d).

  The substrate 702 includes a second wiring 730 disposed on the second surface 890. The second wiring 730 is coupled to the lower via 732, and the lower via 732 extends from the second wiring 730 to a part of the lower electrode 706. The substrate 702 also includes first wiring 734 disposed on the first surface 880. The first wiring 734 is coupled to the upper via 736, and the upper via 736 extends from the first wiring 734 to the center electrode 710. Center electrode 710 is coupled to vertical MTJ stack 708. The substrate 702 also includes a process opening 738 that selectively removes a portion of the vertical MTJ structure 704 to deposit an intermetallic dielectric material in the process opening 738, followed by chemical mechanical polishing (CMP). ) Can be formed by performing the process.

  In certain embodiments, the vertical MTJ stack 708 includes a second sidewall 714 having a second magnetic domain 724. The second magnetic domain 724 can be made to represent a second data value. The vertical MTJ stack 708 also includes a bottom wall 870 having a lower magnetic domain 872 that can be made to represent a fourth data value. In one particular example, the data value can be read from the vertical MTJ stack 708 by applying a voltage to the first wire 734 and comparing the current in the second wire 730 with the reference current. Alternatively, the data value can be written to the vertical MTJ stack 708 by applying a write current to one of the first wiring 734 and the second wiring 730. In one particular embodiment, the length (a) and width (b) of the vertical MTJ stack 708 shown in FIG. 7 is longer than the trench depth (d), and the magnetic domain 724 of the second sidewall 714 is: Substantially parallel to the first surface 880 of the substrate 702 and in a horizontal direction (ie, perpendicular to the direction of the sidewall depth (d), but not in the direction of the sidewall length (a) ) And extend.

  FIG. 9 is a cross-sectional view 900 of the circuit device 700 of FIG. 7 taken along line 9-9 of FIG. FIG. 900 illustrates a first intermetal dielectric layer 850, a second intermetal dielectric layer 852, a first cap layer 854, a third intermetal dielectric layer 856, a second cap layer 858, and a third cap layer. 860, a fourth intermetal dielectric layer 862, and a fifth intermetal dielectric layer 864 is included. The substrate 702 has a first surface 880 and a second surface 890. The substrate 702 includes a vertical MTJ structure 704 having a bottom electrode 706, a vertical MTJ stack 708, and a center electrode 710. The substrate 702 also includes first wiring 734 that is disposed and patterned on the first surface 880. The first wiring 734 is coupled to the upper via 736, and the upper via 736 extends from the first wiring 734 to the center electrode 710. The substrate 702 also includes second wiring 730 on the second surface 890. The second wiring 730 is coupled to the lower via 732, and the lower via 732 extends from the second wiring 730 to a part of the lower electrode 706. The vertical MTJ stack 708 includes a first sidewall 716 having a first magnetic domain 726, a third sidewall 712 having a third magnetic domain 722, and a bottom wall 870 having a lower magnetic domain 872. In this particular aspect, the magnetic domains 726 and 722 are oriented horizontally (ie, not perpendicular to the direction of the sidewall depth (d), but in the direction of the sidewall length (a)), and the lower domain 872 is Orients vertically (ie, horizontally in the direction of sidewall length (a), but not in the direction of sidewall depth (d)).

  In certain embodiments, the vertical MTJ stack 708 can be configured to store up to four unique data values. The first data value can be represented by the first magnetic domain 722, the second data value can be represented by the second magnetic domain 724, and the third data value can be represented by the third magnetic domain 726. The fourth data value can be represented by the lower magnetic domain 872. In another particular embodiment, a fourth sidewall having a fourth magnetic domain may be included, and the fourth magnetic domain may represent a fifth data value.

  FIG. 10 is a specific illustration of a storage device 1000 that includes a substrate 1002 having a perpendicular magnetic tunnel junction (MTJ) cell 1004 in a deep trench that can be configured to store multiple data values, such as multiple bits. FIG. 6 is a top view of an exemplary embodiment. A perpendicular magnetic tunnel junction (MTJ) cell 1004 includes a lower electrode 1006, a vertical MTJ stack 1008, and a center electrode 1010. The vertical MTJ cell 1004 includes a length (a) and a width (b), and the length (a) is equal to or greater than the width (b). The substrate 1002 includes an upper via 1036 that is coupled to the center electrode 1010 and a lower via 1032 that is coupled to the lower electrode 1006. The substrate 1002 also includes a first interconnect 1034 coupled to the lower via 1032 and a second interconnect 1030 coupled to the upper via 1036. The substrate 1002 includes a process opening 1038.

  The vertical MTJ stack 1008 has a pinned (fixed) magnetic layer that has a fixed magnetic domain with a fixed direction and can be pinned by a reference layer, a tunnel barrier layer, and a magnetic domain that can be changed or programmed via a write current. Includes a free magnetic layer. In certain embodiments, the pinned magnetic layer of the perpendicular MTJ stack 1008 may include one or more layers. In addition, the vertical MTJ stack 1008 may include other layers. The vertical MTJ cell 1004 includes a first side wall 1012 having a first magnetic domain 1022, a second side wall 1014 having a second magnetic domain 1024, and a third side wall 1016 having a third magnetic domain 1026. The vertical MTJ cell 1004 may also include a bottom wall 1170 having a fourth magnetic domain 1172 (see FIG. 11). The first magnetic domain 1022, the second magnetic domain 1024, the third magnetic domain 1026, and the fourth magnetic domain 1172 are independent. In certain embodiments, the first magnetic domain 1022, the second magnetic domain 1024, the third magnetic domain 1026, and the fourth magnetic domain 1172 are configured to represent respective data values. In general, the orientation of the magnetic domains 1022, 1024, 1026 and 1172 is determined by the stored data values. For example, the value “0” may be represented by a first direction and the value “1” may be represented by a second direction.

  FIG. 11 is a cross-sectional view 1100 of circuit device 1000 of FIG. 10 taken along line 11-11 of FIG. FIG. 1100 shows a first intermetal dielectric layer 1150, a second intermetal dielectric layer 1152, a first cap layer 1154, a third intermetal dielectric layer 1156, a second cap layer 1158, and a third cap layer. A substrate 1002 having 1160, a fourth intermetal dielectric layer 1162, and a fifth intermetal dielectric layer 1164 is included. The substrate 1002 has a first surface 1180 and a second surface 1190. The substrate 1002 also includes a vertical MTJ structure 1004 that includes a vertical MTJ stack 1008. The lower electrode 1006, the vertical MTJ stack 1008, and the upper electrode 1010 are disposed in the trench of the substrate 1002. The trench has a depth (d). In this example, the depth (d) is longer than the width (b) of the side wall 1014.

  The substrate 1002 includes a second wiring 1030 that is disposed on the first surface 1180 and patterned. Second wiring 1030 is coupled to upper via 1036, and upper via 1036 extends from second wiring 1030 to center electrode 1010. Center electrode 1010 is coupled to vertical MTJ stack 1008. The substrate 1002 also includes a first wiring 1034 disposed on the second surface 1190. The first wiring 1034 is coupled to the lower via 1032, and the lower via 1032 extends from the first wiring 1034 to a part of the lower electrode 1006. The substrate 1002 further includes a process opening 1038 that selectively removes a portion of the vertical MTJ stack 1008 to deposit an intermetallic dielectric material in the process opening 1038, followed by chemical mechanical polishing ( It can be formed by performing a CMP) process.

  In certain embodiments, the vertical MTJ stack 1008 includes a second sidewall 1014 having a second magnetic domain 1024. The second magnetic domain 1024 can be adapted to represent a second data value. The vertical MTJ stack 1008 also includes a bottom wall 1170 having a lower magnetic domain 1172 that can be made to represent a fourth data value. In one particular example, the data value can be read from the vertical MTJ stack 1008 by applying a voltage to the second wire 1030 and comparing the current in the first wire 1034 with a reference current. Alternatively, the data value can be written to the vertical MTJ stack 1008 by applying a write current between the first wiring 1034 and the second wiring 1030. In one particular embodiment, the length (a) and width (b) of the vertical MTJ stack 1008 shown in FIG. 10 is shorter than the trench depth (d), and the magnetic domain 1024 possessed by the second sidewall 1014 is: Extending substantially parallel to the first surface 1180 of the substrate 1002 and in the direction of length (a).

  12 is a cross-sectional view 1200 of the circuit device 1000 of FIG. 10 taken along line 12-12 of FIG. FIG. 1200 illustrates a first intermetal dielectric layer 1150, a second intermetal dielectric layer 1152, a first cap layer 1154, a third intermetal dielectric layer 1156, a second cap layer 1158, and a third cap layer. A substrate 1002 having 1160, a fourth intermetal dielectric layer 1162, and a fifth intermetal dielectric layer 1164 is included. The substrate 1002 has a first surface 1180 and a second surface 1190. The substrate 1002 includes a vertical MTJ structure 1004 having a bottom electrode 1006, a vertical MTJ stack 1008, and a center electrode 1010. The substrate 1002 also includes first wiring 1034 that is disposed and patterned on the second surface 1190. The first wiring 1034 is coupled to the lower via 1032, and the lower via 1032 extends from the first wiring 1034 to a part of the lower electrode 1006. The substrate 1002 also includes a second wiring 1030 on the first surface 1180. Second wiring 1030 is coupled to upper via 1036, and upper via 1036 extends from second wiring 1030 to center electrode 1010.

  The vertical MTJ stack 1008 includes a first sidewall 1016 having a first magnetic domain 1026, a third sidewall 1012 having a third magnetic domain 1022, and a bottom wall 1170 having a lower magnetic domain 1172. In this particular aspect, the trench depth (d) is longer than the length (a) and width (b) of the vertical MTJ stack 1008, and the first magnetic domain 1022 and the third magnetic domain 1026 are in a substantially horizontal direction. (I.e., perpendicular to the direction of the sidewall depth (d), but not in the direction of the sidewall length (a)), the fourth magnetic domain 1072 extends in a substantially perpendicular direction (i.e., It extends horizontally in the direction of the side wall length (a) but not in the direction of the side wall depth (d).

  In certain embodiments, the vertical MTJ stack 1008 may be configured to store up to four unique data values. The first data value can be represented by the first magnetic domain 1022, the second data value can be represented by the second magnetic domain 1024, and the third data value can be represented by the third magnetic domain 1026. The fourth data value can be represented by the lower magnetic domain 1172. In another particular embodiment, a fourth sidewall having a fourth magnetic domain may be included, and the fourth magnetic domain may represent a fifth data value.

  FIG. 13 is a cross-sectional view of a circuit board 1300 after deposition of a cap thin film layer and via photoetching, photoresist stripping, via filling, and via chemical mechanical polishing (CMP) processes. The circuit board 1300 is disposed on the first intermetal dielectric layer 1301, the wiring 1303, the second intermetal dielectric layer 1302 disposed on the first intermetal dielectric layer 1301, and the intermetal dielectric layer 1302. The cap thin film layer 1304 is included. In certain embodiments, the photoresist layer was applied by spin coating the photoresist to the cap film layer 1304. A photo-etching process was applied to define the trench pattern in the cap layer 1304 and the intermetal dielectric 1302. The photoresist layer was stripped after etching to expose openings or vias 1306 through the cap thin film layer 1304 and the intermetal dielectric layer 1302. A conductive or via filling material 1308 was deposited in the opening 1306 and a via CMP process was performed to polish the circuit board 1300.

  14 illustrates the deposition of an intermetal dielectric layer, the deposition of a cap thin film, the trench photo-etching process, the stripping of the photoresist in the trench, the deposition of the bottom electrode, the deposition of the perpendicular magnetic tunnel junction (MTJ) thin film, the deposition of the top electrode, And FIG. 14 is a cross-sectional view 1400 of the circuit board 1300 of FIG. 13 showing multiple trenches and multiple vertical MTJ structures after a reverse photoetch process. The circuit board 1300 includes a second intermetal dielectric layer 1302, a cap thin film layer 1304, and a via filling material 1308. A third intermetal dielectric layer 1410 is deposited on the cap thin film layer 1304. A second cap thin film layer 1412 is deposited on the third intermetal dielectric layer 1410. The trench 1414 is defined in the cap thin film layer 1412 and the third intermetal dielectric layer 1410, for example, by performing a trench photoetching and cleaning process. A perpendicular magnetic tunnel junction (MTJ) cell 1416 is deposited in the trench 1414. The vertical MTJ cell 1416 includes a lower electrode 1418 coupled to the lower via filling material 1308, a vertical MTJ stack 1420 coupled to the lower electrode 1418, and an upper electrode 1422 coupled to the vertical MTJ stack 1420. A photoresist layer 1424 is patterned on the upper electrode 1422. A reverse photoetch process is applied to the photoresist layer 1424, the top electrode 1422, the vertical MTJ stack 1420, and the bottom electrode 1418 to remove excess material that is not in the trench 1414. As shown in FIG. 14, a plurality of trenches 1414 may be defined in the cap thin film layer 1412 and the third intermetal dielectric layer 1410, and a vertical MTJ cell 1416 may be deposited in each trench 1414.

  In this particular example, trench 1414 is defined to have a trench depth (d). The thickness of the bottom electrode 1418 is defined to have an associated vertical MTJ cell depth (c). In one particular example, the vertical MTJ cell depth (c) is approximately equal to the trench depth (d) minus the thickness of the bottom electrode 1418.

  In general, by creating vertical MTJ cell 1416 in trench 1414, the dimensions of trench 1414 define the dimensions of vertical MTJ cell 1416. Further, since trench 1414 defines the dimensions of vertical MTJ cell 1416, vertical MTJ cell 1416 can be formed without performing a critical and expensive photo-etching process on vertical MTJ cell 1416, and therefore vertical Reduce problems associated with oxidation, rounded corners, and other erosion associated with MTJ cell 1416.

  FIG. 15 is a cross-sectional view 1500 of the circuit board 1300 of FIG. 14 after reverse photoresist stripping and an MTJ CMP process that stops at the cap film layer. The circuit board 1300 includes a first intermetal dielectric layer 1301, a wiring 1303, a second intermetal dielectric layer 1302, and a first cap layer 1304. Cross-sectional view 1500 includes a second intermetal dielectric layer 1410, a second cap layer 1412, and a vertical MTJ structure 1416. The vertical MTJ structure 1416 has a vertical MTJ cell depth (d) and is formed in a trench 1414 having a trench depth (d). The vertical MTJ structure 1416 includes a lower electrode 1418, a vertical MTJ stack 1420, and an upper electrode 1422 that are coupled to the via filling material 1308. A photoresist strip process is applied and a vertical MTJ chemical mechanical polishing (CMP) process is applied to remove a portion of the vertical MTJ structure 1416 to produce a substantially flat surface 1530. The CMP process stops at the second cap film layer 1412.

  FIG. 16 is a cross-sectional view 1600 of circuit board 1300 of FIG. 15 taken along line 16-16 of FIG. 15 after photoresist has been spin-coated and patterned and vertical MTJ sidewall etching has been performed. is there. Sidewall etching is an optional process step. The circuit board 1300 includes a first intermetal dielectric layer 1301, a wiring 1303, a second intermetal dielectric layer 1302, a first cap thin film layer 1304, and a via filling material 1308. A third intermetal dielectric layer 1410 and a second cap layer 1412 are deposited on the first cap thin film layer 1304. A trench 1414 is defined in the second cap layer 1412 and the second intermetal dielectric layer 1410. The lower electrode 1418, the vertical MTJ stack 1420, and the upper electrode 1422 are formed in the trench 1414. A chemical mechanical polishing (CMP) process is applied to produce a substantially flat surface 1530. Photoresist layer 1646 is spin coated and process pattern openings 1652 are defined using a photoetch process. The photo-etching process removes the sidewalls from the vertical MTJ cell 1416, resulting in a substantially U-shaped vertical MTJ cell 1416 (viewed from above).

  FIG. 17 illustrates the circuit board 1300 shown in FIG. 16 after deposition of intermetal dielectric material into the process opening 1652, execution of a chemical mechanical polishing (CMP) process, and deposition of the third cap layer 1644. FIG. The circuit board 1300 includes a first intermetal dielectric layer 1301, a wiring 1303, a second intermetal dielectric layer 1302, a first cap thin film layer 1304, and a via filling material 1308. A third intermetal dielectric layer 1410 and a second cap layer 1412 are deposited on the first cap thin film layer 1304. A trench 1414 is defined in the second cap layer 1412 and the second intermetal dielectric layer 1410. The lower electrode 1418, the vertical MTJ stack 1420, and the upper electrode 1422 are formed in the trench 1414. A chemical mechanical polishing (CMP) process is applied to recover the substantially flat surface 1530. A process opening 1652 is defined using a photoetching process. The photo-etching process removes the sidewalls from the vertical MTJ cell 1416, resulting in a substantially U-shaped vertical MTJ cell 1416 (viewed from above). Process opening 1652 is filled with intermetal dielectric material 1748 and a CMP process is performed to recover substantially flat surface 1530 and third cap layer 1644 is overlying substantially flat surface 1530. It is deposited on.

  FIG. 18 is a cross-sectional view 1800 of a circuit board 1300 that may be coupled to other circuits. The circuit board 1300 includes a first intermetal dielectric layer 1301, a wiring 1303, a second intermetal dielectric layer 1302, a first cap thin film layer 1304, and a via filling material 1308. A third intermetal dielectric layer 1410 and a second cap layer 1412 are deposited on the first cap thin film layer 1304. A trench 1414 is defined in the second cap layer 1412 and the second intermetal dielectric layer 1410. The lower electrode 1418, the vertical MTJ stack 1420, and the upper electrode 1422 are formed in the trench 1414. A chemical mechanical polishing (CMP) process is applied to recover the substantially flat surface 1530. A third cap layer 1644 and a fourth intermetal dielectric layer 1646 are deposited. A photoetching process is applied to define a via 1860 through the fourth intermetal dielectric layer 1646 and the third cap layer 1644. The via 1860 is filled with a conductive material and a via chemical mechanical polishing process is applied. Metal interconnect 1862 is deposited and patterned on the fourth intermetal dielectric layer 1646, and a fifth intermetal dielectric layer 1848 is deposited. When a damascene process is used, vias and metal interconnects can be combined to perform trench patterning, copper plating, and copper CMP in fifth intermetal dielectric layer 1848 and fourth intermetal dielectric layer 1646. . In certain embodiments, another chemical mechanical polishing process may be performed to polish the circuit device. At this stage, the wiring 1303 and the wiring 1862 may be coupled to other circuits and the vertical MTJ cell 1416 may be used to store one or more data values.

  FIG. 19 is a flow diagram of a particular exemplary embodiment of a method of forming a vertical MTJ cell, such as the perpendicular magnetic tunnel junction (MTJ) cell 150 of FIG. At 1902, a metal layer such as the wiring 103 of FIG. 1 is formed over a device substrate such as the device substrate 105 of FIG. Proceeding to 1904, vias are formed and contact the metal layer. In certain embodiments, the vias may be formed using a photo etch process, a photoresist strip process, and a cleaning process, and are filled with a conductive material, such as the conductive material 108 of FIG. Moving to 1906, a dielectric layer, such as the second dielectric layer 336 of FIG. 3, is added over the via. Continuing to 1908, a trench region, such as trench 114 of FIG. 1, is formed by etching a portion of the dielectric layer. Proceeding to 1910, after forming the trench region, a perpendicular magnetic tunnel junction (MTJ) structure, such as the vertical MTJ stack 152 of FIG. 1, is deposited in the trench region. The vertical MTJ structure may include a barrier layer such as the barrier layer 156 of FIG. 1 between a free layer such as the free layer 154 of FIG. 1 and a fixed layer such as the fixed layer 158 of FIG. In certain embodiments, at least one of the pinned layer and the free layer has a magnetic moment proximate to the bottom surface of the trench and substantially perpendicular to the bottom surface of the trench. The vertical MTJ structure may further include a reference layer, such as reference layer 178 of FIG. 1, having a magnetic moment substantially perpendicular to the bottom surface of the trench and proximate to the bottom surface of the trench. Proceeding to 1912, an upper electrode, such as the upper electrode 170 of FIG. 1, is formed over the vertical MTJ structure.

  Moving to 1914, the vertical MTJ structure can be polished. Polishing can be performed without performing a photo-etching process on the vertical MTJ structure. The polishing process may include performing a chemical mechanical polishing (CMP) process to remove excess material, including a portion of the electrode material outside the trench. In certain embodiments, polishing the vertical MTJ structure may include removing the deposited material from the substrate and defining a substantially flat surface.

  Continuing to 1916, a magnetic annealing process may be performed to determine the direction of the magnetic field of the fixed layer, such as the magnetic domain 109 of FIG. The magnetic annealing process may be a three-dimensional (3D) annealing process. All perpendicular MTJ layers may be annealed via a magnetic annealing process, pinning the pinned layer while allowing the free layer to be adjusted by the write current.

  In certain embodiments, as shown in FIG. 14, multiple trenches may be formed, and the step of depositing the vertical MTJ structure is performed by forming an MTJ layer in each of the multiple trenches. Polishing may be performed by a CMP process to remove excess material outside each of the plurality of trenches without etching the MTJ layer of the MTJ structure to form a plurality of substantially similar MTJ devices. it can.

  FIG. 20 is a flow diagram of a second particular exemplary embodiment of a method of forming a perpendicular magnetic tunnel junction (MTJ) cell. At 2002, a cap film layer, such as the cap film layer 1304 of FIG. 14, is deposited on the intermetal dielectric layer (IMD) of the device, such as the second IMD layer 1302 of FIG. Proceeding to 2004, vias are formed using a photo-etching process, a photoresist strip process, and a cleaning process. Following 2006, vias or openings are filled with a conductive material, such as conductive material 1308 of FIG. 14, and a chemical mechanical polishing (CMP) process is performed to remove excess conductive material. Moving to 2008, a cap layer, such as the second cap layer 1412 of FIG. 14, is deposited over the via. Continuing to 2010, a trench, such as trench 1414 of FIG. 14, having dimensions that determine the vertical MTJ structure is defined without performing a photo-etching process on the vertical MTJ structure. Proceeding to 2012, a lower electrode, such as the lower electrode 1418 of FIG. 14, is deposited. Continuing to 2014, a plurality of perpendicular magnetic tunnel junction (MTJ) thin film layers, including a magnetic thin film and a tunnel barrier layer, are deposited to form a vertical MTJ stack, such as the perpendicular magnetic tunnel junction (MTJ) stack 1420 of FIG. Continuing to 2016, an upper electrode, such as the upper electrode 1422 of FIG. 14, is deposited over the vertical MTJ stack to form a vertical MTJ cell. Proceeding to 2018, a reverse photoetch process is performed to remove excess material that does not directly cover the trench. At 2020, a CMP process is performed to remove excess material on the second cap layer. Proceeding to 2022, the vertical MTJ stack is photo-etched to remove one sidewall of the vertical MTJ stack. In certain embodiments, the photo-etching of the vertical MTJ stack defines a process window or process opening. The method proceeds to 2024.

  Referring to FIG. 21, at 2024, the method proceeds to 2126 and a magnetic annealing process is performed on the vertical MTJ stack to direct the magnetic moment. Moving to 2128, a third cap film layer, such as the third cap layer 1644 of FIG. 18, is deposited over the second cap film layer and a second, such as the fourth IMD layer 1646 of FIG. Of IMD is deposited over the third cap film layer. Proceeding to 2130, a second via, such as via 1860 in FIG. 18, is formed using a photo-etching process, and the second via or opening is filled with a conductive material. Proceeding to 2132, a CMP process is performed to polish the conductive material. Continuing to 2134, a metal interconnect deposits a metal layer and photoetches the layer to form the interconnect, or trenches are formed, photoetched, plated, and a chemical mechanical polishing (CMP) process. By doing so, it can be defined. If a damascene process is used, the via process at 2132 and the metal interconnect process at 2134 may be combined as a defined trench photo / etch, photoresist strip, copper plating, and copper CMP process. The method ends at 2136.

  FIG. 22 is a block diagram of an exemplary wireless communication device 2200 that includes a storage device having multiple vertical MTJ structures. The communication device 2200 includes a vertical MTJ structure memory array 2232 disposed in the trench region and a magnetoresistive random access memory (MRAM) 2266 including an array of vertical MTJ structure disposed in the trench region, These memory arrays and MRAM are coupled to a processor such as a digital signal processor (DSP) 2210. The DSP 2210 is coupled to a computer readable medium such as a memory 2231 that stores computer readable instructions such as software 2233. Communication device 2200 also includes a vertical MTJ structure cache memory device 2264 disposed in a trench region coupled to DSP 2210. A vertical MTJ structure cache memory device 2264 disposed in the trench region, a vertical MTJ structure memory array 2232 disposed in the trench region, and a plurality of vertical MTJ structures disposed in the trench region. MRAM device 2266 may include a vertical MTJ cell formed according to a process as described with respect to FIGS.

  FIG. 22 also shows a display controller 2226 coupled to the digital signal processor 2210 and the display 2228. A coder / decoder (CODEC) 2234 may also be coupled to the digital signal processor 2210. Speaker 2236 and microphone 2238 may be coupled to codec 2234.

  FIG. 22 also illustrates that the wireless controller 2240 can be coupled to a digital signal processor 2210 and a wireless antenna 2242. In one particular embodiment, input device 2230 and power source 2244 are coupled to system-on-chip system 2222. Moreover, in certain embodiments, the display 2228, input device 2230, speaker 2236, microphone 2238, wireless antenna 2242, and power source 2244 are external to the system-on-chip system 2222, as shown in FIG. However, each of these may be coupled to a component of the system on chip system 2222, such as an interface or controller.

  The disclosed devices and functions described above (eg, the device of FIGS. 1-18, the method of FIGS. 19-21, or any combination thereof) can be stored in a computer file (eg, RTL, GDSII, GERBER, etc.) can be designed and configured. Some or all of such files may be given to a manufacturing person who manufactures a device based on such files. The resulting product includes a semiconductor wafer, which is then cut into semiconductor dies and packaged into semiconductor chips. The semiconductor chip is used in an electronic device. FIG. 23 illustrates certain exemplary embodiments of an electronic device manufacturing process 2300.

  The physical device information 2302 is received in the manufacturing process 2300, such as by the research computer 2306. The physical device information 2302 has a vertical MTJ structure disposed in the trench region as shown in any of FIGS. 1 to 18, or is formed according to any of FIGS. 19 to 21. Design information representing at least one physical characteristic of a semiconductor device, such as an MTJ device, may be included. For example, physical device information 2302 may include physical parameters, material properties, and structural information input via a user interface 2304 coupled to research computer 2306. Research computer 2306 includes a processor 2308, such as one or more processing cores, coupled to a computer-readable medium, such as memory 2310. The memory 2310 may store computer readable instructions executable to cause the processor 2308 to convert the physical device information 2302 to conform to the file format and generate a library file 2312.

  In certain embodiments, the library file 2312 includes at least one data file that includes converted design information. For example, the library file 2312 has a vertical MTJ structure disposed in a trench region as shown in any of FIGS. 1-18, or is formed according to any of FIGS. 19-21. A library of semiconductor devices, including MTJ devices, may be included and provided for use with electronic design automation (EDA) tool 2320.

  The library file 2312 may be used with an EDA tool 2320 in a design computer 2314 that includes a processor 2316 such as one or more processing cores coupled to a memory 2318. The EDA tool 2320 is stored in the memory 2318 as processor-executable instructions, and a user of the design computer 2314 uses a vertical MTJ device such as that shown in any of FIGS. Alternatively, a circuit formed according to any of FIGS. 19-21 may be designed. For example, a user of design computer 2314 can input circuit design information 2322 via user interface 2324 coupled to design computer 2314. The circuit design information 2322 has a vertical MTJ structure disposed in the trench region as shown in any of FIGS. 1 to 18, or is formed according to any of FIGS. 19 to 21. Design information representing at least one physical characteristic of a semiconductor device, such as a device, may be included. Illustratively, circuit design characteristics include identification of a particular circuit in the circuit design and relationships with other elements, position information, shape size information, interconnect information, or other information representing the physical characteristics of a semiconductor device. Can be included.

  Design computer 2314 may be configured to convert design information including circuit design information 2322 to be compatible with the file format. Illustratively, the file format is a database binary that represents planar geometry, string labels, and other information about circuit layout in a hierarchical format such as the Graphic Data System (GDSII) file format. Can include the format of the file. The design computer 2314 adds information describing the vertical MTJ device shown in any of FIGS. 1-18 or formed according to any of FIGS. 19-21 in addition to other circuitry or information. It may be configured to generate a data file that includes the converted design information, such as a GDSII file 2326. Illustratively, including a vertical MTJ device having a vertical MTJ structure disposed in a trench region as shown in any of FIGS. 1-18, or formed according to any of FIGS. The data file may include information corresponding to a system on chip (SOC), including additional electronic circuitry and components therein.

  The GDSII file 2326 has a vertical MTJ structure disposed in a trench region as shown in any of FIGS. 1-18, or is formed according to any of FIGS. 19-21. May be received in the manufacturing process 2328 to manufacture according to the converted information in the GDSII file 2326. For example, the device manufacturing process provides GDSII file 2326 to mask manufacturer 2330 to create one or more masks, such as a mask used for photolithographic processing, illustrated as representative mask 2332. Can be included. Mask 2332 can be used during the manufacturing process to produce one or more wafers 2334 that can be inspected and divided into dies, such as representative die 2336. Die 2336 has a vertical MTJ device that has a vertical MTJ structure located in a trench region as shown in any of FIGS. 1-18, or is formed according to any of FIGS. Including a circuit.

  The die 2336 can be provided to a packaging process 2338 where the die 2336 is incorporated into the representative package 2340. For example, the package 2340 may include a single die 2336 or multiple dies, such as a system in package (SiP) configuration. Package 2340 may be configured to comply with one or more standards or specifications, such as the Electronics Technology Council (JEDEC) standard.

  Information about the package 2340 can be distributed to various product designers, for example, via a component library stored on the computer 2346. Computer 2346 may include a processor 2348 such as one or more processing cores coupled to memory 2350. A printed circuit board (PCB) tool may be stored in memory 2350 as processor executable instructions to process PCB design information 2342 received from a user of computer 2346 via user interface 2344. PCB design information 2342 has a vertical MTJ structure disposed in a trench region as shown in any of FIGS. 1-18, or formed according to any of FIGS. 19-21. Physical location information on the circuit board of the packaged semiconductor device corresponding to package 2340, including the device, may be included.

  The computer 2346 converts the PCB design information 2342 to have data including the physical location information on the circuit board of the packaged semiconductor device as well as the layout of electrical connections such as wiring and vias. A packaged semiconductor device may be configured to generate a data file such as GERBER file 2352 and the vertical MTJ placed in a trench region as shown in any of FIGS. Corresponds to a package 2340 comprising a vertical MTJ device having a structure or formed according to any of FIGS. In other embodiments, the data file generated by the converted PCB design information may have a format other than the GERBER format.

  The GERBER file 2352 may be used to create a PCB, such as a representative PCB 2356, that is received according to the design information received in the board assembly process 2354 and stored in the GERBER file 2352. For example, the GERBER file 2352 can be uploaded to one or more machines for performing various steps of the PCB manufacturing process. PCB 2356 can be mounted with electronic components including package 2340 to form a typical printed circuit assembly (PCA) 2358.

  PCA 2358 may be received in product manufacturing process 2360 and integrated into one or more electronic devices, such as first exemplary electronic device 2362 and second exemplary electronic device 2364. By way of illustrative and non-limiting example, a first representative electronic device 2362, a second representative electronic device 2364, or both are set-top boxes, music players, video players, entertainment units, navigation devices. , Communication devices, personal digital assistants (PDAs), fixed location data units, and computers. As another illustrative and non-limiting example, one or more of electronic devices 2362 and 2364 may include portable data units such as mobile phones, portable personal communication system (PCS) units, personal digital assistants, all A fixed positioning data unit such as a Global Positioning System (GPS) compatible device, a navigation device, a measurement device, or any other device that stores or retrieves data or computer instructions, or any combination thereof, It may be a remote unit. Although FIG. 23 illustrates remote units according to the teachings of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Embodiments of the present disclosure can be suitably utilized in any device, including active integrated circuits including memory and on-chip circuitry.

  Thus, a vertical MTJ device having a vertical MTJ structure disposed in a trench region as shown in any of FIGS. 1-18, or formed according to any of FIGS. Can be manufactured, processed, and incorporated into an electronic device as described in exemplary process 2300. One or more aspects of the embodiments disclosed with respect to FIGS. 1-22 may be included at various stages of the process, such as in library file 2312, GDSII file 2326, GERBER file 2352, etc. One or more other computer or processor memories (not shown) used at various stages, such as the memory 2310 of the computer 2306, the memory 2318 of the design computer 2314, the memory 2350 of the computer 2346, and the board assembly process 2354 One or more such as mask 2332, die 2336, package 2340, PCA 2358, other products (not shown) such as prototype circuits or devices, or any combination thereof. Other physical It may be incorporated into the facilities embodiment. For example, GDSII file 2326 or manufacturing process 2328 may include a computer-readable tangible medium that stores computer-executable instructions, a controller for a material deposition system, or other electronic device, the instructions of FIGS. A computer or controller to initiate the formation of a vertical MTJ device having a vertical MTJ structure disposed in a trench region as shown or formed according to any of FIGS. Instructions that can be executed by any processor. For example, the instructions may include forming a metal layer over the device substrate, forming a via in contact with the metal layer, adding a dielectric layer over the via, a portion of the dielectric layer, such as in manufacturing stage 2328 May be included in the computer-executable instructions to begin etching to form a trench region and depositing a perpendicular magnetic tunnel junction (MTJ) structure in the trench region. While various representative stages of manufacture from physical device design to final product are shown, in other embodiments, fewer stages may be used or additional stages may be included. . Similarly, process 2300 may be performed by a single entity or by one or more entities that perform various stages of process 2300.

  Various exemplary logic blocks, configurations, modules, circuits, and method steps described in connection with the embodiments disclosed herein may be performed by electronic hardware, computer software executed by a processing unit, or the like. One skilled in the art will further appreciate that it can be implemented as a combination of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functions are implemented as hardware or executable processing instructions depends on the specific application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in a variety of ways for each particular application, but such implementation decisions should not be construed as departing from the scope of the present disclosure.

  The method or algorithm steps described in connection with the embodiments disclosed herein may be implemented directly in hardware, implemented in software modules executed by a processor, or a combination of the two. Software modules include random access memory (RAM), magnetoresistive random access memory (MRAM), spin torque injection magnetoresistive random access memory (STT-MRAM), flash memory, read only memory (ROM), programmable read only memory ( PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), register, hard disk, removable disk, compact disk read only memory (CD-ROM), or It may reside in any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside in a computing device or user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

  The above description of the disclosed embodiments is provided to enable any person skilled in the art to realize or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Accordingly, the present disclosure is not intended to be limited to the embodiments shown herein, but is to the greatest possible extent consistent with the principles and novel features as defined in the following claims. Should be accepted.

DESCRIPTION OF SYMBOLS 100 Circuit board 101 1st intermetallic dielectric layer 102 2nd intermetallic dielectric layer 103 Wiring 105 Device board 107 Magnetic domain 108 Via filling material 114 Trench 150 Vertical magnetic tunnel junction cell 152 Vertical MTJ lamination | stacking 154 Free layer 156 Tunnel barrier layer 158 Pinned Layer 160 Via 170 Upper Electrode 176 Lower Electrode 178 Reference Layer 180 Cap Layer 2232 Vertical MTJ Structure Memory Array 2264 Arranged in the Trench Region 2264 Vertical MTJ Structure Cache Memory Device 2266 Trench Arranged in the Trench Region MRAM including an array of vertical MTJ structures arranged in a region

Claims (44)

A method of manufacturing a semiconductor device, comprising:
Forming a metal layer over the device substrate;
Forming a via in contact with the metal layer;
Adding a dielectric layer over the via;
Etching a portion of the dielectric layer to form a trench region;
Depositing a perpendicular magnetic tunnel junction (MTJ) structure in the trench region.   The method of claim 1, further comprising polishing the vertical MTJ structure.   The method of claim 2, wherein the polishing step is performed without performing a photo-etching process on the vertical MTJ structure.   The method of claim 2, wherein polishing the vertical MTJ structure comprises removing deposited material from the substrate to define a substantially flat surface.   The method of claim 4, wherein polishing the vertical MTJ structure comprises performing a chemical mechanical polishing (CMP) process to remove excess material.   The method further includes forming a plurality of trenches, wherein the step of depositing a vertical MTJ structure is performed by forming an MTJ layer in each of the plurality of trenches, and the polishing step is a chemical mechanical polishing (CMP) process. The method of claim 2, wherein removing a surplus material outside each of the plurality of trenches to form a plurality of substantially similar MTJ devices without etching the MTJ layer of the MTJ structure. The method described.   The vertical MTJ structure includes a barrier layer between a free layer and a fixed layer, and at least one of the fixed layer and the free layer is proximate to a bottom surface of the trench and substantially at the bottom surface of the trench region. The method of claim 1, having a perpendicular magnetic moment.   The method of claim 1, wherein the vertical MTJ structure is formed without using an MTJ photoetching process.   The method of claim 1, further comprising performing a magnetic annealing process to determine the direction of the magnetic field of the pinned layer.   The method of claim 1, further comprising forming a top electrode over the MTJ structure, wherein the polishing comprises removing a portion of the electrode material outside the trench region.   The steps of forming a metal layer, forming a via, adding a dielectric layer, etching a portion of the dielectric layer, and depositing a vertical MTJ structure are incorporated into an electronic device. The method of claim 1, wherein the method is executed on a processor.   A semiconductor device comprising a perpendicular magnetic tunnel junction (MTJ) structure disposed in a trench region.   The semiconductor device of claim 12, wherein the vertical MTJ structure has a substantially U-shaped cross section.   The semiconductor device of claim 12, wherein the vertical MTJ structure has a substantially L-shaped cross section.   The semiconductor device of claim 12, wherein the vertical MTJ structure has a substantially rectangular cross section.   The semiconductor device of claim 12, wherein the trench region has a substantially U-shaped cross section.   The semiconductor device of claim 12, wherein the trench region has a substantially L-shaped cross section.   The semiconductor device of claim 12, wherein the trench region has a substantially rectangular cross section.   The semiconductor device of claim 12, wherein at least a portion of the trench region has a substantially curved shape.   The semiconductor device of claim 12, wherein a shape of the MTJ structure is defined by the trench region without etching the MTJ structure.   The vertical MTJ structure includes a barrier layer between a free layer and a fixed layer, and at least one of the fixed layer and the free layer is proximate to a bottom surface of the trench region and substantially on the bottom surface of the trench region. The semiconductor device of claim 12 having a magnetic moment perpendicular to.   The semiconductor device of claim 21, wherein the vertical MTJ structure includes a reference layer having a magnetic moment proximate to the bottom surface of the trench region and substantially perpendicular to the bottom surface of the trench region.   The semiconductor device of claim 21, wherein the vertical MTJ structure includes a cap layer covering the free layer.   The semiconductor device of claim 12, wherein the vertical MTJ structure comprises iron / platinum.   The semiconductor device of claim 12, wherein the vertical MTJ structure comprises cobalt / platinum.   The semiconductor device of claim 12, wherein the vertical MTJ structure comprises cobalt / nickel.   The semiconductor device of claim 22, wherein the reference layer comprises platinum.   The semiconductor device of claim 12, wherein the semiconductor device is incorporated into at least one semiconductor die.   And further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, and a computer, The semiconductor device of claim 12, wherein the semiconductor die is incorporated. A method of manufacturing a semiconductor device, comprising:
Depositing a first cap thin film layer over an intermetal dielectric (IMD) layer of the device;
Performing a photo / etch / photoresist strip process on the first cap thin film layer and the intermetal dielectric layer to define vias;
Depositing a first conductive material in the via;
Performing a chemical mechanical polishing (CMP) process to polish the first conductive material;
Depositing a cap layer;
Defining a trench in the device, the trench having dimensions that determine the shape of the MTJ structure without performing a photo-etching process on the MTJ structure;
Depositing a second conductive material to form a bottom electrode in the trench;
Forming a vertical MTJ stack on the lower electrode, the vertical MTJ stack including a magnetic thin film having a magnetic moment perpendicular to a surface of the lower electrode, and the MTJ stack including a tunnel barrier layer; , Steps and
Depositing a third conductive material to form an upper electrode;
Performing a reverse photo / etch process to remove material extending beyond the trench;
Performing a CMP process to remove material on the second cap thin film layer;
Depositing a third cap thin film layer on the second cap thin film layer;
Performing a magnetic annealing process to determine the direction of the magnetic moment;
Depositing a second IMD layer over the third cap thin film layer;
Performing photo / etching on the third cap thin film layer and the second IMD layer to define a second via;
Depositing a second conductive material in the second via;
Performing a CMP process to polish the second conductive material;
Depositing a metal layer over the second via.   31. The method of claim 30, further comprising performing a photo / etch to remove a portion of the vertical MTJ stack along the trench sidewall. A method of manufacturing a semiconductor device, comprising:
A first step for forming a metal layer over the device substrate;
A second step for forming a via in contact with the metal layer;
A third step for adding a dielectric layer over the via;
A fourth step for etching a portion of the dielectric layer to form a trench region;
And a fifth step for depositing a perpendicular magnetic tunnel junction (MTJ) structure in the trench region.   33. The method of claim 32, wherein the first step, the second step, the third step, the fourth step, and the fifth step are performed in a processor embedded in an electronic device. . A computer-readable tangible medium storing instructions executable by a computer, the instructions comprising:
Instructions executable by the computer to initiate the step of forming a metal layer over the device substrate;
Instructions executable by the computer to initiate a step of forming a via in contact with the metal layer;
Instructions executable by the computer to initiate the step of adding a dielectric layer over the via;
Instructions executable by the computer to initiate a step of etching a portion of the dielectric layer to form a trench region;
A computer readable tangible medium comprising instructions executable by the computer to initiate a step of depositing a perpendicular magnetic tunnel junction (MTJ) structure in the trench region.   35. The computer readable tangible medium of claim 34, wherein the instructions are executable by a processor embedded in a device selected from the group consisting of a communication device, a fixed location data unit, and a computer. Receiving design information representative of at least one physical characteristic of a semiconductor device, the semiconductor device including a vertical MTJ structure disposed in a trench region;
Converting the design information to conform to a file format;
Generating a data file containing the converted design information.   38. The method of claim 36, wherein the data file includes GDSII format. Receiving a data file containing design information corresponding to a semiconductor device;
Manufacturing the semiconductor device according to the design information, the semiconductor device comprising a vertical MTJ structure disposed in a trench region.   40. The method of claim 38, wherein the data file has a GDSII format. Receiving design information including physical location information on a circuit board of the packaged semiconductor device, wherein the packaged semiconductor device including a semiconductor structure is disposed in a trench region; Including a MTJ structure;
Converting the design information to generate a data file.   41. The method of claim 40, wherein the data file has a GERBER format. Receiving a data file including design information including physical location information on the circuit board of the packaged semiconductor device;
Manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device is disposed in a trench region; Including a semiconductor structure comprising:   43. The method of claim 42, wherein the data file has a GERBER format.   The circuit board is incorporated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communication device, personal digital assistant (PDA), fixed location data unit, and computer. 43. The method of claim 42, further comprising a step.