JP2017103425A - Semiconductor package and package on package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress warpage of a semiconductor package with a cavity and improve a quality of connection with another wiring board.SOLUTION: A semiconductor package 100 of an embodiment includes: a build-up wiring layer 11; a first pad 21 and a second pad 22 that are formed on a first surface 11F of the build-up wiring layer 11; a first mold resin part 10 that covers the first surface 11F of the build-up wiring layer 11, and has a cavity 5 exposing the first pad 21 and an opening 14a exposing the second pad 22; a conductor post 14 formed by a plating layer in the opening 14a; a first semiconductor element 105 that is mounted onto the first pad 21; and a second mold resin part 70 that is formed in at least the cavity 5. A coefficient of thermal expansion of a resin insulation layer 3 in the build-up wiring layer 11 and a surface direction of the second mold resin part 70 is larger than that of the surface direction of the first mold resin part 10.SELECTED DRAWING: Figure 1A

Description

  The present invention relates to a semiconductor package having a cavity and a package-on-package having such a semiconductor package.

  Patent Document 1 discloses a chip built-in substrate in which a semiconductor chip is built. In the chip-embedded substrate of Patent Document 1, the second substrate is bonded to the first substrate on which the semiconductor chip is mounted. A sealing connection layer is formed between the first substrate and the second substrate to seal the semiconductor chip and connect the wiring of the first substrate and the wiring of the second substrate. The sealing connection layer is formed of an insulating layer and an electrical connection member. The chip built-in substrate of Patent Document 1 has a spacer in the sealing connection layer for controlling the distance between the substrates and reducing the warpage of the chip built-in substrate.

International Publication No. 2007/0669606

  In the chip-embedded substrate of Patent Document 1, the first substrate and the second substrate are bonded together by the sealing connection layer. However, it is considered difficult to sufficiently suppress the warpage of the chip built-in substrate with only the spacer in the sealing connection layer.

  According to another aspect of the present invention, there is provided a semiconductor package in which a resin insulating layer and a conductor layer are alternately stacked, a build-up wiring layer having a first surface and a second surface opposite to the first surface, and a first of the build-up wiring layers. A first pad and a second pad formed on one surface; a first surface covering the first surface of the build-up wiring layer; a cavity exposing the first pad; and an opening exposing the second pad. 1 mold resin part, a conductor post formed of a plating layer in the opening of the first mold resin part so as to contact the second pad, a first semiconductor element mounted on the first pad, and at least the A second mold resin portion formed in the cavity. The thermal expansion coefficient of the resin insulating layer is larger than the thermal expansion coefficient of the first mold resin part, and the thermal expansion coefficient of the second mold resin part is larger than the thermal expansion coefficient of the first mold resin part.

  According to the embodiment of the present invention, warpage of the semiconductor package and the package-on-package can be suppressed. It is considered that the reliability of the connection with the external wiring board of the semiconductor package or the connection within the package-on-package is improved.

Sectional drawing of the semiconductor package of one Embodiment of this invention. Sectional drawing of the semiconductor package of other embodiment of this invention. FIG. 1B is a cross-sectional view of a package-on-package according to an embodiment of the present invention in which a second semiconductor element is mounted on the semiconductor package shown in FIG. 1A. The enlarged view which shows the example by which the end surface and side surface of the conductor post of FIG. 1A are roughened. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG. The figure which shows the manufacturing method of the semiconductor package shown by FIG.

  One embodiment of a semiconductor package of the present invention will be described with reference to the drawings. 1A and 1B are diagrams illustrating a cross section of a semiconductor package 100 according to an embodiment. The semiconductor package 100 includes a printed wiring board 1 having a cavity (concave portion) 5, a first semiconductor element 105 mounted in the cavity 5, and at least a second mold resin portion 70 formed in the cavity 5. doing. FIG. 1A shows an example in which an external wiring board 110 is connected to the conductor post 14. An external wiring board or the like can be mounted on one surface of the semiconductor package 100 in this way. The printed wiring board 1 further includes a build-up wiring layer 11 having a first surface 11F and a second surface 11B opposite to the first surface 11F, and a first mold that covers the first surface 11F of the build-up wiring layer 11. The resin portion 10, the first pad 21 and the second pad 22, and the conductor post 14 are provided. The first pad 21 and the second pad 22 are formed on the first surface 11F of the buildup wiring layer 11. The first pad 21 is connected to an electronic component (first semiconductor element 105 in the example of FIG. 1A). The cavity 5 is provided in the first mold resin portion 10 so as to expose the first pad 21. The first mold resin portion 10 also includes an opening 14 a that exposes the second pad 22. As shown in FIGS. 1A and 1B, a part of the second pad 22 only needs to be exposed from the first mold resin portion 10. The conductor post 14 is formed of a plating layer in the opening 14 a of the first mold resin portion 10 so as to be in contact with the second pad 22. The end face 14 b of the conductor post 14 is exposed on the surface of the first mold resin portion 10. In the example of FIG. 1A, the second pad 22 and the conductor post 14 are connected to the external wiring board 110 via the bump 111. In the example of FIGS. 1A and 1B, the build-up wiring layer 11 includes a first resin insulating layer 30 and a second resin insulating layer 31 (hereinafter, the first and second resin insulating layers 30 and 31 are collectively shown). It may be simply referred to as “resin insulating layer 3”).

  In the semiconductor package 100 shown in FIG. 1A, the second mold resin part 70 is formed in the cavity 5 and further covers the surface 10F on the opposite side of the build-up wiring layer 11 side of the first mold resin part 10. . The second mold resin portion 70 is provided with an opening 71 that exposes the end surface 14b of the conductor post 14 opposite to the second pad 22 side from the bottom surface.

  In the embodiment, the thermal expansion coefficient in the surface direction of the resin insulating layer 3 (hereinafter, “the thermal expansion coefficient in the surface direction” may be simply described as “thermal expansion coefficient”) is the first mold resin portion 10. The thermal expansion coefficient in the surface direction of the second mold resin part 70 is larger than the thermal expansion coefficient in the surface direction, and is larger than the thermal expansion coefficient in the surface direction of the first mold resin part 10. The 1st and 2nd mold resin parts 10 and 70 may be constituted by resin material which has an inorganic filler, respectively. In that case, the content of the inorganic filler in the second mold resin part 70 may be lower than the content of the inorganic filler in the first mold resin part 10. 1A and 1B, when the build-up wiring layer 11 includes a plurality of resin insulation layers, the thermal expansion coefficient in the surface direction of the resin insulation layer 3 is the resin insulation layer in the build-up wiring layer 11 respectively. It is the average value of the thermal expansion coefficient in the surface direction. That is, in the embodiment shown in FIGS. 1A and 1B, the thermal expansion coefficient in the surface direction of the resin insulating layer 3 is the thermal expansion coefficient in the surface direction of the first resin insulating layer 30 and the heat in the surface direction of the second resin insulating layer 31. It is the average value of the expansion coefficient.

  In the embodiment shown in FIG. 1A, from the first surface 1F of the printed wiring board 1 toward the second surface 11B of the build-up wiring layer 11, the second mold resin portion 70, the first mold resin portion 10, and the resin insulating layer A three-layer structure composed of three layers is formed. The resin material constituting the first mold resin portion 10 preferably has a thermal expansion coefficient in the surface direction that is close to the thermal expansion coefficient in the surface direction of the first semiconductor element 105, and the cavity 5 and the conductor post 14 are formed. The easy one is selected. On the other hand, the coefficient of thermal expansion in the surface direction of the resin insulating layer 3 can vary greatly depending on the presence or absence of the reinforcing material and the filler content contained in each resin insulating layer in the resin insulating layer 3. In the present embodiment, the thermal expansion coefficient in the surface direction of the first mold resin portion 10 is smaller than the thermal expansion coefficient in the surface direction of the resin insulating layer 3.

  Since the thermal expansion coefficient in the surface direction of the first mold resin portion 10 which is an intermediate layer of the three-layer structure is smaller than the thermal expansion coefficient in the surface direction of the resin insulating layer 3, the two layers are convex downward in a high temperature state. The shape tends to warp. By disposing the second mold resin part 70 having a thermal expansion coefficient in the surface direction larger than the thermal expansion coefficient in the surface direction of the first mold resin part 10 above the first mold resin part 10, between the two layers, Warpage tends to occur in a convex shape at high temperature. Therefore, downward warping can be suppressed. The warp of the semiconductor package 100 is reduced.

  That is, in the semiconductor package 100 of the embodiment, the coefficient of thermal expansion in the surface direction of the second mold resin part 70 and the resin insulating layer 3 sandwiching the first mold resin part 10 from both sides is the surface of the first mold resin part 10. Greater than the coefficient of thermal expansion in the direction. It is considered that warpage of the semiconductor package 100 is suppressed.

  The coefficient of thermal expansion in the surface direction of the second mold resin part 70, the first mold resin part 10, and the resin insulating layer 3 can be adjusted by, for example, the content of the inorganic filler. Since the thermal expansion coefficient in the surface direction of the resin insulating layer 3 is larger than the thermal expansion coefficient in the surface direction of the first mold resin part 10, the inorganic filler content of the second mold resin part 70 is the inorganic content of the first mold resin part 10. It can be made lower than the filler content. Thereby, the thermal expansion coefficient in the surface direction of the second mold resin part 70 becomes larger than the thermal expansion coefficient in the surface direction of the first mold resin part 10.

  The semiconductor package 100 is formed with a sandwich structure in which a resin layer having a high thermal expansion coefficient in the plane direction and a resin layer having a low thermal expansion coefficient in the plane direction is sandwiched, thereby suppressing warpage in a high temperature state such as mounting. . It is considered that the connection reliability between the printed wiring board 1 and the external wiring board 110 connected to the second pad 22 via the first semiconductor element 105 or the conductor post 14 is high.

  FIG. 1B shows a cross-sectional view of a semiconductor package 100 of another embodiment. The second mold resin forming the second mold resin portion 70 of the printed wiring board 1 in the semiconductor package 100 is filled only in the cavity 5.

  In the embodiment shown in FIG. 1B, a resin part 72 composed of the second mold resin part 70 and the first mold resin part 10 is formed. Since the thermal expansion coefficient in the surface direction of the first mold resin portion 10 is smaller than the thermal expansion coefficient in the surface direction of the resin insulating layer 3, the semiconductor package 100 is warped in a convex shape at a high temperature. Cheap. By making the thermal expansion coefficient in the surface direction of the second mold resin part 70 larger than the thermal expansion coefficient in the surface direction of the first mold resin part 10, the thermal expansion coefficient in the surface direction of the entire resin part 72 is increased. As a result, the occurrence of a downwardly convex warp is suppressed. The warp of the semiconductor package 100 is reduced. The connection reliability of the semiconductor package 100 is improved.

  The cavity 5 exposes the first pad 21 on the bottom surface 5 b, and has an opening on the surface 10 </ b> F of the first mold resin portion 10. In the example shown in FIGS. 1A and 1B, the first semiconductor element 105 is connected to the printed wiring board 1 via the first pad 21. A plurality of semiconductor elements and electronic components other than the semiconductor elements may be accommodated in the cavity 5, and each may be connected to the wiring layer of the printed wiring board 1 via the first pad 21. The arrangement and size of the cavities 5 and the number and arrangement of the first pads 21 can be appropriately selected according to the number of semiconductor elements mounted in the cavities 5 and the arrangement of the electrodes. The planar shape of the cavity 5 is, for example, a rectangle or a square. “Planar shape” means an outer peripheral shape in a plan view in which a plane perpendicular to the thickness direction of the printed wiring board 1 is drawn as a horizontal plane (hereinafter, “planar shape” is used in the same meaning). The planar shape of the cavity 5 is not limited to this, and may be another shape such as a circle. Depending on the shape of the semiconductor element or the like accommodated in the cavity 5, the cavity 5 can be formed in an arbitrary planar shape.

  Examples of the first semiconductor element 105 include a single semiconductor element, a semiconductor element having a redistribution layer, and a WLP (Wafer Level Package).

  The build-up wiring layer 11 includes resin insulating layers (first and second resin insulating layers 30 and 31) that are alternately stacked and conductor layers (first, second, and third conductor layers) having a predetermined wiring pattern. 20, 40, 60). That is, in the semiconductor package 100 shown in FIGS. 1A and 1B, the first resin insulating layer 30 is formed on the first surface 11F side of the buildup wiring layer 11. A first conductor layer 20 is formed on the first resin insulation layer 30. A second conductor layer 40 and a second resin insulation layer 31 are formed on the side of the first resin insulation layer 30 opposite to the first conductor layer 20 side. A third conductor layer 60 is formed on the second resin insulating layer 31 on the side opposite to the second conductor layer 40 side. The third conductor layer 60 is embedded in the second resin insulation layer 31. One surface of the third conductor layer 60 is exposed from the second resin insulating layer 31. The first conductor layer 20 and the second conductor layer 40, and the second conductor layer 40 and the third conductor layer 60 are connected by via conductors 35 and 55 penetrating the first and second resin insulation layers 30 and 31, respectively. Has been.

  The first resin insulation layer 30 and the second resin insulation layer 31 in the buildup wiring layer 11 are mainly formed of a resin material such as an epoxy resin. The resin material may be a prepreg material in which a reinforcing material is impregnated with epoxy or another resin composition. The reinforcing material is not particularly limited, and glass fiber or the like is preferably used. The resin material may contain 30% by mass or more and 80% by mass or less of an inorganic filler such as silica or alumina. The first and second resin insulation layers 30 and 31 are formed to have a thickness of 10 μm or more and 100 μm or less, for example.

  When the buildup wiring layer 11 includes a plurality of resin insulating layers as in the example of FIGS. 1A and 1B, preferably, all the resin insulating layers are formed of the same resin material. However, different resin materials may be used.

The resin material which comprises the 1st mold resin part 10 and the 2nd mold resin part 70 will not be specifically limited if it has the thermal expansion coefficient of the above-mentioned surface direction. An example of the material is an epoxy resin. The inorganic filler that can be included in the first mold resin part 10 and the second mold resin part 70 is, for example, SiO ₂ . The inorganic filler may be alumina. The amount of the inorganic filler contained in the first mold resin part 10 is, for example, 75% by mass or more and 85% by mass or less. The amount of the inorganic filler contained in the second mold resin part 70 is, for example, 60% by mass or more and 75% by mass or less.

  The first mold resin portion 10 has a thickness of, for example, 50 μm or more and 150 μm or less. This thickness is approximately equal to the depth of the cavity 5. The depth of the cavity 5 is a distance from the surface 10F of the first mold resin portion 10 to the surface of the first pad 21. This distance can be easily adjusted, for example, by changing the thickness of the dummy member 7 (see FIG. 4G) used when forming the first mold resin portion 10, as will be described later. The depth of the cavity 5 is arbitrarily selected according to the thickness of the first semiconductor element 105 mounted on the first pad 21.

  An end face 14b of the conductor post 14 opposite to the second pad 22 side is exposed on the surface 10F of the first mold resin portion 10 opposite to the buildup wiring layer 11 side. The opening 14 a is formed, for example, by irradiating the first mold resin part 10 with laser light from the surface 10 </ b> F of the first mold resin part 10. The power of the laser beam tends to gradually weaken from the surface 10F side of the first mold resin portion 10 toward the second pad 22 side. Therefore, the opening 14a and the conductor post 14 formed of a plating layer in the opening 14a have a tapered shape that decreases in diameter toward the second pad 22, as shown in FIG. 1A.

  The conductor post 14 may be formed by filling the opening 14a with a conductor made of an electroless plating film and an electrolytic plating film. The connection between the first conductor layer 20 and the conductor post 14 is a joint between the same kind of metals. It is considered that the conductor post 14 is firmly joined to the first conductor layer 20. It is considered that the stress due to the difference in thermal expansion coefficient between the conductor post 14 and the first conductor layer 20 is also small. As will be described later, the inner wall surface of the opening 14a is preferably roughened before the plating process. The contact area between the conductor post 14 and the wall surface of the opening 14a is increased, and the adhesion between the conductor post 14 and the first mold resin portion 10 is improved.

  The conductor post 14 has a height of 50 μm or more and 150 μm or less. The height of the conductor post 14 is set according to the thickness of the first mold resin portion 10. That is, the height of the conductor post 14 can be set according to the depth of the cavity 5. 1A and 1B show an example in which the end face 14b of the conductor post 14 of the printed wiring board 1 is recessed from the surface 10F of the first mold resin portion 10. FIG. In connection with an external wiring board via the conductor post 14, the portion of the first mold resin portion 10 can be a wall of a bonding material such as solder. It is possible to prevent an electrical short circuit from being caused by contact between an adjacent electrode or the like and a bonding material. However, the end face 14b of the conductor post 14 may be formed substantially flush with the surface 10F of the first mold resin portion 10.

  In the embodiment shown in FIGS. 1A and 1B, the second mold resin portion 70 covers the surface 10 </ b> F of the first mold resin portion 10. A surface 105 </ b> F opposite to the surface facing the buildup wiring layer 11 of the first semiconductor element 105 is covered with the second mold resin portion 70. Accordingly, the first semiconductor element 105 is protected from external stress. Further, the intrusion of moisture into the cavity 5 is prevented. In addition, the stress generated at the junction with the first semiconductor element 105 can be reduced. As a result, there is an advantage that connection reliability is improved.

  The first semiconductor element 105 has an electrode 106. The electrode 106 is connected to the first pad 21 exposed on the bottom surface 5 b of the cavity 5 of the printed wiring board 1. The connection method between the electrode 106 and the first pad 21 is not particularly limited. For example, an intermetallic joint may be formed between the two by heating, pressurizing, and / or exciting. . The electrode 106 and the first pad 21 may be connected using a bonding material (not shown) formed of a conductive material such as solder. In the example shown in FIG. 1A, one semiconductor element (first semiconductor element 105) is accommodated in the cavity 5, but a plurality of semiconductor elements may be mounted on the printed wiring board 1. The kind of semiconductor element accommodated is not particularly limited. Preferably, a semiconductor element having a thickness not exceeding the depth of the cavity 5 is mounted.

  As shown in FIG. 1A, the external wiring board 110 connected to the semiconductor package 100 includes bumps 111 on the connection pads 112 on the surface on the semiconductor package 100 side. The bumps 111 are connected to the build-up wiring layer 11 of the printed wiring board 1 through the conductor posts 14 and the second pads 22.

  The thickness of the second mold resin part 70 covering the first semiconductor element 105 and the surface 10F of the first mold resin part 10 may be arbitrary. In the example shown in FIG. 1A, the wiring board 110 is connected leaving a space between the second mold resin portion 70 and the wiring board 110. Even if the second mold resin portion 70 expands or contracts, it is considered that stress is hardly generated in the bump 111. However, the second mold resin portion 70 may have a thickness that completely fills the gap between the printed wiring board 1 and the wiring board 110. The second mold resin portion 70 only needs to be formed so as to cover at least the first semiconductor element 105, and may be formed only in the cavity 5 as shown in FIG. 1B.

  The structure and material of the external wiring board 110 are not particularly limited. The wiring board 110 may be a printed wiring board (for example, a coreless wiring board) configured by a resin insulating layer made of a resin material and a conductor layer made of copper foil or the like. The wiring board 110 may be a wiring board in which a conductor film is formed on the surface of an insulating substrate made of an inorganic material such as alumina or aluminum nitride. The material of the bump 111 is not particularly limited, and any conductive material can be used. Preferably, a metal such as solder is used.

  FIG. 2 shows an example of a package-on-package 101 in which the second semiconductor element 115 is mounted on the external wiring board 110 shown in FIG. 1A. Components similar to those of the semiconductor package 100 shown in FIG. 1A are denoted by the same reference numerals, and detailed description thereof is omitted. An electrode (not shown) provided on one surface of the second semiconductor element 115 is connected to the wiring board 110 by a bonding wire 116. The second semiconductor elements 115 may be connected by a flip chip mounting method. By using the package-on-package 101 illustrated in FIG. 2, a semiconductor device that is small, has high functionality, and has high internal connection reliability can be provided.

  The inner wall surface of the opening 14a of the first mold resin portion 10 can be roughened by a desmear process in the opening 14a described later. Therefore, the side surface in contact with the first mold resin portion 10 of the conductor post 14 formed in the opening 14a can also be a rough surface. Further, the end face 14b of the conductor post 14 on the side opposite to the second pad 22 side can also be roughened during etching when the metal film 82 described later is removed. The end surface 14b of the conductor post 14 and the side surface in contact with the first mold resin portion 10 of the conductor post 14 may have different surface roughness. This embodiment is shown as an enlarged view of the conductor post 14 in FIG. The surface roughness of the end face 14b of the conductor post 14 is, for example, an arithmetic average roughness of 0.1 μm or more and 1.0 μm or less, preferably 0.2 μm or more and 0.5 μm or less. The surface roughness of the side surface of the conductor post 14 in contact with the first mold resin portion 10 is, for example, 1.0 μm or more and 10 μm or less, preferably 1.0 μm or more and 5.0 μm or less. The surface roughness of this side surface can be adjusted by adjusting the roughness of the inner wall surface of the opening 14a in the first mold resin portion 10 by the aforementioned desmear process. Preferably, the roughness of the end face 14 b of the conductor post 14 is smaller than the roughness of the side face of the conductor post 14 that is in contact with the first mold resin portion 10.

  Next, an embodiment of a method for manufacturing the semiconductor package 100 shown in FIG. 1A will be described with reference to FIGS.

  In the manufacturing method of the semiconductor package 100 of the present embodiment, first, as shown in FIG. 4A, a base plate 80 and a metal film (metal foil) 82 with a carrier copper foil 81 are prepared as starting materials. The carrier copper foil 81 and the metal film 82 of the metal film with the carrier copper foil are bonded by, for example, a thermoplastic adhesive (not shown). And the carrier copper foil 81 of the metal film with carrier copper foil is affixed on the base board 80 which consists of prepregs, for example by thermocompression bonding. The carrier copper foil 81 and the metal film 82 may be joined only at a margin near the outer periphery. The base plate 80 only needs to have moderate rigidity. For example, the base plate 80 may be a metal plate such as copper or an insulating plate such as ceramics. The metal film 82 is, for example, a copper foil having a thickness of 3 μm or more and 8 μm or less.

  4A to 4K show an example of a manufacturing method in which a metal film 82 is bonded to both sides of the base plate 80, and the buildup wiring layer 11 and the like are formed on each side. However, the build-up wiring layer 11 or the like may be formed only on one surface of the base plate 80. In the following description, the description on the other surface 80B side, and the reference numeral on the other surface 80B side in each drawing are omitted.

  As shown in FIG. 4B, the conductor pattern of the third conductor layer 60 is formed on the metal film 82. The conductor pattern of the third conductor layer 60 is formed in the following process. A resist pattern (not shown) having an opening at a position where the conductor pattern of the third conductor layer 60 is formed is formed. The plating conductor is filled in the opening of the resist pattern by electrolytic plating using the metal film 82 as a seed layer. By removing the resist pattern, the third conductor layer 60 having a predetermined conductor pattern is formed. The third conductor layer 60 is preferably formed to a thickness of about 5 μm or more and about 25 μm or less.

Next, as shown in FIG. 4C, the second resin insulation layer 31 is formed on the metal film 82 and on the third conductor layer 60. For example, a film-like insulating material is laminated on the third conductor layer 60, pressed and heated. Subsequently, a CO ₂ laser beam is preferably applied to a predetermined place on the surface of the second resin insulating layer 31 opposite to the third conductor layer 60 side. As shown in FIG. 4D, a conduction hole 55 a having a tapered shape that decreases in diameter toward the third conductor layer 60 may be formed.

  As shown in FIG. 4D, the metal layer 41 is formed in the conduction hole 55a and on the surface of the second resin insulation layer 31 by, for example, electroless plating. The metal layer 41 may be formed by sputtering or vacuum deposition.

  A resist pattern (not shown) having openings at predetermined positions is formed on the metal layer 41. A plating film is formed on the surface of the metal layer 41 as a seed layer by electrolytic plating. As shown in FIG. 4E, the second conductor layer 40 is formed by the metal layer 41 and the plating film 42 on the second resin insulating layer 31. The via conductor 55 is formed by the metal layer 41 and the plating film 42 in the conduction hole 55a. The resist pattern is removed. The exposed portion of the metal layer 41 is removed by etching or the like. Although the material of the metal layer 41 and the plating film 42 is not specifically limited, Preferably, copper is used. The second conductor layer 40 is preferably formed to a thickness of 5 μm or more and 25 μm or less.

  Next, the first resin insulation layer 30 is formed on the second conductor layer 40 and the second resin insulation layer 31 by the same method as the method for forming the second resin insulation layer 31. The first conductor layer 20 is formed on the first resin insulating layer 30 by the same method as the method for forming the second conductor layer 40. A via conductor 35 penetrating the first resin insulating layer 30 is formed by a method similar to the method of forming the via conductor 55 (FIG. 4F). Thereby, the build-up wiring layer 11 having a three-layer structure is formed. Four or more build-up wiring layers 11 may be formed. Depending on the layer structure of the printed wiring board to be manufactured, the steps described with reference to FIGS. In this embodiment, the first pad 21 and the second pad 22 are formed on the first conductor layer 20 because of the three-layer structure. A solder resist (not shown) may be formed on the first resin insulation layer 30 and the first conductor layer 20.

  As shown in FIG. 4G, the dummy member 7 is disposed in the formation region of the cavity 5 on the first surface 11F of the build-up wiring layer 11. The dummy member 7 is, for example, a resin film formed in substantially the same size and shape as the formation region of the cavity 5. For example, a film that has good adhesion to the first pad 21 and the first resin insulation layer 30 but does not exhibit strong adhesion can be used. For example, the dummy member 7 may be bonded by an adhesive 8 as shown in FIG. 4G. As the dummy member 7 and the adhesive 8, a material that does not adhere to the first mold resin portion 10 is preferable. The dummy member 7 is made of a resin material such as polyimide, for example. As the adhesive 8, an adhesive having an adhesive property that can be peeled from the first pad 21 and the first resin insulating layer 30 is used. By appropriately selecting the thickness of the dummy member 7 and / or the adhesive 8, the depth of the cavity 5 can be easily adjusted.

  Subsequently, the first mold resin portion 10 is formed so as to cover the dummy member 7 (FIG. 4H). The mold resin that forms the first mold resin portion 10 is supplied onto the one surface 7F of the dummy member 7 by discharging from a nozzle in a liquid or pasty state, for example. A film-shaped mold resin may be laminated on the dummy member 7 and heated. The dummy member 7 and the first resin insulating layer 30 can be covered with mold resin softened by heating or the like. The first mold resin portion 10 is formed so that the surface 10F of the first mold resin portion 10 is positioned above the one surface 7F of the dummy member 7. The first mold resin portion 10 is formed to a thickness of, for example, 50 μm or more and 150 μm or less.

  As shown in FIG. 4I, an opening 14a penetrating the first mold resin portion 10 is formed. FIG. 4I shows an opening 14 a formed so as to expose a part of the second pad 22. After the opening 14a is formed, desmear treatment in the opening 14a is preferably performed by immersion in a permanganic acid solution or the like in order to remove the adhered resin residue. The surface roughness of the inner wall surface of the opening 14a can be adjusted by adjusting the treatment time with a permanganic acid solution or the like used for the desmear treatment. It is considered that the adhesion between the conductor post 14 and the wall surface of the opening 14a is improved. During the desmear process, the surface 10F of the first mold resin portion 10 may be roughened.

  Subsequently, the conductor post 14 is formed in the opening 14a. An electroless plating film is formed on the inner wall surface of the opening 14a. An electrolytic plating film is formed using the electroless plating film as a seed layer (FIG. 4J). The opening 14a is filled with the electroless plating film and the electrolytic plating film, and the conductor post 14 is formed. The conductor film 17 can also be formed on the surface of the first mold resin portion 10.

  As shown in FIG. 4K, the surface side of the first mold resin portion 10 is polished so that the one surface 7F of the dummy member 7 is exposed from the first mold resin portion 10. Preferably, the polishing of the first mold resin portion 10 ends when the one surface 7F of the dummy member 7 is exposed. The depth of the cavity 5 is substantially equal to the thickness of the dummy member 7. Further, in order to form the cavity 5 having a desired depth, the portion on the one surface 7F side of the dummy member 7 and the first mold resin portion 10 until the thickness of the dummy member 7 becomes equal to the desired depth of the cavity 5. May be polished. For example, sand blasting, buffing, or chemical mechanical polishing (CMP) is used for polishing the first mold resin portion 10, but the polishing method is not limited thereto.

  Thereafter, as shown in FIG. 4L, the base plate 80 and the carrier copper foil 81 are removed. As described above, the carrier copper foil 81 and the metal film 82 are bonded by the thermoplastic resin. Therefore, for example, the base plate 80, the carrier copper foil 81, and the metal film 82 are easily separated by increasing the temperature and applying a force. As a result, the joint surface of the metal film 82 with the carrier copper foil 81 is exposed. In addition, when this carrier copper foil 81 and the metal film 82 are adhere | attached only in the circumference | surroundings, both are easily isolate | separated by cut | disconnecting the inner side of the adhere | attached part. FIG. 4L shows a printed wiring board on the upper surface side of the base plate 80 in FIG. 4K.

  The dummy member 7 is removed from the printed wiring board in the process. For example, one surface 7F of the dummy member 7 is attracted to a jig or the like, and the dummy member 7 is pulled up. When the adhesive 8 is used, the adhesive 8 is preferably removed together with the dummy member 7. The dummy member 7 and the adhesive 8 may be removed with a solvent or the like. As shown in FIG. 4M, a cavity 5 surrounded by the first mold resin portion 10 is formed.

  The metal film 82 is removed by etching or the like. When the same material as the metal film 82 is used for the conductor post 14 and the first pad 21, the end surface 14b of the conductor post 14 and the exposed surface 21a of the first pad 21 are simultaneously etched (FIG. 4N). As a result, the end face 14 b of the conductor post 14 may be recessed from the surface of the first mold resin portion 10. Further, as described above, the end face 14b of the conductor post 14 may be roughened.

  After removing the metal film 82, as shown in FIG. 4O, the first semiconductor element 105 is flip-chip mounted in the cavity 5, for example. The electrode 106 of the first semiconductor element 105 is connected to the first pad 21 by, for example, an intermetallic junction with the first pad 21. A bonding material such as solder may be used.

  Subsequently, as shown in FIG. 4P, the second mold resin portion 70 is formed. The mold resin that forms the second mold resin portion 70 is filled in at least the cavity 5. The method for forming the second mold resin portion 70 is not particularly limited, and for example, it may be heated and cured after a liquid resin material is injected. As in the semiconductor package 100 shown in FIG. 1A, the second mold resin portion 70 may be formed so as to cover the entire surface 10F of the first mold resin portion 10. In that case, the opening 71 is formed after the formation of the second mold resin portion 70. The opening 71 can be formed, for example, by irradiating the second mold resin portion 70 on the end face 14b of the conductor post 14 with laser light. The semiconductor package 100 is completed. When the external wiring board 110 shown in FIG. 1A is connected, for example, the external wiring board 110 may be mounted by solder reflow or the like before the second mold resin portion 70 is formed. Thereafter, the resin material of the second mold resin portion 70 may be injected from the gap between the external wiring board 110 and the first mold resin portion 10. Note that a solder resist (not shown) may be applied to the back surface side of the semiconductor package 100 (the second surface 11B side of the buildup wiring layer 11) as necessary.

DESCRIPTION OF SYMBOLS 1 Printed wiring board 1F First surface 5 of printed wiring board 5 Cavity 5b Bottom surface of cavity 7 Dummy member 7F One side of dummy member 10 First mold resin part 11 Build-up wiring layer 11F First surface 11B of build-up wiring layer Build-up wiring Layer second surface 14 conductor post 14b conductor post end surface 20 first conductor layer 21 first pad 22 second pad 30 first resin insulation layer 31 second resin insulation layer 40 second conductor layer 60 third conductor layer 70 first 2 mold resin part 80 base plate 81 carrier copper foil 82 metal film 100 semiconductor package 101 package-on-package 105 first semiconductor element 110 wiring board 111 bump 115 second semiconductor element 116 bonding wire

Claims (10)

A buildup wiring layer having a first surface and a second surface opposite to the first surface, wherein the resin insulating layers and the conductor layers are alternately laminated;
A first pad and a second pad formed on the first surface of the build-up wiring layer;
A first mold resin portion that covers the first surface of the build-up wiring layer and includes a cavity that exposes the first pad and an opening that exposes the second pad;
A conductor post formed by a plating layer in the opening of the first mold resin portion so as to be in contact with the second pad;
A first semiconductor element mounted on the first pad;
At least a second mold resin portion formed in the cavity;
A semiconductor package comprising:
The thermal expansion coefficient in the surface direction of the resin insulating layer is larger than the thermal expansion coefficient in the surface direction of the first mold resin part, and the thermal expansion coefficient in the surface direction of the second mold resin part is the surface of the first mold resin part. Greater than the coefficient of thermal expansion in the direction. 2. The semiconductor package according to claim 1, wherein the second mold resin portion covers a surface of the first mold resin portion opposite to the build-up wiring layer. 2. The semiconductor package according to claim 1, wherein the conductor post has a tapered shape whose diameter decreases toward the second pad. 2. The semiconductor package according to claim 1, wherein an end surface of the conductor post opposite to the second pad side is flush with the surface of the first mold resin portion or is recessed from the surface. 2. The semiconductor package according to claim 1, wherein a roughness of an end surface of the conductor post opposite to the second pad side is smaller than a roughness of a side surface in contact with the first mold resin portion. 2. The semiconductor package according to claim 1, wherein the first and second mold resin parts are made of a resin material having an inorganic filler, and the content of the inorganic filler in the second mold resin part is the first mold resin. It is lower than the content of the inorganic filler. 7. The semiconductor package according to claim 6, wherein the first mold resin part is made of a resin material containing an inorganic filler of 75% by mass or more and 85% by mass or less. 7. The semiconductor package according to claim 6, wherein the second mold resin portion is made of a resin material containing an inorganic filler of 60% by mass or more and 75% by mass or less. The semiconductor package according to claim 6, wherein the inorganic filler contains SiO ₂ . The package on package by which the external wiring board is connected to the said conductor post in the semiconductor package of any one of Claims 1-9.

Images