JP2017093237A - Semiconductor integrated circuit for earth leakage circuit breaker - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for low cost earth leakage circuit breaker corresponding to detection of a leakage current of pulsating waveform subjected to half-wave rectification.SOLUTION: The integration circuit 7 of a semiconductor integrated circuit for earth leakage circuit breaker includes a clock synthesis circuit 11 outputting a high frequency first clock signal for addition operation and a low frequency second clock signal for subtraction operation, based on a signal (leakage signal) S2 indicating whether or not the absolute value of a detection signal, detected by a zero-phase current transformer, exceeds a constant voltage value. An up-down counter 12 adds by the first clock signal when the absolute value of a detection signal exceeds the constant voltage value, otherwise subtracts by the second clock signal. Since the subtraction ratio lowers compared with addition, leakage determination even of a leakage current of pulsating waveform is possible, because subtraction of integrated value is suppressed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit for a leakage breaker, and more particularly to a semiconductor integrated circuit for a leakage breaker that detects a leakage by detecting a sine wave AC waveform and a pulsating waveform of a leakage current detected by a zero-phase current transformer.

  An earth leakage circuit breaker that can prevent electric shocks and fires due to electric leakage by cutting off the supply from the distribution system when a ground fault occurs in the equipment connected to the distribution system and the ground fault current flows above a certain level. It has been known. Below, the structure and operation | movement of a general earth-leakage circuit breaker are demonstrated.

  FIG. 8 is a diagram showing a schematic configuration of the earth leakage breaker, FIG. 9 is a diagram showing a main part waveform of the semiconductor integrated circuit for earth leakage breaker when a sine wave AC waveform is detected, and FIG. 10 is a diagram when a pulsating current waveform is detected It is a figure which shows the principal part waveform of the semiconductor integrated circuit for earth-leakage circuit breakers.

  As shown in FIG. 8, the earth leakage circuit breaker 1 includes, for example, a cutoff switch 2 and a zero-phase current transformer (ZCT: ZCT) installed in an AC power supply line to which AC power is supplied to a load L via a transformer T. Zero-phase-sequence Current Transformer) 3 and a leakage detection circuit 4 that detects leakage based on the output of the zero-phase current transformer 3. The zero-phase current transformer 3 detects the zero-phase current obtained by synthesizing the currents of the three phases by passing the three phases of the AC power supply line all at once through one current transformer. In normal time, zero-phase current is not detected, and zero-phase current is detected when current leakage occurs and the balance between the three-phase current and phase is lost. The output of this zero-phase current transformer 3 is connected to a leakage detection circuit 4.

  The leakage detection circuit 4 includes a current detection resistor Rs that converts a zero-phase current signal detected by the zero-phase current transformer 3 into a voltage signal, a filter amplifier 5, a full-wave detection comparator circuit 6, an integration circuit 7, And a time delay circuit 8.

  The filter amplifier 5 has one end connected to one end of the current detection resistor Rs, one end connected to the other end of the resistor R1, resistors R2, R3 and a capacitor C1, and one end connected to the other end of the resistor R2. The capacitor C2 and the operational amplifier OP are provided. The other end of the resistor R2 and one end of the capacitor C2 are connected to the inverting input of the operational amplifier OP, the other end of the current detection resistor Rs and the other end of the capacitor C1 are connected to the non-inverting input, and the resistor is connected to the output. The other end of R3 and the other end of the capacitor C2 are connected. A bias voltage V_RIN is applied to the non-inverting input of the operational amplifier OP. Thus, the filter amplifier 5 has a function of a low-pass filter in which the cutoff frequency is determined by the resistance values of the resistors R1, R2, and R3 and the capacitance values of the capacitors C1 and C2, and an inverting amplifier function in which the gain is determined by the resistors R1 and R3. doing. The filter amplifier 5 outputs a signal S1 amplified by superimposing the bias voltage V_RIN and the detection signal.

  Here, the operational amplifier OP, the full-wave detection comparator circuit 6, the integration circuit 7 and the time delay circuit 8 of the filter amplifier 5 are integrated to form a semiconductor integrated circuit 9 for a leakage breaker. Therefore, the inverting input of the operational amplifier OP is connected to the other end of the resistor R2 and one end of the capacitor C2 via the terminal VIN of the semiconductor integrated circuit 9 for earth leakage breaker, and the non-inverting input is connected to the current detection resistor via the terminal RIN. The other end of Rs and the other end of the capacitor C1 are connected. The output of the operational amplifier OP is connected to the other end of the resistor R3 and the other end of the capacitor C2 via a terminal FIN. The terminal OUT of the semiconductor integrated circuit 9 for earth leakage breaker is connected to the cutoff switch 2.

  The full-wave detection comparator circuit 6 includes two comparators CMP1 and CMP2 and an OR gate OR. A reference voltage V_RIN + v whose potential is higher by a constant voltage v than the bias voltage V_RIN is applied to the inverting input of the comparator CMP1, and a reference voltage whose potential is lower by a constant voltage v than the bias voltage V_RIN is applied to the non-inverting input of the comparator CMP2. V_RIN-v is applied. The output of the filter amplifier 5 is connected to the non-inverting input of the comparator CMP1 and the inverting input of the comparator CMP2, and the outputs of the comparators CMP1 and CMP2 are connected to the input of the OR gate OR. The output of the OR gate OR constitutes the output of the full-wave detection comparator circuit 6. Thus, the full-wave detection comparator circuit 6 determines whether or not the detected voltage absolute value of the signal S1 output by the filter amplifier 5 (that is, the full-wave rectified voltage of the signal S1) exceeds a certain voltage value (v). , A signal (leakage signal) S2 that becomes a high level or a low level is output.

  The integration circuit 7 is constituted by an up / down counter that performs addition when the signal S2 output from the full-wave detection comparator circuit 6 is at a high level and performs subtraction when the signal S2 is at a low level. The integration circuit 7 determines whether there is a leakage based on the integrated value of the up / down counter, and outputs a signal (leakage determination signal) S3. In addition, this integrating circuit 7 is obtained by digitizing an integrating circuit based on an analog circuit using charging / discharging of a capacitor in Patent Document 1. Here, it is assumed that the frequency of the reference clock signal used for the addition operation and the subtraction operation is, for example, 100 kHz (10 microsecond (μs) cycle), and the up / down counter is configured by, for example, 10 stages of D flip-flops. In this case, the integration circuit 7 can count a time value of about 10 milliseconds (ms) at the maximum as an accumulation time of the leakage, and the time value of 8 ms which is a reference for determining the leakage in the integration circuit 7. Counting is possible.

  The time delay circuit 8 determines whether or not the determination of electric leakage by the integration circuit 7 has continued for a predetermined time, and causes the cutoff switch 2 to perform a cutoff operation according to the determination result. That is, the earth leakage breaker 1 does not immediately shut off the cutoff switch 2 when the integrating circuit 7 determines that the earth leakage has occurred, but only after the determination of the earth leakage continues for a predetermined time, the earth leakage breaker 2 is cut off. The reason for this is that the timing at which the cut-off switch of each earth leakage breaker cuts off is adjusted for protection coordination with this earth leakage breaker 1 and other earth leakage breakers connected in series and parallel. The predetermined time determined by the extension circuit is set to a longer time for an earth leakage breaker arranged at a higher level of the distribution system.

  Next, the operation of the earth leakage breaker 1 will be described. First, when a leakage occurs, the leakage current detection signal detected by the zero-phase current transformer 3 flows through the current detection resistor Rs, and a leakage voltage proportional to the leakage current detection signal is generated at both ends of the current detection resistor Rs. Is done. This leakage voltage is amplified by the filter amplifier 5 and output as a signal S1. As shown in FIG. 9, the signal S <b> 1 has a sine wave AC waveform centered on the bias voltage V_RIN and is supplied to the full wave detection comparator circuit 6.

  In the full-wave detection comparator circuit 6, when the comparator CMP1 receives a signal S1 having a higher potential than the reference voltage V_RIN + v, it outputs a high level signal and receives a signal S1 having a lower potential than the reference voltage V_RIN + v. A low level signal is output. The comparator CMP2 outputs a low-level signal when a signal S1 having a higher potential than the reference voltage V_RIN-v is input, and receives a signal S1 having a lower potential than the reference voltage V_RIN-v. A high level signal is output. The OR gate OR outputs a high level signal when receiving a high level signal from one of the comparators CMP1 and CMP2, and outputs a low level signal when receiving a low level signal from both the comparators CMP1 and CMP2. To do. That is, the full-wave detection comparator circuit 6 outputs a high level signal S2 when the absolute value of the detection voltage of the signal S1 exceeds a certain voltage, and outputs a low level signal S2 when it does not exceed the certain voltage. Here, the full-wave detection comparator circuit 6 determines that a leakage has occurred when outputting a high level signal, and determines that there is no leakage when outputting a low level signal. .

  The integration circuit 7 adds the time value when receiving the high level signal S2 from the full wave detection comparator circuit 6, and subtracts the time value when receiving the low level signal S2. As a result, as shown in the schematic operation of the integrating circuit in FIG. 9, the integrated value of the integrating circuit 7 rises while the signal S2 is at the high level, and falls while the signal S2 is at the low level. The integration circuit 7 outputs a high level signal S3 when the integrated value rises and exceeds the determination threshold value VthH, and then outputs a low level signal when the integrated value decreases and falls below the determination threshold value VthL. . Here, when the integration circuit 7 outputs a high level signal, the integration circuit 7 determines that a leakage has occurred or that there is a possibility of a leakage. When the integration circuit 7 outputs a low level signal, the possibility of a leakage is present. Is determined to be low.

  The time delay circuit 8 determines whether or not to operate the cutoff switch 2 based on the signal S3 output from the integration circuit 7. When the high level signal output from the integrating circuit 7 continues beyond the set time value, the time delay circuit 8 operates the cutoff switch 2 to open the AC power supply line.

  Next, the case where the current detected by the zero-phase current transformer 3 is a half-wave rectified pulsating waveform will be described. As shown in FIG. 10, when the signal S1 output from the filter amplifier 5 has a pulsating waveform, the full-wave detection comparator circuit 6 only applies when the signal S1 output from the filter amplifier 5 is higher in potential than the reference voltage V_RIN + v. , Output a high level signal. For this reason, the signal S2 output from the full-wave detection comparator circuit 6 is overwhelmingly shorter than the time during which the high level is at the low level. In the integration circuit 7, since the addition operation and the subtraction operation are performed at the same speed, the integrated value of the integration circuit 7 does not readily reach the determination threshold value VthH, and since the subtraction time is long, It will be subtracted to zero. That is, a leakage current such as a half-wave rectified pulsating waveform cannot be detected by the leakage detection circuit 4 as shown in FIG.

  However, according to the leakage protection characteristic defined as “Type A” in IEC 60947-2, JIS C8201-2-2, etc., there is a demand for a leakage breaker capable of detecting leakage even for the above pulsating waveform. . In response to such a demand, for example, an earth leakage breaker as described in Patent Document 2 is known. According to this earth leakage breaker, the hall element built-in type second zero-phase current transformer, a DC conversion circuit that obtains a DC component signal from the output of the hall element, and the first zero connected to the earth leakage detection circuit. An excitation conductor that passes through the iron core of the phase current transformer and allows the output signal of the DC conversion circuit to flow is newly provided. As a result, the magnetic field of the signal flowing through the exciting conductor is reversely biased to add to the first zero-phase current transformer to cancel the DC bias, and the first zero-phase current transformer is half-wave rectified pulsating waveform Can be detected as a full-wave rectified waveform containing no DC component.

JP 2000-102158 A JP 2010-14478 A

  However, in the earth leakage circuit breaker as described in Patent Document 2, it is necessary to make a significant change by adding a second zero-phase current transformer having a built-in Hall element, a DC conversion circuit, and an exciting conductor. There is a problem that not only the configuration is increased, but also the cost is increased.

  The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor integrated circuit for an earth leakage breaker corresponding to the earth leakage protection characteristics of “Type A” without significantly changing the existing configuration. And

  In order to solve the above-mentioned problems, the present invention amplifies the leakage current detection signal detected by the zero-phase current transformer, converts it into a detection voltage, and outputs it, and the detection voltage absolute of the detection voltage output by the amplifier. A full-wave detection comparator circuit that determines whether the value exceeds a certain voltage value and outputs a leakage signal, and adds a time value while the detection voltage absolute value exceeds the certain voltage, and the detection voltage absolute A semiconductor integrated circuit for earth leakage circuit breaker comprising: an integration circuit that subtracts the time value while the value does not exceed the constant voltage and outputs an earth leakage determination signal when the integrated value of the time value exceeds a first threshold value Is provided. In the semiconductor integrated circuit for an earth leakage breaker, the integration circuit includes the up / down counter for outputting an integrated value obtained by adding or subtracting the time value, and the earth leakage signal as a reference clock signal for the up / down counter for counting the time value. Based on the clock synthesis circuit that outputs a first clock signal at the time of addition and outputs a second clock signal having a frequency lower than that of the first clock signal at the time of subtraction, and the integrated value of the up / down counter becomes the first threshold value. A first threshold value detection circuit that detects that the up / down counter is stopped and outputs the leakage determination signal; and after the first threshold value detection circuit stops the addition operation of the up / down counter, Before detecting that the integrated value of the up / down counter has decreased to a second threshold value smaller than the first threshold value, A second threshold detection circuit for stopping the output of the leakage determination signal; and a zero count detection circuit for detecting that the integrated value of the up / down counter has decreased to zero and stopping the subtraction operation of the up / down counter. ing.

  The semiconductor integrated circuit for earth leakage circuit breaker having the above configuration has a pulsating current leakage in which the subtraction period becomes longer by reducing the frequency of the second clock signal to be subtracted from the first clock signal to be added by the up / down counter. There is an advantage that detection can be performed even for current.

It is a figure which shows the structural example of the integration circuit of the semiconductor integrated circuit for earth-leakage circuit breakers which concerns on 1st Embodiment. It is a circuit diagram which shows the structural example of a clock synthetic | combination circuit. It is a figure which shows the principal part waveform in a clock synthetic | combination circuit. It is a figure which shows the principal part waveform of the semiconductor integrated circuit for earth-leakage circuit breakers when a sine wave alternating current waveform is detected. It is a figure which shows the principal part waveform of the semiconductor integrated circuit for earth-leakage circuit breakers when a pulsating flow waveform is detected. It is a circuit diagram which shows the structural example of the clock synthetic | combination circuit used for the integration circuit of the semiconductor integrated circuit for earth-leakage circuit breakers which concerns on 2nd Embodiment. It is a figure which shows the principal part waveform in a clock synthetic | combination circuit. It is a figure which shows schematic structure of an earth-leakage circuit breaker. It is a figure which shows the principal part waveform of the semiconductor integrated circuit for earth-leakage circuit breakers when a sine wave alternating current waveform is detected. It is a figure which shows the principal part waveform of the semiconductor integrated circuit for earth-leakage circuit breakers when a pulsating flow waveform is detected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The overall configuration of the earth leakage breaker is the same as that shown in FIG. 8. Therefore, the explanation of the portion excluding the integration circuit of the semiconductor integrated circuit for earth leakage breaker, which is the main part of the present invention, is shown in FIG. 8 may be referred to. Moreover, in the following description, the same code | symbol may be used for a terminal name, the voltage in a terminal, a signal, etc.

  1 is a diagram showing a configuration example of an integration circuit of a semiconductor integrated circuit for earth leakage circuit breakers according to the first embodiment, FIG. 2 is a circuit diagram showing a configuration example of a clock synthesis circuit, and FIG. 3 is a main part of the clock synthesis circuit. It is a figure which shows a waveform.

  As shown in FIG. 1, the integration circuit 7 of the semiconductor integrated circuit 9 for earth leakage circuit breaker includes a clock synthesis circuit 11, an up / down counter 12, a zero count detection circuit 13, an 800 count detection circuit 14, and a 400 count detection. Circuit 15. The integration circuit 7 also includes AND gates AND1 and AND2, inverters INV1, INV2, and INV3, a NOR gate NOR, and an RS flip-flop RS-FF.

  The clock synthesis circuit 11 outputs a synthesized clock signal CLOCK synthesized by receiving the first clock signal, the second clock signal, and the signal S2 of the full-wave detection comparator circuit 6. The synthesized clock signal CLOCK is input to the up / down counter 12 as a reference clock signal. Here, the first clock signal is set to 100 kHz, and the second clock signal is set to 5 kHz having a frequency lower than that of the first clock signal. This second clock signal is generated, for example, by dividing the first clock signal.

  The up / down counter 12 has a terminal CLOCK, a terminal CMP_OUT, a terminal UP_STOP, a terminal DOWN_STOP, and a terminal INITIAL. The output of the clock synthesizing circuit 11 is input to the terminal CLOCK, the signal S2 is input to the terminal CMP_OUT, and the initial reset signal is input to the terminal INITIAL.

  The up / down counter 12 is constituted by ten D flip-flops D-FF1, D-FF2,..., D-FF10, and performs an addition operation or a subtraction operation on the input synthesized clock signal CLOCK by a signal S2. That is, the up / down counter 12 performs an addition operation when the signal S2 is at a high level, and performs a subtraction operation when the signal S2 is at a low level. In the up / down counter 12, all the D flip-flops D-FF1 to D-FF10 are reset by an initial reset signal that is output when the power supply voltage is stabilized when the power is turned on.

  The outputs Q1, Q2,..., Q10 of the D flip-flops D-FF1 to D-FF10 are input to the zero count detection circuit 13, the 800 count detection circuit 14, and the 400 count detection circuit 15, respectively.

  The zero count detection circuit 13 determines whether or not the integrated value of the up / down counter 12 is zero. If all the outputs Q1, Q2,... The signal is input to the terminal DOWN_STOP of the up / down counter 12. As a result, the up / down counter 12 stops the subtraction operation when the integrated value is subtracted to zero.

  The 800 count detection circuit 14 determines whether or not the integrated value of the up / down counter 12 has increased to reach the determination threshold value VthH, and when the integrated value reaches 800 counts corresponding to the determination threshold value VthH, The signal is output. The output of the 800 count detection circuit 14 is connected to one input of the AND gate AND1, and the signal S2 is input to the other input of the AND gate AND1. The output of the AND gate AND1 is connected to the terminal UP_STOP of the up / down counter 12 via the set input S of the RS flip-flop RS-FF and the inverter INV2. Thus, when the high level signal S2 is input and the 800 count detection circuit 14 detects the integrated value of 800 counts, the RS flip-flop RS-FF outputs the high level signal S3 as the integration circuit output. . At the same time, the 800 count detection circuit 14 stops the addition operation of the up / down counter 12 by supplying a low level signal to the terminal UP_STOP of the up / down counter 12.

  The 400 count detection circuit 15 constitutes a digital comparator with hysteresis together with the 800 count detection circuit 14, and after the integrated value of the up / down counter 12 reaches the determination threshold value VthH, the integrated value reaches the determination threshold value VthL by the subtraction operation. Determine whether or not. The 400 count detection circuit 15 outputs a high level signal when detecting that the integrated value of the up / down counter 12 has decreased to a value of 400 counts corresponding to the determination threshold VthL after reaching the determination threshold VthH. The output of the 400 count detection circuit 15 is connected to one input of the AND gate AND2, and the signal S2 is input to the other input of the AND gate AND2 via the inverter INV1. An output of the AND gate AND2 is connected to one input of the NOR gate NOR, and an initial reset signal is input to the other input of the NOR gate NOR via the inverter INV3. The output of the NOR gate NOR is connected to the reset input R of the RS flip-flop RS-FF. As a result, when the low level signal S2 is input to the up / down counter 12 and the 400 count detection circuit 15 detects the integrated value of 400 counts, the RS flip-flop RS-FF is reset as an integration circuit output. A low level signal S3 is output. The RS flip-flop RS-FF is also reset when the initial reset signal is input, and the signal S3 is forcibly set to a low level.

  As shown in FIG. 2, the clock synthesis circuit 11 includes inverters INV11 and INV12, a NOR gate NOR11, a NAND gate NAND11, and an OR gate OR11.

  The NAND gate NAND11 receives the first clock signal at one input and the signal S2 at the other input. The output of the NAND gate NAND11 is connected to one input of the OR gate OR11 via the inverter INV12 and supplies the high-speed data signal DH. In the NOR gate NOR11, the second clock signal is input to one input via the inverter INV11, and the signal S2 is input to the other input. The output of the NOR gate NOR11 is connected to the other input of the OR gate OR11 and supplies the low speed data signal DL.

  Next, the operation of the clock synthesis circuit 11 will be described with reference to FIG. The NAND gate NAND11 and the inverter INV12 (that is, the AND gate) generate the high-speed data signal DH by passing the first clock signal only during the period when the signal S2 is at the high level. Inverter INV11 and NOR gate NOR11 generate the low-speed data signal DL by allowing the second clock signal to pass only during the period when signal S2 is at a low level. The OR gate OR11 synthesizes the high-speed data signal DH and the low-speed data signal DL and outputs a synthesized clock signal CLOCK.

Next, the operation of the earth leakage breaker 1 including the earth leakage breaker semiconductor integrated circuit 9 including the integrating circuit 7 configured as described above will be described.
FIG. 4 is a diagram showing a main part waveform of a semiconductor integrated circuit for earth leakage breaker when a sine wave AC waveform is detected, and FIG. 5 is a diagram showing a main part waveform of the semiconductor integrated circuit for earth leakage breaker when a pulsating current waveform is detected. It is.

  First, when a leakage occurs, the leakage current detection signal detected by the zero-phase current transformer 3 flows through the current detection resistor Rs, and a leakage voltage proportional to the leakage current detection signal is generated at both ends of the current detection resistor Rs. Is done. This leakage voltage is amplified by the filter amplifier 5 and output. The signal S1 output from the filter amplifier 5 has a sinusoidal AC waveform centered on the bias voltage V_RIN as shown in FIG. 4 and is supplied to the full-wave detection comparator circuit 6.

  In the full-wave detection comparator circuit 6, when the signal S1 having a higher potential than the reference voltage V_RIN + v is input and when the filter amplifier output having a lower potential than the reference voltage V_RIN-v is input, the comparators CMP1 and CMP2 , Output a high level signal. That is, the comparators CMP1 and CMP2 output a high level signal when the detected voltage absolute value of the signal S1 exceeds a certain voltage value. Further, when the voltage of the filter amplifier output is between the reference voltage V_RIN-v and the reference voltage V_RIN + v, the comparators CMP1 and CMP2 output a low level signal. That is, the comparators CMP1 and CMP2 output a low level signal when the detected voltage absolute value of the signal S1 does not exceed a certain voltage value. Therefore, the OR gate OR receives the outputs of the comparators CMP1 and CMP2, outputs the signal S2 shown as the full-wave rectification comparator output in FIG.

  In the integration circuit 7, when the signal S2 received from the full-wave detection comparator circuit 6 is at a high level, the clock synthesis circuit 11 outputs a first clock signal of 100 kHz, and the up / down counter 12 performs an addition operation with the first clock signal. I do. Next, when the low-level signal S2 is received from the full-wave detection comparator circuit 6, the clock synthesis circuit 11 outputs a second clock signal of 5 kHz, and the up / down counter 12 performs a subtraction operation with the second clock signal. Since the frequency of the second clock signal performing the subtraction operation is 1/20 of the frequency of the first clock signal performing the addition operation, the speed subtracted by the subtraction operation is 1/20 of the speed added by the addition operation. For this reason, according to the schematic operation of the integration circuit shown in FIG. 4, the integrated value of the up / down counter 12 changes more slowly when it decreases than when it increases. Thereafter, upon receiving the high level signal S2 from the full wave detection comparator circuit 6, the up / down counter 12 performs the addition operation with the first clock signal of 100 kHz.

  As described above, when the leakage current having the sine wave AC waveform as shown in FIG. 4 is continuously detected, the integrated value of the up / down counter 12 increases, and the 800 count detection circuit 14 eventually determines the determination threshold VthH. To reach. Then, since the 800 count detection circuit 14 outputs a high level signal, the RS flip-flop RS-FF is set and the integration circuit output outputs a high level signal S3, and the up / down counter 12 performs the addition operation. Is stopped.

  Here, when the leakage state is recovered, the full-wave detection comparator circuit 6 outputs only a low level signal. Then, since the up / down counter 12 performs the subtraction operation by the second clock signal, the integrated value decreases, and eventually the 400 count detection circuit 15 decreases to the determination threshold value VthL. Then, the 400 count detection circuit 15 outputs a high level signal, so that the RS flip-flop RS-FF is reset and the signal S3 of the integration circuit output becomes low level.

  Furthermore, when the zero count detection circuit 13 detects that the integrated value has become zero following the subtraction of the up / down counter 12, the zero count detection circuit 13 outputs a high level signal, and the up / down counter 12 Stops the subtraction operation at that time.

  Next, the case where the current detected by the zero-phase current transformer 3 is a half-wave rectified pulsating waveform will be described. As shown in FIG. 5, when the output of the filter amplifier 5 is a pulsating waveform, the full-wave detection comparator circuit 6 has a high level only when the signal S1 from the filter amplifier 5 is higher in potential than the reference voltage V_RIN + v. Output a signal. Thereby, in the integration circuit 7, the up / down counter 12 performs the addition operation with the first clock signal of 100 kHz only during the period when the high level signal is input.

  When the signal S1 of the filter amplifier 5 has a potential lower than the reference voltage V_RIN + v and the full-wave detection comparator circuit 6 outputs a low level signal S2, the up / down counter 12 performs a subtraction operation with the second clock signal of 5 kHz. Do. In this case, since the speed subtracted by the subtraction operation is 1/20 of the speed added by the addition operation, the integrated value of the up / down counter 12 decreases slowly.

  Subsequently, when the signal S2 of the full-wave detection comparator circuit 6 becomes a high level, the up / down counter 12 performs an addition operation with the first clock signal from the integrated value at that time. In the example of FIG. 5, immediately before the high level of the signal S2 of the full-wave detection comparator circuit 6 ends, the integrated value of the up / down counter 12 reaches the determination threshold value VthH, and the integrating circuit 7 outputs the high level signal S3. Output.

  As described above, according to the integration circuit 7, the frequency of the clock signal is lowered during the subtraction operation of the up / down counter 12 than during the addition operation. For this reason, even if the time per cycle detected by the full-wave detection comparator circuit 6 is short, such as a leakage current having a pulsating waveform, the total integrated value of the up / down counter 12 becomes positive. Is possible. In addition, this integration circuit 7 makes the determination that there is a leakage current considerably by slowing down the subtraction operation. However, this time is sufficiently shorter than the time for determining the leakage current duration until the time delay circuit 8 shuts off the cutoff switch 2, so that there is no practical problem.

  The above integrating circuit 7 is obtained by adding a clock synthesizing circuit 11 whose configuration is shown in FIG. 2 or a clock synthesizing circuit 11a to be described later and a 5 kHz clock generating circuit (not shown) to an existing integrating circuit that operates with a clock signal of 100 kHz. realizable. Therefore, it is possible to provide a semiconductor integrated circuit for an earth leakage breaker corresponding to the leakage protection characteristic of “Type A” that can detect an earth leakage current having a pulsating current waveform relatively easily.

  FIG. 6 is a circuit diagram showing a configuration example of a clock synthesis circuit used in the integration circuit of the semiconductor integrated circuit for earth leakage circuit breaker according to the second embodiment, and FIG. 7 is a diagram showing main waveforms in the clock synthesis circuit. . In FIG. 6, the same components as those shown in FIG. 2 are denoted by the same reference numerals.

  In this clock synthesis circuit 11a, D flip-flops D-FF11 and D-FF12 and an inverter INV13 are added to the circuit of FIG. That is, a D flip-flop D-FF11 is arranged between the NOR gate NOR11 and the OR gate OR11, and a D flip-flop D-FF12 is arranged between the full-wave detection comparator output (signal S2 input), the NOR gate NOR11, and the NAND gate NAND11. ing. The first clock signal is supplied to the clock inputs of the D flip-flops D-FF11 and D-FF12 via the inverter INV13. The D flip-flops D-FF11 and D-FF12 are configured to be reset when receiving an initialization reset signal.

  Here, the D flip-flop D-FF12 latches the signal S2 in synchronization with the first clock signal, and outputs a leakage detection signal normalized to the first clock signal. Further, the D flip-flop D-FF11 latches the signal 5k_DL of the second clock signal in synchronization with the first clock signal, and outputs a low-speed data signal DL normalized to the first clock signal.

  Next, the operation of the clock synthesis circuit 11a will be described with reference to FIG. First, the full-wave detection comparator output is converted into a leakage detection signal that becomes a high level and a low level in synchronization with the fall of the first clock signal. The NAND gate NAND11 and the inverter INV12 (that is, the AND gate) generate the high-speed data signal DH by passing the first clock signal only during a period when the leakage detection signal is at a high level. The inverter INV11 and the NOR gate NOR11 generate the signal 5k_DL by passing the second clock signal only during a period when the leakage detection signal is at a low level, and the signal 5k_DL is low-speed data synchronized with the falling of the first clock signal. Converted to signal DL. The OR gate OR11 synthesizes the high-speed data signal DH and the low-speed data signal DL and outputs a synthesized clock signal CLOCK.

  According to the clock synthesis circuit 11a, the signal S2 and the second clock signal can be synchronized with the first clock signal. For this reason, for example, it is possible to prevent generation of an impulse voltage having a small time width as seen in the high-speed data signal DH and the synthesized clock signal CLOCK in FIG. 3, and the up / down counter 12 can be stably operated. become able to. Of course, in the case of normalization by the first clock signal, the high-speed data signal DH, the low-speed data signal DL, and the synthesized clock signal CLOCK have an error corresponding to the ON time width (5 μs) of 100 kHz. However, such an error is sufficiently shorter than the accumulated time of 8 ms (for 800 clocks) and is within an allowable range.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to these preferred embodiments, and various changes and modifications can be made within the spirit of the present invention. is there. For example, in this embodiment, the frequency of the first clock signal is set to 100 kHz, and the frequency of the second clock signal is set to 5 kHz that is 1/20 of the first clock signal. However, the present invention is not limited to this value.

DESCRIPTION OF SYMBOLS 1 Leakage breaker 2 Breaking switch 3 Zero phase current transformer 4 Leakage detection circuit 5 Filter amplifier 6 Full wave detection comparator circuit 7 Integration circuit 8 Time delay circuit 9 Semiconductor integrated circuit for earth leakage breaker 11, 11a Clock synthesis circuit 12 Up / down counter 13 Zero count detection circuit 14 800 count detection circuit (first threshold value detection circuit)
15 400 count detection circuit (second threshold detection circuit)
AND1, AND2 AND gate C1, C2 capacitor CMP1, CMP2 comparator D-FF1 to D-FF10, D-FF11, D-FF12 D flip-flop INV1, INV2, INV3, INV11, INV12, INV13 Inverter L Load NAND11 NAND gate NOR, NOR11 NOR gate OP operational amplifier OR, OR11 OR gate R1, R2, R3 resistance RS-FF RS flip-flop Rs current detection resistance T transformer

Claims (3)

An amplifier that amplifies the leakage current detection signal detected by the zero-phase current transformer, converts it to a detection voltage and outputs it, and determines whether the detection voltage absolute value of the detection voltage output by the amplifier exceeds a certain voltage value. A full-wave detection comparator circuit for outputting a leakage signal, and adding a time value while the detected voltage absolute value exceeds the fixed voltage, and while the detected voltage absolute value does not exceed the fixed voltage, In a semiconductor integrated circuit for earth leakage circuit breaker comprising an integration circuit that subtracts a time value and outputs an earth leakage determination signal when the integrated value of the time value exceeds a first threshold value,
The integration circuit includes:
An up / down counter that outputs an integrated value obtained by adding or subtracting the time value;
As a reference clock signal for the up / down counter for counting the time value, a first clock signal is output at the time of addition based on the leakage signal, and a second clock signal having a frequency lower than that of the first clock signal is output at the time of subtraction. A clock synthesis circuit;
A first threshold value detection circuit that detects that the integrated value of the up / down counter has reached the first threshold value, stops the addition operation of the up / down counter, and outputs the leakage determination signal;
After the first threshold detection circuit stops the addition operation of the up / down counter, it detects that the integrated value of the up / down counter has decreased to a second threshold smaller than the first threshold, and outputs the leakage determination signal. A second threshold detection circuit to be stopped;
A zero count detection circuit for detecting that the integrated value of the up / down counter has decreased to zero and stopping the subtraction operation of the up / down counter;
A semiconductor integrated circuit for an earth leakage circuit breaker.   2. The semiconductor integrated circuit for an earth leakage breaker according to claim 1, wherein the clock synthesizing circuit standardizes the leakage signal and the second clock signal in synchronization with the first clock signal.   A time delay circuit that receives the leakage determination signal from the integration circuit and determines whether or not a time value determined to be a leakage has continued for a predetermined time, and operates a cutoff switch according to the determination result; 2. The semiconductor integrated circuit for an earth leakage circuit breaker according to claim 1, wherein:

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