JP2017085857A - Dc/dc converter and control circuit therefor, control method, and system power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve response delay, instability and the like due to switching of the number of channels in a multichannel DC/DC converter.SOLUTION: The DC/DC converter operates with at least one continuous PWM period as a period group T. When the number of active channels is L, in each PWM period included in the period group T, switching transistors of the L channels are turned on and off. For the remaining (M-L) channels, the connection point between the switching transistor and a rectifying element is controlled to have high impedance. Also, during the period group T, each of the M switching transistors is controlled to be on and off at least once.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a DC / DC converter.

In various electronic devices, a DC / DC converter that converts a DC voltage of one voltage value into a DC voltage of another voltage value is used. In order to suppress the ripple of the input current of the DC / DC converter, a multi-phase DC / DC converter is used. FIG. 1 is a circuit diagram of a multi-phase boost DC / DC converter (simply referred to as a DC / DC converter) 900. The DC / DC converter 900 receives the DC input voltage _VIN on the input line 902 and generates a boosted output voltage _VOUT on the output line 904. The DC / DC converter 900 is configured with M channels (M is an integer of 2 or more). The DC / DC converter 900 has a switching transistor M1, an inductor L1, and a rectifier element D1 for each channel, and has an output capacitor C1 common to the M channels. In this specification, channel numbers are indicated by subscripts as necessary.

The controller 910 includes an error amplifier 912 common to the M channels, peak current mode pulse modulators 914_1 to 914_M provided for each channel, and drivers 922_1 to 922_M provided for each channel. Resistors R11, R12 are, divide the output voltage _{V OUT} minute, generates a feedback signal _{V FB} corresponding to the output voltage _{V OUT.} The error amplifier 912 amplifies an error between the feedback signal V _FB and the reference value V _REF that is a target value thereof, and generates an error signal V _ERR corresponding to the error. The error signal V _ERR is supplied to a plurality of channels of pulse modulators 914_1 to 914_M.

The pulse modulator 914 includes a PWM (pulse width modulation) comparator 916, a logic circuit 918, and a slope compensator 920. The current sense resistor R1 is provided to detect a current flowing through the switching transistor M1 during the ON period of the switching transistor M1, and generates a current detection signal _VIS indicating the current. The slope compensator 920 superimposes the slope signal V _SLOPE on the current detection signal V _IS . The PWM comparator 916 compares the current detection signal V _IS and the error signal V _ERR , and asserts a reset signal (also referred to as an off signal) ICMP (for example, high level) when the current detection signal V _IS reaches the error signal V _ERR. . In response to the reset signal ICMP, the logic circuit 918 transitions the PWM signal _SPWM to an off level (for example, a low level) that instructs the switching transistor M1 to be turned off. In addition, the logic circuit 918 transitions the PWM signal S _PWM to an on level (for example, a high level) instructing the switching transistor M1 to be turned on in response to a PWM clock (also referred to as a set signal or an on signal) that is asserted every predetermined period. Let The driver 922 drives the switching transistor M1 in response to the PWM signal _{S PWM.}

In a multi-channel DC / DC converter, the number of active channels may be changed according to the state of a load connected to the output line 904, in other words, according to the load current I _LOAD . For example, an M = 4 channel DC / DC converter may be configured to be selectable from 1 channel operation, 2 channel operation, and 4 channel operation.

  2 (a) and 2 (b) are diagrams for explaining switching of the number of active channels. 2A shows a single channel (single phase) operation, and FIG. 2B shows a two channel operation (two phase operation). As shown in FIG. 2A, in the single channel operation, only the first channel CH1 is switched and the second channel CH2 is stopped. As shown in FIG. 2B, in the 2-channel multi operation, the first channel CH1 and the second channel CH2 are switched with a predetermined phase difference.

  As a result of examining the switching operation of the number of channels in the multi-channel DC / DC converter, the present inventor has come to recognize the following problems. In the single channel operation of FIG. 2A, the operation of the inactive second channel CH2 is completely stopped. Therefore, when the single channel operation of FIG. 2A is switched to the 2-channel operation of FIG. 2B, the response of the second channel CH2 is delayed. For example, in the bootstrap DC / DC converter, during the single channel operation, the bootstrap capacitor is not charged for the second channel CH2, and the transistor cannot be switched for several cycles immediately after switching to the 2-channel operation.

  Or even in DC / DC converters other than the bootstrap system, the steady state (current or current at any node) inside the control circuit differs between single-channel operation and 2-channel operation, so that transition takes time. It becomes a cause of response delay and instability.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of the exemplary purposes of one aspect thereof is a DC / DC converter capable of improving problems such as response delay and instability associated with switching of the number of channels, and its The provision of control circuits.

  One embodiment of the present invention relates to a control circuit for a DC / DC converter having a plurality of M channels (M is an integer of 2 or more). The DC / DC converter has a switching transistor, an inductor, and a rectifying element provided for each channel. The control circuit includes an error amplifier that amplifies an error between the feedback signal corresponding to the output voltage of the DC / DC converter and its target value and generates an error signal, and M pulse width modulators corresponding to the M channels. , Each of which generates a PWM (Pulse Width Modulation) signal having a duty ratio according to an error signal, and a multi-phase controller that switches the number of active channels L (1 ≦ L ≦ M) And comprising. With at least one continuous PWM cycle as a cycle group, in each PWM cycle included in the cycle group, the switching transistors of L channels are on / off controlled, and the remaining (ML) channels are The connection point between the switching transistor and the rectifying element is controlled to have a high impedance, and each of the M switching transistors is on / off controlled at least once during the period group.

  Focusing on one PWM cycle, since L switching transistors are switched, the current supply capability is equivalent to the conventional L channel operation. When the period group is taken as a unit, the switching transistors of all the channels are switched at least once during that period. As a result, the states of the pulse width modulators and other circuits of all channels can be maintained close to the active state, and problems such as response delay and instability can be improved.

  When M = 2 and L = 1, the period group includes two PWM periods. (I) In the first PWM period included in the period group, the switching transistor of the first channel switches, and the second channel (Ii) In the second PWM cycle included in the cycle group, the first channel may become high impedance, and the switching transistor of the second channel may be switched. When L = 2, the cycle group includes one PWM cycle. (I) In one PWM cycle included in the cycle group, the switching transistor of the first channel and the switching transistor of the second channel are switched. Also good.

  When L = 2, the switching transistor of the first channel and the switching transistor of the second channel may be switched with a phase difference of 180 °.

  When M = 4 and L = 1, the period group includes four PWM periods. (I) In the first PWM period included in the period group, the switching transistor of the first channel switches and the second channel To the fourth channel becomes high impedance, (ii) in the second PWM period included in the period group, the switching transistor of the second channel is switched, and the first, third, and fourth channels become high impedance, and (iii) period In the third PWM cycle included in the group, the switching transistor of the third channel switches, and the first, second, and fourth channels become high impedance. (Iv) In the fourth PWM cycle included in the cycle group, the fourth channel The switching transistor switches, and the first, second, and third channels Channel may be a high impedance. When L = 2, the period group includes two PWM periods. (I) In the first PWM period included in the period group, the switching transistors of two channels among the first to fourth channels are switched, and the remaining Two channels may become high impedance, and (ii) in the second PWM period included in the period group, the remaining two channels of switching transistors may be switched, and the two channels may become high impedance. When L = 4, the periodic group includes one PWM period, and (i) the switching transistors of the first to fourth channels may switch in a single PWM period included in the periodic group.

  When L = 2, in the first PWM period, the two channel switching transistors are switched with a phase difference of 180 °, and in the second PWM period, the remaining two channels of the switching transistors are switched with a phase difference of 180 °. When 4 = 4, the switching transistors of 4 channels may switch with a phase difference of 90 ° in a single PWM cycle.

  When the number of PWM periods included in the period group is K, K = M / L may be satisfied.

Each of the M pulse width modulators is in a peak current mode, each of which compares the current detection signal indicating the current flowing through the corresponding switching transistor with an error signal, and turns off the PWM signal according to the output of the comparator And a logic circuit that makes a transition to a level. For each of the plurality of M channels, the control circuit superimposes a correction signal corresponding to the difference between the corresponding current detection signal and the average value of the plurality of M channel current detection signals on at least one of the two inputs of the corresponding comparator. A current balance circuit may be further provided.
According to this aspect, the coil currents of a plurality of channels can be balanced. When this current balance circuit is used, the response delay of the current balance circuit may become a problem when the number of channels L is changed, but the response delay of the current balance circuit is caused by operating all the channels during the period group. Can solve the problem.

  The current balance circuit may superimpose the correction signal on the input on the error signal side for each of the plurality of M channels.

  The DC / DC converter may be a bootstrap system. Since all the channels operate during the period group, the voltage of the bootstrap capacitor can be maintained, so that desired characteristics can be obtained immediately after the number of channels is changed.

  The DC / DC converter may be a step-down type. In particular, in a step-down DC / DC converter, when the voltage of the bootstrap capacitor becomes small, the switching transistor cannot be driven. By maintaining the voltage of the bootstrap capacitor, the switching transistor can be driven even immediately after switching. This makes it possible to improve response delay.

  In one embodiment, the control circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to a DC / DC converter. The DC / DC converter includes any one of the control circuits described above.

  Another aspect of the invention relates to a system power supply. The system power supply may include the above-described DC / DC converter.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, response delay and instability associated with switching of the number of channels can be improved.

FIG. 3 is a circuit diagram of a multi-phase boost DC / DC converter. 2 (a) and 2 (b) are diagrams for explaining switching of the number of active channels. 1 is a circuit diagram of a DC / DC converter including a control circuit according to an embodiment. 4A and 4B are operation waveform diagrams of the DC / DC converter with M = 2. FIGS. 5A to 5C are operation waveform diagrams of the DC / DC converter with M = 4. FIG. 3 is a circuit diagram illustrating a first embodiment of a control circuit. 7A and 7B are operation waveform diagrams of the DC / DC converter of FIG. It is a circuit diagram which shows the structural example of a current balance circuit. It is a circuit diagram which shows the structural example of a superimposition circuit. It is a circuit diagram which shows the structural example of a sample hold circuit. FIG. 11 is an operation waveform diagram of the sample and hold circuit of FIG. 10. It is a circuit diagram showing an example of composition of an individual current generating circuit, an average current generating circuit, and a differential current generating circuit. FIGS. 13A and 13B are circuit diagrams showing a second embodiment of the DC / DC converter. It is a block diagram of the system power supply using the DC / DC converter which concerns on embodiment. FIGS. 15A and 15B are operation waveform diagrams of a DC / DC converter according to a modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  “Signal A (voltage, current) is in response to signal B (voltage, current)” means that signal A has a correlation with signal B. Specifically, (i) signal A Is signal B, (ii) signal A is proportional to signal B, (iii) signal A is obtained by level shifting signal B, and (iv) signal A is obtained by amplifying signal B. If (v) signal A is obtained by inverting signal B, it means (vi) or any combination thereof. It will be understood by those skilled in the art that the “depending” range is determined depending on the type and application of the signals A and B.

FIG. 3 is a circuit diagram of the DC / DC converter 100 including the control circuit 200 according to the embodiment. As in FIG. 1, the DC / DC converter 100 is a multi-channel, multi-phase boost converter that receives a DC input voltage _VIN on the input line 102 and a boosted output voltage V _OUT on the output line 104. Is generated. The DC / DC converter 100 includes a plurality of M channels (M is an integer of 2 or more). The number of channels M is arbitrary, and may be determined according to the use of the DC / DC converter 100, such as 2 channels, 3 channels, 4 channels, 6 channels, 8 channels, 12 channels, and 16 channels.

  The DC / DC converter 100 includes an output circuit 110 and a control circuit 200. The output circuit 110 includes a switching transistor M1, an inductor L1, and a rectifying element D1 for each channel, and includes an output capacitor C1 and resistors R11 and R12 that are common to the M channels.

The control circuit 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate. The control circuit 200 has an output (OUT) terminal for each channel. The control circuit 200 also has a common feedback (FB) terminal for all channels. A feedback signal V _FB corresponding to the output voltage _VOUT is fed back to the FB terminal. Control circuit 200, as the feedback signal _{V FB} approaches its target value _{V REF,} and controls the switching transistor _M1 1 to M1 _M Multiple channels CH1～CHM. The switching transistor M1 may be integrated in the control circuit 200.

The control circuit 200 includes an error amplifier 202, pulse width modulators 204_1 to 204_M, drivers 212_1 to 212_M, and a current balance circuit 220. The error amplifier 202 amplifies an error between the feedback signal V _FB corresponding to the output voltage V _OUT of the DC / DC converter 100 and its target value V _REF to generate an error signal V _ERR .

The M pulse width modulators 204_1 to 204_M correspond to M channels. The pulse width modulator 204 — i (1 ≦ i ≦ M) generates a PWM signal S _PWMi having a duty ratio corresponding to the error signal V _ERR .

The plurality of drivers 212_1 to 212_M correspond to the plurality of channels CH1 to CHM. i-th driver 212_i, in response to the PWM signal _{S PWM} from the corresponding pulse width modulator 204_I, driving the corresponding switching transistor M1_1.

The multi-phase controller 250 switches the active channel among the plurality of channels CH1 to CHM according to the DC / DC converter 100 and the load state. For example, the multi-phase controller 250 controls the number L of active channels (1 ≦ L ≦ M) and the operation phase based on the load current I _LOAD of the DC / DC converter 100. Specifically, the multi-phase controller 250 increases the number of active channels as the load current I _LOAD increases. The multi-phase controller 250 may monitor the load current I _LOAD or may change the number of channels based on a control command from an external microcomputer or a control signal from a load connected to the output line 104. Good.

The plurality of channels CH1 to CHM are controlled as follows.
That is, when the L channel of the M channel is active, PWM period _{T 1,} T 2 ... at least one continuous (and the K), the _{T K} as a cycle group _{T G,} each contained in a period group _{T G} PWM period _{T 1,} T 2 ..., in _{T K,} the switching transistor of L channel is turned on, is turned off control for the remaining (M-L) number of channels, the connection of the switching transistor M1 and the rectifying element D1 The point is controlled to be high impedance (Hi-Z), and each of the M switching transistors M1 is turned on at least once during the periodic group T _G (= T ₁ , T ₂ ..., T _K ). Controlled off.

The above is the configuration of the control circuit 200. Next, the operation will be described.
4A and 4B are operation waveform diagrams of the DC / DC converter with M = 2. The vertical axis and horizontal axis of the waveform diagrams and time charts in this specification are appropriately expanded and reduced for easy understanding, and each waveform shown is also simplified for easy understanding. Or it is exaggerated or emphasized. 4A shows the case of L = 1, and FIG. 4B shows the case of L = 2. As shown in FIG. 4A, when L1 =, the periodic group _TG includes K = 2 PWM periods T ₁ and T ₂ , and (i) in the first PWM period T ₁ included in the periodic group _TG . , the switching transistor M1 ₁ of the first channel CH1 is switched, the second channel CH2 becomes high impedance. In the 2PWM period _{T 2} contained in (ii) period group _{T G,} the first channel CH1 is a high impedance, the switching transistor M1 ₂ of the second channel CH2 is switched.

As shown in FIG. 4B, when L = 2, the periodic group _TG includes one PWM period. In one PWM period included in (i) the period group _{T G,} the switching transistor M1 ₁ of the first channel CH1, the switching transistor M1 ₂ of the second channel CH2 is switched. Note when a L = 2, switching transistors M1 ₁ and the switching transistor M1 ₂ of the second channel CH2 of the first channel CH1 can be switched with a phase difference of 180 °. Thereby, the current ripple can be reduced.

  FIGS. 5A to 5C are operation waveform diagrams of the DC / DC converter with M = 4. FIG. 5 (a) shows the case of L = 1, FIG. 5 (b) shows the case of L = 2, and FIG. 5 (c) shows the case of L = 4.

As shown in FIG. 5A, when L = 1, the period group _TG includes K = 4 PWM periods T _{1 to} T ₄ . (I) In the 1PWM period _{T 1,} the switching transistor M1 ₁ of the first channel CH1 is switched, the fourth channel CH4 is high impedance from the second channel CH2. (Ii) In the 2PWM period _{T 2,} the switching transistor M1 ₂ of the second channel CH2 is switched, first, third, fourth channel is a high impedance. In (iii) the 3PWM period _{T 3,} the switching transistor M1 ₃ of the third channel CH3 is switched, first, second, fourth channel is a high impedance. (Iv) In the 4PWM period _{T 4,} the switching transistor M1 ₄ of the fourth channel Ch4 is switched, first, second, third channel is a high impedance.

As shown in FIG. 5B, when L = 2, the period group _TG includes K = 2 PWM periods T ₁ and T ₂ . (I) In the 1PWM period _{T 1,} the switching transistor _M1 1, M1 ₂ of two channels of the fourth channel from the first (here CH1, CH2) are switching, the remaining two channels (here CH3, CH4) Becomes high impedance. (Ii) In the 2PWM period _{T 2,} and the switching transistor _M1 3, M1 ₄ switching of the remaining two channels (CH3, CH4), 2-channel (CH1, CH1) is a high impedance. In each PWM cycle, the switching transistor M1 may switch with a phase difference of 180 ° to reduce current ripple.

As shown in FIG. 5C, when L = 4, the period group _TG includes K = 1 PWM period.
In a single PWM cycle, the switching transistor _M1 1 to M1 ₄ of the fourth channel from the first is switched. These switching transistors M1 _{1 to} M1 ₄ may be switched with a phase difference of 90 ° in order to reduce current ripple.

In general, when K is the number of PWM periods included in the period group _TG , K = M / L may be set. Thereby, the switching transistors of all the channels can be controlled equally.

The above is the operation of the control circuit 200 and the DC / DC converter 100 including the control circuit 200.
Focusing on one PWM cycle, since L switching transistors are switched, the current supply capability is equivalent to the conventional L channel operation. When the periodic group _TG is taken as a unit, the switching transistors M1 _{1 to} M1 _M of all the channels are switched at least once during that period. As a result, the state of the pulse width modulator of all channels and other circuits (for example, a bootstrap circuit to be described later and a current balance circuit to be described later) can be maintained close to an active state. Qualitative can be improved.

  The present invention is understood as the block diagram and circuit diagram of FIG. 3 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. In the following, more specific embodiments will be described in order not to narrow the scope of the present invention, but to help understanding and clarify the essence and circuit operation of the present invention.

(First embodiment)
FIG. 6 is a circuit diagram showing a first embodiment of the control circuit 200. In the control circuit 200 of FIG. 6, the pulse width modulator 204 is in the peak current mode. The output circuit 110 includes current sense resistors R1 _{1 to} R1 _M. The current sense resistor R1 for each channel is provided between the corresponding switching transistor M1 and the ground, and a voltage drop proportional to the current (that is, the coil current) flowing through the switching transistor M1 during the ON period of the switching transistor M1 is provided between both ends thereof. Occur. The voltage drop of the current sense resistor R1 is input to the corresponding CS terminal as the current detection signal _VIS . In FIG. 6, the multi-phase controller 250 is omitted.

The pulse width modulator 204 includes a PWM comparator 206, a logic circuit 208, and a slope compensator 210. The PWM comparator 206 of the i-th (1 ≦ i ≦ M) channel compares the current detection signal V _IS indicating the current I _M1 flowing through the corresponding switching transistor M1 with the error signal V _ERR . The logic circuit 208 transitions the PWM signal to an off level (for example, a low level) in response to the output (reset signal) ICMP of the PWM comparator 206. The logic circuit 208 causes the PWM signal to transition to the on level in synchronization with the PWM clock (set signal) asserted at the PWM cycle interval. The slope compensator 210 superimposes the slope voltage V _SLOPE on one of the current detection signal V _{IS and the} error signal V _ERR .

For each of the plurality of channels CH1 to CHM, the current balance circuit 220 corresponds to the difference between the corresponding current detection signal V _ISi and the average value V _AVE of the current detection signals V _{IS1 to} V _ISM of the plurality of channels CH1 to CHM. The correction signal V _CMPi is superimposed on at least one of the two inputs of the corresponding PWM comparator 206_i.

Preferably, the current balance circuit 220 superimposes the correction signals V _{CMP1 to VCMPM} on the error signal V _ERR side input (the inverting input terminal side of the PWM comparator 206 in FIG. 3) for each of the plurality of channels CH1 to CHM. That is, the PWM comparator 206_i compares the error signal V _ERRi on which the correction signal V _CMPi is superimposed with the current detection signal V _ISi, and asserts the ICMP signal when V _ISi > V _ERRi .

For example, the current balance circuit 220 samples the peaks of the current detection signals V _{IS1 to} V _ISM of the plurality of channels CH1 to CHM, and corrects the correction signals V _{CMP1 to} V _CMP based on the sampled current detection signals V _IS1 ′ to V _ISM ′. _{A CMPM} can be generated. The current detection signal V _ISi peaks in the i-th channel when the switching transistor M1 is turned off, that is, when the ICMP signal is asserted. Therefore, by holding the peak, the ICMP signal or the PWM signal can be used as the timing signal, so that the control can be simplified.

Next, the operation of the control circuit 200 in FIG. 6 will be described. 7A and 7B are operation waveform diagrams of the DC / DC converter 100 of FIG. FIG. 7A shows a waveform when the current balance circuit 220 is not operated. When focusing on the first channel CH1, as shown in FIG. 7A, the peak value I _{PEAK (FB)} of the coil current _IL1 determined according to the error signal _VERR is the peak value of the coil current of all channels. It is assumed that the deviation δI _{1 is} smaller than the average I _AVE .

The operation of the current balance circuit 220 will be described with reference to FIG. The current balance circuit 220 generates a correction signal V _CMP1 corresponding to the deviation δI ₁ and superimposes it on the error signal V _ERR . PWM comparator 206, the corrected error signal _{V ERR1} compared with the current detection signal _{V IS1,} it asserts the ICMP signal when the V _{IS1> V ERR1,} the switching transistor M1 is turned off. The current balance circuit 220 performs the same correction for the other channels CH2 to CHM. The above is the operation of the control circuit 200.

According to the control circuit 200, the current balance circuit 220 causes the peak of the coil current I _Li of each channel CHi to approach the average value I _AVE of the peak of the coil currents I _{L1 to} I _LM of all the channels CH1 to CHM. As a result, the peaks of the coil currents of all the channels coincide with each other, and the current balance between the channels can be improved.

The correction signal V _CMP is superimposed on the error signal V _ERR on the inverting input terminal (−) side of the PWM comparator 206, and the current detection signal V _IS on the non-inverting input terminal (+) side of the PWM comparator 206 has a reverse polarity. Superimposing the correction signal V _CMP is equivalent, and any method may be adopted. By the way, the provision of the current balance circuit 220 is nothing other than the introduction of a new control system, and thus has a considerable influence on the stability of the DC / DC converter 100. As a result of investigation by the present inventor, it has been confirmed that in some circuits, the former (superimposed on the error signal _VERR ) increases the stability of the system. Therefore, by superimposing the correction signal V _CMP on the error signal V _ERR side, the current balance can be improved without impairing the stability of the system. Incidentally, not necessarily the stability of the system is reduced just because superimposing the correction signal V _CMP to the current detection signal V _IS side, if the decrease in stability is not a problem, the current correction signal V _CMP It may be superimposed on the detection signal _VIS side.

  The operation when the current balance circuit 220 of FIG. 6 and multi-channel control are used together will be considered. As shown in FIGS. 2A and 2B, when an inactive channel is completely stopped, the pulse width modulator 204 and the driver 212 of that channel are stopped, and the coil current of that channel becomes zero. When a channel switches from inactive to active, the coil current of that channel increases from zero, so the average value of the coil current immediately after switching is reduced, which adversely affects the current control of other channels. Become.

  As described with reference to FIGS. 3 to 5, if the multi-channel control according to the embodiment is used together, all the channels operate, so that the operation of the current balance circuit 220 can be stabilized. it can.

FIG. 8 is a circuit diagram illustrating a configuration example of the current balance circuit 220. The current balance circuit 220a includes a plurality of sample and hold circuits 222_1 to 222_M corresponding to a plurality of channels. The i-th sample hold circuit 222_i samples the corresponding current detection signal V _ISi at a predetermined timing within each PWM cycle. For example, as described above, when matching the peak of the coil current I _L, the sample-hold circuit 222_i, at the peak of the current detection signal V _ISi, it may be performed sampling. Sampling timing can be generated by using the ICMP signal of the corresponding channel or the negative edge of the PWM signal _SPWM .

Instead of aligning the peaks of the coil currents I _{L1 to} I _LM for all channels, their bottoms may be aligned. In this case, the sample hold circuit 222_i may perform sampling at the bottom of the current detection signal V _ISi , in other words, immediately after the switching transistor M1 is turned on. For example, the sampling timing can be generated using the positive edge of the PWM signal _SPWM . Alternatively, the sampling timing may be set at an arbitrary position (20%, 40%, 50%, 80%, etc.) within the PWM cycle.

  The current balance circuit 220a further includes a plurality of individual current generation circuits 224_1 to 224_M, an average current generation circuit 226, a plurality of difference current generation circuits 228_1 to 228_M, and a plurality of superposition circuits 230_1 to 230_M.

The plurality of individual current generation circuits 224_1 to 224_M correspond to the plurality of channels CH1 to CHM. The i-th individual current generation circuit 224_i generates an individual current I _i corresponding to the corresponding current detection signal V _IS . The average current generation circuit 226 generates an average current I _AVE corresponding to the average of the individual currents I _{1 to} I _M of the plurality of channels CH _{1 to} CHM.
I _AVE = (I ₁ + I ₂ +... + I _M ) / M

The plurality of differential current generation circuits 228_1 to 228_M correspond to the plurality of channels CH1 to CHM. The i-th differential current generation circuit 228_i generates a differential current ΔI _i between the corresponding individual current I _i and the average current I _AVE . The differential current ΔI _i corresponds to the current deviation δI ₁ in the waveform diagram of FIG.

The plurality of superposition circuits 230_1 to 230_M correspond to the plurality of channels CH1 to CHM. The i-th superimposing circuit 230_i uses the offset voltage V _OFSi corresponding to the corresponding differential current ΔI _i as the correction signal V _{CMPi to} the non-inverting input terminal (+) and the inverting input terminal (−) of the corresponding PWM comparator 206. Superimpose on at least one of them.

FIG. 9 is a circuit diagram illustrating a configuration example of the superimposing circuit 230. The superimposing circuit 230_i includes an offset resistor R21_i and a third capacitor C21_i. The offset resistor R21 has a first end E1 connected to the output of the error amplifier 202, and a second end E2 connected to the inverting input terminal (−) of the corresponding PWM comparator 206_i. The third capacitor C21_i is connected in parallel with the offset resistor R21_i. The superimposing circuit 230_i sources and / or sinks the corresponding differential current ΔI _i to the second end of the offset resistor R21_i.

In the superimposing circuit 230, the voltage at the inverting input terminal (−) of the PWM comparator 206 is given by Expression (1).
V _ERRi = V _ERR + ΔV _OFSi = V _ERR + R ₂₁ × ΔI _i (1)
That is, the offset voltage V _OFSi proportional to the differential current ΔI _i can be superimposed on the common error voltage V _ERR independently for each channel. That is, the differential current ΔI _i of each channel does not affect the original error signal V _ERR .

  Further, the current balance gain can be adjusted according to the resistance value of the offset resistor R21. Further, the response speed of the current balance can be adjusted according to the capacity of the third capacitor C21.

FIG. 10 is a circuit diagram showing a configuration example of the sample hold circuit 222. Input terminal Pi of the sample-and-hold circuit 222 is connected to the CSi terminal receives the current detection signal _{V IS.} The first switch SW31 and the second switch SW32 are provided in series between the input terminal Pi and the output terminal Po. First capacitor C31 is connected to a connection node of first switch SW31 and second switch SW32. The second capacitor C32 is connected to the output terminal Po.

FIG. 11 is an operation waveform diagram of the sample and hold circuit 222 of FIG. V _LX is a voltage at a connection node between the inductor L1 and the switching transistor M1 in FIG. 6, Vx is a voltage of the first capacitor C31, and Vy is a voltage of the second capacitor C32. The gain and time constant of the sample and hold circuit 222 can be set according to the capacitance ratio of each of the first capacitor C31 and the second capacitor C32. That is, the smaller the capacitance of the second capacitor C32, the higher the gain of the sample and hold circuit 222 and the faster the response, but an excessively high gain may make the system unstable. Therefore, by setting the capacitance of the second capacitor C32 to be larger than the capacitance of the first capacitor C31, it is possible to realize an appropriate gain and time constant.

FIG. 12 is a circuit diagram showing a configuration example of the individual current generation circuit 224, the average current generation circuit 226, and the differential current generation circuit 228. Since the plurality of individual current generation circuits 224 are similarly configured, the configuration of the first channel will be described. The individual current generation circuit 224_1 includes a V / I conversion circuit 232 and a current distribution circuit 234. The V / I conversion circuit 232 converts the corresponding current detection signal V _IS1 into a current signal I _1C . The configuration of the V / I conversion circuit 232 is not particularly limited, and various known techniques can be used. The current distribution circuit 234 copies the current signal I _1C into two systems, and supplies one system current I _1A to the average current generation circuit 226 and one system current I _1B to the corresponding differential current generation circuit 228_1.

  For example, the current distribution circuit 234 may include replicas M42 and M43 of the transistor M41 of the V / I conversion circuit 232 and replicas R42 and R43 of the resistor R41 of the V / I conversion circuit 232. The gates of the transistors M41, M42, and M43 are connected in common. The configuration of the current distribution circuit 234 is not particularly limited, and a current mirror circuit can also be used.

Average current generation circuit 226 includes a current mirror circuit. The current mirror circuit includes an input transistor M50 and a plurality of output transistors M51 to M5M. The individual currents I _{1A to} I _MA of the plurality of channels CH1 to CHM are input to the input transistor M50. The size of the input transistor M50 and the plurality of output transistors M51 to M5M is M: 1, and the current flowing through each of the plurality of output transistors M51 to M5M is the average current I _AVE .

The differential current generation circuit 228_i is a connection of the wiring 236 in which the average current I _AVE flows, the wiring 238 in which the individual current I _iB flows, and the wiring 240 that reaches the superimposing circuit 230. A differential current ΔI _i = I _AVE −I _iB flows through the wiring 240.

  Note that the configurations of the sample hold circuit 222, the individual current generation circuit 224, the average current generation circuit 226, the differential current generation circuit 228, and the superimposition circuit 230 are not particularly limited, and known circuits can be used.

(Second embodiment)
FIGS. 13A and 13B are circuit diagrams showing a second embodiment of the DC / DC converter 100. FIG. In the second embodiment, the DC / DC converter of each channel is configured by a bootstrap system having an N-channel MOSFET on the high side. 13A and 13B show only the configuration for one channel.

  The DC / DC converter 100 in FIG. 13A is a step-down synchronous rectification type converter, in which the switching transistor M1 is on the high side and the synchronous rectification transistor M2 is on the low side. The diode D2 and the bootstrap capacitor C2 constitute a bootstrap circuit. When switching of the switching transistor M1 and the synchronous rectification transistor M2 is stopped in a certain channel, the bootstrap capacitor C2 is not charged and the voltage at the BST terminal is lowered, so that the switching transistor M1 cannot be turned on. This means that when a certain channel switches from inactive to active, the switching transistor M1 cannot be switched for a while, and the responsiveness deteriorates. As described with reference to FIGS. 3 to 5, if the multi-channel control according to the embodiment is used in combination, all channels operate, so that the stop of the high-side transistor can be suppressed.

  The DC / DC converter 100 in FIG. 13B is a step-up synchronous rectification type converter, in which the switching transistor M1 is on the low side and the synchronous rectification transistor M2 is on the high side. The diode D2 and the bootstrap capacitor C2 constitute a bootstrap circuit. When switching of the switching transistor M1 and the synchronous rectification transistor M2 is stopped in a certain channel, the bootstrap capacitor C2 is not charged and the voltage at the BST terminal is lowered, so that the synchronous rectification transistor M2 cannot be turned on. This is because when a channel switches from inactive to active, the synchronous rectification transistor M2 cannot be switched for a while, that is, it operates as a diode rectification circuit using the body diode of the synchronous rectification transistor M2. , Which means the efficiency will deteriorate. As described with reference to FIGS. 3 to 5, if the multi-channel control according to the embodiment is used in combination, all channels operate, so that deterioration in efficiency can be suppressed.

  Finally, exemplary applications of the DC / DC converter will be described. FIG. 14 is a block diagram of a system power supply using the DC / DC converter according to the embodiment.

System power supply 300 has a configuration (3 lines in this embodiment) multilineage generates a different power supply voltage _{V OUT} for each system SYS1～SYS3, which can be supplied to the various loads.

  System power supply 300 can include any combination of a step-down converter, a step-up converter, and a linear regulator. In FIG. 14, the first system SYS1 is a step-down converter 410, the second system SYS2 is a step-up converter 420, and the third system SYS3 is a linear regulator (LDO: Low Drop Output) 430. The linear regulator may be provided for a plurality of channels. The step-down converter 410 or the step-up converter 420 corresponds to the DC / DC converter 100 described in the embodiment. In FIG. 14, the DC / DC converter is shown as a single channel, but it may be multi-channel multi-phase.

  The system power supply 300 includes a power management IC 302 and other peripheral circuit components. The power management IC 400 includes a control circuit 200 for the step-down converter 410, a control circuit 200 for the step-up converter 420, a linear regulator 402, an interface circuit 404, a sequencer 406, and the like. In addition, the power management IC 400 includes various protection circuits and the like.

The interface circuit 404 is provided for transmitting / receiving control signals and data to / from an external host processor. For example, the interface circuit 404 may conform to an I ² C (Inter IC) bus. The sequencer 406 controls the activation order and timing of the multi-system power supply circuits.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
In the embodiment, the number K of PWM periods included in the period group _TG is K = M / L, but the present invention is not limited to this. FIGS. 15A and 15B are operation waveform diagrams of a DC / DC converter according to a modification. FIG. 15A shows the operation of M = 2 and L = 1. The period group _TG is K = 4. In the first PWM period T ₁ to the third PWM period T ₃ , the first channel CH 1 is switched and the second channel CH 2 is high impedance. In a 4PWM period _{T 4} is the first channel CH1 at a high impedance, the second channel CH2 are switched. As described above, the first channel CH1 may be mainly operated, and the second channel CH2 may be intermittently used during the operation.

FIG. 15B shows the operation of M = 4 and L = 2. The period group _TG is K = 4. In the first PWM period T ₁ and the second PWM period T ₂ , the first channel CH1 and the second channel CH2 are switched, and the third channel CH3 and the fourth channel CH4 are high impedance. . In the subsequent third PWM cycle T ₃ and fourth PWM cycle T ₄ , the third channel CH3 and the fourth channel CH4 are switched, and the first channel CH1 and the second channel CH2 are high impedance.

(Second modification)
The DC / DC converter may be a diode rectification type (asynchronous rectification) or a synchronous rectification type. The present invention is applicable to a step-up / step-down DC / DC converter in addition to a step-up DC / DC converter and a step-down DC / DC converter.

(Third Modification)
With respect to the current balance circuit 220a of FIG. 8, an averaging circuit that generates an average value of the current detection signal _VIS may be provided instead of the sample hold circuit 222. A low pass filter may be used as the averaging circuit.

(Fourth modification)
Detection method of the coil current I _L in FIG. 6 is not particularly limited. For example, the on-resistance of the switching transistor M1 may be used in place of the current sense resistor R1. Alternatively, a replica of the switching transistor M1 connected so that a current proportional to the switching transistor M1 flows may be provided, and the current flowing through the replica may be detected.

(5th modification)
In the current balance circuit 220a of FIG. 8, the current detection signals V _{IS1 to} V _ISM that are voltage signals are converted into current signals, and then addition, subtraction, or average calculation is performed. However, the present invention is not limited to this. While the current detection signal _V IS1 _{~V ISM} is a voltage signal, summing may perform subtraction or averaging operation. The same applies to other signals.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... DC / DC converter, 102 ... Input line, 104 ... Output line, 110 ... Output circuit, M1 ... Switching transistor, L1 ... Inductor, C1 ... Output capacitor, D1 ... Rectifier, 200 ... Control circuit, 202 ... Error amplifier , 204 ... Pulse width modulator, 206 ... PWM comparator, 208 ... Logic circuit, 210 ... Slope compensator, 212 ... Driver, 220 ... Current balance circuit, 222 ... Sample hold circuit, 224 ... Individual current generation circuit, 226 ... Average Current generation circuit, 228... Differential current generation circuit, 230... Superimposition circuit, R21... Offset resistor, C21... Third capacitor, 232... V / I conversion circuit, 234. 1st switch, SW32 ... 2nd switch, C 1 ... first capacitor, C32 ... second capacitor, 300 ... system power, 400 ... power management IC, 402 ... linear regulator, 404 ... interface circuit, 406 ... sequencer.

Claims (16)

A control circuit for a DC / DC converter having a plurality of M channels (M is an integer of 2 or more),
The DC / DC converter includes a switching transistor, an inductor, and a rectifying element provided for each channel.
The control circuit includes:
An error amplifier for amplifying an error between a feedback signal corresponding to the output voltage of the DC / DC converter and its target value and generating an error signal;
M pulse width modulators corresponding to M channels, each of which generates a PWM (Pulse Width Modulation) signal having a duty ratio corresponding to the error signal;
A multi-phase controller that switches the number of active channels L (1 ≦ L ≦ M);
With
With at least one continuous PWM cycle as a cycle group, in each PWM cycle included in the cycle group, the switching transistors of L channels are on / off controlled, and the remaining (ML) channels are The connection point between the switching transistor and the rectifying element is controlled to have a high impedance, and each of the M switching transistors is controlled to be turned on and off at least once during the period group. Control circuit. M = 2,
When L = 1, the period group includes two PWM periods. (I) In the first PWM period included in the period group, the switching transistor of the first channel switches, and the second channel becomes high impedance. (Ii) In the second PWM cycle included in the cycle group, the first channel becomes high impedance, and the switching transistor of the second channel is switched,
When L = 2, the period group includes one PWM period, and (i) in one PWM period included in the period group, the switching transistor of the first channel and the second channel The control circuit according to claim 1, wherein the switching transistor switches.   3. The control circuit according to claim 2, wherein when L = 2, the switching transistor of the first channel and the switching transistor of the second channel are switched with a phase difference of 180 °. M = 4,
When L = 1, the period group includes four PWM periods. (I) In the first PWM period included in the period group, the switching transistor of the first channel switches, and the second channel to the fourth channel. Becomes high impedance, (ii) in the second PWM period included in the period group, the switching transistor of the second channel is switched, and the first, third, and fourth channels become high impedance, and (iii) the period group The third channel switching transistor switches in the third PWM cycle included in the first PWM channel, and the first, second, and fourth channels become high impedance. (Iv) In the fourth PWM cycle included in the cycle group, The channel switching transistor switches and , The second, third channel becomes high impedance,
When L = 2, the period group includes two PWM periods. (I) In the first PWM period included in the period group, two channel switching transistors of the first to fourth channels are switched. The remaining two channels become high impedance. (Ii) In the second PWM period included in the period group, the remaining two channels of switching transistors are switched, and the two channels become high impedance.
When L = 4, the period group includes one PWM period, and (i) the switching transistors of the first to fourth channels switch in a single PWM period included in the period group. The control circuit according to claim 1. When L = 2, in the first PWM period, the two channel switching transistors switch with a phase difference of 180 °, and in the second PWM period, the remaining two channel switching transistors switch with a phase difference of 180 °. And
5. The control circuit according to claim 4, wherein when L = 4, the switching transistors of four channels switch with a phase difference of 90 ° in the single PWM cycle. 6.   6. The control circuit according to claim 1, wherein K = M / L, where K is the number of PWM periods included in the period group. Each of the M pulse width modulators is in a peak current mode, each of which compares a current detection signal indicating a current flowing through a corresponding switching transistor with the error signal, and according to an output of the comparator A logic circuit for transitioning the PWM signal to an off level,
The control circuit includes:
For each of a plurality of M channels, a correction signal corresponding to the difference between the corresponding current detection signal and the average value of the current detection signals of the plurality of M channels is superimposed on at least one of the two inputs of the corresponding comparator. The control circuit according to any one of claims 1 to 6, further comprising a current balance circuit.   8. The control circuit according to claim 7, wherein the current balance circuit superimposes the correction signal on an input on the error signal side for each of the plurality of M channels.   The control circuit according to claim 1, wherein the DC / DC converter is a bootstrap system.   The control circuit according to claim 9, wherein the DC / DC converter is a step-down type.   11. The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate.   A DC / DC converter comprising the control circuit according to claim 1.   A system power supply comprising the DC / DC converter according to claim 12. A method for controlling a plurality of M channels (M is an integer of 2 or more) DC / DC converter,
The DC / DC converter includes a switching transistor, an inductor, and a rectifying element provided for each channel.
The control method is:
Amplifying an error between the feedback signal corresponding to the output voltage of the DC / DC converter and its target value, and generating an error signal;
Selecting the number L of active channels (1 ≦ L ≦ M);
Generating a PWM (Pulse Width Modulation) signal having a duty ratio according to the error signal for each channel;
Using at least one continuous PWM cycle as a cycle group, in each PWM cycle included in the cycle group, the switching transistors of L channels are turned on and off, and the remaining (ML) channels are controlled. Controlling the connection point of the switching transistor and the rectifying element to be high impedance, and controlling each of the M switching transistors at least once during the period group; and
A control method comprising: The step of generating the PWM signal includes:
For each channel, using a comparator, comparing a current detection signal indicating a current flowing through the corresponding switching transistor with the error signal;
Transitioning the PWM (Pulse Width Modulation) signal to an off level based on the result of the comparing step;
Including
The control method is:
For each of a plurality of M channels, a correction signal corresponding to the difference between the corresponding current detection signal and the average value of the current detection signals of the plurality of M channels is superimposed on at least one of the two inputs of the corresponding comparator. The control method according to claim 14, further comprising the step of:   The control method according to claim 15, wherein the DC / DC converter is a bootstrap system.

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