JP2017076672A - Solid state imaging apparatus and method for manufacturing solid state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging apparatus capable of suppressing picture quality of a captured image from being deteriorated, and a method for manufacturing a solid state imaging apparatus.SOLUTION: According to an embodiment, a solid state imaging apparatus includes an adjustment region in unit pixel cells which are arrayed two-dimensionally. The adjustment region is provided in a pixel including a pixel transistor provided therein or a pixel other than the pixel including a pixel transistor provided therein, among a plurality of pixels in the unit pixel cell. The adjustment region is doped with impurities so that the number of electrons generated in the pixel is adjusted.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

  Conventionally, a solid-state imaging device includes a photoelectric conversion element that photoelectrically converts incident light into a signal charge for each imaging pixel (hereinafter simply referred to as “pixel”), and a pixel that processes the photoelectrically converted signal charge. A transistor. In recent solid-state imaging devices, a plurality of photoelectric conversion elements share a pixel transistor, so that the number of pixels can be increased.

  Such a solid-state imaging device generally includes a plurality of unit pixel cells arranged two-dimensionally. Each unit pixel cell includes a plurality of pixels, and a photoelectric conversion element provided in each pixel shares a pixel transistor provided in any one of the pixels, thereby increasing the number of pixels.

  As described above, the unit pixel cell includes a pixel provided with a pixel transistor and a pixel provided with no pixel transistor. A pixel provided with a pixel transistor and a pixel provided with no pixel transistor have different layouts and different dark currents are detected due to this.

  In general, a pixel in which no pixel transistor is provided tends to detect more dark current than a pixel in which a pixel transistor is provided, which causes deterioration in image quality of a captured image.

JP 2006-074009 A

  An object of one embodiment is to provide a solid-state imaging device and a method for manufacturing the solid-state imaging device that can suppress deterioration in image quality of a captured image.

  According to one embodiment, a solid-state imaging device is provided. The solid-state imaging device includes an adjustment region in unit pixel cells that are two-dimensionally arranged. The adjustment region is provided in a pixel other than the pixel provided with the pixel transistor or the pixel provided with the pixel transistor among the plurality of pixels in the unit pixel cell. The adjustment region adjusts the number of electrons generated in the pixel by being doped with impurities.

FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera including the solid-state imaging device according to the first embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment. FIG. 3 is an explanatory diagram showing a layout in the unit pixel cell according to the first embodiment. FIG. 4 is an explanatory diagram illustrating a schematic cross section of a unit pixel cell according to the first embodiment. FIG. 5 is an explanatory diagram illustrating a manufacturing process of the solid-state imaging device according to the first embodiment. FIG. 6 is an explanatory diagram showing a layout in a unit pixel cell according to the second embodiment. FIG. 7 is an explanatory diagram illustrating a schematic cross section of a unit pixel cell according to the second embodiment. FIG. 8 is an explanatory diagram illustrating a pixel array according to the third embodiment. FIG. 9 is an explanatory diagram showing a layout of a unit pixel cell according to the third embodiment.

  Exemplary embodiments of a solid-state imaging device and a method for manufacturing the solid-state imaging device will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera 1 including the solid-state imaging device 14 according to the first embodiment. As shown in FIG. 1, the digital camera 1 includes a camera module 11 and a post-processing unit 12.

  The camera module 11 includes an imaging optical system 13 and a solid-state imaging device 14. The imaging optical system 13 takes in light from a subject and forms a subject image. The solid-state imaging device 14 captures a subject image formed by the imaging optical system 13 and outputs an image signal obtained by the imaging to the post-processing unit 12. In addition to the digital camera 1, the camera module 11 is applied to an electronic device such as a mobile terminal with a camera.

  The post-processing unit 12 includes an ISP (Image Signal Processor) 15, a storage unit 16, and a display unit 17. The ISP 15 performs signal processing of the image signal input from the solid-state imaging device 14. The ISP 15 performs high image quality processing such as noise removal processing, defective pixel correction processing, and resolution conversion processing.

  Then, the ISP 15 outputs the image signal after the signal processing to the signal processing circuit 21 (see FIG. 2) described later provided in the storage unit 16, the display unit 17, and the solid-state imaging device 14 in the camera module 11. An image signal fed back from the ISP 15 to the camera module 11 is used for adjustment and control of the solid-state imaging device 14.

  The storage unit 16 stores the image signal input from the ISP 15 as an image. In addition, the storage unit 16 outputs an image signal of the stored image to the display unit 17 according to a user operation or the like. The display unit 17 displays an image according to an image signal input from the ISP 15 or the storage unit 16. The display unit 17 is, for example, a liquid crystal display.

  Next, the solid-state imaging device 14 included in the camera module 11 will be described with reference to FIG. FIG. 2 is a block diagram illustrating a schematic configuration of the solid-state imaging device 14 according to the first embodiment. As shown in FIG. 2, the solid-state imaging device 14 includes an image sensor 20 and a signal processing circuit 21.

  Here, the case where the image sensor 20 is a so-called surface-irradiation type CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a wiring layer is formed on a surface on which incident light is incident in a pixel that photoelectrically converts incident light will be described. . The image sensor 20 according to the embodiment is not limited to the front side illumination type CMOS image sensor, and may be a back side illumination type CMOS image sensor.

  The image sensor 20 includes a peripheral circuit 22 and a pixel array 23. The peripheral circuit 22 includes a vertical shift register 24, a timing control unit 25, a CDS (correlated double sampling) 26, an ADC (analog / digital conversion unit) 27, and a line memory 28, and these are mainly configured by analog circuits. Is done.

  The pixel array 23 is provided in the imaging region of the image sensor 20. In the pixel array 23, unit pixel cells each including two pixels including a photoelectric conversion element as a set are arranged in a two-dimensional array (matrix) in the horizontal direction (row direction) and the vertical direction (column direction). ing.

  In the unit pixel cell, the photoelectric conversion element of each pixel generates a signal charge (for example, electrons) corresponding to the amount of incident light, and accumulates it in the charge accumulation region in each pixel. The unit pixel cell includes a pixel transistor that performs processing such as outputting signal charges accumulated in the photoelectric conversion element. The pixel transistor is provided in one of the two pixels in the unit pixel cell and is shared by the two photoelectric conversion elements.

  The unit pixel cell according to the first embodiment further includes an adjustment region. The adjustment region adjusts the number of electrons generated in the pixels regardless of the incident light (hereinafter sometimes simply referred to as electrons), thereby making the dark current caused by the electrons substantially equal among the pixels.

  Thereby, the solid-state imaging device 14 can reduce the dark current difference detected between the pixels, and can suppress deterioration in image quality such as luminance unevenness and white scratch of the captured image due to the dark current difference. . This adjustment area will be described later with reference to FIG.

  The timing control unit 25 is a processing unit that outputs a pulse signal serving as a reference for operation timing to the vertical shift register 24, the CDS 26, the ADC 27, and the line memory 28. The vertical shift register 24 is a processing unit that outputs, to the pixel array 23, a selection signal for sequentially selecting pixels for reading signal charges from a plurality of pixels that are two-dimensionally arranged in an array (matrix). .

  The pixel array 23 outputs the signal charge accumulated in each photoelectric conversion element selected in units of rows by the selection signal input from the vertical shift register 24 from the photoelectric conversion element to the CDS 26 as a pixel signal indicating the luminance of each pixel. To do.

  The CDS 26 is a processing unit that removes noise from the pixel signal input from the pixel array 23 by correlated double sampling and outputs the noise to the ADC 27. The ADC 27 is a processing unit that converts an analog pixel signal input from the CDS 26 into a digital pixel signal and outputs the digital pixel signal to the line memory 28. The line memory 28 is a processing unit that temporarily holds the pixel signal input from the ADC 27 and outputs the pixel signal to the signal processing circuit 21 for each row of pixels in the pixel array 23.

  The signal processing circuit 21 is a processing unit that performs predetermined signal processing on the pixel signal input from the line memory 28 and outputs the processed signal to the subsequent processing unit 12, and is mainly configured by a digital circuit. The signal processing circuit 21 performs signal processing such as lens shading correction, flaw correction, and noise reduction processing on the pixel signal.

  As described above, in the image sensor 20, a plurality of pixels arranged in the pixel array 23 photoelectrically converts incident light into signal charges of an amount corresponding to the amount of received light, and accumulates the peripheral circuit 22 in each pixel. Imaging is performed by reading a pixel signal corresponding to the signal charge.

  Next, a layout in the unit pixel cell according to the first embodiment will be described with reference to FIG. FIG. 3 is an explanatory diagram showing a layout in the unit pixel cell C according to the first embodiment. FIG. 3 schematically shows each component arranged in the unit pixel cell C.

  As shown in FIG. 3, the unit pixel cell C is provided with a first pixel PC1 and a second pixel PC2 adjacent to each other. The first pixel PC1 includes a photodiode P1 that is a photoelectric conversion element, and the second pixel PC2 includes a photodiode P2.

  The unit pixel cell C includes a floating diffusion F that holds signal charges transferred from the photodiodes between the photodiodes P1 and P2. The floating diffusion F is shared by the photodiode P1 and the photodiode P2.

  The unit pixel cell C includes a transfer gate T1 between the photodiode P1 and the floating diffusion F, and a transfer gate T2 between the photodiode P2 and the floating diffusion F. The transfer gates T1 and T2 transfer the signal charges accumulated in the photodiodes P1 and P2 to the floating diffusion F when a predetermined voltage is applied.

  The unit pixel cell C includes pixel transistors such as an amplification transistor AM and a row selection transistor AD. The pixel transistor is shared by the photodiode P1 and the photodiode P2.

  The reset transistor R is provided in a region where the gate Rg is adjacent to the floating diffusion F, and resets the potential of the floating diffusion F to the initial potential when a predetermined voltage is applied to the gate Rg. The drain Rd adjacent to the gate Rg is provided on the first pixel PC1 side.

  The amplification transistor AM is provided in the second pixel PC2, and the gate AMg is connected to the floating diffusion F. The amplification transistor AM amplifies the signal charge transferred from the floating diffusion F when a predetermined voltage is applied to the gate AMg. The amplification transistor AM includes a source AMs, a gate AMg, and a drain AMd.

  The row selection transistor AD is provided adjacent to the amplification transistor AM, and outputs a signal charge output from the amplification transistor AM to the vertical signal line when a predetermined voltage is applied to the gate ADg. The row selection transistor AD includes a source ADs, a gate ADg, and a drain ADd, and the source ADs is adjacent to the drain AMd.

  Further, element isolation regions S1 and S2 are provided in regions other than where each element in the unit pixel cell C is provided, and each element is electrically isolated from each other. The element isolation regions S1 and S2 are, for example, STI (Shallow Trench Isolation) regions. The STI region is formed by embedding an insulating member in the formed trench.

  In general, in the STI region, electrons irrelevant to incident light (hereinafter referred to as dark electrons) are generated in a pixel due to crystal defects caused by forming a trench. When such dark electrons are accumulated in the photodiode and output by the pixel transistor, they are detected as a so-called dark current.

  Here, as shown in FIG. 3, the element isolation region S1 of the first pixel PC1 where the pixel transistor is not provided is larger than the element isolation region S2 of the second pixel PC2 where the pixel transistor is provided. For this reason, the dark electrons generated in the first pixel PC1 are larger than the dark electrons generated in the second pixel PC2, causing unevenness in brightness and white scratches in the captured image, and degrading the image quality.

  Therefore, the unit pixel cell C according to the first embodiment includes an adjustment area AA in the first pixel PC1 that adjusts the number of dark electrons that are doped with impurities and that are generated in the pixel regardless of incident light.

  The adjustment area AA is an area having an area where the areas of the element isolation areas of the first pixel PC1 and the second pixel PC2 are substantially the same. The adjustment area AA is electrically isolated from the photodiode P1 by the element isolation area S1, and a transistor for processing signal charges such as a pixel transistor is not disposed.

  As shown in FIG. 3, the adjustment area AA can be arranged so that, for example, the element layout of the first pixel PC1 and the second pixel PC2 is substantially symmetric. Specifically, the adjustment area AA is disposed in the first pixel PC1 facing the amplification transistor AM and the row selection transistor AD with the reset transistor R interposed therebetween.

  The area of the adjustment region AA can be, for example, the area of the amplification transistor AM and the row selection transistor AD. Then, by doping the adjustment area AA with the N-type impurity, the dark electrons generated in the first pixel PC1 are reduced, and are substantially equal to the dark electrons generated in the second pixel PC2.

  Next, the cross section and operation of the adjustment area AA will be described with reference to FIG. FIG. 4 is an explanatory diagram illustrating a schematic cross section of the unit pixel cell C according to the first embodiment. FIG. 4A is an explanatory diagram showing a schematic cross section of the first pixel PC1 along the line AA ′ in FIG. FIG. 4B is an explanatory diagram showing a schematic cross section of the second pixel PC2 along the line BB ′ in FIG. 4A and 4B selectively show the photodiodes P1 and P2, the element isolation regions S1 and S2, and the adjustment region AA.

  As shown in FIG. 4A, in the first pixel PC <b> 1 where no pixel transistor is provided, a P-type semiconductor layer 32 is stacked on the silicon layer 31. The P-type semiconductor layer 32 is, for example, a silicon layer doped with a P-type impurity such as boron. The P-type semiconductor layer 32 includes a photodiode P1 inside.

  For example, the photodiode P1 includes an N-type charge storage region 33a doped with an N-type impurity such as phosphorus (P) and a P-type Si region 34 doped with a P-type impurity such as boron (B). And a PN junction. The N-type charge accumulation region 33a is a region in which light incident from the light receiving surface (here, the upper surface) side is photoelectrically converted into signal charges corresponding to the amount of light and accumulated.

  The P-type semiconductor layer 32 is provided with an element isolation region S1 adjacent to the photodiode P1. The element isolation region S1 is an STI region and may generate dark electrons e unrelated to incident light. When the dark electrons e flow into the charge storage region 33a, dark currents are caused.

  Here, for example, the number (for example, 5) of dark electrons e accumulated in the charge accumulation region 33a of the first pixel PC1 is accumulated in the charge accumulation region 33b of the second pixel PC2 shown in FIG. 4B. There may be more than the number of dark electrons e (for example, 3).

  Therefore, the first pixel PC1 in which no pixel transistor is provided includes an adjustment region AA doped with an N-type impurity having the same conductivity type as the charge storage region 33a at a position separated by the element isolation region S1.

  As shown in FIG. 4A, the N-type adjustment area AA functions as a drain for discharging dark electrons e generated regardless of incident light when a predetermined voltage is applied.

  Thereby, the adjustment area AA can prevent the dark electrons e from flowing into the charge accumulation area 33a. Therefore, in the solid-state imaging device 14 according to the first embodiment, for example, the number of dark electrons e accumulated in the first pixel PC1 and the second pixel PC2 becomes substantially equal (for example, 3), and The detected dark current difference is reduced, and deterioration of the image quality of the captured image can be suppressed.

  Here, although the dark current “difference” detected between the respective pixels is reduced, the dark current itself is detected. Therefore, the post-processing unit 12 described above performs correction to remove the detected dark current. At this time, the post-processing unit 12 can perform the same correction process for all the pixels because the difference in dark current between the pixels is reduced.

  Further, the N-type impurity concentration doped in the adjustment region AA is set lower than the N-type impurity concentration in the charge storage region 33a. This is because, for example, when high concentration N-type impurities are ion-implanted, crystal defects occur in the P-type semiconductor layer 32 due to damage caused by ion implantation, and excessive dark electrons e are generated. In such a case, the adjustment area AA cannot equalize the number of dark electrons e between pixels.

  Next, a method for manufacturing the solid-state imaging device 14 according to the embodiment will be described with reference to FIG. FIG. 5A to FIG. 5C are explanatory diagrams illustrating manufacturing steps of the solid-state imaging device 14 according to the embodiment.

  In addition, in the manufacturing process of the solid-state imaging device 14 according to the embodiment, the manufacturing process of the solid-state imaging device is the same as that of the general solid-state imaging device except for the manufacturing process of each pixel portion. For this reason, a part of the manufacturing process of the pixel shown in FIG. 4A will be described here, and the description of the other processes will be omitted. In the following description, the same components as those shown in FIG. 4 are denoted by the same reference numerals as those shown in FIG.

  When manufacturing the pixel array 23, first, as shown in FIG. 5A, a P-type semiconductor layer 32 is formed on the non-doped silicon layer 31. Here, for example, a P-type semiconductor in which a plurality of pixels (see FIG. 3) are formed later from the surface of the silicon substrate by ion-implanting boron into the silicon substrate from the surface of the silicon substrate and performing an annealing process. Layer 32 is formed.

  Subsequently, for example, RIE (Reactive Ion Etching) is performed on a position where a region where each element is to be formed later is separated in the P-type semiconductor layer 32 in the unit pixel cell C (see FIG. 3) having a plurality of pixels. By doing so, a trench is formed. Thereafter, for example, silicon oxide is deposited in the trench by CVD (Chemical Vapor Deposition) to form the element isolation region S1.

  Thereafter, as shown in FIG. 5B, phosphorus is ion-implanted into the formation position of the photodiode P1, which is a photoelectric conversion element, in the P-type semiconductor layer 32 separated by the element isolation region S1, and annealing treatment is performed. To form an N-type charge storage region 33a.

  Then, a P-type Si region 34 is formed by ion-implanting high-concentration boron into the light-receiving surface side (the upper surface here) of the N-type charge accumulation region 33a and performing an annealing process. A photodiode P1 is formed by a PN junction of the N-type charge storage region 33a and the P-type Si region 34. Note that the photodiode is formed in each of a plurality of pixels in the semiconductor layer.

  Subsequently, as shown in FIG. 5C, an N-type adjustment region AA is formed by performing an annealing process by implanting phosphorus ions on the opposite side across the photodiode P1 and the element isolation region S1. At this time, the N-type impurity concentration of the adjustment region AA is adjusted to be lower than the impurity concentration of the N-type charge accumulation region 33a by adjusting the impurity dose. Thereby, the first pixel PC1 (see FIG. 3) in which the pixel transistor shown in FIG. 4A is not provided is completed.

  In the second pixel PC2 (not shown), a gate is formed by CVD and dry etching in a region that will later become a pixel transistor. Subsequently, phosphorus is ion-implanted to form each source and each drain of the pixel transistor.

  According to the first embodiment, the unit pixel cell C of the solid-state imaging device 14 includes the adjustment area AA in the first pixel PC1 in which no pixel transistor is provided. The adjustment area AA is doped with an N-type impurity having the same conductivity type as that of the charge accumulation area 33a and functions as a drain that discharges dark electrons generated irrespective of incident light, so that the accumulated dark electrons are averaged. Can do.

  Thereby, the solid-state imaging device 14 can reduce dark electrons accumulated in the charge accumulation region 33a. Moreover, the solid-state imaging device 14 can reduce the detected dark current difference by averaging the dark electrons, and can reduce unevenness in the brightness of the captured image.

  Furthermore, the solid-state imaging device 14 can suppress deterioration of image quality such as white scratches in a captured image by simplifying correction for removing the dark current by reducing the dark current difference.

  The N-type adjustment area AA according to the first embodiment is surrounded by the element isolation area S1 in the first pixel PC1 and provided independently. However, the present invention is not limited to this. The drain Rd region may be enlarged, and the enlarged region may be used as the adjustment region AA.

  In this case, the adjustment region AA is formed by ion-implanting high-concentration impurities into the drain Rd including the enlarged region, and then performing annealing by ion-implanting low-concentration impurities for the adjustment region AA into the enlarged region. By forming.

(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. FIG. 6 is an explanatory diagram showing a layout of the unit pixel cell C according to the second embodiment. FIG. 6 schematically shows each component arranged in the unit pixel cell C.

  In the first embodiment, dark electrons are discharged and adjusted by providing an N-type adjustment area AA in the first pixel PC1. On the other hand, the second embodiment differs from the first embodiment in the conductivity type of the pixel in which the adjustment area AA is provided and the impurity to be doped.

  As shown in FIG. 6, the adjustment area AA according to the second embodiment is provided in the second pixel PC2. The second pixel PC2 is a pixel provided with a pixel transistor that processes signal charges.

  In the adjustment area AA according to the second embodiment, the second pixel PC2 in which the pixel transistor is provided is doped with a P-type impurity having a conductivity type opposite to that of the charge accumulation area 33b. Thus, the adjustment area AA has a function of supplying dark electrons to the charge accumulation area 33b.

  Next, the cross section and operation of the adjustment area AA will be described with reference to FIG. FIG. 7 is an explanatory diagram showing a schematic cross section of the unit pixel cell C. As shown in FIG.

  7A is an explanatory diagram showing a schematic cross section of the second pixel PC2 along the line AA ′ in FIG. 6, and FIG. 7B is a diagram illustrating the first pixel PC1 along the line BB ′ in FIG. It is explanatory drawing which shows a typical cross section.

  As shown in FIG. 7A, the adjustment area AA is located on the opposite side of the element isolation area S2 from the photodiode P2, and is doped with P-type impurities. Here, when the adjustment region AA is ion-implanted with a P-type impurity, crystal defects are generated in the P-type semiconductor layer 32 due to damage caused by the ion implantation, and dark electrons e are generated.

  Then, the adjustment area AA according to the second embodiment supplies the dark electrons e to the charge accumulation area 33b. As a result, the number of dark electrons e (for example, 5) in the charge storage region 33b is substantially equal to the number of dark electrons e (for example, 5) in the charge storage region 33a.

  However, since the number of dark electrons e accumulated in the charge accumulation region 33b includes the dark electrons e supplied from the adjustment region AA, the dark current difference detected between the pixels is eliminated, but the unit pixel cell C The amount of dark current increases. At this time, the post-processing unit 12 can perform the correction for removing the dark current by the same processing for all the pixels, so that the correction can be performed more easily.

  Next, a method for manufacturing the solid-state imaging device 14 according to the second embodiment will be described. In the description of the manufacturing method of the second embodiment, the description of the portions overlapping those of the first embodiment will be omitted, and the conductivity type of the pixel provided with the adjustment region AA and the impurity will be described.

  In the manufacturing process of the solid-state imaging device 14 according to the second embodiment, the adjustment area AA is formed in the second pixel PC2 in which the pixel transistor is provided. Specifically, the adjustment area AA is formed by performing an annealing process by implanting boron into the P-type semiconductor layer 32 at a position opposite to the photodiode P2 across the element isolation area S2. Doped with P-type impurities.

  The P-type impurity concentration in the adjustment region AA is adjusted to be lower than the impurity concentration in the N-type charge storage region 33b by adjusting the impurity dose. Thereby, the second pixel PC2 shown in FIG. 7A is completed.

  According to the second embodiment, the unit pixel cell C of the solid-state imaging device 14 includes the adjustment area AA in the second pixel PC2 in which the pixel transistor is provided. The adjustment area AA is doped with a P-type impurity having a conductivity type opposite to that of the charge accumulation area 33b, and supplies the dark electrons e generated regardless of the incident light, thereby averaging the accumulated dark electrons e. Can do.

  Therefore, in the solid-state imaging device 14 according to the second embodiment, for example, the number of dark electrons e accumulated in the first pixel PC1 and the second pixel PC2 is substantially equal (for example, 5), The detected dark current difference is reduced, and deterioration of the image quality of the captured image can be suppressed.

(Third embodiment)
Next, the solid-state imaging device 14 according to the third embodiment will be described. In the first and second embodiments, the number of dark electrons e is adjusted between the pixels in the unit pixel cell C. In the third embodiment, the number of dark electrons e in the entire pixel array 23 is adjusted. Is to adjust. Hereinafter, the third embodiment will be described in detail with reference to FIGS. 8 and 9.

  FIG. 8 is an explanatory diagram illustrating a pixel array 23 according to the third embodiment. As shown in FIG. 8, the unit pixel cells C are two-dimensionally arranged in the pixel array 23.

  Here, a signal processing circuit 21 including a logic circuit (not shown) is disposed outside the peripheral edge 23 b of the pixel array 23. Such a logic circuit may generate heat when performing predetermined signal processing on the pixel signal input from the image sensor 20 described above.

  For this reason, in the unit pixel cell Cb in the peripheral portion 23b, electrons in the unit pixel cell Cb are excited by the influence of heat generation, and more dark electrons e are generated than in the unit pixel cell Ca in the central portion 23a.

  That is, the dark current detected in the entire pixel array 23 is larger in the peripheral portion 23b than in the central portion 23a. As a result, the output captured image may have a brighter peripheral edge than the central portion, and the image quality may deteriorate.

  Therefore, the solid-state imaging device 14 according to the third embodiment adjusts the number of dark electrons e by making a difference in the area of the adjustment area AA between the central portion 23a and the peripheral portion 23b.

  9A is an explanatory diagram showing a layout of the unit pixel cells Ca arranged in the central portion 23a of the pixel array 23, and FIG. 9B is a unit pixel cell arranged in the peripheral portion 23b of the pixel array 23. It is explanatory drawing which shows the layout of Cb. Although FIG. 9 illustrates the case where the N-type adjustment area AA is provided in the first pixel PC1, the present invention is not limited to this, and the P-type adjustment area AA may be provided in the second pixel PC2.

  As shown in FIGS. 9A and 9B, the area of the adjustment region AAb of the unit pixel cell Cb in the peripheral portion 23b is larger than the area of the adjustment region AAa of the unit pixel cell Ca in the central portion 23a.

  Specifically, the unit pixel cell Ca has a smaller adjustment area AAa than the unit pixel cell Cb, so that the area of the element isolation region Sa is increased, and as a result, the generated dark electrons e are increased. On the other hand, the unit pixel cell Cb has a larger adjustment area AAb than the unit pixel cell Ca, so that the element isolation area Sb is reduced, and as a result, the generated dark electrons e are reduced.

  Therefore, the pixel array 23 according to the third embodiment can eliminate the dark current difference of the entire captured image by adjusting the area of the element isolation region at the central portion 23a and the peripheral portion 23b. Thereby, it is possible to suppress deterioration in image quality at the peripheral edge of the captured image.

  In the third embodiment, the number of dark electrons e is adjusted based on the area difference of the adjustment region AA. However, it is sufficient that the generated dark electrons e are smaller in the peripheral portion than in the central portion. It may be adjusted, or the number of adjustment areas to be provided may be adjusted.

  In the third embodiment, the area of the adjustment area AAb is larger than the area of the adjustment area AAa. However, the area of the adjustment area AAb may be smaller than the area of the adjustment area AAa. In such a case, the number of dark electrons e generated by adjusting the impurity concentration of each adjustment region and the number of adjustment regions provided is adjusted.

  In addition, the unit pixel cell C of the solid-state imaging device 14 according to each of the above-described embodiments has a two-pixel structure, but the present invention is not limited to this, and the unit pixel cell may have a structure of three or more pixels. Good.

  In such a case, the unit pixel cell includes one pixel provided with a pixel transistor and a plurality of pixels provided with no pixel transistor. The adjustment area AA according to the embodiment is provided in each of the plurality of pixels, thereby adjusting the number of dark electrons e generated regardless of incident light.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  C, Ca, Cb unit pixel cell, AA, AAa, AAb adjustment area, S1, S2, Sa, Sb element isolation area, 14 solid-state imaging device, P1, P2 photodiode, 33a, 33b charge storage area, 23 pixel array, 23a central part, 23b peripheral part, R reset transistor, AM amplification transistor, AD row selection transistor.

Claims (5)

Among a plurality of pixels in the unit pixel cell arrayed two-dimensionally, an electron is provided in a pixel provided with a pixel transistor or a pixel other than a pixel provided with the pixel transistor, and is generated in the pixel by being doped with impurities. A solid-state imaging device comprising an adjustment region for adjusting the number of the imaging regions. The adjustment area is
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided in a pixel other than the pixel in which the pixel transistor is provided, and the impurity has the same conductivity type as a charge accumulation region of a photoelectric conversion element in the pixel. The adjustment area is
2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided in a pixel in which the pixel transistor is provided, and the impurity has a conductivity type opposite to a charge accumulation region of a photoelectric conversion element in the pixel. The adjustment area is
Impurity concentration is
The solid-state imaging device according to claim 1, wherein the solid-state imaging device is lower than an impurity concentration of a charge storage region of a photoelectric conversion element in the pixel. Forming photoelectric conversion elements in the formation regions of the plurality of pixels in the semiconductor layer,
Forming a pixel transistor in a predetermined pixel among a plurality of pixels in the unit pixel cell for each unit pixel cell including a predetermined number of the photoelectric conversion elements;
Forming an adjustment region for adjusting the number of electrons generated in the pixel by doping an impurity in the predetermined pixel or a pixel other than the predetermined pixel. Method.

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